From dfecda3a5fcb42fe6bc8e83621bf976032ff50c9 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 27 Oct 2022 14:16:49 +0800 Subject: [PATCH 1/6] bin2hex: handle any file length, not just 8 or 4 Treat the input as if it was padded with zeroes to a multiple of 8. This is needed if the .data in a binary changes size, it won't be a nice multiple of 4 or 8. At present the microwatt binaries all are multiples of 8, but making code alterations could make bin2hex fail unexpectedly. Signed-off-by: Matt Johnston --- litedram/gen-src/sdram_init/bin2hex.py | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/litedram/gen-src/sdram_init/bin2hex.py b/litedram/gen-src/sdram_init/bin2hex.py index af278bc..b53b2c9 100755 --- a/litedram/gen-src/sdram_init/bin2hex.py +++ b/litedram/gen-src/sdram_init/bin2hex.py @@ -7,11 +7,8 @@ import struct with open(sys.argv[1], "rb") as f: while True: word = f.read(8) - if len(word) == 8: - print("%016x" % struct.unpack('Q', word)); - elif len(word) == 4: - print("00000000%08x" % struct.unpack('I', word)); - elif len(word) == 0: + if len(word) == 0: exit(0); - else: - raise Exception("Bad length") + if len(word) != 8: + word = word + bytes(8 - len(word)) + print("%016x" % struct.unpack('Q', word)); From 4bd45af739214d8659a4940485500ae508399ecd Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 27 Oct 2022 11:23:30 +0800 Subject: [PATCH 2/6] Move alt_reset to syscon Instead of connecting core_alt_reset to litedram init_done, it moves to a syscon register bit. This simplifies top- files and future soc_reset handling. sdram main.c can unset the alt_reset bit after sdram init. Signed-off-by: Matt Johnston --- core_dram_tb.vhdl | 5 +---- dram_tb.vhdl | 1 - fpga/top-acorn-cle-215.vhdl | 8 +------- fpga/top-antmicro-artix-dc-scm.vhdl | 10 +--------- fpga/top-arty.vhdl | 9 +-------- fpga/top-genesys2.vhdl | 8 +------- fpga/top-nexys-video.vhdl | 9 +-------- fpga/top-orangecrab0.2.vhdl | 9 +-------- fpga/top-wukong-v2.vhdl | 10 +--------- include/microwatt_soc.h | 1 + litedram/extras/litedram-wrapper-l2.vhdl | 4 ---- soc.vhdl | 9 ++++----- syscon.vhdl | 16 ++++++++++++---- 13 files changed, 25 insertions(+), 74 deletions(-) diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl index a0251e3..4a3a0c3 100644 --- a/core_dram_tb.vhdl +++ b/core_dram_tb.vhdl @@ -32,7 +32,6 @@ architecture behave of core_dram_tb is signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - signal core_alt_reset : std_ulogic; -- SPI signal spi_sck : std_ulogic; @@ -84,8 +83,7 @@ begin spi_flash_cs_n => spi_cs_n, spi_flash_sdat_o => spi_sdat_o, spi_flash_sdat_oe => spi_sdat_oe, - spi_flash_sdat_i => spi_sdat_i, - alt_reset => core_alt_reset + spi_flash_sdat_i => spi_sdat_i ); flash: entity work.s25fl128s @@ -135,7 +133,6 @@ begin rst => rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, wb_in => wb_dram_in, wb_out => wb_dram_out, diff --git a/dram_tb.vhdl b/dram_tb.vhdl index ce22f30..c8e7b2c 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -58,7 +58,6 @@ begin rst => rst, system_clk => clk, system_reset => soc_rst, - core_alt_reset => open, pll_locked => open, wb_in => wb_in, diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl index fd5fd5c..7f03506 100644 --- a/fpga/top-acorn-cle-215.vhdl +++ b/fpga/top-acorn-cle-215.vhdl @@ -84,9 +84,6 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -162,8 +159,7 @@ begin wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, - wb_ext_is_dram_init => wb_ext_is_dram_init, - alt_reset => core_alt_reset + wb_ext_is_dram_init => wb_ext_is_dram_init ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -231,7 +227,6 @@ begin led1 <= pll_rst; led2 <= not system_clk_locked; led3 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -289,7 +284,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-antmicro-artix-dc-scm.vhdl b/fpga/top-antmicro-artix-dc-scm.vhdl index b8fd75f..bd0dcd5 100644 --- a/fpga/top-antmicro-artix-dc-scm.vhdl +++ b/fpga/top-antmicro-artix-dc-scm.vhdl @@ -121,9 +121,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -240,9 +237,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); @@ -303,8 +298,6 @@ begin pll_locked_out => system_clk_locked ); - core_alt_reset <= '0'; - d11_led <= '0'; d12_led <= soc_rst; d13_led <= system_clk; @@ -376,7 +369,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index ecdd5d4..b6b8913 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -139,9 +139,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -258,9 +255,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); --uart_pmod_rts_n <= '0'; @@ -333,7 +328,6 @@ begin led0_b_pwm <= '1'; led0_r_pwm <= '1'; led0_g_pwm <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -402,7 +396,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl index ecdaa66..d876362 100644 --- a/fpga/top-genesys2.vhdl +++ b/fpga/top-genesys2.vhdl @@ -87,9 +87,6 @@ architecture behaviour of toplevel is signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -165,8 +162,7 @@ begin wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, - wb_ext_is_dram_init => wb_ext_is_dram_init, - alt_reset => core_alt_reset + wb_ext_is_dram_init => wb_ext_is_dram_init ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -234,7 +230,6 @@ begin led1 <= pll_rst; led2 <= not system_clk_locked; led3 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -292,7 +287,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => soc_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index beb4045..f18f80e 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -128,9 +128,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -220,9 +217,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2 @@ -282,7 +277,6 @@ begin led0 <= '1'; led1 <= not soc_rst; led2 <= '0'; - core_alt_reset <= '0'; -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed @@ -350,7 +344,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl index ada940c..f773323 100644 --- a/fpga/top-orangecrab0.2.vhdl +++ b/fpga/top-orangecrab0.2.vhdl @@ -110,9 +110,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- Status LED signal led0_b_pwm : std_ulogic; signal led0_r_pwm : std_ulogic; @@ -231,9 +228,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash @@ -284,7 +279,6 @@ begin led0_b_pwm <= '1'; led0_r_pwm <= '1'; led0_g_pwm <= '0'; - core_alt_reset <= '0'; end generate; @@ -341,7 +335,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl index d3f7bd8..2b6d4e1 100644 --- a/fpga/top-wukong-v2.vhdl +++ b/fpga/top-wukong-v2.vhdl @@ -128,9 +128,6 @@ architecture behaviour of toplevel is -- for conversion from non-pipelined wishbone to pipelined signal wb_sddma_stb_sent : std_ulogic; - -- Control/status - signal core_alt_reset : std_ulogic; - -- SPI flash signal spi_sck : std_ulogic; signal spi_cs_n : std_ulogic; @@ -225,9 +222,7 @@ begin -- DMA wishbone wishbone_dma_in => wb_sddma_in, - wishbone_dma_out => wb_sddma_out, - - alt_reset => core_alt_reset + wishbone_dma_out => wb_sddma_out ); -- SPI Flash @@ -282,8 +277,6 @@ begin pll_locked_out => system_clk_locked ); - core_alt_reset <= '0'; - -- Vivado barfs on those differential signals if left -- unconnected. So instanciate a diff. buffer and feed -- it a constant '0'. @@ -351,7 +344,6 @@ begin rst => pll_rst, system_clk => system_clk, system_reset => dram_sys_rst, - core_alt_reset => core_alt_reset, pll_locked => system_clk_locked, wb_in => wb_dram_in, diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index ab55287..3e6830b 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -52,6 +52,7 @@ #define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) #define SYS_REG_CTRL_CORE_RESET (1ull << 1) #define SYS_REG_CTRL_SOC_RESET (1ull << 2) +#define SYS_REG_CTRL_ALT_RESET (1ull << 3) #define SYS_REG_DRAMINITINFO 0x30 #define SYS_REG_SPI_INFO 0x38 #define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 652e727..8069b8e 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -44,7 +44,6 @@ entity litedram_wrapper is rst : in std_ulogic; system_clk : out std_ulogic; system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; pll_locked : out std_ulogic; -- Wishbone ports: @@ -420,9 +419,6 @@ begin assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) report "geometry bits don't add up" severity FAILURE; - -- alternate core reset address set when DRAM is not initialized. - core_alt_reset <= not init_done; - -- Init code BRAM memory slave init_ram_0: entity work.dram_init_mem generic map( diff --git a/soc.vhdl b/soc.vhdl index 7daca5f..3282ca9 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -127,10 +127,7 @@ entity soc is -- GPIO signals gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); - gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); - - -- DRAM controller signals - alt_reset : in std_ulogic := '0' + gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0') ); end entity soc; @@ -166,6 +163,7 @@ architecture behaviour of soc is -- Syscon signals signal dram_at_0 : std_ulogic; signal do_core_reset : std_ulogic; + signal alt_reset : std_ulogic; signal wb_syscon_in : wb_io_master_out; signal wb_syscon_out : wb_io_slave_out; @@ -768,7 +766,8 @@ begin wishbone_out => wb_syscon_out, dram_at_0 => dram_at_0, core_reset => do_core_reset, - soc_reset => open -- XXX TODO + soc_reset => open, -- XXX TODO + alt_reset => alt_reset ); -- diff --git a/syscon.vhdl b/syscon.vhdl index 727f4e7..99fa835 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -34,7 +34,8 @@ entity syscon is -- System control ports dram_at_0 : out std_ulogic; core_reset : out std_ulogic; - soc_reset : out std_ulogic + soc_reset : out std_ulogic; + alt_reset : out std_ulogic ); end entity syscon; @@ -76,10 +77,11 @@ architecture behaviour of syscon is -- CLKINFO contains the CLK frequency is HZ in the bottom 40 bits -- CTRL register bits - constant SYS_REG_CTRL_BITS : positive := 3; + constant SYS_REG_CTRL_BITS : positive := 4; constant SYS_REG_CTRL_DRAM_AT_0 : integer := 0; constant SYS_REG_CTRL_CORE_RESET : integer := 1; constant SYS_REG_CTRL_SOC_RESET : integer := 2; + constant SYS_REG_CTRL_ALT_RESET : integer := 3; -- SPI Info register bits -- @@ -102,6 +104,7 @@ architecture behaviour of syscon is -- Ctrl register signal reg_ctrl : std_ulogic_vector(SYS_REG_CTRL_BITS-1 downto 0); signal reg_ctrl_out : std_ulogic_vector(63 downto 0); + signal ctrl_init_alt_reset : std_ulogic; -- Others signal reg_info : std_ulogic_vector(63 downto 0); @@ -128,11 +131,12 @@ architecture behaviour of syscon is -- Wishbone response latch signal wb_rsp : wb_io_slave_out; begin - -- Generated output signals dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); + alt_reset <= reg_ctrl(SYS_REG_CTRL_ALT_RESET); + -- Info register is hard wired info_has_uart <= '1' when HAS_UART else '0'; @@ -211,12 +215,16 @@ begin end if; end process; + -- Initial state + ctrl_init_alt_reset <= '1' when HAS_DRAM else '0'; + -- Register writes regs_write: process(clk) begin if rising_edge(clk) then if (rst) then - reg_ctrl <= (others => '0'); + reg_ctrl <= (SYS_REG_CTRL_ALT_RESET => ctrl_init_alt_reset, + others => '0'); else if wishbone_in.cyc and wishbone_in.stb and wishbone_in.we then -- Change this if CTRL ever has more than 32 bits From 1874cad5b70309f5a690527661bc1ad2b0276e08 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 27 Oct 2022 11:20:27 +0800 Subject: [PATCH 3/6] litedram: only run sdram init at first boot Subsequent boots can skip the dram configuration, it will already be in a usable state. Signed-off-by: Matt Johnston --- litedram/gen-src/sdram_init/main.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index b42502d..2d99410 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -285,10 +285,14 @@ uint64_t main(void) try_flash = true; } printf("\n"); - if (ftr & SYS_REG_INFO_HAS_DRAM) { + if (ftr & SYS_REG_INFO_HAS_DRAM && !ddrctrl_init_done_read()) { printf("LiteDRAM built from LiteX %s\n", LITEX_GIT_SHA1); sdram_init(); } + + val = readq(SYSCON_BASE + SYS_REG_CTRL); + writeq(val & ~SYS_REG_CTRL_ALT_RESET, SYSCON_BASE + SYS_REG_CTRL); + if (ftr & SYS_REG_INFO_HAS_BRAM) { printf("Booting from BRAM...\n"); return 0; From 89d8cf0788ab18cd16c896fb15468cce11fa7cd0 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 27 Oct 2022 13:02:05 +0800 Subject: [PATCH 4/6] Regenerate litedram with updated sdram init Using litedram c770dd62edc281c370f9e2c694fe4ac1525a0b4a litex e570b612b2a9d8f8d2002d79497bda0dc35b936a Signed-off-by: Matt Johnston --- .../acorn-cle-215/litedram_core.init | 1935 +- .../generated/acorn-cle-215/litedram_core.v | 26386 +++++++------- litedram/generated/arty/litedram_core.init | 1935 +- litedram/generated/arty/litedram_core.v | 26382 +++++++------- .../generated/genesys2/litedram_core.init | 2537 +- litedram/generated/genesys2/litedram_core.v | 30260 ++++++++-------- .../generated/nexys-video/litedram_core.init | 1935 +- .../generated/nexys-video/litedram_core.v | 26382 +++++++------- .../orangecrab-85-0.2/litedram_core.init | 1917 +- .../orangecrab-85-0.2/litedram_core.v | 22103 +++++------ litedram/generated/sim/litedram_core.init | 1158 +- litedram/generated/sim/litedram_core.v | 25946 ++++++------- .../generated/wukong-v2/litedram_core.init | 1935 +- litedram/generated/wukong-v2/litedram_core.v | 26382 +++++++------- 14 files changed, 99377 insertions(+), 97816 deletions(-) diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init index 9006b18..61e54f3 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.init +++ b/litedram/generated/acorn-cle-215/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842adc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048002135 -386100207c7f1b78 -6000000048001b4d +6000000048002139 +7fc3f3787c7f1b78 +6000000048001b59 7fe3fb78382100b0 -000000004800283c -0000018001000000 +000000004800285c +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842ad283c4c0001 +3842ad203c4c0001 7d6000267c0802a6 -9161000848002775 -48001b49f821fed1 +9161000848002799 +48001b55f821fed1 3c62ffff60000000 -4bffff4138637af0 +4bffff3938637b18 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b10 -3c62ffff4bffff1d -38637b307bff0020 -7c0004ac4bffff0d +63ff000838637b38 +3c62ffff4bffff15 +38637b587bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b48 +4bfffee938637b70 4d80000073e90002 3c62ffff41820010 -4bfffed938637b50 +4bfffed138637b78 4e00000073e90004 3c62ffff41820010 -4bfffec138637b58 +4bfffeb938637b80 4d00000073e90008 3c62ffff41820010 -4bfffea938637b60 +4bfffea138637b88 4182001073e90010 -38637b703c62ffff -73ff01004bfffe95 +38637b983c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637b80 -3b7b7b883f62ffff -4bfffe717f63db78 +4bfffe7938637ba8 +3b7b7bb03f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637b90 +4bfffe4138637bb8 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637ba8 +4bfffe1938637bd0 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637bc07884b282 -3d20c0004bfffdfd +38637be87884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637bd87c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c00 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637bf8 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c2057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c185784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c4057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c38 -7f40efaa7c0004ac +4bfffc8138637c60 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c503c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637c783c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637c607bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637c803c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c48 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637d90 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048001865 -38637db03c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847c983c62ffff -4bfffb0938637ca8 -6000000048000c3d -3c82ffff4bffff54 -38847c983c62ffff -4bfffae938637ca8 -6000000048000c1d -3c62ffff4bffff80 -4bfffad138637cc8 -38a000403c9ef000 -3861007078840020 -60000000480017ed -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637c883be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637cb838847ca8 +48000ccd4bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637cd8 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637c703c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637cf0 +38a000403c9af000 +7884002038610070 +6000000048001819 +e92100703d400002 614a464c3c62ffff -794a83e438637ce0 +794a83e438637d08 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d003c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d283c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637d6088810070 +38637d8888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d183ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637db8 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048001771 +38637dd83c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d403b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d40 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637d68 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480022507d638120 -38a000383c9ef000 -386100b078840020 -6000000048001705 +480022547d638120 +38a000383c9ff000 +788400207f23cb78 +60000000480016f1 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -60000000480016bd -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +60000000480016a9 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,7 +742,7 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -3842a6e83c4c0001 +3842a6c03c4c0001 4182006828030002 4182003028030003 4082007c28030001 @@ -815,26 +820,26 @@ ebe100b8eb8100c0 614a100c39200000 000000004bffffd4 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -7c0802a63842a444 -60e700033ce08020 -78e7002039200000 -f821ffa148001e99 -3941001f7c7d1b78 -7d0a4a143bc10020 -7d4903a639400004 +7c0802a63842a41c +f821ffa148001ead +392000003cc08020 +7c7d1b7860c60003 +78c6002038e1001f +3bc1002039400004 +7d4903a67d074a14 788407e0788af862 -7c8438387c8400d0 +7c8430387c8400d0 7d4453787c8a5278 4200ffe49d480001 2829001039290004 -3d40c8004082ffc4 +3d40c8004082ffc8 614a100c39200000 7c0004ac794a0020 3d40c8007d20572a @@ -843,11 +848,11 @@ f821ffa148001e99 4bfffc8938600009 4bffff2d3860000f 3cc0c8003d20c800 -60c6107461291014 -792900207fcaf378 +612910147fcaf378 +7929002060c61074 38a0000478c60020 -7ca903a638eaffff -8ca7000139000000 +3900000038eaffff +8ca700017ca903a6 7ca82b787905400c 7c0004ac4200fff4 392900187ca04f2a @@ -862,7 +867,7 @@ f821ffa148001e99 57e3063e38800017 4bfffc2d3fe0c800 3860000f63ff082c -7bff00204bfffe89 +4bfffe857bff0020 7c60fe2a7c0004ac 4bfffe055463063e 7c60fe2a7c0004ac @@ -879,17 +884,17 @@ f821ffa148001e99 3be100303860000b 3860000f4bfffb65 3ce0c8004bfffe09 -60e710183d60c800 -3c6033333c005555 -616b10783d800f0f -78e7002038800000 -211d000138a00000 -6063333360005555 -796b0020618c0f0f +3c0055553d60c800 +3d800f0f3c603333 +38a0000038800000 +60e71018211d0001 +60005555616b1078 +618c0f0f60633333 +796b002078e70020 7d203e2a7c0004ac 792900203ba00004 -38c100347fa903a6 -9d26ffff39400004 +3940000438c10034 +9d26ffff7fa903a6 7929c202394affff 392000044200fff4 7d2452147d2903a6 @@ -906,18 +911,18 @@ f821ffa148001e99 552906be7d293214 394a00017ca54a14 38e700184200ff9c -7c2758003bde0004 -4082ff5438840004 +388400043bde0004 +4082ff547c275800 78a3002038210060 -0000000048001c48 +0000000048001c4c 0000038001000000 -3842a1783c4c0001 -48001bcd7c0802a6 -7c7f1b78f821ff61 -4bfffb213b800000 +3842a1503c4c0001 +48001bd17c0802a6 +3b800000f821ff61 +4bfffb217c7f1b78 7fe3fb783880002a -388000544bfffd15 -7c7e1b783bbc0001 +4bfffd113bbc0001 +7c7e1b7838800054 4bfffd017fe3fb78 2c0300007c63f214 2c1d00204182001c @@ -925,9 +930,9 @@ f821ffa148001e99 4bfffb2d7fbceb78 7f9de3784bffffc0 3b5c00047fe3fb78 -7fe3fb784bfffb19 -4bfffb0d7f5bd378 -3bc0ffff7fe3fb78 +4bfffb153bc0ffff +7f5bd3787fe3fb78 +7fe3fb784bfffb09 7fe3fb784bfffb01 3880002a4bfffaf9 4bfffca17fe3fb78 @@ -941,590 +946,587 @@ f821ffa148001e99 4bffffb84bfffab1 3ba0ffff3b800020 2c1effff4bffff80 -2c1a001f4082001c -418100083bc00000 -3b9c000523da001f -2c1dffff7fdee214 -3c62ffff4082001c -4bfff2a138637dc8 -382100a060000000 -7cbdf05048001b00 -7ca50e707c9df214 -789cfee27ca50194 -7ca507b43c62ffff -38637dd87f84e378 -4bfff2693bc00008 -7fe3fb7860000000 -4bfff9d93ba00000 -4bfffb9538600064 -4082003c7c1ce800 -7fe3fb783880002a -388000544bfffbbd -7fe3fb787c7d1b78 -7c63ea144bfffbad -4182ff882c030000 -2c1e00003bdeffff -4bffff784082ffb4 -3bbd00017fe3fb78 -386000644bfff9d1 -4bffffac4bfffb41 -0100000000000000 -3c4c000100000780 -3d20c80038429fa4 -7929002061291000 -7d404e2a7c0004ac -4d820020280a000e -3940000e7c0802a6 -f821ffa1f8010010 -7d404f2a7c0004ac +23da001f40820018 +3b9c00052c1a001f +7fdee2147fc0f05e +4082001c2c1dffff 38637df03c62ffff -600000004bfff1a5 -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -3d20c80038429f3c -7929002061291000 -7d404e2a7c0004ac -4d820020280a0001 -394000017c0802a6 +600000004bfff27d +48001b08382100a0 +7c9df2147cbdf050 +3bc000083c62ffff +7ca501947ca50e70 +38637e00789cfee2 +7ca507b47f84e378 +600000004bfff245 +3ba000007fe3fb78 +386000644bfff9dd +7c1ce8004bfffb99 +3880002a4082003c +4bfffbc17fe3fb78 +7c7d1b7838800054 +4bfffbb17fe3fb78 +2c0300007c63ea14 +3bdeffff4182ff88 +4082ffb42c1e0000 +7fe3fb784bffff78 +4bfff9d53bbd0001 +4bfffb4538600064 +000000004bffffac +0000078001000000 +38429f803c4c0001 +612910003d20c800 +7c0004ac79290020 +280a000e7d404e2a +7c0802a64d820020 f821ffa1f8010010 -7d404f2a7c0004ac -38637e183c62ffff -600000004bfff13d -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429ed4 -39297e403d22ffff -f821ff01480018f5 -3f00c8003f80c800 -3e62ffff3e82ffff -639c08043f22ffff -3e42ffff63180820 -3b4000013ba00000 -3ae00000f9210060 -3a737e583a947e50 -7b9c00203b397b88 -3a527e607b180020 -7fb0eb787ba307e0 -7f56e8304bfff8c5 +7c0004ac3940000e +3c62ffff7d404f2a +4bfff18138637e18 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429f183c4c0001 +612910003d20c800 +7c0004ac79290020 +280a00017d404e2a +7c0802a64d820020 +f821ffa1f8010010 +7c0004ac39400001 +3c62ffff7d404f2a +4bfff11938637e40 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429eb03c4c0001 +480019057c0802a6 +3f80c800f821ff01 +3ba000003f00c800 +3ae000003b400001 +3e82ffff3d22ffff +3f22ffff3e62ffff +63180820639c0804 +39297e683e42ffff +3a737e803a947e78 +7b9c00203b397bb0 +3a527e887b180020 +7ba307e0f9210060 +7f56e8307fb0eb78 3a2000003be00000 7fbe07b439e00000 -7de507b4e8610060 -39c000207fc4f378 -4bfff0813b600000 -7fc3f37860000000 -3880002a4bfff7f5 -4bfff9e97fc3f378 -7c751b7838800054 -4bfff9d97fc3f378 -7c6400347c63aa14 -7e83a37821230080 -548a60265484d97e -7d2952147c8407b4 -4bfff0317f7b4a14 +e86100604bfff8b5 +7fc4f3787de507b4 +3b60000039c00020 +600000004bfff05d +4bfff7f97fc3f378 +7fc3f3783880002a +388000544bfff9ed +7fc3f3787c751b78 +7c63aa144bfff9dd +212300807c640034 +5484d97e7e83a378 +7c8407b4548a6026 +7f7b4a147d295214 +600000004bfff00d +4bfff7f57fc3f378 +4082ffac35ceffff +4bffeff17e639b78 7fc3f37860000000 -35ceffff4bfff7f1 -7e639b784082ffac -600000004bfff015 -4bfffc557fc3f378 -4bfff0017f23cb78 -7c11d84060000000 -7dff7b784080000c -2c0f00077f71db78 -7c0004ac4182002c -7c0004ac7ec0e72a -7c0004ac7f40c72a -39ef00017ee0e72a -3ba000014bffff30 -7fe507b44bffff08 -7e4393787fc4f378 -4bffefa97bff0020 -7a0307e060000000 -393f00014bfff7b5 -420000287d2903a6 -4bfffbd57fc3f378 -4bffef817f23cb78 -2c1d000060000000 -382101004182ffb4 -7c0004ac480017ac -7c0004ac7ec0e72a -7c0004ac7f40c72a -4bffffc07ee0e72a -0100000000000000 -3c4c000100001280 -7c0802a638429cfc -f821ffa1f8010010 -386000004bfffd4d -386000004bfff6a5 -386000014bfff735 -386000014bfff695 -3c62ffff4bfff725 -4bffef0138637e78 -4bfffde960000000 -382100604bfffd7d -e801001038600001 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429c8c -6129082c3d20c800 -480016cd79290020 -3b000002f821ff51 -7f004f2a7c0004ac -3b2000033d20c800 -7929002061290830 -7f204f2a7c0004ac -3c62ffff3fc0c800 -38637e883c804000 -4bffee7963de0800 -3b80000160000000 -7bde00204bfffc8d -7f80f72a7c0004ac -3be00000386003e8 -7c0004ac4bfff799 -386003e87fe0f72a -4bfff7853f60c800 -7c0004ac7b7b0020 -3f40c8007fe0df2a -7b5a0020635a0004 -7fe0d72a7c0004ac -63bd100c3fa0c800 -7c0004ac7bbd0020 -3fc0c8007fe0ef2a -7bde002063de1010 +7f23cb784bfffc59 +600000004bffefdd +4080000c7c11d840 +7f71db787dff7b78 +4182002c2c0f0007 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +4bffff3039ef0001 +4bffff083ba00001 +7fc4f3787fe507b4 +7bff00207e439378 +600000004bffef85 +4bfff7b97a0307e0 +7d2903a6393f0001 +7fc3f37842000028 +7f23cb784bfffbd9 +600000004bffef5d +4182ffb42c1d0000 +480017b438210100 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +000000004bffffc0 +0000128001000000 +38429cd83c4c0001 +f80100107c0802a6 +4bfffd4df821ffa1 +4bfff6a938600000 +4bfff73938600000 +4bfff69938600001 +4bfff72938600001 +38637ea03c62ffff +600000004bffeedd +4bfffd7d4bfffde9 +3860000138210060 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429c683c4c0001 +480016e17c0802a6 +3d20c800f821ff51 +6129082c3b000002 +7c0004ac79290020 +3d20c8007f004f2a +612908303b200003 +7c0004ac79290020 +3fc0c8007f204f2a +3c8040003c62ffff +38637eb03b800001 +4bffee5163de0800 +7bde002060000000 +7c0004ac4bfffc89 +386003e87f80f72a +4bfff79d3be00000 7fe0f72a7c0004ac -3920000c3ee0c800 -7af7002062f71000 -7d20bf2a7c0004ac -6063c35038600000 -7c0004ac4bfff719 -7c0004ac7fe0ef2a -3920000e7fe0f72a -7d20bf2a7c0004ac -4bfff6f538602710 -7c0004ac39200200 -7c0004ac7d20ef2a -3860000f7f00f72a -7c0004ac4bfff42d -7c0004ac7fe0ef2a -3860000f7f20f72a -392000064bfff415 +3f60c800386003e8 +7b7b00204bfff789 +7fe0df2a7c0004ac +635a00043f40c800 +7c0004ac7b5a0020 +3fa0c8007fe0d72a +7bbd002063bd100c +7fe0ef2a7c0004ac +63de10103fc0c800 +7c0004ac7bde0020 +3ee0c8007fe0f72a +62f710003920000c +7c0004ac7af70020 +386000007d20bf2a +4bfff71d6063c350 +7fe0ef2a7c0004ac +7fe0f72a7c0004ac +7c0004ac3920000e +386027107d20bf2a +392002004bfff6f9 7d20ef2a7c0004ac -7f80f72a7c0004ac -4bfff3f93860000f -7c0004ac39200930 +7f00f72a7c0004ac +4bfff4313860000f +7fe0ef2a7c0004ac +7f20f72a7c0004ac +4bfff4193860000f +7c0004ac39200006 7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff3dd -392004004bfff681 +3860000f7f80f72a +392009304bfff3fd 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff3b938600003 -4bfff65d386000c8 -4bfffb994bfffddd -3c6040003c800020 -60000000480006e9 -408200242c030000 -7c0004ac7c691b78 -7c0004ac7f80d72a -382100b07f80df2a -4800153c7d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bfff3e13860000f +4bfff685386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff3bd +4bfffddd4bfff661 +3c8000204bfffb99 +480006e13c604000 +2c03000060000000 +7c691b7840820024 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000980 -7c0802a638429a5c -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffec7938637ea8 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637eb03c62ffff -600000004bffec3d -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ec07ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b4382100b0 +38c0000048001544 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000098001000000 +38429a383c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ed03c62ffff +600000004bffec55 +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ed0 -0100000000000000 -3c4c000100000080 -7c0802a63842998c -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffec1938637ed8 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637ee8 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ee078c60020 +38637ef87ca54b92 +000000004bffffa4 +0000008001000000 +384299683c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffeb9d -4bfffef97fe3fb78 -38637ef03c62ffff -600000004bffeb85 -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -384298e83c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffeb7938637f08 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffeb6138637f18 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384298c4 +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffeb59 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffeb09 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffeb3d42000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffeaed7fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384297d83c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187ef87bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637ef8 -3c62ffff4bfffde5 -4bffe9a138637b88 -4bffea0560000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a6384297b4 +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f20 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f20 +38637bb03c62ffff +600000004bffe97d +600000004bffe9e9 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f08 -3c62ffff4bfffd8d -4bffe94938637b88 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f08 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384296183c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f30 +38637bb03c62ffff +600000004bffe925 +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f307ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a6384295f4 +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f183c62ffff -4bffe8197cbc2b78 -3c62ffff60000000 -4092000c38637f30 -38637f403c62ffff -600000004bffe7fd -4bfffb597fc3f378 -38637f503c62ffff -600000004bffe7e5 -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f402e3b0000 +600000004bffe7f5 38637f583c62ffff -4bffe7617f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffe74938637f68 +3c62ffff4092000c +4bffe7d938637f68 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffe7c138637f78 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8005f57d3602a6 +7929002078ea0020 +639ce1003c62ffff +38637f807d295050 +7f9c4b927f9ee1d2 +600000004bffe73d +4bfffabd7f83e378 +38637f903c62ffff +600000004bffe725 +38637bb03c62ffff +600000004bffe715 +600000004bffe781 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4005f5 +3c62ffff79290020 +7d29e050614ae100 +7fde51d238637f98 +4bffe6797fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffe66138637f90 3c62ffff60000000 -4bffe73938637b88 -4bffe79d60000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f70 -600000004bffe69d -4bfff9f97fc3f378 -38637f683c62ffff -600000004bffe685 -38637b883c62ffff -600000004bffe675 -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384293e03c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffe65138637bb0 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384293c4 +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f807fc4f378 -600000004bffe5ed -4bfff9497fe3fb78 -38637f503c62ffff +7c641b787f9c205e +38637fa83c62ffff 600000004bffe5d5 +4bfff9557fe3fb78 +38637f783c62ffff +600000004bffe5bd 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffe58938637f90 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fa838800000 -600000004bffe55d -7be5f0823c62ffff -38637fc07fc4f378 -600000004bffe545 -38637fd83c62ffff -600000004bffe535 -3821008038600000 -48000d987c6307b4 -38637fe83c62ffff -600000004bffe515 -4bffffe038600001 -0100000000000000 -3c4c000100000480 -60000000384292b4 -6000000089228068 -2c09000039428060 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228060 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428060 -4e8000207d2057ea +4bffe57138637fb8 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fd0 +4bffe54978a5f082 +3c62ffff60000000 +7fc4f3787be5f082 +4bffe53138637fe8 +6000000060000000 +4bffe52138628000 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffe50138628010 +3860000160000000 +000000004bffffe0 +0000048001000000 +384292a03c4c0001 +6000000060000000 +3942808889228090 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e922808860000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94280885469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842922c -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384291cc -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428060 -9942806860000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942806060000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228068 -3920ff806108200c -7c0004ac79080020 -e92280607d2047aa -7d404faa7c0004ac -794ac202e9228060 -7c0004ac39290004 -e92280607d404faa -3929000c39400003 +384292183c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384291b83c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f942808860000000 +6000000039400000 +3d40001c99428090 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf9428088 +7d495392614a2000 +600000004182ffa0 +9922809039200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace9228088 +e92280887d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228060 +39400003e9228088 +7c0004ac3929000c +e92280887d404faa +7c0004ac39290010 +e92280887d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228060 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 -0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +000000004e800020 +0000000000000000 +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428e94 -f821ffa1480008e9 +7c0802a638428e84 +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1536,36 +1538,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428dc4 -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428db4 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428d483c4c0001 -3d22ffff7c0802a6 -2b860010e9297ff8 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428d383c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922800060000000 +2b8600107caa2b78 +f9210020e9228020 +e922802860000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -1573,253 +1575,256 @@ e922800060000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428c54 -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b7488 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428c483c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b7494 +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028018 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c676443cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028040 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a7654 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942801860000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280187aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028040 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028040 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2801038610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280387de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1870,15 +1875,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v index bea0247..22c0e22 100644 --- a/litedram/generated/acorn-cle-215/litedram_core.v +++ b/litedram/generated/acorn-cle-215/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:07:00 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:23 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [15:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [25:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [15:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [25:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -69,1941 +69,2065 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; -wire iodelay_clk; -wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [15:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [15:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [15:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [15:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [15:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [15:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [15:0] litedramcore_master_p0_address = 16'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [15:0] litedramcore_master_p1_address = 16'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [15:0] litedramcore_master_p2_address = 16'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [15:0] litedramcore_master_p3_address = 16'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [15:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [15:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [22:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [22:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [22:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [22:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [22:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [22:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [22:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [22:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [15:0] litedramcore_dfi_p0_address = 16'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [15:0] litedramcore_dfi_p1_address = 16'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [15:0] litedramcore_dfi_p2_address = 16'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [15:0] litedramcore_dfi_p3_address = 16'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [15:0] litedramcore_cmd_payload_a = 16'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [6:0] litedramcore_sequencer_counter = 7'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [22:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine0_row = 16'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [22:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine1_row = 16'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [22:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine2_row = 16'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [22:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine3_row = 16'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [22:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine4_row = 16'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [22:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine5_row = 16'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [22:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine6_row = 16'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [22:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [22:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [22:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0; -reg [15:0] litedramcore_bankmachine7_row = 16'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [15:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [15:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [15:0] litedramcore_nop_a = 16'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [25:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [15:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [15:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [15:0] rhs_array_muxed1 = 16'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [15:0] rhs_array_muxed7 = 16'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [22:0] rhs_array_muxed12 = 23'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [22:0] rhs_array_muxed15 = 23'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [22:0] rhs_array_muxed18 = 23'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [22:0] rhs_array_muxed21 = 23'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [22:0] rhs_array_muxed24 = 23'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [22:0] rhs_array_muxed27 = 23'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [22:0] rhs_array_muxed30 = 23'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [22:0] rhs_array_muxed33 = 23'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [15:0] array_muxed1 = 16'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [15:0] array_muxed8 = 16'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [15:0] array_muxed15 = 16'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [15:0] array_muxed22 = 16'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg rst_1 = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire reset; +reg power_down = 1'd0; +wire locked; +wire clkin; +wire clkout0; +wire clkout_buf0; +wire clkout1; +wire clkout_buf1; +wire clkout2; +wire clkout_buf2; +wire clkout3; +wire clkout_buf3; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +reg a7ddrphy_wlevel_strobe_re = 1'd0; +wire a7ddrphy_wlevel_strobe_r; +reg a7ddrphy_wlevel_strobe_we = 1'd0; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg a7ddrphy_rdly_dq_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_r; +reg a7ddrphy_rdly_dq_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_inc_re = 1'd0; +wire a7ddrphy_rdly_dq_inc_r; +reg a7ddrphy_rdly_dq_inc_we = 1'd0; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_r; +reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_r; +reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [15:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [15:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [15:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [15:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +wire [2:0] a7ddrphy_pads_ba; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip21; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip31; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [15:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [15:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [15:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [15:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [15:0] litedramcore_master_p0_address = 16'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [15:0] litedramcore_master_p1_address = 16'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [15:0] litedramcore_master_p2_address = 16'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [15:0] litedramcore_master_p3_address = 16'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +wire [15:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [15:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [15:0] litedramcore_csr_dfi_p2_address; +wire [2:0] litedramcore_csr_dfi_p2_bank; +reg litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg litedramcore_csr_dfi_p2_we_n = 1'd1; +wire litedramcore_csr_dfi_p2_cke; +wire litedramcore_csr_dfi_p2_odt; +wire litedramcore_csr_dfi_p2_reset_n; +reg litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p2_wrdata; +wire litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; +wire litedramcore_csr_dfi_p2_rddata_en; +reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; +reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [15:0] litedramcore_csr_dfi_p3_address; +wire [2:0] litedramcore_csr_dfi_p3_bank; +reg litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg litedramcore_csr_dfi_p3_we_n = 1'd1; +wire litedramcore_csr_dfi_p3_cke; +wire litedramcore_csr_dfi_p3_odt; +wire litedramcore_csr_dfi_p3_reset_n; +reg litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p3_wrdata; +wire litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; +wire litedramcore_csr_dfi_p3_rddata_en; +reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; +reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0; +reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; +reg litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg litedramcore_ext_dfi_p2_we_n = 1'd1; +reg litedramcore_ext_dfi_p2_cke = 1'd0; +reg litedramcore_ext_dfi_p2_odt = 1'd0; +reg litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; +reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0; +reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; +reg litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg litedramcore_ext_dfi_p3_we_n = 1'd1; +reg litedramcore_ext_dfi_p3_cke = 1'd0; +reg litedramcore_ext_dfi_p3_odt = 1'd0; +reg litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; +reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_phaseinjector2_csrfield_cs; +wire litedramcore_phaseinjector2_csrfield_we; +wire litedramcore_phaseinjector2_csrfield_cas; +wire litedramcore_phaseinjector2_csrfield_ras; +wire litedramcore_phaseinjector2_csrfield_wren; +wire litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +reg litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_r; +reg litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; +wire litedramcore_phaseinjector2_rddata_we; +reg litedramcore_phaseinjector2_rddata_re = 1'd0; +wire litedramcore_phaseinjector3_csrfield_cs; +wire litedramcore_phaseinjector3_csrfield_we; +wire litedramcore_phaseinjector3_csrfield_cas; +wire litedramcore_phaseinjector3_csrfield_ras; +wire litedramcore_phaseinjector3_csrfield_wren; +wire litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +reg litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_r; +reg litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; +wire litedramcore_phaseinjector3_rddata_we; +reg litedramcore_phaseinjector3_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [22:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [22:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [22:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [22:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [22:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [22:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [22:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [22:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [15:0] litedramcore_dfi_p0_address = 16'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [15:0] litedramcore_dfi_p1_address = 16'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [15:0] litedramcore_dfi_p2_address = 16'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [15:0] litedramcore_dfi_p3_address = 16'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [15:0] litedramcore_cmd_payload_a = 16'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [6:0] litedramcore_sequencer_counter = 7'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [22:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [22:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [22:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [25:0] litedramcore_bankmachine0_syncfifo0_din; +wire [25:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [25:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [25:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [22:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine0_row = 16'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [22:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [22:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [22:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [25:0] litedramcore_bankmachine1_syncfifo1_din; +wire [25:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [25:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [25:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [22:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine1_row = 16'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [22:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [22:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [22:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [25:0] litedramcore_bankmachine2_syncfifo2_din; +wire [25:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [25:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [25:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [22:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine2_row = 16'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [22:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [22:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [22:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [25:0] litedramcore_bankmachine3_syncfifo3_din; +wire [25:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [25:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [25:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [22:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine3_row = 16'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [22:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [22:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [22:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [25:0] litedramcore_bankmachine4_syncfifo4_din; +wire [25:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [25:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [25:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [22:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine4_row = 16'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [22:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [22:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [22:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [25:0] litedramcore_bankmachine5_syncfifo5_din; +wire [25:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [25:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [25:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [22:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine5_row = 16'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [22:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [22:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [22:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [25:0] litedramcore_bankmachine6_syncfifo6_din; +wire [25:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [25:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [25:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [22:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine6_row = 16'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [22:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [22:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [22:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [25:0] litedramcore_bankmachine7_syncfifo7_din; +wire [25:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [25:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [25:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [25:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [22:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [22:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [22:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [22:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [22:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [22:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0; +reg [15:0] litedramcore_bankmachine7_row = 16'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +wire [1:0] litedramcore_rdcmdphase; +wire [1:0] litedramcore_wrcmdphase; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [15:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [15:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [15:0] litedramcore_nop_a = 16'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [25:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_rst0_re = 1'd0; +wire csrbank1_rst0_r; +reg csrbank1_rst0_we = 1'd0; +wire csrbank1_rst0_w; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_r; +reg csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_w; +reg csrbank1_wlevel_en0_re = 1'd0; +wire csrbank1_wlevel_en0_r; +reg csrbank1_wlevel_en0_we = 1'd0; +wire csrbank1_wlevel_en0_w; +reg csrbank1_rdphase0_re = 1'd0; +wire [1:0] csrbank1_rdphase0_r; +reg csrbank1_rdphase0_we = 1'd0; +wire [1:0] csrbank1_rdphase0_w; +reg csrbank1_wrphase0_re = 1'd0; +wire [1:0] csrbank1_wrphase0_r; +reg csrbank1_wrphase0_we = 1'd0; +wire [1:0] csrbank1_wrphase0_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [15:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [15:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +reg csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [15:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [15:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +reg csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_w; +reg csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_r; +reg csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_w; +reg csrbank2_dfii_pi2_address0_re = 1'd0; +wire [15:0] csrbank2_dfii_pi2_address0_r; +reg csrbank2_dfii_pi2_address0_we = 1'd0; +wire [15:0] csrbank2_dfii_pi2_address0_w; +reg csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +reg csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; +reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +reg csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +reg csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_w; +reg csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_r; +reg csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_w; +reg csrbank2_dfii_pi3_address0_re = 1'd0; +wire [15:0] csrbank2_dfii_pi3_address0_r; +reg csrbank2_dfii_pi3_address0_we = 1'd0; +wire [15:0] csrbank2_dfii_pi3_address0_w; +reg csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +reg csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; +reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +reg csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +reg csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_reset0; +wire litedramcore_reset1; +wire litedramcore_reset2; +wire litedramcore_reset3; +wire litedramcore_reset4; +wire litedramcore_reset5; +wire litedramcore_reset6; +wire litedramcore_reset7; +wire litedramcore_pll_fb; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [15:0] rhs_array_muxed1 = 16'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [15:0] rhs_array_muxed7 = 16'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [22:0] rhs_array_muxed12 = 23'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [22:0] rhs_array_muxed15 = 23'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [22:0] rhs_array_muxed18 = 23'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [22:0] rhs_array_muxed21 = 23'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [22:0] rhs_array_muxed24 = 23'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [22:0] rhs_array_muxed27 = 23'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [22:0] rhs_array_muxed30 = 23'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [22:0] rhs_array_muxed33 = 23'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [15:0] array_muxed1 = 16'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [15:0] array_muxed8 = 16'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [15:0] array_muxed15 = 16'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [15:0] array_muxed22 = 16'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2047,144 +2171,144 @@ assign ddram_ba = a7ddrphy_pads_ba; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); @@ -2192,1074 +2316,1074 @@ assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7d assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) - 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) - 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) - 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) - 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) - 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) - 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) - 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) - 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) - 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) - 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) - 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) - 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) - 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) - 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) - 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) - 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) - 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) - 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) - 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) - 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) - 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) - 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) - 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) - 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) - 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) - 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) - 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) - 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) - 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) - 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) - 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) - 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) - 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) - 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) - 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) - 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -3390,892 +3514,892 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; - end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; - end - end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; - end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; - end - end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end - end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end - end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end - end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end - end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; - end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; - end - end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; - end - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; - end - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; - end - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; - end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; - end - end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; - end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; - end - end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; - end - end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; - end - end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; - end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; - end - end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end - end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; - end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; - end - end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; - end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; - end - end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; - end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; - end - end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; - end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; - end - end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; - end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; - end - end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; - end - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; - end - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; - end - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - litedramcore_master_p3_address <= 16'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; - end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; - end - end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; - end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; - end - end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; - end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; - end - end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; - end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; - end - end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end + end else begin + litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end + end else begin + litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end + end else begin + litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + end else begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + end + end else begin + litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + end + end else begin + litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + end else begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + end + end else begin + litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + end + end else begin + litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + end + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + end + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + end + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 16'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 16'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address <= 16'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + end else begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; + end + end else begin + litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + end else begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + end + end else begin + litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end + end else begin + litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end + end else begin + litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end + end else begin + litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end + end else begin + litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + end else begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + end + end else begin + litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + end else begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + end + end else begin + litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + end + end else begin + litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + end else begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + end + end else begin + litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + end + end else begin + litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address <= 16'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end + end else begin + litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end + end else begin + litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end + end else begin + litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end + end else begin + litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -4290,36 +4414,36 @@ assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -4328,36 +4452,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -4366,36 +4490,36 @@ assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_ assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); - end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + end else begin + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); - end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + end else begin + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); - end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + end else begin + litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; @@ -4404,36 +4528,36 @@ assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_ assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); - end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + end else begin + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); - end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + end else begin + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); - end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + end else begin + litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; @@ -4511,4590 +4635,4686 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[22:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[22:7] != litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[22:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[22:7] != litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[22:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[22:7] != litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[22:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[22:7] != litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[22:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[22:7] != litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[22:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[22:7] != litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[22:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[22:7] != litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[22:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 16'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 16'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[22:7] != litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase end assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); @@ -9127,15 +9347,15 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9145,106 +9365,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9254,22 +9474,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -9286,473 +9506,473 @@ assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -9798,26 +10018,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -9829,129 +10049,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -9967,201 +10187,201 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); - end + csrbank1_rst0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; - end + csrbank1_rst0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_re <= interface1_bank_bus_we; + end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); - end + csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; - end + csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; - end + csrbank1_wlevel_en0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); - end + csrbank1_wlevel_en0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; - end + a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; - end + csrbank1_rdphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_rdphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_wrphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; - end + csrbank1_wrphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_re <= interface1_bank_bus_we; + end end assign csrbank1_rst0_w = a7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10172,328 +10392,328 @@ assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -10563,1194 +10783,1194 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 16'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 16'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 23'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 23'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 23'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 23'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 16'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 16'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 23'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 23'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 23'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 23'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 23'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 23'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 23'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 23'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 16'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 16'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 16'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 16'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 23'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 23'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 23'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 23'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 16'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 16'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 16'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 16'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); @@ -11763,2132 +11983,2132 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); - end else begin - ic_reset <= 1'd0; - end - if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; - end + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); + end else begin + ic_reset <= 1'd0; + end + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; + end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; - end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; - end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; - end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; - end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; - end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; - end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; - end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; - end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; - end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; - end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; - end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; - end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; - end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; - end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; - end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; - end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; - end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; - end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; - end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; - end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; - end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; - end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; - end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; - end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; - end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; - end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; - end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; - end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; - end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; - end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; - end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; - end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; - end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; - end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; - end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; - end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; - end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 10'd781; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 7'd73)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 7'd73)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; - end - endcase - end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; - end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; - end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; - end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; - end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; - end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; - end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; - end - 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; - end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r; - end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; - end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; - end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; - end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r; - end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; - end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; - end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; - if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 16'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 16'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 16'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 16'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 16'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 7'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine0_row <= 16'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine1_row <= 16'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine2_row <= 16'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine3_row <= 16'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine4_row <= 16'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine5_row <= 16'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine6_row <= 16'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 23'd0; - litedramcore_bankmachine7_row <= 16'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if (litedramcore_csr_dfi_p2_rddata_valid) begin + litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + end + if (litedramcore_csr_dfi_p3_rddata_valid) begin + litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 7'd73)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 7'd73)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[22:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_rst0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + end + endcase + end + if (csrbank1_rst0_re) begin + a7ddrphy_rst_storage <= csrbank1_rst0_r; + end + a7ddrphy_rst_re <= csrbank1_rst0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + end + a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; + if (csrbank1_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + end + a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; + litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + if (sys_rst) begin + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 32'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 32'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_rddata_status <= 32'd0; + litedramcore_phaseinjector2_rddata_re <= 1'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_rddata_status <= 32'd0; + litedramcore_phaseinjector3_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 16'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 16'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 16'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 16'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 16'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 7'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine0_row <= 16'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine1_row <= 16'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine2_row <= 16'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine3_row <= 16'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine4_row <= 16'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine5_row <= 16'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine6_row <= 16'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0; + litedramcore_bankmachine7_row <= 16'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -15855,14 +16075,14 @@ IOBUF IOBUF_15( reg [25:0] storage[0:15]; reg [25:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -15873,14 +16093,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [25:0] storage_1[0:15]; reg [25:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -15891,14 +16111,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [25:0] storage_2[0:15]; reg [25:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -15909,14 +16129,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [25:0] storage_3[0:15]; reg [25:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -15927,14 +16147,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [25:0] storage_4[0:15]; reg [25:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -15945,14 +16165,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [25:0] storage_5[0:15]; reg [25:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -15963,14 +16183,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [25:0] storage_6[0:15]; reg [25:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -15981,14 +16201,14 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [25:0] storage_7[0:15]; reg [25:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( @@ -16082,7 +16302,8 @@ PLLE2_ADV #( .LOCKED(locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), @@ -16092,7 +16313,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), @@ -16102,7 +16324,8 @@ PLLE2_ADV #( .Q(iodelay_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), @@ -16112,7 +16335,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), @@ -16122,7 +16346,8 @@ PLLE2_ADV #( .Q(sys_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), @@ -16132,7 +16357,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), @@ -16142,7 +16368,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), @@ -16152,7 +16379,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), @@ -16165,5 +16393,5 @@ PLLE2_ADV #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:07:00. +// Auto-Generated by LiteX on 2022-10-28 19:01:23. //------------------------------------------------------------------------------ diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 9006b18..61e54f3 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842adc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048002135 -386100207c7f1b78 -6000000048001b4d +6000000048002139 +7fc3f3787c7f1b78 +6000000048001b59 7fe3fb78382100b0 -000000004800283c -0000018001000000 +000000004800285c +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842ad283c4c0001 +3842ad203c4c0001 7d6000267c0802a6 -9161000848002775 -48001b49f821fed1 +9161000848002799 +48001b55f821fed1 3c62ffff60000000 -4bffff4138637af0 +4bffff3938637b18 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b10 -3c62ffff4bffff1d -38637b307bff0020 -7c0004ac4bffff0d +63ff000838637b38 +3c62ffff4bffff15 +38637b587bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b48 +4bfffee938637b70 4d80000073e90002 3c62ffff41820010 -4bfffed938637b50 +4bfffed138637b78 4e00000073e90004 3c62ffff41820010 -4bfffec138637b58 +4bfffeb938637b80 4d00000073e90008 3c62ffff41820010 -4bfffea938637b60 +4bfffea138637b88 4182001073e90010 -38637b703c62ffff -73ff01004bfffe95 +38637b983c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637b80 -3b7b7b883f62ffff -4bfffe717f63db78 +4bfffe7938637ba8 +3b7b7bb03f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637b90 +4bfffe4138637bb8 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637ba8 +4bfffe1938637bd0 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637bc07884b282 -3d20c0004bfffdfd +38637be87884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637bd87c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c00 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637bf8 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c2057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c185784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c4057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c38 -7f40efaa7c0004ac +4bfffc8138637c60 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c503c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637c783c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637c607bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637c803c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c48 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637d90 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048001865 -38637db03c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847c983c62ffff -4bfffb0938637ca8 -6000000048000c3d -3c82ffff4bffff54 -38847c983c62ffff -4bfffae938637ca8 -6000000048000c1d -3c62ffff4bffff80 -4bfffad138637cc8 -38a000403c9ef000 -3861007078840020 -60000000480017ed -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637c883be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637cb838847ca8 +48000ccd4bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637cd8 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637c703c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637cf0 +38a000403c9af000 +7884002038610070 +6000000048001819 +e92100703d400002 614a464c3c62ffff -794a83e438637ce0 +794a83e438637d08 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d003c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d283c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637d6088810070 +38637d8888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d183ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637db8 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048001771 +38637dd83c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d403b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d40 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637d68 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480022507d638120 -38a000383c9ef000 -386100b078840020 -6000000048001705 +480022547d638120 +38a000383c9ff000 +788400207f23cb78 +60000000480016f1 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -60000000480016bd -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +60000000480016a9 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,7 +742,7 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -3842a6e83c4c0001 +3842a6c03c4c0001 4182006828030002 4182003028030003 4082007c28030001 @@ -815,26 +820,26 @@ ebe100b8eb8100c0 614a100c39200000 000000004bffffd4 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -7c0802a63842a444 -60e700033ce08020 -78e7002039200000 -f821ffa148001e99 -3941001f7c7d1b78 -7d0a4a143bc10020 -7d4903a639400004 +7c0802a63842a41c +f821ffa148001ead +392000003cc08020 +7c7d1b7860c60003 +78c6002038e1001f +3bc1002039400004 +7d4903a67d074a14 788407e0788af862 -7c8438387c8400d0 +7c8430387c8400d0 7d4453787c8a5278 4200ffe49d480001 2829001039290004 -3d40c8004082ffc4 +3d40c8004082ffc8 614a100c39200000 7c0004ac794a0020 3d40c8007d20572a @@ -843,11 +848,11 @@ f821ffa148001e99 4bfffc8938600009 4bffff2d3860000f 3cc0c8003d20c800 -60c6107461291014 -792900207fcaf378 +612910147fcaf378 +7929002060c61074 38a0000478c60020 -7ca903a638eaffff -8ca7000139000000 +3900000038eaffff +8ca700017ca903a6 7ca82b787905400c 7c0004ac4200fff4 392900187ca04f2a @@ -862,7 +867,7 @@ f821ffa148001e99 57e3063e38800017 4bfffc2d3fe0c800 3860000f63ff082c -7bff00204bfffe89 +4bfffe857bff0020 7c60fe2a7c0004ac 4bfffe055463063e 7c60fe2a7c0004ac @@ -879,17 +884,17 @@ f821ffa148001e99 3be100303860000b 3860000f4bfffb65 3ce0c8004bfffe09 -60e710183d60c800 -3c6033333c005555 -616b10783d800f0f -78e7002038800000 -211d000138a00000 -6063333360005555 -796b0020618c0f0f +3c0055553d60c800 +3d800f0f3c603333 +38a0000038800000 +60e71018211d0001 +60005555616b1078 +618c0f0f60633333 +796b002078e70020 7d203e2a7c0004ac 792900203ba00004 -38c100347fa903a6 -9d26ffff39400004 +3940000438c10034 +9d26ffff7fa903a6 7929c202394affff 392000044200fff4 7d2452147d2903a6 @@ -906,18 +911,18 @@ f821ffa148001e99 552906be7d293214 394a00017ca54a14 38e700184200ff9c -7c2758003bde0004 -4082ff5438840004 +388400043bde0004 +4082ff547c275800 78a3002038210060 -0000000048001c48 +0000000048001c4c 0000038001000000 -3842a1783c4c0001 -48001bcd7c0802a6 -7c7f1b78f821ff61 -4bfffb213b800000 +3842a1503c4c0001 +48001bd17c0802a6 +3b800000f821ff61 +4bfffb217c7f1b78 7fe3fb783880002a -388000544bfffd15 -7c7e1b783bbc0001 +4bfffd113bbc0001 +7c7e1b7838800054 4bfffd017fe3fb78 2c0300007c63f214 2c1d00204182001c @@ -925,9 +930,9 @@ f821ffa148001e99 4bfffb2d7fbceb78 7f9de3784bffffc0 3b5c00047fe3fb78 -7fe3fb784bfffb19 -4bfffb0d7f5bd378 -3bc0ffff7fe3fb78 +4bfffb153bc0ffff +7f5bd3787fe3fb78 +7fe3fb784bfffb09 7fe3fb784bfffb01 3880002a4bfffaf9 4bfffca17fe3fb78 @@ -941,590 +946,587 @@ f821ffa148001e99 4bffffb84bfffab1 3ba0ffff3b800020 2c1effff4bffff80 -2c1a001f4082001c -418100083bc00000 -3b9c000523da001f -2c1dffff7fdee214 -3c62ffff4082001c -4bfff2a138637dc8 -382100a060000000 -7cbdf05048001b00 -7ca50e707c9df214 -789cfee27ca50194 -7ca507b43c62ffff -38637dd87f84e378 -4bfff2693bc00008 -7fe3fb7860000000 -4bfff9d93ba00000 -4bfffb9538600064 -4082003c7c1ce800 -7fe3fb783880002a -388000544bfffbbd -7fe3fb787c7d1b78 -7c63ea144bfffbad -4182ff882c030000 -2c1e00003bdeffff -4bffff784082ffb4 -3bbd00017fe3fb78 -386000644bfff9d1 -4bffffac4bfffb41 -0100000000000000 -3c4c000100000780 -3d20c80038429fa4 -7929002061291000 -7d404e2a7c0004ac -4d820020280a000e -3940000e7c0802a6 -f821ffa1f8010010 -7d404f2a7c0004ac +23da001f40820018 +3b9c00052c1a001f +7fdee2147fc0f05e +4082001c2c1dffff 38637df03c62ffff -600000004bfff1a5 -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -3d20c80038429f3c -7929002061291000 -7d404e2a7c0004ac -4d820020280a0001 -394000017c0802a6 +600000004bfff27d +48001b08382100a0 +7c9df2147cbdf050 +3bc000083c62ffff +7ca501947ca50e70 +38637e00789cfee2 +7ca507b47f84e378 +600000004bfff245 +3ba000007fe3fb78 +386000644bfff9dd +7c1ce8004bfffb99 +3880002a4082003c +4bfffbc17fe3fb78 +7c7d1b7838800054 +4bfffbb17fe3fb78 +2c0300007c63ea14 +3bdeffff4182ff88 +4082ffb42c1e0000 +7fe3fb784bffff78 +4bfff9d53bbd0001 +4bfffb4538600064 +000000004bffffac +0000078001000000 +38429f803c4c0001 +612910003d20c800 +7c0004ac79290020 +280a000e7d404e2a +7c0802a64d820020 f821ffa1f8010010 -7d404f2a7c0004ac -38637e183c62ffff -600000004bfff13d -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429ed4 -39297e403d22ffff -f821ff01480018f5 -3f00c8003f80c800 -3e62ffff3e82ffff -639c08043f22ffff -3e42ffff63180820 -3b4000013ba00000 -3ae00000f9210060 -3a737e583a947e50 -7b9c00203b397b88 -3a527e607b180020 -7fb0eb787ba307e0 -7f56e8304bfff8c5 +7c0004ac3940000e +3c62ffff7d404f2a +4bfff18138637e18 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429f183c4c0001 +612910003d20c800 +7c0004ac79290020 +280a00017d404e2a +7c0802a64d820020 +f821ffa1f8010010 +7c0004ac39400001 +3c62ffff7d404f2a +4bfff11938637e40 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429eb03c4c0001 +480019057c0802a6 +3f80c800f821ff01 +3ba000003f00c800 +3ae000003b400001 +3e82ffff3d22ffff +3f22ffff3e62ffff +63180820639c0804 +39297e683e42ffff +3a737e803a947e78 +7b9c00203b397bb0 +3a527e887b180020 +7ba307e0f9210060 +7f56e8307fb0eb78 3a2000003be00000 7fbe07b439e00000 -7de507b4e8610060 -39c000207fc4f378 -4bfff0813b600000 -7fc3f37860000000 -3880002a4bfff7f5 -4bfff9e97fc3f378 -7c751b7838800054 -4bfff9d97fc3f378 -7c6400347c63aa14 -7e83a37821230080 -548a60265484d97e -7d2952147c8407b4 -4bfff0317f7b4a14 +e86100604bfff8b5 +7fc4f3787de507b4 +3b60000039c00020 +600000004bfff05d +4bfff7f97fc3f378 +7fc3f3783880002a +388000544bfff9ed +7fc3f3787c751b78 +7c63aa144bfff9dd +212300807c640034 +5484d97e7e83a378 +7c8407b4548a6026 +7f7b4a147d295214 +600000004bfff00d +4bfff7f57fc3f378 +4082ffac35ceffff +4bffeff17e639b78 7fc3f37860000000 -35ceffff4bfff7f1 -7e639b784082ffac -600000004bfff015 -4bfffc557fc3f378 -4bfff0017f23cb78 -7c11d84060000000 -7dff7b784080000c -2c0f00077f71db78 -7c0004ac4182002c -7c0004ac7ec0e72a -7c0004ac7f40c72a -39ef00017ee0e72a -3ba000014bffff30 -7fe507b44bffff08 -7e4393787fc4f378 -4bffefa97bff0020 -7a0307e060000000 -393f00014bfff7b5 -420000287d2903a6 -4bfffbd57fc3f378 -4bffef817f23cb78 -2c1d000060000000 -382101004182ffb4 -7c0004ac480017ac -7c0004ac7ec0e72a -7c0004ac7f40c72a -4bffffc07ee0e72a -0100000000000000 -3c4c000100001280 -7c0802a638429cfc -f821ffa1f8010010 -386000004bfffd4d -386000004bfff6a5 -386000014bfff735 -386000014bfff695 -3c62ffff4bfff725 -4bffef0138637e78 -4bfffde960000000 -382100604bfffd7d -e801001038600001 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429c8c -6129082c3d20c800 -480016cd79290020 -3b000002f821ff51 -7f004f2a7c0004ac -3b2000033d20c800 -7929002061290830 -7f204f2a7c0004ac -3c62ffff3fc0c800 -38637e883c804000 -4bffee7963de0800 -3b80000160000000 -7bde00204bfffc8d -7f80f72a7c0004ac -3be00000386003e8 -7c0004ac4bfff799 -386003e87fe0f72a -4bfff7853f60c800 -7c0004ac7b7b0020 -3f40c8007fe0df2a -7b5a0020635a0004 -7fe0d72a7c0004ac -63bd100c3fa0c800 -7c0004ac7bbd0020 -3fc0c8007fe0ef2a -7bde002063de1010 +7f23cb784bfffc59 +600000004bffefdd +4080000c7c11d840 +7f71db787dff7b78 +4182002c2c0f0007 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +4bffff3039ef0001 +4bffff083ba00001 +7fc4f3787fe507b4 +7bff00207e439378 +600000004bffef85 +4bfff7b97a0307e0 +7d2903a6393f0001 +7fc3f37842000028 +7f23cb784bfffbd9 +600000004bffef5d +4182ffb42c1d0000 +480017b438210100 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +000000004bffffc0 +0000128001000000 +38429cd83c4c0001 +f80100107c0802a6 +4bfffd4df821ffa1 +4bfff6a938600000 +4bfff73938600000 +4bfff69938600001 +4bfff72938600001 +38637ea03c62ffff +600000004bffeedd +4bfffd7d4bfffde9 +3860000138210060 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429c683c4c0001 +480016e17c0802a6 +3d20c800f821ff51 +6129082c3b000002 +7c0004ac79290020 +3d20c8007f004f2a +612908303b200003 +7c0004ac79290020 +3fc0c8007f204f2a +3c8040003c62ffff +38637eb03b800001 +4bffee5163de0800 +7bde002060000000 +7c0004ac4bfffc89 +386003e87f80f72a +4bfff79d3be00000 7fe0f72a7c0004ac -3920000c3ee0c800 -7af7002062f71000 -7d20bf2a7c0004ac -6063c35038600000 -7c0004ac4bfff719 -7c0004ac7fe0ef2a -3920000e7fe0f72a -7d20bf2a7c0004ac -4bfff6f538602710 -7c0004ac39200200 -7c0004ac7d20ef2a -3860000f7f00f72a -7c0004ac4bfff42d -7c0004ac7fe0ef2a -3860000f7f20f72a -392000064bfff415 +3f60c800386003e8 +7b7b00204bfff789 +7fe0df2a7c0004ac +635a00043f40c800 +7c0004ac7b5a0020 +3fa0c8007fe0d72a +7bbd002063bd100c +7fe0ef2a7c0004ac +63de10103fc0c800 +7c0004ac7bde0020 +3ee0c8007fe0f72a +62f710003920000c +7c0004ac7af70020 +386000007d20bf2a +4bfff71d6063c350 +7fe0ef2a7c0004ac +7fe0f72a7c0004ac +7c0004ac3920000e +386027107d20bf2a +392002004bfff6f9 7d20ef2a7c0004ac -7f80f72a7c0004ac -4bfff3f93860000f -7c0004ac39200930 +7f00f72a7c0004ac +4bfff4313860000f +7fe0ef2a7c0004ac +7f20f72a7c0004ac +4bfff4193860000f +7c0004ac39200006 7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff3dd -392004004bfff681 +3860000f7f80f72a +392009304bfff3fd 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff3b938600003 -4bfff65d386000c8 -4bfffb994bfffddd -3c6040003c800020 -60000000480006e9 -408200242c030000 -7c0004ac7c691b78 -7c0004ac7f80d72a -382100b07f80df2a -4800153c7d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bfff3e13860000f +4bfff685386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff3bd +4bfffddd4bfff661 +3c8000204bfffb99 +480006e13c604000 +2c03000060000000 +7c691b7840820024 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000980 -7c0802a638429a5c -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffec7938637ea8 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637eb03c62ffff -600000004bffec3d -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ec07ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b4382100b0 +38c0000048001544 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000098001000000 +38429a383c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ed03c62ffff +600000004bffec55 +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ed0 -0100000000000000 -3c4c000100000080 -7c0802a63842998c -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffec1938637ed8 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637ee8 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ee078c60020 +38637ef87ca54b92 +000000004bffffa4 +0000008001000000 +384299683c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffeb9d -4bfffef97fe3fb78 -38637ef03c62ffff -600000004bffeb85 -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -384298e83c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffeb7938637f08 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffeb6138637f18 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384298c4 +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffeb59 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffeb09 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffeb3d42000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffeaed7fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384297d83c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187ef87bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637ef8 -3c62ffff4bfffde5 -4bffe9a138637b88 -4bffea0560000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a6384297b4 +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f20 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f20 +38637bb03c62ffff +600000004bffe97d +600000004bffe9e9 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f08 -3c62ffff4bfffd8d -4bffe94938637b88 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f08 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384296183c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f30 +38637bb03c62ffff +600000004bffe925 +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f307ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a6384295f4 +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f183c62ffff -4bffe8197cbc2b78 -3c62ffff60000000 -4092000c38637f30 -38637f403c62ffff -600000004bffe7fd -4bfffb597fc3f378 -38637f503c62ffff -600000004bffe7e5 -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f402e3b0000 +600000004bffe7f5 38637f583c62ffff -4bffe7617f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffe74938637f68 +3c62ffff4092000c +4bffe7d938637f68 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffe7c138637f78 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8005f57d3602a6 +7929002078ea0020 +639ce1003c62ffff +38637f807d295050 +7f9c4b927f9ee1d2 +600000004bffe73d +4bfffabd7f83e378 +38637f903c62ffff +600000004bffe725 +38637bb03c62ffff +600000004bffe715 +600000004bffe781 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4005f5 +3c62ffff79290020 +7d29e050614ae100 +7fde51d238637f98 +4bffe6797fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffe66138637f90 3c62ffff60000000 -4bffe73938637b88 -4bffe79d60000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f70 -600000004bffe69d -4bfff9f97fc3f378 -38637f683c62ffff -600000004bffe685 -38637b883c62ffff -600000004bffe675 -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384293e03c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffe65138637bb0 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384293c4 +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f807fc4f378 -600000004bffe5ed -4bfff9497fe3fb78 -38637f503c62ffff +7c641b787f9c205e +38637fa83c62ffff 600000004bffe5d5 +4bfff9557fe3fb78 +38637f783c62ffff +600000004bffe5bd 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffe58938637f90 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fa838800000 -600000004bffe55d -7be5f0823c62ffff -38637fc07fc4f378 -600000004bffe545 -38637fd83c62ffff -600000004bffe535 -3821008038600000 -48000d987c6307b4 -38637fe83c62ffff -600000004bffe515 -4bffffe038600001 -0100000000000000 -3c4c000100000480 -60000000384292b4 -6000000089228068 -2c09000039428060 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228060 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428060 -4e8000207d2057ea +4bffe57138637fb8 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fd0 +4bffe54978a5f082 +3c62ffff60000000 +7fc4f3787be5f082 +4bffe53138637fe8 +6000000060000000 +4bffe52138628000 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffe50138628010 +3860000160000000 +000000004bffffe0 +0000048001000000 +384292a03c4c0001 +6000000060000000 +3942808889228090 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e922808860000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94280885469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842922c -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384291cc -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428060 -9942806860000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942806060000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228068 -3920ff806108200c -7c0004ac79080020 -e92280607d2047aa -7d404faa7c0004ac -794ac202e9228060 -7c0004ac39290004 -e92280607d404faa -3929000c39400003 +384292183c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384291b83c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f942808860000000 +6000000039400000 +3d40001c99428090 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf9428088 +7d495392614a2000 +600000004182ffa0 +9922809039200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace9228088 +e92280887d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228060 +39400003e9228088 +7c0004ac3929000c +e92280887d404faa +7c0004ac39290010 +e92280887d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228060 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 -0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +000000004e800020 +0000000000000000 +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428e94 -f821ffa1480008e9 +7c0802a638428e84 +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1536,36 +1538,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428dc4 -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428db4 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428d483c4c0001 -3d22ffff7c0802a6 -2b860010e9297ff8 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428d383c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922800060000000 +2b8600107caa2b78 +f9210020e9228020 +e922802860000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -1573,253 +1575,256 @@ e922800060000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428c54 -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b7488 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428c483c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b7494 +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028018 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c676443cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028040 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a7654 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942801860000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280187aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028040 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028040 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2801038610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280387de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1870,15 +1875,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 593bee2..ea758b2 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:06:55 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:18 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [13:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [13:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -69,1941 +69,2065 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; -wire iodelay_clk; -wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [13:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [13:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [13:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [13:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [13:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_master_p0_address = 14'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [13:0] litedramcore_master_p1_address = 14'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [13:0] litedramcore_master_p2_address = 14'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [13:0] litedramcore_master_p3_address = 14'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [13:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [20:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [20:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [20:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [20:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [20:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [20:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [20:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [20:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [13:0] litedramcore_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [13:0] litedramcore_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [13:0] litedramcore_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [13:0] litedramcore_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [13:0] litedramcore_cmd_payload_a = 14'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [20:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine0_row = 14'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [20:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine1_row = 14'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [20:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine2_row = 14'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [20:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine3_row = 14'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [20:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine4_row = 14'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [20:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine5_row = 14'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [20:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine6_row = 14'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [20:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine7_row = 14'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [13:0] litedramcore_nop_a = 14'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [23:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg rst_1 = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire reset; +reg power_down = 1'd0; +wire locked; +wire clkin; +wire clkout0; +wire clkout_buf0; +wire clkout1; +wire clkout_buf1; +wire clkout2; +wire clkout_buf2; +wire clkout3; +wire clkout_buf3; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +reg a7ddrphy_wlevel_strobe_re = 1'd0; +wire a7ddrphy_wlevel_strobe_r; +reg a7ddrphy_wlevel_strobe_we = 1'd0; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg a7ddrphy_rdly_dq_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_r; +reg a7ddrphy_rdly_dq_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_inc_re = 1'd0; +wire a7ddrphy_rdly_dq_inc_r; +reg a7ddrphy_rdly_dq_inc_we = 1'd0; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_r; +reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_r; +reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [13:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [13:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [13:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [13:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +wire [2:0] a7ddrphy_pads_ba; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip21; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip31; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [13:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_master_p0_address = 14'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [13:0] litedramcore_master_p1_address = 14'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [13:0] litedramcore_master_p2_address = 14'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [13:0] litedramcore_master_p3_address = 14'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +wire [13:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p2_address; +wire [2:0] litedramcore_csr_dfi_p2_bank; +reg litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg litedramcore_csr_dfi_p2_we_n = 1'd1; +wire litedramcore_csr_dfi_p2_cke; +wire litedramcore_csr_dfi_p2_odt; +wire litedramcore_csr_dfi_p2_reset_n; +reg litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p2_wrdata; +wire litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; +wire litedramcore_csr_dfi_p2_rddata_en; +reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; +reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p3_address; +wire [2:0] litedramcore_csr_dfi_p3_bank; +reg litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg litedramcore_csr_dfi_p3_we_n = 1'd1; +wire litedramcore_csr_dfi_p3_cke; +wire litedramcore_csr_dfi_p3_odt; +wire litedramcore_csr_dfi_p3_reset_n; +reg litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p3_wrdata; +wire litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; +wire litedramcore_csr_dfi_p3_rddata_en; +reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; +reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; +reg litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg litedramcore_ext_dfi_p2_we_n = 1'd1; +reg litedramcore_ext_dfi_p2_cke = 1'd0; +reg litedramcore_ext_dfi_p2_odt = 1'd0; +reg litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; +reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; +reg litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg litedramcore_ext_dfi_p3_we_n = 1'd1; +reg litedramcore_ext_dfi_p3_cke = 1'd0; +reg litedramcore_ext_dfi_p3_odt = 1'd0; +reg litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; +reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_phaseinjector2_csrfield_cs; +wire litedramcore_phaseinjector2_csrfield_we; +wire litedramcore_phaseinjector2_csrfield_cas; +wire litedramcore_phaseinjector2_csrfield_ras; +wire litedramcore_phaseinjector2_csrfield_wren; +wire litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +reg litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_r; +reg litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; +wire litedramcore_phaseinjector2_rddata_we; +reg litedramcore_phaseinjector2_rddata_re = 1'd0; +wire litedramcore_phaseinjector3_csrfield_cs; +wire litedramcore_phaseinjector3_csrfield_we; +wire litedramcore_phaseinjector3_csrfield_cas; +wire litedramcore_phaseinjector3_csrfield_ras; +wire litedramcore_phaseinjector3_csrfield_wren; +wire litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +reg litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_r; +reg litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; +wire litedramcore_phaseinjector3_rddata_we; +reg litedramcore_phaseinjector3_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [20:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [20:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [20:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [20:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [20:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [20:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [20:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [20:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [13:0] litedramcore_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [13:0] litedramcore_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [13:0] litedramcore_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [13:0] litedramcore_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [13:0] litedramcore_cmd_payload_a = 14'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [20:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [20:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [23:0] litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [23:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [23:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [20:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine0_row = 14'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [20:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [20:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [23:0] litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [23:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [23:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [20:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine1_row = 14'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [20:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [20:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [23:0] litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [23:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [23:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [20:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine2_row = 14'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [20:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [20:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [23:0] litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [23:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [23:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [20:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine3_row = 14'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [20:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [20:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [23:0] litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [23:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [23:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [20:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine4_row = 14'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [20:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [20:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [23:0] litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [23:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [23:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [20:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine5_row = 14'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [20:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [20:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [23:0] litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [23:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [23:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [20:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine6_row = 14'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [20:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [20:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [23:0] litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [23:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [23:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [20:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine7_row = 14'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +wire [1:0] litedramcore_rdcmdphase; +wire [1:0] litedramcore_wrcmdphase; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [13:0] litedramcore_nop_a = 14'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [23:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_rst0_re = 1'd0; +wire csrbank1_rst0_r; +reg csrbank1_rst0_we = 1'd0; +wire csrbank1_rst0_w; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_r; +reg csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_w; +reg csrbank1_wlevel_en0_re = 1'd0; +wire csrbank1_wlevel_en0_r; +reg csrbank1_wlevel_en0_we = 1'd0; +wire csrbank1_wlevel_en0_w; +reg csrbank1_rdphase0_re = 1'd0; +wire [1:0] csrbank1_rdphase0_r; +reg csrbank1_rdphase0_we = 1'd0; +wire [1:0] csrbank1_rdphase0_w; +reg csrbank1_wrphase0_re = 1'd0; +wire [1:0] csrbank1_wrphase0_r; +reg csrbank1_wrphase0_we = 1'd0; +wire [1:0] csrbank1_wrphase0_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +reg csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +reg csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_w; +reg csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_r; +reg csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_w; +reg csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi2_address0_r; +reg csrbank2_dfii_pi2_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi2_address0_w; +reg csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +reg csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; +reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +reg csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +reg csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_w; +reg csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_r; +reg csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_w; +reg csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi3_address0_r; +reg csrbank2_dfii_pi3_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi3_address0_w; +reg csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +reg csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; +reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +reg csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +reg csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_reset0; +wire litedramcore_reset1; +wire litedramcore_reset2; +wire litedramcore_reset3; +wire litedramcore_reset4; +wire litedramcore_reset5; +wire litedramcore_reset6; +wire litedramcore_reset7; +wire litedramcore_pll_fb; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2047,144 +2171,144 @@ assign ddram_ba = a7ddrphy_pads_ba; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); @@ -2192,1074 +2316,1074 @@ assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7d assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) - 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) - 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) - 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) - 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) - 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) - 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) - 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) - 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) - 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) - 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) - 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) - 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) - 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) - 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) - 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) - 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) - 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) - 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) - 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) - 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) - 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) - 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) - 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) - 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) - 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) - 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) - 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) - 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) - 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) - 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) - 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) - 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) - 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) - 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) - 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) - 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -3390,892 +3514,892 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end + litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; - end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; - end - end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; - end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; - end - end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; - end - end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; - end - end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; - end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; - end - end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end - end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; - end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; - end - end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; - end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; - end - end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; - end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; - end - end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; - end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; - end - end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; - end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; - end - end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; - end - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; - end - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; - end - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - litedramcore_master_p3_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; - end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; - end - end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; - end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; - end - end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; - end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; - end - end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; - end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; - end - end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end -end -always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; - end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; - end - end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; - end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; - end - end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end - end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end - end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end - end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end - end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; - end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; - end - end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; - end - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; - end - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; - end - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + end else begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; + end + end else begin + litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + end else begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + end + end else begin + litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end + end else begin + litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end + end else begin + litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end + end else begin + litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end + end else begin + litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + end else begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + end + end else begin + litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + end else begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + end + end else begin + litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + end + end else begin + litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + end else begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + end + end else begin + litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + end + end else begin + litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end + end else begin + litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end + end else begin + litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end + end else begin + litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end + end else begin + litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end + end else begin + litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end + end else begin + litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end + end else begin + litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + end else begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + end + end else begin + litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + end + end else begin + litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + end else begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + end + end else begin + litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + end + end else begin + litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + end + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + end + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + end + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -4290,36 +4414,36 @@ assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -4328,36 +4452,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -4366,36 +4490,36 @@ assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_ assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); - end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + end else begin + litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); - end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + end else begin + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); - end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + end else begin + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; @@ -4404,36 +4528,36 @@ assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_ assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); - end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + end else begin + litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); - end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + end else begin + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); - end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + end else begin + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; @@ -4511,4590 +4635,4686 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase end assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); @@ -9127,15 +9347,15 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9145,106 +9365,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9254,22 +9474,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -9286,473 +9506,473 @@ assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -9798,26 +10018,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -9829,129 +10049,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -9967,201 +10187,201 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; - end + csrbank1_rst0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); - end + csrbank1_rst0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); - end + csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; - end + csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; - end + csrbank1_wlevel_en0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); - end + csrbank1_wlevel_en0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; - end + a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_rdphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; - end + csrbank1_rdphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_re <= interface1_bank_bus_we; + end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; - end + csrbank1_wrphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_wrphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_rst0_w = a7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10172,328 +10392,328 @@ assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -10563,1194 +10783,1194 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 14'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 14'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 14'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 14'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 21'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 21'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 21'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 21'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 14'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 14'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 14'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 14'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 21'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 21'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 21'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 21'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 14'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 14'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 14'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 14'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); @@ -11763,2132 +11983,2132 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); - end else begin - ic_reset <= 1'd0; - end - if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; - end + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); + end else begin + ic_reset <= 1'd0; + end + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; + end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; - end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; - end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; - end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; - end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; - end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; - end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; - end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; - end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; - end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; - end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; - end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; - end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; - end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; - end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; - end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; - end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; - end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; - end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; - end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; - end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; - end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; - end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; - end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; - end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; - end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; - end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; - end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; - end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; - end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; - end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; - end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; - end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; - end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; - end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; - end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; - end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; - end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 10'd781; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; - end - endcase - end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; - end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; - end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; - end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; - end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; - end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; - end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; - end - 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; - end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; - end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; - end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; - end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; - end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; - end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; - end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; - end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; - if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 14'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 14'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 14'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 14'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 14'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine0_row <= 14'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine1_row <= 14'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine2_row <= 14'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine3_row <= 14'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine4_row <= 14'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine5_row <= 14'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine6_row <= 14'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine7_row <= 14'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if (litedramcore_csr_dfi_p2_rddata_valid) begin + litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + end + if (litedramcore_csr_dfi_p3_rddata_valid) begin + litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_rst0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + end + endcase + end + if (csrbank1_rst0_re) begin + a7ddrphy_rst_storage <= csrbank1_rst0_r; + end + a7ddrphy_rst_re <= csrbank1_rst0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + end + a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; + if (csrbank1_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + end + a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; + litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + if (sys_rst) begin + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 32'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 32'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_rddata_status <= 32'd0; + litedramcore_phaseinjector2_rddata_re <= 1'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_rddata_status <= 32'd0; + litedramcore_phaseinjector3_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 14'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 14'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 14'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 14'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 14'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine0_row <= 14'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine1_row <= 14'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine2_row <= 14'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine3_row <= 14'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine4_row <= 14'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine5_row <= 14'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine6_row <= 14'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine7_row <= 14'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -15811,14 +16031,14 @@ IOBUF IOBUF_15( reg [23:0] storage[0:15]; reg [23:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -15829,14 +16049,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [23:0] storage_1[0:15]; reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -15847,14 +16067,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [23:0] storage_2[0:15]; reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -15865,14 +16085,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [23:0] storage_3[0:15]; reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -15883,14 +16103,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [23:0] storage_4[0:15]; reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -15901,14 +16121,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [23:0] storage_5[0:15]; reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -15919,14 +16139,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [23:0] storage_6[0:15]; reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -15937,14 +16157,14 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [23:0] storage_7[0:15]; reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( @@ -16038,7 +16258,8 @@ PLLE2_ADV #( .LOCKED(locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), @@ -16048,7 +16269,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), @@ -16058,7 +16280,8 @@ PLLE2_ADV #( .Q(iodelay_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), @@ -16068,7 +16291,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), @@ -16078,7 +16302,8 @@ PLLE2_ADV #( .Q(sys_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), @@ -16088,7 +16313,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), @@ -16098,7 +16324,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), @@ -16108,7 +16335,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), @@ -16121,5 +16349,5 @@ PLLE2_ADV #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:06:55. +// Auto-Generated by LiteX on 2022-10-28 19:01:19. //------------------------------------------------------------------------------ diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init index 1ede481..a0de849 100644 --- a/litedram/generated/genesys2/litedram_core.init +++ b/litedram/generated/genesys2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842bcc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048002f15 -386100207c7f1b78 -600000004800292d +6000000048002f19 +7fc3f3787c7f1b78 +6000000048002939 7fe3fb78382100b0 -000000004800361c -0000018001000000 +000000004800363c +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842bc283c4c0001 +3842bc203c4c0001 7d6000267c0802a6 -9161000848003555 -48002929f821fed1 +9161000848003579 +48002935f821fed1 3c62ffff60000000 -4bffff41386379d0 +4bffff39386379f8 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff0008386379f0 -3c62ffff4bffff1d -38637a107bff0020 -7c0004ac4bffff0d +63ff000838637a18 +3c62ffff4bffff15 +38637a387bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637a28 +4bfffee938637a50 4d80000073e90002 3c62ffff41820010 -4bfffed938637a30 +4bfffed138637a58 4e00000073e90004 3c62ffff41820010 -4bfffec138637a38 +4bfffeb938637a60 4d00000073e90008 3c62ffff41820010 -4bfffea938637a40 +4bfffea138637a68 4182001073e90010 -38637a503c62ffff -73ff01004bfffe95 +38637a783c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637a60 -3b7b7a683f62ffff -4bfffe717f63db78 +4bfffe7938637a88 +3b7b7a903f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637a70 +4bfffe4138637a98 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637a88 +4bfffe1938637ab0 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637aa07884b282 -3d20c0004bfffdfd +38637ac87884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637ab87c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637ae0 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637ad8 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637b0057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637af85784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637b2057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637b18 -7f40efaa7c0004ac +4bfffc8138637b40 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637b303c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637b583c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637b407bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637b603c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637b28 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637c70 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048002645 -38637c903c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847b783c62ffff -4bfffb0938637b88 -60000000480019d9 -3c82ffff4bffff54 -38847b783c62ffff -4bfffae938637b88 -60000000480019b9 -3c62ffff4bffff80 -4bfffad138637ba8 -38a000403c9ef000 -3861007078840020 -60000000480025cd -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637b683be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637b9838847b88 +48001a694bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637bb8 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637b503c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637bd0 +38a000403c9af000 +7884002038610070 +60000000480025f9 +e92100703d400002 614a464c3c62ffff -794a83e438637bc0 +794a83e438637be8 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637be03c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637c083c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637c4088810070 +38637c6888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397bf83ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637c98 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048002551 +38637cb83c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187c203b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637c20 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637c48 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480030307d638120 -38a000383c9ef000 -386100b078840020 -60000000480024e5 +480030347d638120 +38a000383c9ff000 +788400207f23cb78 +60000000480024d1 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -600000004800249d -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +6000000048002489 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,7 +742,7 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -3842b5e83c4c0001 +3842b5c03c4c0001 4182006828030002 4182003028030003 4082007c28030001 @@ -838,8 +843,8 @@ ebe100b8eb8100c0 0000000000000000 7c0004ac00000000 390000047d201e2a -7d0903a679290020 -9d2affff39440004 +3944000479290020 +9d2affff7d0903a6 4200fff87929c202 7c0004ac38630004 7869c2227c601e2a @@ -848,18 +853,18 @@ ebe100b8eb8100c0 9864000499240005 000000004e800020 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -7c0802a63842b23c -3fe0c800fbe1fff8 +7c0802a63842b214 +f8010010fbe1fff8 +3fe0c800f821ffd1 63ff080439200001 7bff00207d231830 -f821ffd1f8010010 7c60ff2a7c0004ac 614a082c3d40c800 7c0004ac794a0020 @@ -870,18 +875,18 @@ f821ffd1f8010010 4bffff6538600064 7c0004ac39200000 382100307d20ff2a -0000000048002b7c +0000000048002b80 0000018001000000 -3842b1b03c4c0001 -3d40c8007c0802a6 -614a100c7d708026 -794a002039200086 -48002aa191610008 -83a280fc60000000 -7c7f1b78f821fec1 -7cb72b787c982378 +3842b1883c4c0001 +7d7080267c0802a6 +48002ab591610008 +3d40c800f821feb1 +614a100c60000000 +7c9823787c7f1b78 +83a281247cb72b78 +39200086794a0020 7fbd01947fbd1670 -23bd00207ebd00d0 +23bd00207e9d00d0 7d20572a7c0004ac 3bc000013d20c800 7929002061291010 @@ -890,126 +895,126 @@ f821ffd1f8010010 6129080c3d20c800 7c0004ac79290020 386000647fc04f2a -4bfffead3e80c800 -629408103d22ffff -6000000039297ca8 +600000003e60c800 3b41008060000000 +3b6000003bc00000 +4bfffe953ac10060 +627308103d22ffff +3a0281243a2280a0 +39297cd0fb410090 +f92100a07a730020 +39297ce03d22ffff 3d22fffff9210098 -39297cb83bc00000 -7a9400203b600000 -f92100903ac10060 -3a2280783d22ffff -3a0280fc39297cc0 -3d22fffff92100a0 -f92100a839297cd8 -7f7c07b42e370000 -e861009841920014 -4bfff3f17f84e378 -7f83e37860000000 -4bfffe693b200000 -39c0000138600064 -7c1dc8004bfffe21 +f92100a839297ce8 +39297d003d22ffff +2e370000f92100b0 +419200147f7c07b4 +7f84e378e86100a0 +600000004bfff3c5 +3b2000007f83e378 +39c000003aa00001 +386000644bfffe5d +7c1dc8004bfffe19 4192001041810128 -4bfff3c1e86100a0 -2c1d000060000000 -38e000003920ffff -7d3ff12e3b20ffff -39c000007ba90020 -3880000038c00000 -3929000138b5001f -3920000140800008 -7ce83b782c290001 -408201603929ffff -4bfffdf97f83e378 -4bfffdb538600064 -2c0900007d31f02e -7d3ff12e418001bc -7d3ff02e3b200000 -418101907c09c800 -3b7b0001409201f8 -2c1b00043b5affff -4082ff2c3bde0004 -392000063d40c800 -794a0020614a100c -7d20572a7c0004ac -392000013d40c800 -794a0020614a1010 -7d20572a7c0004ac -4bfff9913860000f -392000003d40c800 -794a0020614a080c -7d20572a7c0004ac -3bff001039200004 -386000017d2903a6 -2c090000853ffffc -3860000040800008 -382101404200fff0 +4bfff391e86100a8 +3920ffff60000000 +394000012c1d0000 +3b20ffff38c00000 +38a000003aa00000 +7d3ff12e39000000 +388000017ba90020 +392900013874001f +2c2900017d2a481e +3929ffff7cca3378 +7f83e37840820160 +386000644bfffded +7d31f02e4bfffda9 +418001b02c090000 +7d3ff12e3b200000 +7c09c8007d3ff02e +409201ec41810184 +3b5affff3b7b0001 +2c1b00043bde0004 +3d40c8004082ff24 +614a100c39200006 +7c0004ac794a0020 +3d40c8007d20572a +614a101039200001 +7c0004ac794a0020 +3860000f7d20572a +3d40c8004bfff985 +614a080c39200000 +7c0004ac794a0020 +392000047d20572a +386000013bff0010 +853ffffc7d2903a6 +7c60181e2c090000 +382101504200fff4 816100087c6307b4 -480028c87d708120 -3a6000007f0fc378 -7c0004ac3a400000 -386000647dc0a72a -3c60c8004bfffcd9 -6063101c38810080 -4bfffc6978630020 -2c07000088fa0003 -3a7300014182004c -4082ffc835efffff -7e6407b47e4a07b4 -78840fe07c845050 -419200107c99b1ae -4bfff241e8610090 -7f83e37860000000 -4bfff9b13b390001 -4bfffc7538600064 -3a5200014bfffe54 -2c0400004bffffb8 -4182002c7d47b0ae -418200107c054000 -2c0a0000554a063e -7d06405040820024 -418000207c194000 -4800001038800000 -2c0a0000554a063e -38e7000140820018 -7d1943784bfffe50 -4bffffdc7cce3378 -388000017ce63b78 -7f83e3784bffffe4 +480028c47d708120 +3a4000007f08c378 +f90100b839e00000 +7ea09f2a7c0004ac +4bfffccd38600064 +e88100903c60c800 +786300206063101c +88fa00034bfffc5d +2c070000e90100b8 +3a52000141820048 +4082ffc03508ffff +7c95701e7c0f9000 +419200147c99b1ae +7c8407b4e8610098 +600000004bfff20d +3b3900017f83e378 +386000644bfff9a5 +4bfffe504bfffc69 +4bffffbc39ef0001 +7ce6b0ae2c080000 +7c0350004182002c +54e7063e41820010 +408200242c070000 +7c1950007d455050 +3900000041800020 +70e700ff48000010 +7d08209e7ca5509e +4bfffe5038c60001 +7cb52b787d595378 +7f83e3784bffffdc 4bfff9313b390001 4bfffbf538600064 -2c0e00004bfffe54 +2c1500004bfffe60 2c19000041820038 -7ddff12e4081fe50 -7d3ff02e3b200000 -4081fe3c7c09c800 +3b2000004081fe5c +7d3ff02e7ebff12e +4081fe487c09c800 3b3900017f83e378 386000644bfff8f5 4bffffe04bfffbb9 7d29167081300000 7c09c8007d290194 -4bffffc04080fe10 +4bffffc04080fe1c 2c04ffff7c9ff02e 3c62ffff40820018 -4bfff13938637cc8 -4bfffdf060000000 -7c8407b4e86100a8 -600000004bfff125 -000000004bfffddc +4bfff11138637cf0 +4bfffdfc60000000 +7c8407b4e86100b0 +600000004bfff0fd +000000004bfffde8 0000128003000000 -3842adc83c4c0001 -3ce080207c0802a6 -3920000060e70003 -480026e178e70020 -7c7e1b78f821ff61 -3be100203941001f -394000087d0a4a14 +3842ada03c4c0001 +480026f57c0802a6 +3cc08020f821ff61 +60c6000339200000 +38e1001f7c7e1b78 +3940000878c60020 +7d074a143be10020 788af8627d4903a6 7c8400d0788407e0 -7c8a52787c843838 +7c8a52787c843038 9d4800017d445378 392900084200ffe4 -4082ffc428290020 +4082ffc828290020 392000003d40c800 794a0020614a100c 7d20572a7c0004ac @@ -1018,17 +1023,17 @@ e861009841920014 386000097d20572a 3860000f4bfff70d 3d20c8004bfffab9 -612910143ca0c800 -7fe8fb7860a51094 +7fe8fb783ca0c800 +60a5109461291014 78a5002079290020 38c8ffff38800004 -38e000007c8903a6 -8c86000139400004 +3940000438e00000 +8c8600017c8903a6 78e4400c394affff 4200fff07c872378 7c804f2a7c0004ac 38c9000438800004 -38e800037c8903a6 +7c8903a638e80003 7944400c8c870001 4200fff47c8a2378 7c80372a7c0004ac @@ -1043,8 +1048,8 @@ e861009841920014 388000177c60ee2a 3fa0c8005463063e 63bd08444bfff681 -4bfff9e53860000f -7c0004ac7bbd0020 +7bbd00203860000f +7c0004ac4bfff9e1 5463063e7c60ee2a 7c0004ac4bfff905 5463063e7c60ee2a @@ -1058,15 +1063,15 @@ e861009841920014 614a10103d40c800 7c0004ac794a0020 3860000b7d20572a -4bfff5b93fa0c800 -3f00c8003860000f -63bd101c4bfff961 +3f00c8003fa0c800 3f2033333ee05555 -6318109c3ec00f0f -7bbd00203b600000 -3b4100403b800000 +3b6000003ec00f0f +4bfff5a13b800000 +3860000f63bd101c +3b4100406318109c 62f7555523de0003 62d60f0f63393333 +7bbd00204bfff931 7f44d3787b180020 4bfff8c17fa3eb78 3940000039200008 @@ -1084,22 +1089,22 @@ e861009841920014 552906be7d294214 394a00017f9c4a14 3bbd00204200ff9c -7c3dc0003b7b0008 -4082ff703bff0008 +3bff00083b7b0008 +4082ff707c3dc000 7b830020382100a0 -000000004800247c +0000000048002480 00000a8001000000 -3842aae83c4c0001 -7c0802a67d708026 -2e25000091610008 -f821ff7148002419 +3842aac03c4c0001 +7d7080267c0802a6 +4800242191610008 +2e250000f821ff71 4192001c7c7f1b78 7c641b787c852378 -38637ce83c62ffff -600000004bffedf5 +38637d103c62ffff +600000004bffedcd 3f62ffff7fe3fb78 -3ba000204bfff5c5 -3b7b7cb83bc00000 +3bc000003ba00020 +3b7b7ce04bfff5bd 7fe3fb783880002a 388000544bfffcc9 7fe3fb787c7c1b78 @@ -1108,27 +1113,27 @@ f821ff7148002419 548960265484d97e 7fde4a147d291a14 7c8407b441920014 -4bffed917f63db78 +4bffed697f63db78 7fe3fb7860000000 37bdffff4bfff5b1 419200144082ffa8 -38637cf83c62ffff -600000004bffed6d +38637d203c62ffff +600000004bffed45 7bc3002038210090 7d70812081610008 -00000000480023a8 +00000000480023ac 0000058003000000 -3842aa003c4c0001 -7c0802a67d600026 -2e25000091610008 -f821ff514800231d +3842a9d83c4c0001 +7d6000267c0802a6 +9161000848002329 +2e250000f821ff51 7c9723787c7f1b78 7cfd3b787cda3378 7c641b7841920018 -38637d003c62ffff -600000004bffed05 -f84100187f4903a6 -7f4cd3787fe3fb78 +38637d283c62ffff +600000004bffecdd +7fe3fb787f4903a6 +f84100187f4cd378 4e8004213b600000 3880002ae8410018 4bfffbd57fe3fb78 @@ -1136,18 +1141,18 @@ f84100187f4903a6 4bfffbc57fe3fb78 4192001c7fc3f214 3c62ffff7fc40034 -5484d97e38637cb8 -600000004bffecad +5484d97e38637ce0 +600000004bffec85 3b9b00012c1e0000 2c1c00204182002c 7fa903a6418200d0 -7fe3fb78f8410018 -7f9be3787faceb78 +7faceb787fe3fb78 +7f9be378f8410018 e84100184e800421 7f7cdb784bffff94 7fa903a63bc00004 -7fe3fb78f8410018 -4e8004217faceb78 +7faceb787fe3fb78 +4e800421f8410018 37deffffe8410018 3adb00044082ffe4 7ed9b3783bc0ffff @@ -1156,231 +1161,231 @@ e84100184e800421 7fe3fb787c781b78 7f03c2144bfffb21 7f0400344192001c -38637cb83c62ffff -4bffec095484d97e +38637ce03c62ffff +4bffebe15484d97e 2c18000060000000 2c1effff41820010 7f3ecb7840820008 2c19001f3b390001 7fa903a64181002c -7fe3fb78f8410018 -4e8004217faceb78 +7faceb787fe3fb78 +4e800421f8410018 4bffff8ce8410018 3b80ffff3b600020 2c1effff4bffff50 -2c16001f4082001c -418100083bc00000 -3b7b000523d6001f -7f7cf2147fdeda14 -7f7b0e702d370000 -2d9cffff7f7b0194 -4092002c577b06fe -408e0108418a0050 -38637d083c62ffff -600000004bffeb6d -81610008382100b0 -480021987d638120 -3f22ffff3c62ffff -3b397a6838637cf8 -600000004bffeb45 -7f23cb78408a0018 -600000004bffeb35 -4bffffc4408e0054 -3c62ffff408e001c -4bffeb1938637d08 +23d6001f40820018 +3b7b00052c16001f +7fdeda147fc0f05e +2d3700007f7cf214 +7f7b0e702d9cffff +577b06fe7f7b0194 +418a00504092002c +3c62ffff408e0108 +4bffeb4938637d30 +382100b060000000 +7d63812081610008 +3c62ffff480021a0 +38637d203f22ffff +4bffeb213b397a90 +408a001860000000 +4bffeb117f23cb78 +408e005460000000 +408e001c4bffffc4 +38637d303c62ffff +600000004bffeaf5 +4bffffa07f23cb78 +3c62ffff7cbcf050 +7ca50e707f6407b4 +38637d407ca50194 +4bffeac97ca507b4 7f23cb7860000000 -7cbcf0504bffffa0 -7ca50e703c62ffff -7f6407b47ca50194 -7ca507b438637d18 -600000004bffeaed -4bffeae17f23cb78 -3bc0000860000000 -7fe3fb787f4903a6 -7f4cd378f8410018 -4e8004213b800000 -38600064e8410018 -7c1cd8004bfff501 -3880002a40820064 -4bfff99d7fe3fb78 -7c7c1b7838800054 -4bfff98d7fe3fb78 -2c0300007c63e214 -3bdeffff4182ff20 -4082ffa42c1e0000 -7cbcf0504bffff10 -7ca50e703c62ffff -7f6407b47ca50194 -7ca507b438637d18 -600000004bffea55 -7fa903a64bffff74 -f84100187fe3fb78 -3b9c00017faceb78 +600000004bffeabd +7f4903a63bc00008 +7f4cd3787fe3fb78 +3b800000f8410018 e84100184e800421 -4bfff47538600064 -000000004bffff74 -00000a8003000000 -3842a6d03c4c0001 -fbe1fff87c0802a6 -392000013fe0c800 -7d23183063ff0804 -f80100107bff0020 -7c0004acf821ffd1 -3d40c8007c60ff2a -794a0020614a0830 -7d20572a7c0004ac -4bfff41538600064 -7c0004ac39200000 -382100307d20ff2a -000000004800202c -0000018001000000 -3842a6603c4c0001 -fbe1fff87c0802a6 -392000013fe0c800 -7d23183063ff0804 -f80100107bff0020 -7c0004acf821ffd1 -3d40c8007c60ff2a -794a0020614a082c -7d20572a7c0004ac -4bfff3a538600064 -7c0004ac39200000 -382100307d20ff2a -0000000048001fbc -0000018001000000 -3842a5f03c4c0001 -612910003d20c800 -7c0004ac79290020 -280a000e7d404e2a -7c0802a64d820020 -f80100103940000e -7c0004acf821ffa1 -3c62ffff7d404f2a -4bffe8f138637d30 -3821006060000000 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -3842a5883c4c0001 -612910003d20c800 -7c0004ac79290020 -280a00017d404e2a -7c0802a64d820020 -f801001039400001 -7c0004acf821ffa1 -3c62ffff7d404f2a -4bffe88938637d58 -3821006060000000 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -3842a5203c4c0001 -3c80c8007c0802a6 -7884002060840808 -f821ff3148001e39 -7c80262a7c0004ac -5484103a60000000 -908280fc3c62ffff -7c8407b438637d80 -600000004bffe825 -8122807060000000 -418202002c090000 -83e2806c60000000 -408200082c1fffff -600000003be00000 -2c1dffff83a28068 -6000000040820014 -7fbd0e7083a280fc -3c62ffff7fbd0194 -7fe407b47fa507b4 -4bffe7c938637da0 -3c62ffff60000000 -4bffe7b938637db8 -3d40c80060000000 -614a081439200001 +4bfff50538600064 +408200647c1cd800 +7fe3fb783880002a +388000544bfff9a1 +7fe3fb787c7c1b78 +7c63e2144bfff991 +4182ff202c030000 +2c1e00003bdeffff +4bffff104082ffa4 +3c62ffff7cbcf050 +7ca50e707f6407b4 +38637d407ca50194 +4bffea317ca507b4 +4bffff7460000000 +7fe3fb787fa903a6 +f84100187faceb78 +4e8004213b9c0001 +38600064e8410018 +4bffff744bfff479 +0300000000000000 +3c4c000100000a80 +7c0802a63842a6ac +f8010010fbe1fff8 +3fe0c800f821ffd1 +63ff080439200001 +7bff00207d231830 +7c60ff2a7c0004ac +614a08303d40c800 7c0004ac794a0020 386000647d20572a -4bfff1dd3f00c800 -6000000063180818 -3bc0ffff3ec2ffff -3b60ffff3b400000 -3b2000013b800000 -3ae280fc7b180020 -7c1df8003ad67cb8 -3c62ffff41810144 -38637dc07fc407b4 -600000004bffe74d +392000004bfff419 +7d20ff2a7c0004ac +4800203438210030 +0100000000000000 +3c4c000100000180 +7c0802a63842a63c +f8010010fbe1fff8 +3fe0c800f821ffd1 +63ff080439200001 +7bff00207d231830 +7c60ff2a7c0004ac +614a082c3d40c800 +7c0004ac794a0020 +386000647d20572a +392000004bfff3a9 +7d20ff2a7c0004ac +48001fc438210030 +0100000000000000 +3c4c000100000180 +3d20c8003842a5cc +7929002061291000 +7d404e2a7c0004ac +4d820020280a000e +f80100107c0802a6 +3940000ef821ffa1 +7d404f2a7c0004ac +38637d583c62ffff +600000004bffe8cd +e801001038210060 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +3d20c8003842a564 +7929002061291000 +7d404e2a7c0004ac +4d820020280a0001 +f80100107c0802a6 +39400001f821ffa1 +7d404f2a7c0004ac +38637d803c62ffff +600000004bffe865 +e801001038210060 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +7c0802a63842a4fc +f821ff3148001e49 +608408083c80c800 +7c0004ac78840020 +600000007c80262a +3c62ffff5484103a +38637da890828124 +4bffe8017c8407b4 +6000000060000000 +2c09000081228098 +6000000041820200 +2c1fffff83e28094 +3be0000040820008 +83a2809060000000 +408200142c1dffff +83a2812460000000 +7fbd01947fbd0e70 +7fa507b43c62ffff +38637dc87fe407b4 +600000004bffe7a5 +38637de03c62ffff +600000004bffe795 +392000013d40c800 +794a0020614a0814 +7d20572a7c0004ac +386000643f00c800 +3ea2ffff60000000 +3b4000003bc0ffff +3b8000003b60ffff +4bfff1c563180818 +3ae100603b200001 +3ab57ce03ac28124 +7c1df8007b180020 +3c62ffff41810140 +38637de87fc407b4 +600000004bffe725 7fc407b43c62ffff -4bffe73938637dd0 +4bffe71138637df8 2c1e000060000000 -3c62ffff40800128 -4bffe72138637df8 +3c62ffff40800124 +4bffe6f938637e20 38a0000160000000 3861006038800080 2c0300004bfff221 -408201507c691b78 +4082014c7c691b78 7d2307b4382100d0 7c0004ac48001d30 386000647f20c72a -4bfff12d3ab50001 -4180ffe87c15f800 -392000007c1fe000 -7d3cf85041800008 +4bfff12d3a940001 +4180ffe87c14f800 +7d3cf8507c1fe000 38a0000038800008 -7f9c4a1438610060 -38e000044bfff1c9 -38c1005c81370000 -394000007ce903a6 -390000007c641b78 -7d2901947d291670 -2c07ffff84e60004 -7ce74a1441820010 -7d083a14394a0001 -2c0a00004200ffe8 -7d0853d641820008 -7d290e7021290020 -7ce848507d290194 -408000082c070000 -7c0ad0407ce94050 -7c07d84041800018 -7ffefb7840800010 -7cfb3b787d5a5378 -4bffe6297ec3b378 -3bff000160000000 -7f95e3784bfffebc -600000004bffff38 -4bfffec483c280b8 -392000013d40c800 -794a0020614a0814 -7d20572a7c0004ac -3f80c80038600064 -639c08184bfff031 -3ba000013be00000 -7c1ff0007b9c0020 -7c0004ac4182fea4 -386000647fa0e72a -4bfff0053bff0001 -7fdef0f84bffffe4 -4bfffeac57c90ffe +7d20481e7ee3bb78 +4bfff1cd7f9c4a14 +38e0000481360000 +3940000038c1005c +7ce903a639000000 +7d2916707c641b78 +84e600047d290194 +418200102c07ffff +394a00017ce74a14 +4200ffe87d083a14 +418200082c0a0000 +212900207d0853d6 +7d2901947d290e70 +2c0700007ce84850 +7ce9405040800008 +418000187c0ad040 +408000107c07d840 +7d5a53787ffefb78 +7ea3ab787cfb3b78 +4bffe6013bff0001 +4bfffec060000000 +4bffff3c7f94e378 +83c280e060000000 +3d40c8004bfffec8 +614a081439200001 +7c0004ac794a0020 +3f80c8007d20572a +3be0000038600064 +639c08183ba00001 +7b9c00204bfff029 +4182fea87c1ff000 +7fa0e72a7c0004ac +3bff000138600064 +4bffffe44bfff009 +392000012c1e0000 +4bfffeac7d20481e 0100000000000000 -3c4c000100000b80 -7c0802a63842a254 -f821ff4148001b79 -3f02ffff3ee2ffff -3ea2ffff3f22ffff -3af74b703bc00000 -3b397a683b184b24 -57c3063e3ab57e08 -4bffedd13b400000 -3ba000003ac00000 -57df063e7fdc07b4 +3c4c000100000c80 +7c0802a63842a22c +f821ff4148001b7d +3ee2ffff3bc00000 +3f22ffff3f02ffff +3af74b983ea2ffff +3b397a903b184b4c +57c3063e3ab57e30 +3ac000003b400000 +7fdc07b43ba00000 +4bffedc157df063e 7fa407b438a00001 4bfff7157f83e378 7f06c3787ee7bb78 3880000138a00000 7f83e3787c7b1b78 7f23cb784bfff7e1 -600000004bffe515 +600000004bffe4ed 4080000c7c16d840 7f76db787fbaeb78 418200142c1d0007 @@ -1388,587 +1393,584 @@ f821ff4148001b79 4bffffa44bffedb1 7f84e3787f4507b4 3ba000007ea3ab78 -600000004bffe4d5 +600000004bffe4ad 4bffed417fe3fb78 4082003c7c1dd000 7f06c3787ee7bb78 3880000138a00000 3bde00017f83e378 7f23cb784bfff769 -600000004bffe49d +600000004bffe475 4082ff302c1e0004 -48001ac4382100c0 +48001ac8382100c0 3bbd00017fe3fb78 4bffffb44bffed41 0100000000000000 3c4c000100000b80 -7c0802a63842a124 -f821ff1148001a2d -4bfffb253be00000 +7c0802a63842a0fc +f821ff1148001a31 +4bfffb213be00000 7fc3f3787ffe07b4 7fc3f3784bffeecd 57e3063e4bffec1d 4bffeca93bff0001 4082ffdc2c1f0004 -3f80c8003c62ffff -3f00c80038637e20 -600000004bffe415 -3c62ffff4bfffbb1 -38637e383ee0c800 -4bffe3f9639c0804 -6318083c60000000 -6000000062f70840 -3e62ffff3e82ffff -3ba000013be00000 -7b9c00203ac00000 -7af700207b180020 -3a947e603aa280bc -57f0063e3a737e58 -3b40ffff7fb2f830 +3f60c8003c62ffff +3ee0c8003f00c800 +3e82ffff60000000 +3be000003e62ffff +637b080438637e48 +62f708406318083c +3ac000003ba00001 +3a947e883aa280e4 +600000004bffe3bd +7b1800207b7b0020 +3a737e807af70020 +3c62ffff4bfffb6d +4bffe39938637e60 +57f0063e60000000 +39c0ffff7fb2f830 3bc000003b200000 -7e1183787ffb07b4 -7e40e72a7c0004ac +7e1183787ffa07b4 +7e40df2a7c0004ac 7fa0c72a7c0004ac 392900017bc90020 -4200018c7d2903a6 -7ec0e72a7c0004ac -39e000007e038378 -39c000004bffebe5 -7dc407b438a00000 -4bfff5357f63db78 -408000087c0f1840 -7e238b787c6f1b78 -4bffec0539ce0001 -4082ffd42c0e0008 -4081000c7c0fc840 -7df97b787fdaf378 -2c1e00083bde0002 -7be917644082ff80 -2c1e00007fd5482e -2c1affff40800128 -7f64db784082011c -4bffe2f97e639b78 -3bc0ffff60000000 -7e40e72a7c0004ac -7fa0c72a7c0004ac -7bc900202c1e0000 -4080000839290001 -2c29000139200001 -408200f43929ffff -7ec0e72a7c0004ac -283f00043bff0001 -3c62ffff4082fef4 -38637a683f22ffff -4bffe2993f42ffff +420001887d2903a6 +7ec0df2a7c0004ac +3b8000007e038378 +4bffebe139e00000 +38a000007de407b4 +39ef00017f43d378 +7c1c18404bfff531 +7e238b787f83e01e +2c0f00084bffec09 +7c1cc8404082ffd8 +7fcef3784081000c +3bde00027f99e378 +4082ff842c1e0008 +7fd5482e7be91764 +408001282c1e0000 +4082011c2c0effff +7e639b787f44d378 +4bffe2d13bc0ffff +7c0004ac60000000 +7c0004ac7e40df2a +7bc900207fa0c72a +394000012c1e0000 +7d2a481e39290001 +3929ffff2c290001 +7c0004ac408200f4 +3bff00017ec0df2a +4082fef8283f0004 +3f22ffff3c62ffff +3ea2ffff3f42ffff +3bc000003ec2ffff +3b394b9838637a90 +3ab559543b5a4b4c +4bffe2593ad659c4 3c62ffff60000000 -38637e683ea2ffff -4bffe2813ec2ffff -3bc0000060000000 -3b5a4b243b394b70 -3ad659a03ab55930 -3ae0000057c3063e -3b0000004bffead5 +4bffe24938637e90 +57c3063e60000000 +3b0000003ae00000 7fdc07b43ba00000 -38a0000057df063e -7f83e3787fa407b4 -7f27cb784bfff419 -38a000007f46d378 -7c7b1b7838800000 -4bfff4e57f83e378 -4081000c7c1bb840 -7fb8eb787f77db78 -7fe3fb782c1d0007 -4bffeac541820044 -4bffffb03bbd0001 -7fa0bf2a7c0004ac -7f5ed3784bfffe6c -7f64db787fc507b4 -4bffe1d97e83a378 -4bfffee460000000 -7fa0bf2a7c0004ac -4bffea394bfffefc -7c1dc0003ba00000 -7f27cb7840820064 -38a000007f46d378 -7f83e37838800000 -4bfff45d3bde0001 -7ec6b3787ea7ab78 -3880000138a00001 -4bfff4457f83e378 -4082ff142c1e0004 -38637e803c62ffff -600000004bffe16d -4bfff89d4bfffbd5 -38600001382100f0 -7fe3fb7848001774 -4bffea0d3bbd0001 -000000004bffff8c -0000128001000000 -38429df03c4c0001 -390000107c0802a6 -392000017d0903a6 -9122807060000000 -3922807460000000 -480017013940ffff -95490004f821ff61 -390000104200fffc -392280b860000000 -7d0903a63940ffff +4bffeac957df063e +7fa407b438a00000 +4bfff41d7f83e378 +7f46d3787f27cb78 +3880000038a00000 +7f83e3787c7b1b78 +7c1bb8404bfff4e9 +7f77db784081000c +2c1d00077fb8eb78 +418200447fe3fb78 +3bbd00014bffeac9 +7c0004ac4bffffb0 +4bfffe707fa0bf2a +7fc507b47dde7378 +7e83a3787f44d378 +600000004bffe1b5 +7c0004ac4bfffee4 +4bfffefc7fa0bf2a +3ba000004bffea3d +408200647c1dc000 +7f46d3787f27cb78 +3880000038a00000 +3bde00017f83e378 +7ea7ab784bfff461 +38a000017ec6b378 +7f83e37838800001 +2c1e00044bfff449 +3c62ffff4082ff14 +4bffe14938637ea8 +4bfffbd960000000 +382100f04bfff89d +4800177c38600001 +3bbd00017fe3fb78 +4bffff8c4bffea11 +0100000000000000 +3c4c000100001280 +7c0802a638429dcc +f821ff6148001729 +3900001039200001 +7d0903a660000000 +6000000091228098 +3922809c3940ffff 4200fffc95490004 -3b8000013d20c800 -7929002061290844 -7f804f2a7c0004ac -3b2000023d20c800 -7929002061290848 -7f204f2a7c0004ac -3c62ffff3fc0c800 -38637e903c804000 -4bffe09963de0800 -7bde002060000000 -7c0004ac4bfff761 -386003e87f80f72a -4bffeac53be00000 -7fe0f72a7c0004ac -3f60c800386003e8 -7b7b00204bffeab1 -7fe0df2a7c0004ac -635a00043f40c800 -7c0004ac7b5a0020 -3fa0c8007fe0d72a -7bbd002063bd100c -7fe0ef2a7c0004ac -63de10103fc0c800 -7c0004ac7bde0020 -3f00c8007fe0f72a -631810003920000c -7c0004ac7b180020 -386000007d20c72a -4bffea456063c350 -7fe0ef2a7c0004ac -7fe0f72a7c0004ac -7c0004ac3920000e -386027107d20c72a -392002004bffea21 -7d20ef2a7c0004ac -7f20f72a7c0004ac -4bffe6513860000f -7fe0ef2a7c0004ac -7c0004ac39200003 -3860000f7d20f72a -392000064bffe635 -7d20ef2a7c0004ac +6000000039000010 +7d0903a63940ffff +95490004392280e0 +3d20c8004200fffc +612908443b800001 +7c0004ac79290020 +3d20c8007f804f2a +612908483b200002 +7c0004ac79290020 +3fc0c8007f204f2a +3c8040003c62ffff +63de080038637eb8 +600000004bffe075 +4bfff7617bde0020 7f80f72a7c0004ac -4bffe6193860000f -7c0004ac39200920 +3be00000386003e8 +7c0004ac4bffeac9 +386003e87fe0f72a +4bffeab53f60c800 +7c0004ac7b7b0020 +3f40c8007fe0df2a +7b5a0020635a0004 +7fe0d72a7c0004ac +63bd100c3fa0c800 +7c0004ac7bbd0020 +3fc0c8007fe0ef2a +7bde002063de1010 +7fe0f72a7c0004ac +3920000c3f00c800 +7b18002063181000 +7d20c72a7c0004ac +6063c35038600000 +7c0004ac4bffea49 +7c0004ac7fe0ef2a +3920000e7fe0f72a +7d20c72a7c0004ac +4bffea2538602710 +7c0004ac39200200 +7c0004ac7d20ef2a +3860000f7f20f72a +7c0004ac4bffe655 +392000037fe0ef2a +7d20f72a7c0004ac +4bffe6393860000f +7c0004ac39200006 7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bffe5fd -392004004bffe9a9 +3860000f7f80f72a +392009204bffe61d 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bffe5d938600003 -4bffe985386000c8 -4bfff66d4bfffad5 -3c6040003c800020 -60000000480006e9 -7c691b782c030000 -7c0004ac40820020 -7c0004ac7f80d72a -382100a07f80df2a -480015407d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bffe6013860000f +4bffe9ad386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bffe5dd +4bfffad94bffe989 +3c8000204bfff66d +480006e13c604000 +2c03000060000000 +408200207c691b78 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000880 -7c0802a638429b7c -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffde9938637eb0 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637eb83c62ffff -600000004bffde5d -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ec87ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b4382100a0 +38c0000048001548 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000088001000000 +38429b583c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ed83c62ffff +600000004bffde75 +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ed8 -0100000000000000 -3c4c000100000080 -7c0802a638429aac -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffde3938637ee0 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637ef0 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ee878c60020 +38637f007ca54b92 +000000004bffffa4 +0000008001000000 +38429a883c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffddbd -4bfffef97fe3fb78 -38637ef83c62ffff -600000004bffdda5 -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -38429a083c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffdd9938637f10 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffdd8138637f20 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384299e4 +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffdd79 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffdd29 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffdd5d42000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffdd0d7fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384298f83c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187f007bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637f00 -3c62ffff4bfffde5 -4bffdbc138637a68 -4bffdc2560000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a6384298d4 +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f28 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f28 +38637a903c62ffff +600000004bffdb9d +600000004bffdc09 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f10 -3c62ffff4bfffd8d -4bffdb6938637a68 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f10 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384297383c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f38 +38637a903c62ffff +600000004bffdb45 +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f387ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a638429714 +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f203c62ffff -4bffda397cbc2b78 -3c62ffff60000000 -4092000c38637f38 -38637f483c62ffff -600000004bffda1d -4bfffb597fc3f378 -38637f583c62ffff -600000004bffda05 -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f482e3b0000 +600000004bffda15 38637f603c62ffff -4bffd9817f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffd96938637f70 +3c62ffff4092000c +4bffd9f938637f70 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffd9e138637f80 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8005f57d3602a6 +7929002078ea0020 +639ce1003c62ffff +38637f887d295050 +7f9c4b927f9ee1d2 +600000004bffd95d +4bfffabd7f83e378 +38637f983c62ffff +600000004bffd945 +38637a903c62ffff +600000004bffd935 +600000004bffd9a1 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4005f5 +3c62ffff79290020 +7d29e050614ae100 +7fde51d238637fa0 +4bffd8997fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffd88138637f98 3c62ffff60000000 -4bffd95938637a68 -4bffd9bd60000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f78 -600000004bffd8bd -4bfff9f97fc3f378 -38637f703c62ffff -600000004bffd8a5 -38637a683c62ffff -600000004bffd895 -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384295003c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffd87138637a90 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384294e4 +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f887fc4f378 -600000004bffd80d -4bfff9497fe3fb78 -38637f583c62ffff +7c641b787f9c205e +38637fb03c62ffff 600000004bffd7f5 +4bfff9557fe3fb78 +38637f803c62ffff +600000004bffd7dd 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffd7a938637f98 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fb038800000 -600000004bffd77d -7be5f0823c62ffff -38637fc87fc4f378 -600000004bffd765 -38637fe03c62ffff -600000004bffd755 -3821008038600000 -48000d987c6307b4 -38637ff03c62ffff -600000004bffd735 -4bffffe038600001 -0100000000000000 -3c4c000100000480 -60000000384293d4 -6000000089228108 -2c09000039428100 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228100 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428100 -4e8000207d2057ea +4bffd79138637fc0 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fd8 +4bffd76978a5f082 +3c62ffff60000000 +7fc4f3787be5f082 +4bffd75138637ff0 +6000000060000000 +4bffd74138628008 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffd72138628018 +3860000160000000 +000000004bffffe0 +0000048001000000 +384293c03c4c0001 +6000000060000000 +3942812889228130 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e922812860000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94281285469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842934c -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384292ec -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428100 -9942810860000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942810060000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228108 -3920ff806108200c -7c0004ac79080020 -e92281007d2047aa -7d404faa7c0004ac -794ac202e9228100 -7c0004ac39290004 -e92281007d404faa -3929000c39400003 +384293383c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384292d83c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f942812860000000 +6000000039400000 +3d40001c99428130 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf9428128 +7d495392614a2000 +600000004182ffa0 +9922813039200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace9228128 +e92281287d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228100 +39400003e9228128 +7c0004ac3929000c +e92281287d404faa +7c0004ac39290010 +e92281287d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228100 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 -0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +000000004e800020 +0000000000000000 +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428fb4 -f821ffa1480008e9 +7c0802a638428fa4 +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1980,36 +1982,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428ee4 -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428ed4 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428e683c4c0001 -600000007c0802a6 -2b860010e9228000 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428e583c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922800860000000 +2b8600107caa2b78 +f9210020e9228028 +e922803060000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -2017,253 +2019,256 @@ e922800860000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428d74 -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b7368 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428d683c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b7374 +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028020 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c675243cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028048 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a7534 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942802060000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280207aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028048 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028048 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2801838610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280407de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -2314,15 +2319,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v index 14b291e..9f8030a 100644 --- a/litedram/generated/genesys2/litedram_core.v +++ b/litedram/generated/genesys2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:06:58 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:21 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [14:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [3:0] ddram_dm, - inout wire [31:0] ddram_dq, - inout wire [3:0] ddram_dqs_p, - inout wire [3:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [31:0] user_port_native_0_wdata_we, - input wire [255:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [255:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [3:0] ddram_dm, + inout wire [31:0] ddram_dq, + inout wire [3:0] ddram_dqs_p, + inout wire [3:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [31:0] user_port_native_0_wdata_we, + input wire [255:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [255:0] user_port_native_0_rdata_data ); @@ -69,2256 +69,2380 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; -wire iodelay_clk; -wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg k7ddrphy_rst_storage = 1'd0; -reg k7ddrphy_rst_re = 1'd0; -reg [3:0] k7ddrphy_dly_sel_storage = 4'd0; -reg k7ddrphy_dly_sel_re = 1'd0; -reg [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8; -reg k7ddrphy_half_sys8x_taps_re = 1'd0; -reg k7ddrphy_wlevel_en_storage = 1'd0; -reg k7ddrphy_wlevel_en_re = 1'd0; -reg k7ddrphy_wlevel_strobe_re = 1'd0; -wire k7ddrphy_wlevel_strobe_r; -reg k7ddrphy_wlevel_strobe_we = 1'd0; -reg k7ddrphy_wlevel_strobe_w = 1'd0; -reg k7ddrphy_cdly_rst_re = 1'd0; -wire k7ddrphy_cdly_rst_r; -reg k7ddrphy_cdly_rst_we = 1'd0; -reg k7ddrphy_cdly_rst_w = 1'd0; -reg k7ddrphy_cdly_inc_re = 1'd0; -wire k7ddrphy_cdly_inc_r; -reg k7ddrphy_cdly_inc_we = 1'd0; -reg k7ddrphy_cdly_inc_w = 1'd0; -reg k7ddrphy_rdly_dq_rst_re = 1'd0; -wire k7ddrphy_rdly_dq_rst_r; -reg k7ddrphy_rdly_dq_rst_we = 1'd0; -reg k7ddrphy_rdly_dq_rst_w = 1'd0; -reg k7ddrphy_rdly_dq_inc_re = 1'd0; -wire k7ddrphy_rdly_dq_inc_r; -reg k7ddrphy_rdly_dq_inc_we = 1'd0; -reg k7ddrphy_rdly_dq_inc_w = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire k7ddrphy_rdly_dq_bitslip_rst_r; -reg k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire k7ddrphy_rdly_dq_bitslip_r; -reg k7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg k7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg k7ddrphy_wdly_dq_rst_re = 1'd0; -wire k7ddrphy_wdly_dq_rst_r; -reg k7ddrphy_wdly_dq_rst_we = 1'd0; -reg k7ddrphy_wdly_dq_rst_w = 1'd0; -reg k7ddrphy_wdly_dq_inc_re = 1'd0; -wire k7ddrphy_wdly_dq_inc_r; -reg k7ddrphy_wdly_dq_inc_we = 1'd0; -reg k7ddrphy_wdly_dq_inc_w = 1'd0; -reg k7ddrphy_wdly_dqs_rst_re = 1'd0; -wire k7ddrphy_wdly_dqs_rst_r; -reg k7ddrphy_wdly_dqs_rst_we = 1'd0; -reg k7ddrphy_wdly_dqs_rst_w = 1'd0; -reg k7ddrphy_wdly_dqs_inc_re = 1'd0; -wire k7ddrphy_wdly_dqs_inc_r; -reg k7ddrphy_wdly_dqs_inc_we = 1'd0; -reg k7ddrphy_wdly_dqs_inc_w = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire k7ddrphy_wdly_dq_bitslip_rst_r; -reg k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire k7ddrphy_wdly_dq_bitslip_r; -reg k7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg k7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] k7ddrphy_rdphase_storage = 2'd1; -reg k7ddrphy_rdphase_re = 1'd0; -reg [1:0] k7ddrphy_wrphase_storage = 2'd2; -reg k7ddrphy_wrphase_re = 1'd0; -wire [14:0] k7ddrphy_dfi_p0_address; -wire [2:0] k7ddrphy_dfi_p0_bank; -wire k7ddrphy_dfi_p0_cas_n; -wire k7ddrphy_dfi_p0_cs_n; -wire k7ddrphy_dfi_p0_ras_n; -wire k7ddrphy_dfi_p0_we_n; -wire k7ddrphy_dfi_p0_cke; -wire k7ddrphy_dfi_p0_odt; -wire k7ddrphy_dfi_p0_reset_n; -wire k7ddrphy_dfi_p0_act_n; -wire [63:0] k7ddrphy_dfi_p0_wrdata; -wire k7ddrphy_dfi_p0_wrdata_en; -wire [7:0] k7ddrphy_dfi_p0_wrdata_mask; -wire k7ddrphy_dfi_p0_rddata_en; -reg [63:0] k7ddrphy_dfi_p0_rddata = 64'd0; -wire k7ddrphy_dfi_p0_rddata_valid; -wire [14:0] k7ddrphy_dfi_p1_address; -wire [2:0] k7ddrphy_dfi_p1_bank; -wire k7ddrphy_dfi_p1_cas_n; -wire k7ddrphy_dfi_p1_cs_n; -wire k7ddrphy_dfi_p1_ras_n; -wire k7ddrphy_dfi_p1_we_n; -wire k7ddrphy_dfi_p1_cke; -wire k7ddrphy_dfi_p1_odt; -wire k7ddrphy_dfi_p1_reset_n; -wire k7ddrphy_dfi_p1_act_n; -wire [63:0] k7ddrphy_dfi_p1_wrdata; -wire k7ddrphy_dfi_p1_wrdata_en; -wire [7:0] k7ddrphy_dfi_p1_wrdata_mask; -wire k7ddrphy_dfi_p1_rddata_en; -reg [63:0] k7ddrphy_dfi_p1_rddata = 64'd0; -wire k7ddrphy_dfi_p1_rddata_valid; -wire [14:0] k7ddrphy_dfi_p2_address; -wire [2:0] k7ddrphy_dfi_p2_bank; -wire k7ddrphy_dfi_p2_cas_n; -wire k7ddrphy_dfi_p2_cs_n; -wire k7ddrphy_dfi_p2_ras_n; -wire k7ddrphy_dfi_p2_we_n; -wire k7ddrphy_dfi_p2_cke; -wire k7ddrphy_dfi_p2_odt; -wire k7ddrphy_dfi_p2_reset_n; -wire k7ddrphy_dfi_p2_act_n; -wire [63:0] k7ddrphy_dfi_p2_wrdata; -wire k7ddrphy_dfi_p2_wrdata_en; -wire [7:0] k7ddrphy_dfi_p2_wrdata_mask; -wire k7ddrphy_dfi_p2_rddata_en; -reg [63:0] k7ddrphy_dfi_p2_rddata = 64'd0; -wire k7ddrphy_dfi_p2_rddata_valid; -wire [14:0] k7ddrphy_dfi_p3_address; -wire [2:0] k7ddrphy_dfi_p3_bank; -wire k7ddrphy_dfi_p3_cas_n; -wire k7ddrphy_dfi_p3_cs_n; -wire k7ddrphy_dfi_p3_ras_n; -wire k7ddrphy_dfi_p3_we_n; -wire k7ddrphy_dfi_p3_cke; -wire k7ddrphy_dfi_p3_odt; -wire k7ddrphy_dfi_p3_reset_n; -wire k7ddrphy_dfi_p3_act_n; -wire [63:0] k7ddrphy_dfi_p3_wrdata; -wire k7ddrphy_dfi_p3_wrdata_en; -wire [7:0] k7ddrphy_dfi_p3_wrdata_mask; -wire k7ddrphy_dfi_p3_rddata_en; -reg [63:0] k7ddrphy_dfi_p3_rddata = 64'd0; -wire k7ddrphy_dfi_p3_rddata_valid; -wire k7ddrphy_sd_clk_se_nodelay; -wire k7ddrphy_sd_clk_se_delayed; -wire [2:0] k7ddrphy_pads_ba; -wire k7ddrphy_oq0; -wire k7ddrphy_oq1; -wire k7ddrphy_oq2; -wire k7ddrphy_oq3; -wire k7ddrphy_oq4; -wire k7ddrphy_oq5; -wire k7ddrphy_oq6; -wire k7ddrphy_oq7; -wire k7ddrphy_oq8; -wire k7ddrphy_oq9; -wire k7ddrphy_oq10; -wire k7ddrphy_oq11; -wire k7ddrphy_oq12; -wire k7ddrphy_oq13; -wire k7ddrphy_oq14; -wire k7ddrphy_oq15; -wire k7ddrphy_oq16; -wire k7ddrphy_oq17; -wire k7ddrphy_oq18; -wire k7ddrphy_oq19; -wire k7ddrphy_oq20; -wire k7ddrphy_oq21; -wire k7ddrphy_oq22; -wire k7ddrphy_oq23; -wire k7ddrphy_oq24; -reg k7ddrphy_dqs_oe = 1'd0; -wire k7ddrphy_dqs_preamble; -wire k7ddrphy_dqs_postamble; -wire k7ddrphy_dqs_oe_delay_tappeddelayline; -reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg k7ddrphy_dqspattern0 = 1'd0; -reg k7ddrphy_dqspattern1 = 1'd0; -reg [7:0] k7ddrphy_dqspattern_o = 8'd0; -wire k7ddrphy_dqs_o_no_delay0; -wire k7ddrphy_dqs_o_delayed0; -wire k7ddrphy_dqs_t0; -reg [7:0] k7ddrphy_bitslip00 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r0 = 16'd0; -wire k7ddrphy0; -wire k7ddrphy_dqs_o_no_delay1; -wire k7ddrphy_dqs_o_delayed1; -wire k7ddrphy_dqs_t1; -reg [7:0] k7ddrphy_bitslip10 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r0 = 16'd0; -wire k7ddrphy1; -wire k7ddrphy_dqs_o_no_delay2; -wire k7ddrphy_dqs_o_delayed2; -wire k7ddrphy_dqs_t2; -reg [7:0] k7ddrphy_bitslip20 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r0 = 16'd0; -wire k7ddrphy2; -wire k7ddrphy_dqs_o_no_delay3; -wire k7ddrphy_dqs_o_delayed3; -wire k7ddrphy_dqs_t3; -reg [7:0] k7ddrphy_bitslip30 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r0 = 16'd0; -wire k7ddrphy3; -wire k7ddrphy_dm_o_nodelay0; -reg [7:0] k7ddrphy_bitslip01 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay1; -reg [7:0] k7ddrphy_bitslip11 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay2; -reg [7:0] k7ddrphy_bitslip21 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r1 = 16'd0; -wire k7ddrphy_dm_o_nodelay3; -reg [7:0] k7ddrphy_bitslip31 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r1 = 16'd0; -wire k7ddrphy_dq_oe; -wire k7ddrphy_dq_oe_delay_tappeddelayline; -reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire k7ddrphy_dq_o_nodelay0; -wire k7ddrphy_dq_o_delayed0; -wire k7ddrphy_dq_i_nodelay0; -wire k7ddrphy_dq_i_delayed0; -wire k7ddrphy_dq_t0; -reg [7:0] k7ddrphy_bitslip02 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip03; -reg [7:0] k7ddrphy_bitslip04 = 8'd0; -reg [2:0] k7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip0_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay1; -wire k7ddrphy_dq_o_delayed1; -wire k7ddrphy_dq_i_nodelay1; -wire k7ddrphy_dq_i_delayed1; -wire k7ddrphy_dq_t1; -reg [7:0] k7ddrphy_bitslip12 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip13; -reg [7:0] k7ddrphy_bitslip14 = 8'd0; -reg [2:0] k7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip1_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay2; -wire k7ddrphy_dq_o_delayed2; -wire k7ddrphy_dq_i_nodelay2; -wire k7ddrphy_dq_i_delayed2; -wire k7ddrphy_dq_t2; -reg [7:0] k7ddrphy_bitslip22 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip23; -reg [7:0] k7ddrphy_bitslip24 = 8'd0; -reg [2:0] k7ddrphy_bitslip2_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip2_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay3; -wire k7ddrphy_dq_o_delayed3; -wire k7ddrphy_dq_i_nodelay3; -wire k7ddrphy_dq_i_delayed3; -wire k7ddrphy_dq_t3; -reg [7:0] k7ddrphy_bitslip32 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value2 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r2 = 16'd0; -wire [7:0] k7ddrphy_bitslip33; -reg [7:0] k7ddrphy_bitslip34 = 8'd0; -reg [2:0] k7ddrphy_bitslip3_value3 = 3'd7; -reg [15:0] k7ddrphy_bitslip3_r3 = 16'd0; -wire k7ddrphy_dq_o_nodelay4; -wire k7ddrphy_dq_o_delayed4; -wire k7ddrphy_dq_i_nodelay4; -wire k7ddrphy_dq_i_delayed4; -wire k7ddrphy_dq_t4; -reg [7:0] k7ddrphy_bitslip40 = 8'd0; -reg [2:0] k7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip41; -reg [7:0] k7ddrphy_bitslip42 = 8'd0; -reg [2:0] k7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip4_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay5; -wire k7ddrphy_dq_o_delayed5; -wire k7ddrphy_dq_i_nodelay5; -wire k7ddrphy_dq_i_delayed5; -wire k7ddrphy_dq_t5; -reg [7:0] k7ddrphy_bitslip50 = 8'd0; -reg [2:0] k7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip51; -reg [7:0] k7ddrphy_bitslip52 = 8'd0; -reg [2:0] k7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip5_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay6; -wire k7ddrphy_dq_o_delayed6; -wire k7ddrphy_dq_i_nodelay6; -wire k7ddrphy_dq_i_delayed6; -wire k7ddrphy_dq_t6; -reg [7:0] k7ddrphy_bitslip60 = 8'd0; -reg [2:0] k7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip61; -reg [7:0] k7ddrphy_bitslip62 = 8'd0; -reg [2:0] k7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip6_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay7; -wire k7ddrphy_dq_o_delayed7; -wire k7ddrphy_dq_i_nodelay7; -wire k7ddrphy_dq_i_delayed7; -wire k7ddrphy_dq_t7; -reg [7:0] k7ddrphy_bitslip70 = 8'd0; -reg [2:0] k7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip71; -reg [7:0] k7ddrphy_bitslip72 = 8'd0; -reg [2:0] k7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip7_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay8; -wire k7ddrphy_dq_o_delayed8; -wire k7ddrphy_dq_i_nodelay8; -wire k7ddrphy_dq_i_delayed8; -wire k7ddrphy_dq_t8; -reg [7:0] k7ddrphy_bitslip80 = 8'd0; -reg [2:0] k7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip81; -reg [7:0] k7ddrphy_bitslip82 = 8'd0; -reg [2:0] k7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip8_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay9; -wire k7ddrphy_dq_o_delayed9; -wire k7ddrphy_dq_i_nodelay9; -wire k7ddrphy_dq_i_delayed9; -wire k7ddrphy_dq_t9; -reg [7:0] k7ddrphy_bitslip90 = 8'd0; -reg [2:0] k7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip91; -reg [7:0] k7ddrphy_bitslip92 = 8'd0; -reg [2:0] k7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip9_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay10; -wire k7ddrphy_dq_o_delayed10; -wire k7ddrphy_dq_i_nodelay10; -wire k7ddrphy_dq_i_delayed10; -wire k7ddrphy_dq_t10; -reg [7:0] k7ddrphy_bitslip100 = 8'd0; -reg [2:0] k7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip101; -reg [7:0] k7ddrphy_bitslip102 = 8'd0; -reg [2:0] k7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip10_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay11; -wire k7ddrphy_dq_o_delayed11; -wire k7ddrphy_dq_i_nodelay11; -wire k7ddrphy_dq_i_delayed11; -wire k7ddrphy_dq_t11; -reg [7:0] k7ddrphy_bitslip110 = 8'd0; -reg [2:0] k7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip111; -reg [7:0] k7ddrphy_bitslip112 = 8'd0; -reg [2:0] k7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip11_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay12; -wire k7ddrphy_dq_o_delayed12; -wire k7ddrphy_dq_i_nodelay12; -wire k7ddrphy_dq_i_delayed12; -wire k7ddrphy_dq_t12; -reg [7:0] k7ddrphy_bitslip120 = 8'd0; -reg [2:0] k7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip121; -reg [7:0] k7ddrphy_bitslip122 = 8'd0; -reg [2:0] k7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip12_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay13; -wire k7ddrphy_dq_o_delayed13; -wire k7ddrphy_dq_i_nodelay13; -wire k7ddrphy_dq_i_delayed13; -wire k7ddrphy_dq_t13; -reg [7:0] k7ddrphy_bitslip130 = 8'd0; -reg [2:0] k7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip131; -reg [7:0] k7ddrphy_bitslip132 = 8'd0; -reg [2:0] k7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip13_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay14; -wire k7ddrphy_dq_o_delayed14; -wire k7ddrphy_dq_i_nodelay14; -wire k7ddrphy_dq_i_delayed14; -wire k7ddrphy_dq_t14; -reg [7:0] k7ddrphy_bitslip140 = 8'd0; -reg [2:0] k7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip141; -reg [7:0] k7ddrphy_bitslip142 = 8'd0; -reg [2:0] k7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip14_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay15; -wire k7ddrphy_dq_o_delayed15; -wire k7ddrphy_dq_i_nodelay15; -wire k7ddrphy_dq_i_delayed15; -wire k7ddrphy_dq_t15; -reg [7:0] k7ddrphy_bitslip150 = 8'd0; -reg [2:0] k7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip151; -reg [7:0] k7ddrphy_bitslip152 = 8'd0; -reg [2:0] k7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip15_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay16; -wire k7ddrphy_dq_o_delayed16; -wire k7ddrphy_dq_i_nodelay16; -wire k7ddrphy_dq_i_delayed16; -wire k7ddrphy_dq_t16; -reg [7:0] k7ddrphy_bitslip160 = 8'd0; -reg [2:0] k7ddrphy_bitslip16_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip16_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip161; -reg [7:0] k7ddrphy_bitslip162 = 8'd0; -reg [2:0] k7ddrphy_bitslip16_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip16_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay17; -wire k7ddrphy_dq_o_delayed17; -wire k7ddrphy_dq_i_nodelay17; -wire k7ddrphy_dq_i_delayed17; -wire k7ddrphy_dq_t17; -reg [7:0] k7ddrphy_bitslip170 = 8'd0; -reg [2:0] k7ddrphy_bitslip17_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip17_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip171; -reg [7:0] k7ddrphy_bitslip172 = 8'd0; -reg [2:0] k7ddrphy_bitslip17_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip17_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay18; -wire k7ddrphy_dq_o_delayed18; -wire k7ddrphy_dq_i_nodelay18; -wire k7ddrphy_dq_i_delayed18; -wire k7ddrphy_dq_t18; -reg [7:0] k7ddrphy_bitslip180 = 8'd0; -reg [2:0] k7ddrphy_bitslip18_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip18_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip181; -reg [7:0] k7ddrphy_bitslip182 = 8'd0; -reg [2:0] k7ddrphy_bitslip18_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip18_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay19; -wire k7ddrphy_dq_o_delayed19; -wire k7ddrphy_dq_i_nodelay19; -wire k7ddrphy_dq_i_delayed19; -wire k7ddrphy_dq_t19; -reg [7:0] k7ddrphy_bitslip190 = 8'd0; -reg [2:0] k7ddrphy_bitslip19_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip19_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip191; -reg [7:0] k7ddrphy_bitslip192 = 8'd0; -reg [2:0] k7ddrphy_bitslip19_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip19_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay20; -wire k7ddrphy_dq_o_delayed20; -wire k7ddrphy_dq_i_nodelay20; -wire k7ddrphy_dq_i_delayed20; -wire k7ddrphy_dq_t20; -reg [7:0] k7ddrphy_bitslip200 = 8'd0; -reg [2:0] k7ddrphy_bitslip20_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip20_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip201; -reg [7:0] k7ddrphy_bitslip202 = 8'd0; -reg [2:0] k7ddrphy_bitslip20_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip20_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay21; -wire k7ddrphy_dq_o_delayed21; -wire k7ddrphy_dq_i_nodelay21; -wire k7ddrphy_dq_i_delayed21; -wire k7ddrphy_dq_t21; -reg [7:0] k7ddrphy_bitslip210 = 8'd0; -reg [2:0] k7ddrphy_bitslip21_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip21_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip211; -reg [7:0] k7ddrphy_bitslip212 = 8'd0; -reg [2:0] k7ddrphy_bitslip21_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip21_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay22; -wire k7ddrphy_dq_o_delayed22; -wire k7ddrphy_dq_i_nodelay22; -wire k7ddrphy_dq_i_delayed22; -wire k7ddrphy_dq_t22; -reg [7:0] k7ddrphy_bitslip220 = 8'd0; -reg [2:0] k7ddrphy_bitslip22_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip22_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip221; -reg [7:0] k7ddrphy_bitslip222 = 8'd0; -reg [2:0] k7ddrphy_bitslip22_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip22_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay23; -wire k7ddrphy_dq_o_delayed23; -wire k7ddrphy_dq_i_nodelay23; -wire k7ddrphy_dq_i_delayed23; -wire k7ddrphy_dq_t23; -reg [7:0] k7ddrphy_bitslip230 = 8'd0; -reg [2:0] k7ddrphy_bitslip23_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip23_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip231; -reg [7:0] k7ddrphy_bitslip232 = 8'd0; -reg [2:0] k7ddrphy_bitslip23_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip23_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay24; -wire k7ddrphy_dq_o_delayed24; -wire k7ddrphy_dq_i_nodelay24; -wire k7ddrphy_dq_i_delayed24; -wire k7ddrphy_dq_t24; -reg [7:0] k7ddrphy_bitslip240 = 8'd0; -reg [2:0] k7ddrphy_bitslip24_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip24_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip241; -reg [7:0] k7ddrphy_bitslip242 = 8'd0; -reg [2:0] k7ddrphy_bitslip24_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip24_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay25; -wire k7ddrphy_dq_o_delayed25; -wire k7ddrphy_dq_i_nodelay25; -wire k7ddrphy_dq_i_delayed25; -wire k7ddrphy_dq_t25; -reg [7:0] k7ddrphy_bitslip250 = 8'd0; -reg [2:0] k7ddrphy_bitslip25_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip25_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip251; -reg [7:0] k7ddrphy_bitslip252 = 8'd0; -reg [2:0] k7ddrphy_bitslip25_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip25_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay26; -wire k7ddrphy_dq_o_delayed26; -wire k7ddrphy_dq_i_nodelay26; -wire k7ddrphy_dq_i_delayed26; -wire k7ddrphy_dq_t26; -reg [7:0] k7ddrphy_bitslip260 = 8'd0; -reg [2:0] k7ddrphy_bitslip26_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip26_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip261; -reg [7:0] k7ddrphy_bitslip262 = 8'd0; -reg [2:0] k7ddrphy_bitslip26_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip26_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay27; -wire k7ddrphy_dq_o_delayed27; -wire k7ddrphy_dq_i_nodelay27; -wire k7ddrphy_dq_i_delayed27; -wire k7ddrphy_dq_t27; -reg [7:0] k7ddrphy_bitslip270 = 8'd0; -reg [2:0] k7ddrphy_bitslip27_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip27_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip271; -reg [7:0] k7ddrphy_bitslip272 = 8'd0; -reg [2:0] k7ddrphy_bitslip27_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip27_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay28; -wire k7ddrphy_dq_o_delayed28; -wire k7ddrphy_dq_i_nodelay28; -wire k7ddrphy_dq_i_delayed28; -wire k7ddrphy_dq_t28; -reg [7:0] k7ddrphy_bitslip280 = 8'd0; -reg [2:0] k7ddrphy_bitslip28_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip28_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip281; -reg [7:0] k7ddrphy_bitslip282 = 8'd0; -reg [2:0] k7ddrphy_bitslip28_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip28_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay29; -wire k7ddrphy_dq_o_delayed29; -wire k7ddrphy_dq_i_nodelay29; -wire k7ddrphy_dq_i_delayed29; -wire k7ddrphy_dq_t29; -reg [7:0] k7ddrphy_bitslip290 = 8'd0; -reg [2:0] k7ddrphy_bitslip29_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip29_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip291; -reg [7:0] k7ddrphy_bitslip292 = 8'd0; -reg [2:0] k7ddrphy_bitslip29_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip29_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay30; -wire k7ddrphy_dq_o_delayed30; -wire k7ddrphy_dq_i_nodelay30; -wire k7ddrphy_dq_i_delayed30; -wire k7ddrphy_dq_t30; -reg [7:0] k7ddrphy_bitslip300 = 8'd0; -reg [2:0] k7ddrphy_bitslip30_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip30_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip301; -reg [7:0] k7ddrphy_bitslip302 = 8'd0; -reg [2:0] k7ddrphy_bitslip30_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip30_r1 = 16'd0; -wire k7ddrphy_dq_o_nodelay31; -wire k7ddrphy_dq_o_delayed31; -wire k7ddrphy_dq_i_nodelay31; -wire k7ddrphy_dq_i_delayed31; -wire k7ddrphy_dq_t31; -reg [7:0] k7ddrphy_bitslip310 = 8'd0; -reg [2:0] k7ddrphy_bitslip31_value0 = 3'd7; -reg [15:0] k7ddrphy_bitslip31_r0 = 16'd0; -wire [7:0] k7ddrphy_bitslip311; -reg [7:0] k7ddrphy_bitslip312 = 8'd0; -reg [2:0] k7ddrphy_bitslip31_value1 = 3'd7; -reg [15:0] k7ddrphy_bitslip31_r1 = 16'd0; -reg k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [63:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [7:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [63:0] litedramcore_slave_p0_rddata = 64'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [63:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [7:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [63:0] litedramcore_slave_p1_rddata = 64'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [63:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [7:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [63:0] litedramcore_slave_p2_rddata = 64'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [63:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [7:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [63:0] litedramcore_slave_p3_rddata = 64'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [63:0] litedramcore_master_p0_wrdata = 64'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [63:0] litedramcore_master_p1_wrdata = 64'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [14:0] litedramcore_master_p2_address = 15'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [63:0] litedramcore_master_p2_wrdata = 64'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p2_wrdata_mask = 8'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [14:0] litedramcore_master_p3_address = 15'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [63:0] litedramcore_master_p3_wrdata = 64'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p3_wrdata_mask = 8'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [255:0] litedramcore_interface_wdata = 256'd0; -reg [31:0] litedramcore_interface_wdata_we = 32'd0; -wire [255:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [14:0] litedramcore_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [14:0] litedramcore_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [14:0] litedramcore_nop_a = 15'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [255:0] user_port_wdata_payload_data; -wire [31:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [255:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [3:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [3:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_r; -reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_r; -reg csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_w; -reg csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_r; -reg csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_r; -reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_r; -reg csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_w; -reg csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_r; -reg csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata1_r; -reg csrbank2_dfii_pi2_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata1_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata1_r; -reg csrbank2_dfii_pi2_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata1_w; -reg csrbank2_dfii_pi2_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata0_r; -reg csrbank2_dfii_pi2_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata0_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata1_r; -reg csrbank2_dfii_pi3_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata1_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata1_r; -reg csrbank2_dfii_pi3_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata1_w; -reg csrbank2_dfii_pi3_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata0_r; -reg csrbank2_dfii_pi3_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata0_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [14:0] array_muxed15 = 15'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [14:0] array_muxed22 = 15'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg rst_1 = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire reset; +reg power_down = 1'd0; +wire locked; +wire clkin; +wire clkout0; +wire clkout_buf0; +wire clkout1; +wire clkout_buf1; +wire clkout2; +wire clkout_buf2; +wire clkout3; +wire clkout_buf3; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg k7ddrphy_rst_storage = 1'd0; +reg k7ddrphy_rst_re = 1'd0; +reg [3:0] k7ddrphy_dly_sel_storage = 4'd0; +reg k7ddrphy_dly_sel_re = 1'd0; +reg [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8; +reg k7ddrphy_half_sys8x_taps_re = 1'd0; +reg k7ddrphy_wlevel_en_storage = 1'd0; +reg k7ddrphy_wlevel_en_re = 1'd0; +reg k7ddrphy_wlevel_strobe_re = 1'd0; +wire k7ddrphy_wlevel_strobe_r; +reg k7ddrphy_wlevel_strobe_we = 1'd0; +reg k7ddrphy_wlevel_strobe_w = 1'd0; +reg k7ddrphy_cdly_rst_re = 1'd0; +wire k7ddrphy_cdly_rst_r; +reg k7ddrphy_cdly_rst_we = 1'd0; +reg k7ddrphy_cdly_rst_w = 1'd0; +reg k7ddrphy_cdly_inc_re = 1'd0; +wire k7ddrphy_cdly_inc_r; +reg k7ddrphy_cdly_inc_we = 1'd0; +reg k7ddrphy_cdly_inc_w = 1'd0; +reg k7ddrphy_rdly_dq_rst_re = 1'd0; +wire k7ddrphy_rdly_dq_rst_r; +reg k7ddrphy_rdly_dq_rst_we = 1'd0; +reg k7ddrphy_rdly_dq_rst_w = 1'd0; +reg k7ddrphy_rdly_dq_inc_re = 1'd0; +wire k7ddrphy_rdly_dq_inc_r; +reg k7ddrphy_rdly_dq_inc_we = 1'd0; +reg k7ddrphy_rdly_dq_inc_w = 1'd0; +reg k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire k7ddrphy_rdly_dq_bitslip_rst_r; +reg k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg k7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire k7ddrphy_rdly_dq_bitslip_r; +reg k7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg k7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg k7ddrphy_wdly_dq_rst_re = 1'd0; +wire k7ddrphy_wdly_dq_rst_r; +reg k7ddrphy_wdly_dq_rst_we = 1'd0; +reg k7ddrphy_wdly_dq_rst_w = 1'd0; +reg k7ddrphy_wdly_dq_inc_re = 1'd0; +wire k7ddrphy_wdly_dq_inc_r; +reg k7ddrphy_wdly_dq_inc_we = 1'd0; +reg k7ddrphy_wdly_dq_inc_w = 1'd0; +reg k7ddrphy_wdly_dqs_rst_re = 1'd0; +wire k7ddrphy_wdly_dqs_rst_r; +reg k7ddrphy_wdly_dqs_rst_we = 1'd0; +reg k7ddrphy_wdly_dqs_rst_w = 1'd0; +reg k7ddrphy_wdly_dqs_inc_re = 1'd0; +wire k7ddrphy_wdly_dqs_inc_r; +reg k7ddrphy_wdly_dqs_inc_we = 1'd0; +reg k7ddrphy_wdly_dqs_inc_w = 1'd0; +reg k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire k7ddrphy_wdly_dq_bitslip_rst_r; +reg k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg k7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire k7ddrphy_wdly_dq_bitslip_r; +reg k7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg k7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] k7ddrphy_rdphase_storage = 2'd1; +reg k7ddrphy_rdphase_re = 1'd0; +reg [1:0] k7ddrphy_wrphase_storage = 2'd2; +reg k7ddrphy_wrphase_re = 1'd0; +wire [14:0] k7ddrphy_dfi_p0_address; +wire [2:0] k7ddrphy_dfi_p0_bank; +wire k7ddrphy_dfi_p0_cas_n; +wire k7ddrphy_dfi_p0_cs_n; +wire k7ddrphy_dfi_p0_ras_n; +wire k7ddrphy_dfi_p0_we_n; +wire k7ddrphy_dfi_p0_cke; +wire k7ddrphy_dfi_p0_odt; +wire k7ddrphy_dfi_p0_reset_n; +wire k7ddrphy_dfi_p0_act_n; +wire [63:0] k7ddrphy_dfi_p0_wrdata; +wire k7ddrphy_dfi_p0_wrdata_en; +wire [7:0] k7ddrphy_dfi_p0_wrdata_mask; +wire k7ddrphy_dfi_p0_rddata_en; +reg [63:0] k7ddrphy_dfi_p0_rddata = 64'd0; +wire k7ddrphy_dfi_p0_rddata_valid; +wire [14:0] k7ddrphy_dfi_p1_address; +wire [2:0] k7ddrphy_dfi_p1_bank; +wire k7ddrphy_dfi_p1_cas_n; +wire k7ddrphy_dfi_p1_cs_n; +wire k7ddrphy_dfi_p1_ras_n; +wire k7ddrphy_dfi_p1_we_n; +wire k7ddrphy_dfi_p1_cke; +wire k7ddrphy_dfi_p1_odt; +wire k7ddrphy_dfi_p1_reset_n; +wire k7ddrphy_dfi_p1_act_n; +wire [63:0] k7ddrphy_dfi_p1_wrdata; +wire k7ddrphy_dfi_p1_wrdata_en; +wire [7:0] k7ddrphy_dfi_p1_wrdata_mask; +wire k7ddrphy_dfi_p1_rddata_en; +reg [63:0] k7ddrphy_dfi_p1_rddata = 64'd0; +wire k7ddrphy_dfi_p1_rddata_valid; +wire [14:0] k7ddrphy_dfi_p2_address; +wire [2:0] k7ddrphy_dfi_p2_bank; +wire k7ddrphy_dfi_p2_cas_n; +wire k7ddrphy_dfi_p2_cs_n; +wire k7ddrphy_dfi_p2_ras_n; +wire k7ddrphy_dfi_p2_we_n; +wire k7ddrphy_dfi_p2_cke; +wire k7ddrphy_dfi_p2_odt; +wire k7ddrphy_dfi_p2_reset_n; +wire k7ddrphy_dfi_p2_act_n; +wire [63:0] k7ddrphy_dfi_p2_wrdata; +wire k7ddrphy_dfi_p2_wrdata_en; +wire [7:0] k7ddrphy_dfi_p2_wrdata_mask; +wire k7ddrphy_dfi_p2_rddata_en; +reg [63:0] k7ddrphy_dfi_p2_rddata = 64'd0; +wire k7ddrphy_dfi_p2_rddata_valid; +wire [14:0] k7ddrphy_dfi_p3_address; +wire [2:0] k7ddrphy_dfi_p3_bank; +wire k7ddrphy_dfi_p3_cas_n; +wire k7ddrphy_dfi_p3_cs_n; +wire k7ddrphy_dfi_p3_ras_n; +wire k7ddrphy_dfi_p3_we_n; +wire k7ddrphy_dfi_p3_cke; +wire k7ddrphy_dfi_p3_odt; +wire k7ddrphy_dfi_p3_reset_n; +wire k7ddrphy_dfi_p3_act_n; +wire [63:0] k7ddrphy_dfi_p3_wrdata; +wire k7ddrphy_dfi_p3_wrdata_en; +wire [7:0] k7ddrphy_dfi_p3_wrdata_mask; +wire k7ddrphy_dfi_p3_rddata_en; +reg [63:0] k7ddrphy_dfi_p3_rddata = 64'd0; +wire k7ddrphy_dfi_p3_rddata_valid; +wire k7ddrphy_sd_clk_se_nodelay; +wire k7ddrphy_sd_clk_se_delayed; +wire [2:0] k7ddrphy_pads_ba; +wire k7ddrphy_oq0; +wire k7ddrphy_oq1; +wire k7ddrphy_oq2; +wire k7ddrphy_oq3; +wire k7ddrphy_oq4; +wire k7ddrphy_oq5; +wire k7ddrphy_oq6; +wire k7ddrphy_oq7; +wire k7ddrphy_oq8; +wire k7ddrphy_oq9; +wire k7ddrphy_oq10; +wire k7ddrphy_oq11; +wire k7ddrphy_oq12; +wire k7ddrphy_oq13; +wire k7ddrphy_oq14; +wire k7ddrphy_oq15; +wire k7ddrphy_oq16; +wire k7ddrphy_oq17; +wire k7ddrphy_oq18; +wire k7ddrphy_oq19; +wire k7ddrphy_oq20; +wire k7ddrphy_oq21; +wire k7ddrphy_oq22; +wire k7ddrphy_oq23; +wire k7ddrphy_oq24; +reg k7ddrphy_dqs_oe = 1'd0; +wire k7ddrphy_dqs_preamble; +wire k7ddrphy_dqs_postamble; +wire k7ddrphy_dqs_oe_delay_tappeddelayline; +reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg k7ddrphy_dqspattern0 = 1'd0; +reg k7ddrphy_dqspattern1 = 1'd0; +reg [7:0] k7ddrphy_dqspattern_o = 8'd0; +wire k7ddrphy_dqs_o_no_delay0; +wire k7ddrphy_dqs_o_delayed0; +wire k7ddrphy_dqs_t0; +reg [7:0] k7ddrphy_bitslip00 = 8'd0; +reg [2:0] k7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip0_r0 = 16'd0; +wire k7ddrphy0; +wire k7ddrphy_dqs_o_no_delay1; +wire k7ddrphy_dqs_o_delayed1; +wire k7ddrphy_dqs_t1; +reg [7:0] k7ddrphy_bitslip10 = 8'd0; +reg [2:0] k7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip1_r0 = 16'd0; +wire k7ddrphy1; +wire k7ddrphy_dqs_o_no_delay2; +wire k7ddrphy_dqs_o_delayed2; +wire k7ddrphy_dqs_t2; +reg [7:0] k7ddrphy_bitslip20 = 8'd0; +reg [2:0] k7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip2_r0 = 16'd0; +wire k7ddrphy2; +wire k7ddrphy_dqs_o_no_delay3; +wire k7ddrphy_dqs_o_delayed3; +wire k7ddrphy_dqs_t3; +reg [7:0] k7ddrphy_bitslip30 = 8'd0; +reg [2:0] k7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip3_r0 = 16'd0; +wire k7ddrphy3; +wire k7ddrphy_dm_o_nodelay0; +reg [7:0] k7ddrphy_bitslip01 = 8'd0; +reg [2:0] k7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip0_r1 = 16'd0; +wire k7ddrphy_dm_o_nodelay1; +reg [7:0] k7ddrphy_bitslip11 = 8'd0; +reg [2:0] k7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip1_r1 = 16'd0; +wire k7ddrphy_dm_o_nodelay2; +reg [7:0] k7ddrphy_bitslip21 = 8'd0; +reg [2:0] k7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip2_r1 = 16'd0; +wire k7ddrphy_dm_o_nodelay3; +reg [7:0] k7ddrphy_bitslip31 = 8'd0; +reg [2:0] k7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip3_r1 = 16'd0; +wire k7ddrphy_dq_oe; +wire k7ddrphy_dq_oe_delay_tappeddelayline; +reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire k7ddrphy_dq_o_nodelay0; +wire k7ddrphy_dq_o_delayed0; +wire k7ddrphy_dq_i_nodelay0; +wire k7ddrphy_dq_i_delayed0; +wire k7ddrphy_dq_t0; +reg [7:0] k7ddrphy_bitslip02 = 8'd0; +reg [2:0] k7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] k7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] k7ddrphy_bitslip03; +reg [7:0] k7ddrphy_bitslip04 = 8'd0; +reg [2:0] k7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] k7ddrphy_bitslip0_r3 = 16'd0; +wire k7ddrphy_dq_o_nodelay1; +wire k7ddrphy_dq_o_delayed1; +wire k7ddrphy_dq_i_nodelay1; +wire k7ddrphy_dq_i_delayed1; +wire k7ddrphy_dq_t1; +reg [7:0] k7ddrphy_bitslip12 = 8'd0; +reg [2:0] k7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] k7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] k7ddrphy_bitslip13; +reg [7:0] k7ddrphy_bitslip14 = 8'd0; +reg [2:0] k7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] k7ddrphy_bitslip1_r3 = 16'd0; +wire k7ddrphy_dq_o_nodelay2; +wire k7ddrphy_dq_o_delayed2; +wire k7ddrphy_dq_i_nodelay2; +wire k7ddrphy_dq_i_delayed2; +wire k7ddrphy_dq_t2; +reg [7:0] k7ddrphy_bitslip22 = 8'd0; +reg [2:0] k7ddrphy_bitslip2_value2 = 3'd7; +reg [15:0] k7ddrphy_bitslip2_r2 = 16'd0; +wire [7:0] k7ddrphy_bitslip23; +reg [7:0] k7ddrphy_bitslip24 = 8'd0; +reg [2:0] k7ddrphy_bitslip2_value3 = 3'd7; +reg [15:0] k7ddrphy_bitslip2_r3 = 16'd0; +wire k7ddrphy_dq_o_nodelay3; +wire k7ddrphy_dq_o_delayed3; +wire k7ddrphy_dq_i_nodelay3; +wire k7ddrphy_dq_i_delayed3; +wire k7ddrphy_dq_t3; +reg [7:0] k7ddrphy_bitslip32 = 8'd0; +reg [2:0] k7ddrphy_bitslip3_value2 = 3'd7; +reg [15:0] k7ddrphy_bitslip3_r2 = 16'd0; +wire [7:0] k7ddrphy_bitslip33; +reg [7:0] k7ddrphy_bitslip34 = 8'd0; +reg [2:0] k7ddrphy_bitslip3_value3 = 3'd7; +reg [15:0] k7ddrphy_bitslip3_r3 = 16'd0; +wire k7ddrphy_dq_o_nodelay4; +wire k7ddrphy_dq_o_delayed4; +wire k7ddrphy_dq_i_nodelay4; +wire k7ddrphy_dq_i_delayed4; +wire k7ddrphy_dq_t4; +reg [7:0] k7ddrphy_bitslip40 = 8'd0; +reg [2:0] k7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip41; +reg [7:0] k7ddrphy_bitslip42 = 8'd0; +reg [2:0] k7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip4_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay5; +wire k7ddrphy_dq_o_delayed5; +wire k7ddrphy_dq_i_nodelay5; +wire k7ddrphy_dq_i_delayed5; +wire k7ddrphy_dq_t5; +reg [7:0] k7ddrphy_bitslip50 = 8'd0; +reg [2:0] k7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip51; +reg [7:0] k7ddrphy_bitslip52 = 8'd0; +reg [2:0] k7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip5_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay6; +wire k7ddrphy_dq_o_delayed6; +wire k7ddrphy_dq_i_nodelay6; +wire k7ddrphy_dq_i_delayed6; +wire k7ddrphy_dq_t6; +reg [7:0] k7ddrphy_bitslip60 = 8'd0; +reg [2:0] k7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip61; +reg [7:0] k7ddrphy_bitslip62 = 8'd0; +reg [2:0] k7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip6_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay7; +wire k7ddrphy_dq_o_delayed7; +wire k7ddrphy_dq_i_nodelay7; +wire k7ddrphy_dq_i_delayed7; +wire k7ddrphy_dq_t7; +reg [7:0] k7ddrphy_bitslip70 = 8'd0; +reg [2:0] k7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip71; +reg [7:0] k7ddrphy_bitslip72 = 8'd0; +reg [2:0] k7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip7_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay8; +wire k7ddrphy_dq_o_delayed8; +wire k7ddrphy_dq_i_nodelay8; +wire k7ddrphy_dq_i_delayed8; +wire k7ddrphy_dq_t8; +reg [7:0] k7ddrphy_bitslip80 = 8'd0; +reg [2:0] k7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip81; +reg [7:0] k7ddrphy_bitslip82 = 8'd0; +reg [2:0] k7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip8_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay9; +wire k7ddrphy_dq_o_delayed9; +wire k7ddrphy_dq_i_nodelay9; +wire k7ddrphy_dq_i_delayed9; +wire k7ddrphy_dq_t9; +reg [7:0] k7ddrphy_bitslip90 = 8'd0; +reg [2:0] k7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip91; +reg [7:0] k7ddrphy_bitslip92 = 8'd0; +reg [2:0] k7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip9_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay10; +wire k7ddrphy_dq_o_delayed10; +wire k7ddrphy_dq_i_nodelay10; +wire k7ddrphy_dq_i_delayed10; +wire k7ddrphy_dq_t10; +reg [7:0] k7ddrphy_bitslip100 = 8'd0; +reg [2:0] k7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip101; +reg [7:0] k7ddrphy_bitslip102 = 8'd0; +reg [2:0] k7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip10_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay11; +wire k7ddrphy_dq_o_delayed11; +wire k7ddrphy_dq_i_nodelay11; +wire k7ddrphy_dq_i_delayed11; +wire k7ddrphy_dq_t11; +reg [7:0] k7ddrphy_bitslip110 = 8'd0; +reg [2:0] k7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip111; +reg [7:0] k7ddrphy_bitslip112 = 8'd0; +reg [2:0] k7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip11_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay12; +wire k7ddrphy_dq_o_delayed12; +wire k7ddrphy_dq_i_nodelay12; +wire k7ddrphy_dq_i_delayed12; +wire k7ddrphy_dq_t12; +reg [7:0] k7ddrphy_bitslip120 = 8'd0; +reg [2:0] k7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip121; +reg [7:0] k7ddrphy_bitslip122 = 8'd0; +reg [2:0] k7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip12_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay13; +wire k7ddrphy_dq_o_delayed13; +wire k7ddrphy_dq_i_nodelay13; +wire k7ddrphy_dq_i_delayed13; +wire k7ddrphy_dq_t13; +reg [7:0] k7ddrphy_bitslip130 = 8'd0; +reg [2:0] k7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip131; +reg [7:0] k7ddrphy_bitslip132 = 8'd0; +reg [2:0] k7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip13_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay14; +wire k7ddrphy_dq_o_delayed14; +wire k7ddrphy_dq_i_nodelay14; +wire k7ddrphy_dq_i_delayed14; +wire k7ddrphy_dq_t14; +reg [7:0] k7ddrphy_bitslip140 = 8'd0; +reg [2:0] k7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip141; +reg [7:0] k7ddrphy_bitslip142 = 8'd0; +reg [2:0] k7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip14_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay15; +wire k7ddrphy_dq_o_delayed15; +wire k7ddrphy_dq_i_nodelay15; +wire k7ddrphy_dq_i_delayed15; +wire k7ddrphy_dq_t15; +reg [7:0] k7ddrphy_bitslip150 = 8'd0; +reg [2:0] k7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip151; +reg [7:0] k7ddrphy_bitslip152 = 8'd0; +reg [2:0] k7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip15_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay16; +wire k7ddrphy_dq_o_delayed16; +wire k7ddrphy_dq_i_nodelay16; +wire k7ddrphy_dq_i_delayed16; +wire k7ddrphy_dq_t16; +reg [7:0] k7ddrphy_bitslip160 = 8'd0; +reg [2:0] k7ddrphy_bitslip16_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip16_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip161; +reg [7:0] k7ddrphy_bitslip162 = 8'd0; +reg [2:0] k7ddrphy_bitslip16_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip16_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay17; +wire k7ddrphy_dq_o_delayed17; +wire k7ddrphy_dq_i_nodelay17; +wire k7ddrphy_dq_i_delayed17; +wire k7ddrphy_dq_t17; +reg [7:0] k7ddrphy_bitslip170 = 8'd0; +reg [2:0] k7ddrphy_bitslip17_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip17_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip171; +reg [7:0] k7ddrphy_bitslip172 = 8'd0; +reg [2:0] k7ddrphy_bitslip17_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip17_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay18; +wire k7ddrphy_dq_o_delayed18; +wire k7ddrphy_dq_i_nodelay18; +wire k7ddrphy_dq_i_delayed18; +wire k7ddrphy_dq_t18; +reg [7:0] k7ddrphy_bitslip180 = 8'd0; +reg [2:0] k7ddrphy_bitslip18_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip18_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip181; +reg [7:0] k7ddrphy_bitslip182 = 8'd0; +reg [2:0] k7ddrphy_bitslip18_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip18_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay19; +wire k7ddrphy_dq_o_delayed19; +wire k7ddrphy_dq_i_nodelay19; +wire k7ddrphy_dq_i_delayed19; +wire k7ddrphy_dq_t19; +reg [7:0] k7ddrphy_bitslip190 = 8'd0; +reg [2:0] k7ddrphy_bitslip19_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip19_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip191; +reg [7:0] k7ddrphy_bitslip192 = 8'd0; +reg [2:0] k7ddrphy_bitslip19_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip19_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay20; +wire k7ddrphy_dq_o_delayed20; +wire k7ddrphy_dq_i_nodelay20; +wire k7ddrphy_dq_i_delayed20; +wire k7ddrphy_dq_t20; +reg [7:0] k7ddrphy_bitslip200 = 8'd0; +reg [2:0] k7ddrphy_bitslip20_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip20_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip201; +reg [7:0] k7ddrphy_bitslip202 = 8'd0; +reg [2:0] k7ddrphy_bitslip20_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip20_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay21; +wire k7ddrphy_dq_o_delayed21; +wire k7ddrphy_dq_i_nodelay21; +wire k7ddrphy_dq_i_delayed21; +wire k7ddrphy_dq_t21; +reg [7:0] k7ddrphy_bitslip210 = 8'd0; +reg [2:0] k7ddrphy_bitslip21_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip21_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip211; +reg [7:0] k7ddrphy_bitslip212 = 8'd0; +reg [2:0] k7ddrphy_bitslip21_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip21_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay22; +wire k7ddrphy_dq_o_delayed22; +wire k7ddrphy_dq_i_nodelay22; +wire k7ddrphy_dq_i_delayed22; +wire k7ddrphy_dq_t22; +reg [7:0] k7ddrphy_bitslip220 = 8'd0; +reg [2:0] k7ddrphy_bitslip22_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip22_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip221; +reg [7:0] k7ddrphy_bitslip222 = 8'd0; +reg [2:0] k7ddrphy_bitslip22_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip22_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay23; +wire k7ddrphy_dq_o_delayed23; +wire k7ddrphy_dq_i_nodelay23; +wire k7ddrphy_dq_i_delayed23; +wire k7ddrphy_dq_t23; +reg [7:0] k7ddrphy_bitslip230 = 8'd0; +reg [2:0] k7ddrphy_bitslip23_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip23_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip231; +reg [7:0] k7ddrphy_bitslip232 = 8'd0; +reg [2:0] k7ddrphy_bitslip23_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip23_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay24; +wire k7ddrphy_dq_o_delayed24; +wire k7ddrphy_dq_i_nodelay24; +wire k7ddrphy_dq_i_delayed24; +wire k7ddrphy_dq_t24; +reg [7:0] k7ddrphy_bitslip240 = 8'd0; +reg [2:0] k7ddrphy_bitslip24_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip24_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip241; +reg [7:0] k7ddrphy_bitslip242 = 8'd0; +reg [2:0] k7ddrphy_bitslip24_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip24_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay25; +wire k7ddrphy_dq_o_delayed25; +wire k7ddrphy_dq_i_nodelay25; +wire k7ddrphy_dq_i_delayed25; +wire k7ddrphy_dq_t25; +reg [7:0] k7ddrphy_bitslip250 = 8'd0; +reg [2:0] k7ddrphy_bitslip25_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip25_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip251; +reg [7:0] k7ddrphy_bitslip252 = 8'd0; +reg [2:0] k7ddrphy_bitslip25_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip25_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay26; +wire k7ddrphy_dq_o_delayed26; +wire k7ddrphy_dq_i_nodelay26; +wire k7ddrphy_dq_i_delayed26; +wire k7ddrphy_dq_t26; +reg [7:0] k7ddrphy_bitslip260 = 8'd0; +reg [2:0] k7ddrphy_bitslip26_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip26_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip261; +reg [7:0] k7ddrphy_bitslip262 = 8'd0; +reg [2:0] k7ddrphy_bitslip26_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip26_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay27; +wire k7ddrphy_dq_o_delayed27; +wire k7ddrphy_dq_i_nodelay27; +wire k7ddrphy_dq_i_delayed27; +wire k7ddrphy_dq_t27; +reg [7:0] k7ddrphy_bitslip270 = 8'd0; +reg [2:0] k7ddrphy_bitslip27_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip27_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip271; +reg [7:0] k7ddrphy_bitslip272 = 8'd0; +reg [2:0] k7ddrphy_bitslip27_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip27_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay28; +wire k7ddrphy_dq_o_delayed28; +wire k7ddrphy_dq_i_nodelay28; +wire k7ddrphy_dq_i_delayed28; +wire k7ddrphy_dq_t28; +reg [7:0] k7ddrphy_bitslip280 = 8'd0; +reg [2:0] k7ddrphy_bitslip28_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip28_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip281; +reg [7:0] k7ddrphy_bitslip282 = 8'd0; +reg [2:0] k7ddrphy_bitslip28_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip28_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay29; +wire k7ddrphy_dq_o_delayed29; +wire k7ddrphy_dq_i_nodelay29; +wire k7ddrphy_dq_i_delayed29; +wire k7ddrphy_dq_t29; +reg [7:0] k7ddrphy_bitslip290 = 8'd0; +reg [2:0] k7ddrphy_bitslip29_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip29_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip291; +reg [7:0] k7ddrphy_bitslip292 = 8'd0; +reg [2:0] k7ddrphy_bitslip29_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip29_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay30; +wire k7ddrphy_dq_o_delayed30; +wire k7ddrphy_dq_i_nodelay30; +wire k7ddrphy_dq_i_delayed30; +wire k7ddrphy_dq_t30; +reg [7:0] k7ddrphy_bitslip300 = 8'd0; +reg [2:0] k7ddrphy_bitslip30_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip30_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip301; +reg [7:0] k7ddrphy_bitslip302 = 8'd0; +reg [2:0] k7ddrphy_bitslip30_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip30_r1 = 16'd0; +wire k7ddrphy_dq_o_nodelay31; +wire k7ddrphy_dq_o_delayed31; +wire k7ddrphy_dq_i_nodelay31; +wire k7ddrphy_dq_i_delayed31; +wire k7ddrphy_dq_t31; +reg [7:0] k7ddrphy_bitslip310 = 8'd0; +reg [2:0] k7ddrphy_bitslip31_value0 = 3'd7; +reg [15:0] k7ddrphy_bitslip31_r0 = 16'd0; +wire [7:0] k7ddrphy_bitslip311; +reg [7:0] k7ddrphy_bitslip312 = 8'd0; +reg [2:0] k7ddrphy_bitslip31_value1 = 3'd7; +reg [15:0] k7ddrphy_bitslip31_r1 = 16'd0; +reg k7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg k7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [63:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [7:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [63:0] litedramcore_slave_p2_rddata = 64'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [63:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [7:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [63:0] litedramcore_slave_p3_rddata = 64'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [14:0] litedramcore_master_p2_address = 15'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [63:0] litedramcore_master_p2_wrdata = 64'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p2_wrdata_mask = 8'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [14:0] litedramcore_master_p3_address = 15'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [63:0] litedramcore_master_p3_wrdata = 64'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p3_wrdata_mask = 8'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p2_address; +wire [2:0] litedramcore_csr_dfi_p2_bank; +reg litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg litedramcore_csr_dfi_p2_we_n = 1'd1; +wire litedramcore_csr_dfi_p2_cke; +wire litedramcore_csr_dfi_p2_odt; +wire litedramcore_csr_dfi_p2_reset_n; +reg litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p2_wrdata; +wire litedramcore_csr_dfi_p2_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask; +wire litedramcore_csr_dfi_p2_rddata_en; +reg [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0; +reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p3_address; +wire [2:0] litedramcore_csr_dfi_p3_bank; +reg litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg litedramcore_csr_dfi_p3_we_n = 1'd1; +wire litedramcore_csr_dfi_p3_cke; +wire litedramcore_csr_dfi_p3_odt; +wire litedramcore_csr_dfi_p3_reset_n; +reg litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p3_wrdata; +wire litedramcore_csr_dfi_p3_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask; +wire litedramcore_csr_dfi_p3_rddata_en; +reg [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0; +reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; +reg litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg litedramcore_ext_dfi_p2_we_n = 1'd1; +reg litedramcore_ext_dfi_p2_cke = 1'd0; +reg litedramcore_ext_dfi_p2_odt = 1'd0; +reg litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0; +reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0; +reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; +reg litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg litedramcore_ext_dfi_p3_we_n = 1'd1; +reg litedramcore_ext_dfi_p3_cke = 1'd0; +reg litedramcore_ext_dfi_p3_odt = 1'd0; +reg litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0; +reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0; +reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_phaseinjector2_csrfield_cs; +wire litedramcore_phaseinjector2_csrfield_we; +wire litedramcore_phaseinjector2_csrfield_cas; +wire litedramcore_phaseinjector2_csrfield_ras; +wire litedramcore_phaseinjector2_csrfield_wren; +wire litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +reg litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_r; +reg litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0; +wire litedramcore_phaseinjector2_rddata_we; +reg litedramcore_phaseinjector2_rddata_re = 1'd0; +wire litedramcore_phaseinjector3_csrfield_cs; +wire litedramcore_phaseinjector3_csrfield_we; +wire litedramcore_phaseinjector3_csrfield_cas; +wire litedramcore_phaseinjector3_csrfield_ras; +wire litedramcore_phaseinjector3_csrfield_wren; +wire litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +reg litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_r; +reg litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0; +wire litedramcore_phaseinjector3_rddata_we; +reg litedramcore_phaseinjector3_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [255:0] litedramcore_interface_wdata = 256'd0; +reg [31:0] litedramcore_interface_wdata_we = 32'd0; +wire [255:0] litedramcore_interface_rdata; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [14:0] litedramcore_dfi_p2_address = 15'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [14:0] litedramcore_dfi_p3_address = 15'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +wire [1:0] litedramcore_rdcmdphase; +wire [1:0] litedramcore_wrcmdphase; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [255:0] user_port_wdata_payload_data; +wire [31:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [255:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_rst0_re = 1'd0; +wire csrbank1_rst0_r; +reg csrbank1_rst0_we = 1'd0; +wire csrbank1_rst0_w; +reg csrbank1_dly_sel0_re = 1'd0; +wire [3:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [3:0] csrbank1_dly_sel0_w; +reg csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_r; +reg csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_w; +reg csrbank1_wlevel_en0_re = 1'd0; +wire csrbank1_wlevel_en0_r; +reg csrbank1_wlevel_en0_we = 1'd0; +wire csrbank1_wlevel_en0_w; +reg csrbank1_rdphase0_re = 1'd0; +wire [1:0] csrbank1_rdphase0_r; +reg csrbank1_rdphase0_we = 1'd0; +wire [1:0] csrbank1_rdphase0_w; +reg csrbank1_wrphase0_re = 1'd0; +wire [1:0] csrbank1_wrphase0_r; +reg csrbank1_wrphase0_we = 1'd0; +wire [1:0] csrbank1_wrphase0_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +reg csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_r; +reg csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_w; +reg csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address0_r; +reg csrbank2_dfii_pi2_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address0_w; +reg csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +reg csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +reg csrbank2_dfii_pi2_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata1_r; +reg csrbank2_dfii_pi2_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata1_w; +reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; +reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +reg csrbank2_dfii_pi2_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata1_r; +reg csrbank2_dfii_pi2_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata1_w; +reg csrbank2_dfii_pi2_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata0_r; +reg csrbank2_dfii_pi2_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata0_w; +reg csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_r; +reg csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_w; +reg csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address0_r; +reg csrbank2_dfii_pi3_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address0_w; +reg csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +reg csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +reg csrbank2_dfii_pi3_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata1_r; +reg csrbank2_dfii_pi3_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata1_w; +reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; +reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +reg csrbank2_dfii_pi3_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata1_r; +reg csrbank2_dfii_pi3_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata1_w; +reg csrbank2_dfii_pi3_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata0_r; +reg csrbank2_dfii_pi3_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata0_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_reset0; +wire litedramcore_reset1; +wire litedramcore_reset2; +wire litedramcore_reset3; +wire litedramcore_reset4; +wire litedramcore_reset5; +wire litedramcore_reset6; +wire litedramcore_reset7; +wire litedramcore_pll_fb; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [14:0] rhs_array_muxed1 = 15'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [14:0] rhs_array_muxed7 = 15'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [21:0] rhs_array_muxed24 = 22'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [21:0] rhs_array_muxed27 = 22'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [21:0] rhs_array_muxed30 = 22'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [21:0] rhs_array_muxed33 = 22'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [14:0] array_muxed1 = 15'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [14:0] array_muxed8 = 15'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [14:0] array_muxed15 = 15'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [14:0] array_muxed22 = 15'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2362,272 +2486,272 @@ assign ddram_ba = k7ddrphy_pads_ba; assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble); assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble); always @(*) begin - k7ddrphy_dfi_p0_rddata <= 64'd0; - k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0]; - k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1]; - k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0]; - k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1]; - k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0]; - k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1]; - k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0]; - k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1]; - k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0]; - k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1]; - k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0]; - k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1]; - k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0]; - k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1]; - k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0]; - k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1]; - k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0]; - k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1]; - k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0]; - k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1]; - k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0]; - k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1]; - k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0]; - k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1]; - k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0]; - k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1]; - k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0]; - k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1]; - k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0]; - k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1]; - k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0]; - k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1]; - k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0]; - k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1]; - k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0]; - k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1]; - k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0]; - k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1]; - k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0]; - k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1]; - k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0]; - k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1]; - k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0]; - k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1]; - k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0]; - k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1]; - k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0]; - k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1]; - k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0]; - k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1]; - k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0]; - k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1]; - k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0]; - k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1]; - k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0]; - k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1]; - k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0]; - k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1]; - k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0]; - k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1]; - k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0]; - k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1]; - k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0]; - k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1]; -end -always @(*) begin - k7ddrphy_dfi_p1_rddata <= 64'd0; - k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2]; - k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3]; - k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2]; - k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3]; - k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2]; - k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3]; - k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2]; - k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3]; - k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2]; - k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3]; - k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2]; - k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3]; - k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2]; - k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3]; - k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2]; - k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3]; - k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2]; - k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3]; - k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2]; - k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3]; - k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2]; - k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3]; - k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2]; - k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3]; - k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2]; - k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3]; - k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2]; - k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3]; - k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2]; - k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3]; - k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2]; - k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3]; - k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2]; - k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3]; - k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2]; - k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3]; - k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2]; - k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3]; - k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2]; - k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3]; - k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2]; - k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3]; - k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2]; - k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3]; - k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2]; - k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3]; - k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2]; - k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3]; - k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2]; - k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3]; - k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2]; - k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3]; - k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2]; - k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3]; - k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2]; - k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3]; - k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2]; - k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3]; - k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2]; - k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3]; - k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2]; - k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3]; - k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2]; - k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3]; -end -always @(*) begin - k7ddrphy_dfi_p2_rddata <= 64'd0; - k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4]; - k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5]; - k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4]; - k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5]; - k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4]; - k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5]; - k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4]; - k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5]; - k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4]; - k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5]; - k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4]; - k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5]; - k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4]; - k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5]; - k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4]; - k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5]; - k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4]; - k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5]; - k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4]; - k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5]; - k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4]; - k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5]; - k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4]; - k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5]; - k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4]; - k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5]; - k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4]; - k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5]; - k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4]; - k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5]; - k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4]; - k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5]; - k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4]; - k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5]; - k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4]; - k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5]; - k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4]; - k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5]; - k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4]; - k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5]; - k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4]; - k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5]; - k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4]; - k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5]; - k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4]; - k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5]; - k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4]; - k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5]; - k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4]; - k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5]; - k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4]; - k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5]; - k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4]; - k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5]; - k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4]; - k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5]; - k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4]; - k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5]; - k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4]; - k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5]; - k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4]; - k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5]; - k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4]; - k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5]; -end -always @(*) begin - k7ddrphy_dfi_p3_rddata <= 64'd0; - k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6]; - k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7]; - k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6]; - k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7]; - k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6]; - k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7]; - k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6]; - k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7]; - k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6]; - k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7]; - k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6]; - k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7]; - k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6]; - k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7]; - k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6]; - k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7]; - k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6]; - k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7]; - k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6]; - k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7]; - k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6]; - k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7]; - k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6]; - k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7]; - k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6]; - k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7]; - k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6]; - k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7]; - k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6]; - k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7]; - k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6]; - k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7]; - k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6]; - k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7]; - k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6]; - k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7]; - k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6]; - k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7]; - k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6]; - k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7]; - k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6]; - k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7]; - k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6]; - k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7]; - k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6]; - k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7]; - k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6]; - k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7]; - k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6]; - k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7]; - k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6]; - k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7]; - k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6]; - k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7]; - k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6]; - k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7]; - k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6]; - k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7]; - k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6]; - k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7]; - k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6]; - k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7]; - k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6]; - k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7]; + k7ddrphy_dfi_p0_rddata <= 64'd0; + k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0]; + k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1]; + k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0]; + k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1]; + k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0]; + k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1]; + k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0]; + k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1]; + k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0]; + k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1]; + k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0]; + k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1]; + k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0]; + k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1]; + k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0]; + k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1]; + k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0]; + k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1]; + k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0]; + k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1]; + k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0]; + k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1]; + k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0]; + k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1]; + k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0]; + k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1]; + k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0]; + k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1]; + k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0]; + k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1]; + k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0]; + k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1]; + k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0]; + k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1]; + k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0]; + k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1]; + k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0]; + k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1]; + k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0]; + k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1]; + k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0]; + k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1]; + k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0]; + k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1]; + k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0]; + k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1]; + k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0]; + k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1]; + k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0]; + k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1]; + k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0]; + k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1]; + k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0]; + k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1]; + k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0]; + k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1]; + k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0]; + k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1]; + k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0]; + k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1]; + k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0]; + k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1]; + k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0]; + k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1]; +end +always @(*) begin + k7ddrphy_dfi_p1_rddata <= 64'd0; + k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2]; + k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3]; + k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2]; + k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3]; + k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2]; + k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3]; + k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2]; + k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3]; + k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2]; + k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3]; + k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2]; + k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3]; + k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2]; + k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3]; + k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2]; + k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3]; + k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2]; + k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3]; + k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2]; + k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3]; + k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2]; + k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3]; + k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2]; + k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3]; + k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2]; + k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3]; + k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2]; + k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3]; + k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2]; + k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3]; + k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2]; + k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3]; + k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2]; + k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3]; + k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2]; + k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3]; + k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2]; + k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3]; + k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2]; + k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3]; + k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2]; + k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3]; + k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2]; + k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3]; + k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2]; + k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3]; + k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2]; + k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3]; + k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2]; + k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3]; + k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2]; + k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3]; + k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2]; + k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3]; + k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2]; + k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3]; + k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2]; + k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3]; + k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2]; + k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3]; + k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2]; + k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3]; + k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2]; + k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3]; +end +always @(*) begin + k7ddrphy_dfi_p2_rddata <= 64'd0; + k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4]; + k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5]; + k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4]; + k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5]; + k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4]; + k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5]; + k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4]; + k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5]; + k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4]; + k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5]; + k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4]; + k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5]; + k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4]; + k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5]; + k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4]; + k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5]; + k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4]; + k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5]; + k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4]; + k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5]; + k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4]; + k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5]; + k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4]; + k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5]; + k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4]; + k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5]; + k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4]; + k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5]; + k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4]; + k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5]; + k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4]; + k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5]; + k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4]; + k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5]; + k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4]; + k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5]; + k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4]; + k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5]; + k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4]; + k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5]; + k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4]; + k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5]; + k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4]; + k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5]; + k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4]; + k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5]; + k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4]; + k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5]; + k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4]; + k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5]; + k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4]; + k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5]; + k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4]; + k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5]; + k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4]; + k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5]; + k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4]; + k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5]; + k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4]; + k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5]; + k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4]; + k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5]; + k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4]; + k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5]; +end +always @(*) begin + k7ddrphy_dfi_p3_rddata <= 64'd0; + k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6]; + k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7]; + k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6]; + k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7]; + k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6]; + k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7]; + k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6]; + k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7]; + k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6]; + k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7]; + k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6]; + k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7]; + k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6]; + k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7]; + k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6]; + k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7]; + k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6]; + k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7]; + k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6]; + k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7]; + k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6]; + k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7]; + k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6]; + k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7]; + k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6]; + k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7]; + k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6]; + k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7]; + k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6]; + k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7]; + k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6]; + k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7]; + k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6]; + k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7]; + k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6]; + k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7]; + k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6]; + k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7]; + k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6]; + k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7]; + k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6]; + k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7]; + k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6]; + k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7]; + k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6]; + k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7]; + k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6]; + k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7]; + k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6]; + k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7]; + k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6]; + k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7]; + k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6]; + k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7]; + k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6]; + k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7]; + k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6]; + k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7]; + k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6]; + k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7]; + k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6]; + k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7]; + k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6]; + k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7]; end assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); @@ -2635,2118 +2759,2118 @@ assign k7ddrphy_dfi_p2_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7d assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage); assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin - k7ddrphy_dqs_oe <= 1'd0; - if (k7ddrphy_wlevel_en_storage) begin - k7ddrphy_dqs_oe <= 1'd1; - end else begin - k7ddrphy_dqs_oe <= k7ddrphy_dq_oe; - end + k7ddrphy_dqs_oe <= 1'd0; + if (k7ddrphy_wlevel_en_storage) begin + k7ddrphy_dqs_oe <= 1'd1; + end else begin + k7ddrphy_dqs_oe <= k7ddrphy_dq_oe; + end end assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1)); assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - k7ddrphy_dqspattern_o <= 8'd0; - k7ddrphy_dqspattern_o <= 7'd85; - if (k7ddrphy_dqspattern0) begin - k7ddrphy_dqspattern_o <= 5'd21; - end - if (k7ddrphy_dqspattern1) begin - k7ddrphy_dqspattern_o <= 7'd84; - end - if (k7ddrphy_wlevel_en_storage) begin - k7ddrphy_dqspattern_o <= 1'd0; - if (k7ddrphy_wlevel_strobe_re) begin - k7ddrphy_dqspattern_o <= 1'd1; - end - end -end -always @(*) begin - k7ddrphy_bitslip00 <= 8'd0; - case (k7ddrphy_bitslip0_value0) - 1'd0: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip10 <= 8'd0; - case (k7ddrphy_bitslip1_value0) - 1'd0: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip20 <= 8'd0; - case (k7ddrphy_bitslip2_value0) - 1'd0: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip30 <= 8'd0; - case (k7ddrphy_bitslip3_value0) - 1'd0: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip01 <= 8'd0; - case (k7ddrphy_bitslip0_value1) - 1'd0: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip11 <= 8'd0; - case (k7ddrphy_bitslip1_value1) - 1'd0: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip21 <= 8'd0; - case (k7ddrphy_bitslip2_value1) - 1'd0: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip31 <= 8'd0; - case (k7ddrphy_bitslip3_value1) - 1'd0: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip02 <= 8'd0; - case (k7ddrphy_bitslip0_value2) - 1'd0: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip04 <= 8'd0; - case (k7ddrphy_bitslip0_value3) - 1'd0: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip12 <= 8'd0; - case (k7ddrphy_bitslip1_value2) - 1'd0: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip14 <= 8'd0; - case (k7ddrphy_bitslip1_value3) - 1'd0: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip22 <= 8'd0; - case (k7ddrphy_bitslip2_value2) - 1'd0: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip24 <= 8'd0; - case (k7ddrphy_bitslip2_value3) - 1'd0: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip32 <= 8'd0; - case (k7ddrphy_bitslip3_value2) - 1'd0: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip34 <= 8'd0; - case (k7ddrphy_bitslip3_value3) - 1'd0: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip40 <= 8'd0; - case (k7ddrphy_bitslip4_value0) - 1'd0: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip42 <= 8'd0; - case (k7ddrphy_bitslip4_value1) - 1'd0: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip50 <= 8'd0; - case (k7ddrphy_bitslip5_value0) - 1'd0: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip52 <= 8'd0; - case (k7ddrphy_bitslip5_value1) - 1'd0: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip60 <= 8'd0; - case (k7ddrphy_bitslip6_value0) - 1'd0: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip62 <= 8'd0; - case (k7ddrphy_bitslip6_value1) - 1'd0: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip70 <= 8'd0; - case (k7ddrphy_bitslip7_value0) - 1'd0: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip72 <= 8'd0; - case (k7ddrphy_bitslip7_value1) - 1'd0: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip80 <= 8'd0; - case (k7ddrphy_bitslip8_value0) - 1'd0: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip82 <= 8'd0; - case (k7ddrphy_bitslip8_value1) - 1'd0: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip90 <= 8'd0; - case (k7ddrphy_bitslip9_value0) - 1'd0: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip92 <= 8'd0; - case (k7ddrphy_bitslip9_value1) - 1'd0: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip100 <= 8'd0; - case (k7ddrphy_bitslip10_value0) - 1'd0: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip102 <= 8'd0; - case (k7ddrphy_bitslip10_value1) - 1'd0: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip110 <= 8'd0; - case (k7ddrphy_bitslip11_value0) - 1'd0: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip112 <= 8'd0; - case (k7ddrphy_bitslip11_value1) - 1'd0: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip120 <= 8'd0; - case (k7ddrphy_bitslip12_value0) - 1'd0: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip122 <= 8'd0; - case (k7ddrphy_bitslip12_value1) - 1'd0: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip130 <= 8'd0; - case (k7ddrphy_bitslip13_value0) - 1'd0: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip132 <= 8'd0; - case (k7ddrphy_bitslip13_value1) - 1'd0: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip140 <= 8'd0; - case (k7ddrphy_bitslip14_value0) - 1'd0: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip142 <= 8'd0; - case (k7ddrphy_bitslip14_value1) - 1'd0: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip150 <= 8'd0; - case (k7ddrphy_bitslip15_value0) - 1'd0: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip152 <= 8'd0; - case (k7ddrphy_bitslip15_value1) - 1'd0: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip160 <= 8'd0; - case (k7ddrphy_bitslip16_value0) - 1'd0: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip162 <= 8'd0; - case (k7ddrphy_bitslip16_value1) - 1'd0: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip170 <= 8'd0; - case (k7ddrphy_bitslip17_value0) - 1'd0: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip172 <= 8'd0; - case (k7ddrphy_bitslip17_value1) - 1'd0: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip180 <= 8'd0; - case (k7ddrphy_bitslip18_value0) - 1'd0: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip182 <= 8'd0; - case (k7ddrphy_bitslip18_value1) - 1'd0: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip190 <= 8'd0; - case (k7ddrphy_bitslip19_value0) - 1'd0: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip192 <= 8'd0; - case (k7ddrphy_bitslip19_value1) - 1'd0: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip200 <= 8'd0; - case (k7ddrphy_bitslip20_value0) - 1'd0: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip202 <= 8'd0; - case (k7ddrphy_bitslip20_value1) - 1'd0: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip210 <= 8'd0; - case (k7ddrphy_bitslip21_value0) - 1'd0: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip212 <= 8'd0; - case (k7ddrphy_bitslip21_value1) - 1'd0: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip220 <= 8'd0; - case (k7ddrphy_bitslip22_value0) - 1'd0: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip222 <= 8'd0; - case (k7ddrphy_bitslip22_value1) - 1'd0: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip230 <= 8'd0; - case (k7ddrphy_bitslip23_value0) - 1'd0: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip232 <= 8'd0; - case (k7ddrphy_bitslip23_value1) - 1'd0: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip240 <= 8'd0; - case (k7ddrphy_bitslip24_value0) - 1'd0: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip242 <= 8'd0; - case (k7ddrphy_bitslip24_value1) - 1'd0: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip250 <= 8'd0; - case (k7ddrphy_bitslip25_value0) - 1'd0: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip252 <= 8'd0; - case (k7ddrphy_bitslip25_value1) - 1'd0: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip260 <= 8'd0; - case (k7ddrphy_bitslip26_value0) - 1'd0: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip262 <= 8'd0; - case (k7ddrphy_bitslip26_value1) - 1'd0: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip270 <= 8'd0; - case (k7ddrphy_bitslip27_value0) - 1'd0: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip272 <= 8'd0; - case (k7ddrphy_bitslip27_value1) - 1'd0: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip280 <= 8'd0; - case (k7ddrphy_bitslip28_value0) - 1'd0: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip282 <= 8'd0; - case (k7ddrphy_bitslip28_value1) - 1'd0: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip290 <= 8'd0; - case (k7ddrphy_bitslip29_value0) - 1'd0: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip292 <= 8'd0; - case (k7ddrphy_bitslip29_value1) - 1'd0: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip300 <= 8'd0; - case (k7ddrphy_bitslip30_value0) - 1'd0: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip302 <= 8'd0; - case (k7ddrphy_bitslip30_value1) - 1'd0: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip310 <= 8'd0; - case (k7ddrphy_bitslip31_value0) - 1'd0: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8]; - end - endcase -end -always @(*) begin - k7ddrphy_bitslip312 <= 8'd0; - case (k7ddrphy_bitslip31_value1) - 1'd0: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1]; - end - 1'd1: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2]; - end - 2'd2: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3]; - end - 2'd3: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4]; - end - 3'd4: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5]; - end - 3'd5: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6]; - end - 3'd6: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7]; - end - 3'd7: begin - k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8]; - end - endcase + k7ddrphy_dqspattern_o <= 8'd0; + k7ddrphy_dqspattern_o <= 7'd85; + if (k7ddrphy_dqspattern0) begin + k7ddrphy_dqspattern_o <= 5'd21; + end + if (k7ddrphy_dqspattern1) begin + k7ddrphy_dqspattern_o <= 7'd84; + end + if (k7ddrphy_wlevel_en_storage) begin + k7ddrphy_dqspattern_o <= 1'd0; + if (k7ddrphy_wlevel_strobe_re) begin + k7ddrphy_dqspattern_o <= 1'd1; + end + end +end +always @(*) begin + k7ddrphy_bitslip00 <= 8'd0; + case (k7ddrphy_bitslip0_value0) + 1'd0: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip10 <= 8'd0; + case (k7ddrphy_bitslip1_value0) + 1'd0: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip20 <= 8'd0; + case (k7ddrphy_bitslip2_value0) + 1'd0: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip30 <= 8'd0; + case (k7ddrphy_bitslip3_value0) + 1'd0: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip01 <= 8'd0; + case (k7ddrphy_bitslip0_value1) + 1'd0: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip11 <= 8'd0; + case (k7ddrphy_bitslip1_value1) + 1'd0: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip21 <= 8'd0; + case (k7ddrphy_bitslip2_value1) + 1'd0: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip31 <= 8'd0; + case (k7ddrphy_bitslip3_value1) + 1'd0: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip02 <= 8'd0; + case (k7ddrphy_bitslip0_value2) + 1'd0: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip04 <= 8'd0; + case (k7ddrphy_bitslip0_value3) + 1'd0: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip12 <= 8'd0; + case (k7ddrphy_bitslip1_value2) + 1'd0: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip14 <= 8'd0; + case (k7ddrphy_bitslip1_value3) + 1'd0: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip22 <= 8'd0; + case (k7ddrphy_bitslip2_value2) + 1'd0: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip24 <= 8'd0; + case (k7ddrphy_bitslip2_value3) + 1'd0: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip32 <= 8'd0; + case (k7ddrphy_bitslip3_value2) + 1'd0: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip34 <= 8'd0; + case (k7ddrphy_bitslip3_value3) + 1'd0: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip40 <= 8'd0; + case (k7ddrphy_bitslip4_value0) + 1'd0: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip42 <= 8'd0; + case (k7ddrphy_bitslip4_value1) + 1'd0: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip50 <= 8'd0; + case (k7ddrphy_bitslip5_value0) + 1'd0: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip52 <= 8'd0; + case (k7ddrphy_bitslip5_value1) + 1'd0: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip60 <= 8'd0; + case (k7ddrphy_bitslip6_value0) + 1'd0: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip62 <= 8'd0; + case (k7ddrphy_bitslip6_value1) + 1'd0: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip70 <= 8'd0; + case (k7ddrphy_bitslip7_value0) + 1'd0: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip72 <= 8'd0; + case (k7ddrphy_bitslip7_value1) + 1'd0: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip80 <= 8'd0; + case (k7ddrphy_bitslip8_value0) + 1'd0: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip82 <= 8'd0; + case (k7ddrphy_bitslip8_value1) + 1'd0: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip90 <= 8'd0; + case (k7ddrphy_bitslip9_value0) + 1'd0: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip92 <= 8'd0; + case (k7ddrphy_bitslip9_value1) + 1'd0: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip100 <= 8'd0; + case (k7ddrphy_bitslip10_value0) + 1'd0: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip102 <= 8'd0; + case (k7ddrphy_bitslip10_value1) + 1'd0: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip110 <= 8'd0; + case (k7ddrphy_bitslip11_value0) + 1'd0: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip112 <= 8'd0; + case (k7ddrphy_bitslip11_value1) + 1'd0: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip120 <= 8'd0; + case (k7ddrphy_bitslip12_value0) + 1'd0: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip122 <= 8'd0; + case (k7ddrphy_bitslip12_value1) + 1'd0: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip130 <= 8'd0; + case (k7ddrphy_bitslip13_value0) + 1'd0: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip132 <= 8'd0; + case (k7ddrphy_bitslip13_value1) + 1'd0: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip140 <= 8'd0; + case (k7ddrphy_bitslip14_value0) + 1'd0: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip142 <= 8'd0; + case (k7ddrphy_bitslip14_value1) + 1'd0: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip150 <= 8'd0; + case (k7ddrphy_bitslip15_value0) + 1'd0: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip152 <= 8'd0; + case (k7ddrphy_bitslip15_value1) + 1'd0: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip160 <= 8'd0; + case (k7ddrphy_bitslip16_value0) + 1'd0: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip162 <= 8'd0; + case (k7ddrphy_bitslip16_value1) + 1'd0: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip170 <= 8'd0; + case (k7ddrphy_bitslip17_value0) + 1'd0: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip172 <= 8'd0; + case (k7ddrphy_bitslip17_value1) + 1'd0: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip180 <= 8'd0; + case (k7ddrphy_bitslip18_value0) + 1'd0: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip182 <= 8'd0; + case (k7ddrphy_bitslip18_value1) + 1'd0: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip190 <= 8'd0; + case (k7ddrphy_bitslip19_value0) + 1'd0: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip192 <= 8'd0; + case (k7ddrphy_bitslip19_value1) + 1'd0: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip200 <= 8'd0; + case (k7ddrphy_bitslip20_value0) + 1'd0: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip202 <= 8'd0; + case (k7ddrphy_bitslip20_value1) + 1'd0: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip210 <= 8'd0; + case (k7ddrphy_bitslip21_value0) + 1'd0: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip212 <= 8'd0; + case (k7ddrphy_bitslip21_value1) + 1'd0: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip220 <= 8'd0; + case (k7ddrphy_bitslip22_value0) + 1'd0: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip222 <= 8'd0; + case (k7ddrphy_bitslip22_value1) + 1'd0: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip230 <= 8'd0; + case (k7ddrphy_bitslip23_value0) + 1'd0: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip232 <= 8'd0; + case (k7ddrphy_bitslip23_value1) + 1'd0: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip240 <= 8'd0; + case (k7ddrphy_bitslip24_value0) + 1'd0: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip242 <= 8'd0; + case (k7ddrphy_bitslip24_value1) + 1'd0: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip250 <= 8'd0; + case (k7ddrphy_bitslip25_value0) + 1'd0: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip252 <= 8'd0; + case (k7ddrphy_bitslip25_value1) + 1'd0: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip260 <= 8'd0; + case (k7ddrphy_bitslip26_value0) + 1'd0: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip262 <= 8'd0; + case (k7ddrphy_bitslip26_value1) + 1'd0: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip270 <= 8'd0; + case (k7ddrphy_bitslip27_value0) + 1'd0: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip272 <= 8'd0; + case (k7ddrphy_bitslip27_value1) + 1'd0: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip280 <= 8'd0; + case (k7ddrphy_bitslip28_value0) + 1'd0: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip282 <= 8'd0; + case (k7ddrphy_bitslip28_value1) + 1'd0: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip290 <= 8'd0; + case (k7ddrphy_bitslip29_value0) + 1'd0: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip292 <= 8'd0; + case (k7ddrphy_bitslip29_value1) + 1'd0: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip300 <= 8'd0; + case (k7ddrphy_bitslip30_value0) + 1'd0: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip302 <= 8'd0; + case (k7ddrphy_bitslip30_value1) + 1'd0: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip310 <= 8'd0; + case (k7ddrphy_bitslip31_value0) + 1'd0: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8]; + end + endcase +end +always @(*) begin + k7ddrphy_bitslip312 <= 8'd0; + case (k7ddrphy_bitslip31_value1) + 1'd0: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1]; + end + 1'd1: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2]; + end + 2'd2: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3]; + end + 2'd3: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4]; + end + 3'd4: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5]; + end + 3'd5: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6]; + end + 3'd6: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7]; + end + 3'd7: begin + k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8]; + end + endcase end assign k7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign k7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -4877,892 +5001,892 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end + litedramcore_csr_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; - end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; - end - end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; - end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; - end - end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; - end - end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; - end - end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; - end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; - end - end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end - end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; - end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; - end - end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; - end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; - end - end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; - end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; - end - end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; - end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; - end - end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - litedramcore_master_p2_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; - end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; - end - end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; - end - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; - end - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; - end - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - litedramcore_master_p3_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; - end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; - end - end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; - end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; - end - end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; - end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; - end - end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; - end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; - end - end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end -end -always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; - end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; - end - end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; - end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; - end - end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end - end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end - end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end - end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end - end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - litedramcore_master_p3_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; - end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; - end - end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; - end - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; - end - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; - end - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + end else begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; + end + end else begin + litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + end else begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + end + end else begin + litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end + end else begin + litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end + end else begin + litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end + end else begin + litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end + end else begin + litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + end else begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + end + end else begin + litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + end else begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + end + end else begin + litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + end + end else begin + litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + end else begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + end + end else begin + litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + end + end else begin + litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end + end else begin + litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end + end else begin + litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end + end else begin + litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end + end else begin + litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end + end else begin + litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end + end else begin + litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end + end else begin + litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + end else begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + end + end else begin + litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + end + end else begin + litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + end else begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + end + end else begin + litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + end + end else begin + litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + end + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + end + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + end + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -5777,36 +5901,36 @@ assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -5815,36 +5939,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -5853,36 +5977,36 @@ assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_ assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); - end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + end else begin + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); - end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + end else begin + litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); - end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + end else begin + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; @@ -5891,36 +6015,36 @@ assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_ assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); - end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + end else begin + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); - end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + end else begin + litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); - end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + end else begin + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; @@ -5998,4590 +6122,4686 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase end assign litedramcore_rdcmdphase = (k7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (k7ddrphy_wrphase_storage - 1'd1); @@ -10614,15 +10834,15 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -10632,106 +10852,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -10741,22 +10961,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -10773,473 +10993,473 @@ assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((k7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((k7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((k7ddrphy_wrphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((k7ddrphy_rdphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((k7ddrphy_wrphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((k7ddrphy_rdphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((k7ddrphy_wrphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((k7ddrphy_rdphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((k7ddrphy_wrphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((k7ddrphy_rdphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -11285,26 +11505,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - litedramcore_interface_wdata <= 256'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 32'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 256'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 32'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -11316,129 +11536,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -11454,279 +11674,279 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); - end + csrbank1_rst0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; - end + csrbank1_rst0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_re <= interface1_bank_bus_we; + end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; - end + csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); - end + csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); - end + csrbank1_wlevel_en0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; - end + csrbank1_wlevel_en0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + end end assign k7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; - end + k7ddrphy_wlevel_strobe_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + end end always @(*) begin - k7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wlevel_strobe_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + end end assign k7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_cdly_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_cdly_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_cdly_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - k7ddrphy_cdly_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_cdly_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + k7ddrphy_cdly_rst_re <= interface1_bank_bus_we; + end end assign k7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_cdly_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we); - end + k7ddrphy_cdly_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_cdly_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - k7ddrphy_cdly_inc_re <= interface1_bank_bus_we; - end + k7ddrphy_cdly_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + k7ddrphy_cdly_inc_re <= interface1_bank_bus_we; + end end assign k7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end assign k7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + k7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + k7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end assign k7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end assign k7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + k7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end always @(*) begin - k7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + k7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end assign k7ddrphy_wdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - k7ddrphy_wdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we); + end end assign k7ddrphy_wdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we; + end end always @(*) begin - k7ddrphy_wdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we); + end end assign k7ddrphy_wdly_dqs_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dqs_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dqs_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_wdly_dqs_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dqs_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we; + end end assign k7ddrphy_wdly_dqs_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dqs_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dqs_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_wdly_dqs_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dqs_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we; + end end assign k7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign k7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - k7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + k7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - k7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; - end + k7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; - end + csrbank1_rdphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_rdphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_rdphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_wrphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; - end + csrbank1_wrphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_wrphase0_re <= interface1_bank_bus_we; + end end assign csrbank1_rst0_w = k7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = k7ddrphy_dly_sel_storage[3:0]; @@ -11737,432 +11957,432 @@ assign csrbank1_wrphase0_w = k7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin + csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin + csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin + litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin + litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin + csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin + csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin + csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin + csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin - csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin + csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin - csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin + csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin + csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin + csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin - csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin + csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin - csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin + csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin - csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin + csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin - csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin + csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -12240,1194 +12460,1194 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 15'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 15'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 22'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 22'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 22'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 22'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 15'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 15'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 22'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 22'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 22'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 22'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 15'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 15'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 15'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 15'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); @@ -13440,2472 +13660,2472 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); - end else begin - ic_reset <= 1'd0; - end - if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; - end + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); + end else begin + ic_reset <= 1'd0; + end + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; + end end always @(posedge sys_clk) begin - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value0 <= 3'd7; - end - k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value0 <= 3'd7; - end - k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value0 <= 3'd7; - end - k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value0 <= 3'd7; - end - k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value1 <= 3'd7; - end - k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value1 <= 3'd7; - end - k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value1 <= 3'd7; - end - k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value1 <= 3'd7; - end - k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]}; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value2 <= 3'd7; - end - k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip0_value3 <= 3'd7; - end - k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value2 <= 3'd7; - end - k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip1_value3 <= 3'd7; - end - k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value2 <= 3'd7; - end - k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip2_value3 <= 3'd7; - end - k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value2 <= 3'd7; - end - k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip3_value3 <= 3'd7; - end - k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip4_value0 <= 3'd7; - end - k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip4_value1 <= 3'd7; - end - k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip5_value0 <= 3'd7; - end - k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip5_value1 <= 3'd7; - end - k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip6_value0 <= 3'd7; - end - k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip6_value1 <= 3'd7; - end - k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip7_value0 <= 3'd7; - end - k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip7_value1 <= 3'd7; - end - k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip8_value0 <= 3'd7; - end - k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip8_value1 <= 3'd7; - end - k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip9_value0 <= 3'd7; - end - k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip9_value1 <= 3'd7; - end - k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip10_value0 <= 3'd7; - end - k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip10_value1 <= 3'd7; - end - k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip11_value0 <= 3'd7; - end - k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip11_value1 <= 3'd7; - end - k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip12_value0 <= 3'd7; - end - k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip12_value1 <= 3'd7; - end - k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip13_value0 <= 3'd7; - end - k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip13_value1 <= 3'd7; - end - k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip14_value0 <= 3'd7; - end - k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip14_value1 <= 3'd7; - end - k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip15_value0 <= 3'd7; - end - k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip15_value1 <= 3'd7; - end - k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip16_value0 <= 3'd7; - end - k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip16_value1 <= 3'd7; - end - k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip17_value0 <= 3'd7; - end - k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip17_value1 <= 3'd7; - end - k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip18_value0 <= 3'd7; - end - k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip18_value1 <= 3'd7; - end - k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip19_value0 <= 3'd7; - end - k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip19_value1 <= 3'd7; - end - k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip20_value0 <= 3'd7; - end - k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip20_value1 <= 3'd7; - end - k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip21_value0 <= 3'd7; - end - k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip21_value1 <= 3'd7; - end - k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip22_value0 <= 3'd7; - end - k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip22_value1 <= 3'd7; - end - k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip23_value0 <= 3'd7; - end - k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip23_value1 <= 3'd7; - end - k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip24_value0 <= 3'd7; - end - k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip24_value1 <= 3'd7; - end - k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip25_value0 <= 3'd7; - end - k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip25_value1 <= 3'd7; - end - k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip26_value0 <= 3'd7; - end - k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip26_value1 <= 3'd7; - end - k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip27_value0 <= 3'd7; - end - k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip27_value1 <= 3'd7; - end - k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip28_value0 <= 3'd7; - end - k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip28_value1 <= 3'd7; - end - k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip29_value0 <= 3'd7; - end - k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip29_value1 <= 3'd7; - end - k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip30_value0 <= 3'd7; - end - k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip30_value1 <= 3'd7; - end - k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin - k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip31_value0 <= 3'd7; - end - k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]}; - if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin - k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1); - end - if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin - k7ddrphy_bitslip31_value1 <= 3'd7; - end - k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]}; - k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en); - k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0; - k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1; - k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2; - k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3; - k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4; - k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5; - k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6; - k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en); - k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0; - k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; - end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 10'd781; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w; - end - 4'd13: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w; - end - 4'd14: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w; - end - 4'd15: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w; - end - 5'd16: begin - interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w; - end - 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; - end - 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; - end - endcase - end - if (csrbank1_rst0_re) begin - k7ddrphy_rst_storage <= csrbank1_rst0_r; - end - k7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r; - end - k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; - end - k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; - end - k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; - end - k7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; - end - k7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 5'd18: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; - end - 5'd25: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; - end - 5'd26: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; - end - 5'd27: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; - end - 5'd28: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; - end - 5'd29: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; - end - 5'd30: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; - end - 5'd31: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; - end - 6'd32: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; - end - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; - end - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; - end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; - end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; - end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata1_re) begin - litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r; - end - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; - end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; - end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; - end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; - end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata1_re) begin - litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r; - end - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; - end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re; - if (sys_rst) begin - k7ddrphy_rst_storage <= 1'd0; - k7ddrphy_rst_re <= 1'd0; - k7ddrphy_dly_sel_storage <= 4'd0; - k7ddrphy_dly_sel_re <= 1'd0; - k7ddrphy_half_sys8x_taps_storage <= 5'd8; - k7ddrphy_half_sys8x_taps_re <= 1'd0; - k7ddrphy_wlevel_en_storage <= 1'd0; - k7ddrphy_wlevel_en_re <= 1'd0; - k7ddrphy_rdphase_storage <= 2'd1; - k7ddrphy_rdphase_re <= 1'd0; - k7ddrphy_wrphase_storage <= 2'd2; - k7ddrphy_wrphase_re <= 1'd0; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - k7ddrphy_bitslip0_value0 <= 3'd7; - k7ddrphy_bitslip1_value0 <= 3'd7; - k7ddrphy_bitslip2_value0 <= 3'd7; - k7ddrphy_bitslip3_value0 <= 3'd7; - k7ddrphy_bitslip0_value1 <= 3'd7; - k7ddrphy_bitslip1_value1 <= 3'd7; - k7ddrphy_bitslip2_value1 <= 3'd7; - k7ddrphy_bitslip3_value1 <= 3'd7; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - k7ddrphy_bitslip0_value2 <= 3'd7; - k7ddrphy_bitslip0_value3 <= 3'd7; - k7ddrphy_bitslip1_value2 <= 3'd7; - k7ddrphy_bitslip1_value3 <= 3'd7; - k7ddrphy_bitslip2_value2 <= 3'd7; - k7ddrphy_bitslip2_value3 <= 3'd7; - k7ddrphy_bitslip3_value2 <= 3'd7; - k7ddrphy_bitslip3_value3 <= 3'd7; - k7ddrphy_bitslip4_value0 <= 3'd7; - k7ddrphy_bitslip4_value1 <= 3'd7; - k7ddrphy_bitslip5_value0 <= 3'd7; - k7ddrphy_bitslip5_value1 <= 3'd7; - k7ddrphy_bitslip6_value0 <= 3'd7; - k7ddrphy_bitslip6_value1 <= 3'd7; - k7ddrphy_bitslip7_value0 <= 3'd7; - k7ddrphy_bitslip7_value1 <= 3'd7; - k7ddrphy_bitslip8_value0 <= 3'd7; - k7ddrphy_bitslip8_value1 <= 3'd7; - k7ddrphy_bitslip9_value0 <= 3'd7; - k7ddrphy_bitslip9_value1 <= 3'd7; - k7ddrphy_bitslip10_value0 <= 3'd7; - k7ddrphy_bitslip10_value1 <= 3'd7; - k7ddrphy_bitslip11_value0 <= 3'd7; - k7ddrphy_bitslip11_value1 <= 3'd7; - k7ddrphy_bitslip12_value0 <= 3'd7; - k7ddrphy_bitslip12_value1 <= 3'd7; - k7ddrphy_bitslip13_value0 <= 3'd7; - k7ddrphy_bitslip13_value1 <= 3'd7; - k7ddrphy_bitslip14_value0 <= 3'd7; - k7ddrphy_bitslip14_value1 <= 3'd7; - k7ddrphy_bitslip15_value0 <= 3'd7; - k7ddrphy_bitslip15_value1 <= 3'd7; - k7ddrphy_bitslip16_value0 <= 3'd7; - k7ddrphy_bitslip16_value1 <= 3'd7; - k7ddrphy_bitslip17_value0 <= 3'd7; - k7ddrphy_bitslip17_value1 <= 3'd7; - k7ddrphy_bitslip18_value0 <= 3'd7; - k7ddrphy_bitslip18_value1 <= 3'd7; - k7ddrphy_bitslip19_value0 <= 3'd7; - k7ddrphy_bitslip19_value1 <= 3'd7; - k7ddrphy_bitslip20_value0 <= 3'd7; - k7ddrphy_bitslip20_value1 <= 3'd7; - k7ddrphy_bitslip21_value0 <= 3'd7; - k7ddrphy_bitslip21_value1 <= 3'd7; - k7ddrphy_bitslip22_value0 <= 3'd7; - k7ddrphy_bitslip22_value1 <= 3'd7; - k7ddrphy_bitslip23_value0 <= 3'd7; - k7ddrphy_bitslip23_value1 <= 3'd7; - k7ddrphy_bitslip24_value0 <= 3'd7; - k7ddrphy_bitslip24_value1 <= 3'd7; - k7ddrphy_bitslip25_value0 <= 3'd7; - k7ddrphy_bitslip25_value1 <= 3'd7; - k7ddrphy_bitslip26_value0 <= 3'd7; - k7ddrphy_bitslip26_value1 <= 3'd7; - k7ddrphy_bitslip27_value0 <= 3'd7; - k7ddrphy_bitslip27_value1 <= 3'd7; - k7ddrphy_bitslip28_value0 <= 3'd7; - k7ddrphy_bitslip28_value1 <= 3'd7; - k7ddrphy_bitslip29_value0 <= 3'd7; - k7ddrphy_bitslip29_value1 <= 3'd7; - k7ddrphy_bitslip30_value0 <= 3'd7; - k7ddrphy_bitslip30_value1 <= 3'd7; - k7ddrphy_bitslip31_value0 <= 3'd7; - k7ddrphy_bitslip31_value1 <= 3'd7; - k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 64'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 64'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 64'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 64'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 15'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 15'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 15'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 15'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 15'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine0_row <= 15'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine1_row <= 15'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine2_row <= 15'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine3_row <= 15'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine4_row <= 15'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine5_row <= 15'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine6_row <= 15'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine7_row <= 15'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline; + k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip0_value0 <= 3'd7; + end + k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip1_value0 <= 3'd7; + end + k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip2_value0 <= 3'd7; + end + k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip3_value0 <= 3'd7; + end + k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip0_value1 <= 3'd7; + end + k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip1_value1 <= 3'd7; + end + k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip2_value1 <= 3'd7; + end + k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip3_value1 <= 3'd7; + end + k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]}; + k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline; + k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip0_value2 <= 3'd7; + end + k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip0_value3 <= 3'd7; + end + k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip1_value2 <= 3'd7; + end + k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip1_value3 <= 3'd7; + end + k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip2_value2 <= 3'd7; + end + k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip2_value3 <= 3'd7; + end + k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip3_value2 <= 3'd7; + end + k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip3_value3 <= 3'd7; + end + k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip4_value0 <= 3'd7; + end + k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip4_value1 <= 3'd7; + end + k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip5_value0 <= 3'd7; + end + k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip5_value1 <= 3'd7; + end + k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip6_value0 <= 3'd7; + end + k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip6_value1 <= 3'd7; + end + k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip7_value0 <= 3'd7; + end + k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip7_value1 <= 3'd7; + end + k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip8_value0 <= 3'd7; + end + k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip8_value1 <= 3'd7; + end + k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip9_value0 <= 3'd7; + end + k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip9_value1 <= 3'd7; + end + k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip10_value0 <= 3'd7; + end + k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip10_value1 <= 3'd7; + end + k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip11_value0 <= 3'd7; + end + k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip11_value1 <= 3'd7; + end + k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip12_value0 <= 3'd7; + end + k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip12_value1 <= 3'd7; + end + k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip13_value0 <= 3'd7; + end + k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip13_value1 <= 3'd7; + end + k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip14_value0 <= 3'd7; + end + k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip14_value1 <= 3'd7; + end + k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip15_value0 <= 3'd7; + end + k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip15_value1 <= 3'd7; + end + k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip16_value0 <= 3'd7; + end + k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip16_value1 <= 3'd7; + end + k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip17_value0 <= 3'd7; + end + k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip17_value1 <= 3'd7; + end + k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip18_value0 <= 3'd7; + end + k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip18_value1 <= 3'd7; + end + k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip19_value0 <= 3'd7; + end + k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip19_value1 <= 3'd7; + end + k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip20_value0 <= 3'd7; + end + k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip20_value1 <= 3'd7; + end + k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip21_value0 <= 3'd7; + end + k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip21_value1 <= 3'd7; + end + k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip22_value0 <= 3'd7; + end + k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip22_value1 <= 3'd7; + end + k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip23_value0 <= 3'd7; + end + k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip23_value1 <= 3'd7; + end + k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip24_value0 <= 3'd7; + end + k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip24_value1 <= 3'd7; + end + k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip25_value0 <= 3'd7; + end + k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip25_value1 <= 3'd7; + end + k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip26_value0 <= 3'd7; + end + k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip26_value1 <= 3'd7; + end + k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip27_value0 <= 3'd7; + end + k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip27_value1 <= 3'd7; + end + k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip28_value0 <= 3'd7; + end + k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip28_value1 <= 3'd7; + end + k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip29_value0 <= 3'd7; + end + k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip29_value1 <= 3'd7; + end + k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip30_value0 <= 3'd7; + end + k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip30_value1 <= 3'd7; + end + k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin + k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip31_value0 <= 3'd7; + end + k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]}; + if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin + k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1); + end + if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin + k7ddrphy_bitslip31_value1 <= 3'd7; + end + k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]}; + k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en); + k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0; + k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1; + k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2; + k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3; + k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4; + k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5; + k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6; + k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en); + k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0; + k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if (litedramcore_csr_dfi_p2_rddata_valid) begin + litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + end + if (litedramcore_csr_dfi_p3_rddata_valid) begin + litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_rst0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w; + end + 4'd13: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w; + end + 4'd14: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w; + end + 4'd15: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w; + end + 5'd16: begin + interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w; + end + 5'd17: begin + interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + end + 5'd18: begin + interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + end + endcase + end + if (csrbank1_rst0_re) begin + k7ddrphy_rst_storage <= csrbank1_rst0_r; + end + k7ddrphy_rst_re <= csrbank1_rst0_re; + if (csrbank1_dly_sel0_re) begin + k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r; + end + k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + if (csrbank1_half_sys8x_taps0_re) begin + k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + end + k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + end + k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_rdphase0_re) begin + k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + end + k7ddrphy_rdphase_re <= csrbank1_rdphase0_re; + if (csrbank1_wrphase0_re) begin + k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + end + k7ddrphy_wrphase_re <= csrbank1_wrphase0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w; + end + 5'd25: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + end + 5'd26: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd27: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + end + 5'd28: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + end + 5'd29: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w; + end + 5'd30: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + end + 5'd31: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w; + end + 6'd32: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + end + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + end + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata1_re) begin + litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r; + end + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata1_re) begin + litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r; + end + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; + litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re; + if (sys_rst) begin + k7ddrphy_rst_storage <= 1'd0; + k7ddrphy_rst_re <= 1'd0; + k7ddrphy_dly_sel_storage <= 4'd0; + k7ddrphy_dly_sel_re <= 1'd0; + k7ddrphy_half_sys8x_taps_storage <= 5'd8; + k7ddrphy_half_sys8x_taps_re <= 1'd0; + k7ddrphy_wlevel_en_storage <= 1'd0; + k7ddrphy_wlevel_en_re <= 1'd0; + k7ddrphy_rdphase_storage <= 2'd1; + k7ddrphy_rdphase_re <= 1'd0; + k7ddrphy_wrphase_storage <= 2'd2; + k7ddrphy_wrphase_re <= 1'd0; + k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + k7ddrphy_bitslip0_value0 <= 3'd7; + k7ddrphy_bitslip1_value0 <= 3'd7; + k7ddrphy_bitslip2_value0 <= 3'd7; + k7ddrphy_bitslip3_value0 <= 3'd7; + k7ddrphy_bitslip0_value1 <= 3'd7; + k7ddrphy_bitslip1_value1 <= 3'd7; + k7ddrphy_bitslip2_value1 <= 3'd7; + k7ddrphy_bitslip3_value1 <= 3'd7; + k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + k7ddrphy_bitslip0_value2 <= 3'd7; + k7ddrphy_bitslip0_value3 <= 3'd7; + k7ddrphy_bitslip1_value2 <= 3'd7; + k7ddrphy_bitslip1_value3 <= 3'd7; + k7ddrphy_bitslip2_value2 <= 3'd7; + k7ddrphy_bitslip2_value3 <= 3'd7; + k7ddrphy_bitslip3_value2 <= 3'd7; + k7ddrphy_bitslip3_value3 <= 3'd7; + k7ddrphy_bitslip4_value0 <= 3'd7; + k7ddrphy_bitslip4_value1 <= 3'd7; + k7ddrphy_bitslip5_value0 <= 3'd7; + k7ddrphy_bitslip5_value1 <= 3'd7; + k7ddrphy_bitslip6_value0 <= 3'd7; + k7ddrphy_bitslip6_value1 <= 3'd7; + k7ddrphy_bitslip7_value0 <= 3'd7; + k7ddrphy_bitslip7_value1 <= 3'd7; + k7ddrphy_bitslip8_value0 <= 3'd7; + k7ddrphy_bitslip8_value1 <= 3'd7; + k7ddrphy_bitslip9_value0 <= 3'd7; + k7ddrphy_bitslip9_value1 <= 3'd7; + k7ddrphy_bitslip10_value0 <= 3'd7; + k7ddrphy_bitslip10_value1 <= 3'd7; + k7ddrphy_bitslip11_value0 <= 3'd7; + k7ddrphy_bitslip11_value1 <= 3'd7; + k7ddrphy_bitslip12_value0 <= 3'd7; + k7ddrphy_bitslip12_value1 <= 3'd7; + k7ddrphy_bitslip13_value0 <= 3'd7; + k7ddrphy_bitslip13_value1 <= 3'd7; + k7ddrphy_bitslip14_value0 <= 3'd7; + k7ddrphy_bitslip14_value1 <= 3'd7; + k7ddrphy_bitslip15_value0 <= 3'd7; + k7ddrphy_bitslip15_value1 <= 3'd7; + k7ddrphy_bitslip16_value0 <= 3'd7; + k7ddrphy_bitslip16_value1 <= 3'd7; + k7ddrphy_bitslip17_value0 <= 3'd7; + k7ddrphy_bitslip17_value1 <= 3'd7; + k7ddrphy_bitslip18_value0 <= 3'd7; + k7ddrphy_bitslip18_value1 <= 3'd7; + k7ddrphy_bitslip19_value0 <= 3'd7; + k7ddrphy_bitslip19_value1 <= 3'd7; + k7ddrphy_bitslip20_value0 <= 3'd7; + k7ddrphy_bitslip20_value1 <= 3'd7; + k7ddrphy_bitslip21_value0 <= 3'd7; + k7ddrphy_bitslip21_value1 <= 3'd7; + k7ddrphy_bitslip22_value0 <= 3'd7; + k7ddrphy_bitslip22_value1 <= 3'd7; + k7ddrphy_bitslip23_value0 <= 3'd7; + k7ddrphy_bitslip23_value1 <= 3'd7; + k7ddrphy_bitslip24_value0 <= 3'd7; + k7ddrphy_bitslip24_value1 <= 3'd7; + k7ddrphy_bitslip25_value0 <= 3'd7; + k7ddrphy_bitslip25_value1 <= 3'd7; + k7ddrphy_bitslip26_value0 <= 3'd7; + k7ddrphy_bitslip26_value1 <= 3'd7; + k7ddrphy_bitslip27_value0 <= 3'd7; + k7ddrphy_bitslip27_value1 <= 3'd7; + k7ddrphy_bitslip28_value0 <= 3'd7; + k7ddrphy_bitslip28_value1 <= 3'd7; + k7ddrphy_bitslip29_value0 <= 3'd7; + k7ddrphy_bitslip29_value1 <= 3'd7; + k7ddrphy_bitslip30_value0 <= 3'd7; + k7ddrphy_bitslip30_value1 <= 3'd7; + k7ddrphy_bitslip31_value0 <= 3'd7; + k7ddrphy_bitslip31_value1 <= 3'd7; + k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 64'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 64'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_rddata_status <= 64'd0; + litedramcore_phaseinjector2_rddata_re <= 1'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_rddata_status <= 64'd0; + litedramcore_phaseinjector3_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 15'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 15'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 15'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -20430,14 +20650,14 @@ IOBUF IOBUF_31( reg [24:0] storage[0:15]; reg [24:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -20448,14 +20668,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [24:0] storage_1[0:15]; reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -20466,14 +20686,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [24:0] storage_2[0:15]; reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -20484,14 +20704,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [24:0] storage_3[0:15]; reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -20502,14 +20722,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [24:0] storage_4[0:15]; reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -20520,14 +20740,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [24:0] storage_5[0:15]; reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -20538,14 +20758,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [24:0] storage_6[0:15]; reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -20556,14 +20776,14 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [24:0] storage_7[0:15]; reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( @@ -20657,7 +20877,8 @@ PLLE2_ADV #( .LOCKED(locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), @@ -20667,7 +20888,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), @@ -20677,7 +20899,8 @@ PLLE2_ADV #( .Q(iodelay_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), @@ -20687,7 +20910,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), @@ -20697,7 +20921,8 @@ PLLE2_ADV #( .Q(sys_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), @@ -20707,7 +20932,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), @@ -20717,7 +20943,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), @@ -20727,7 +20954,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), @@ -20740,5 +20968,5 @@ PLLE2_ADV #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:06:58. +// Auto-Generated by LiteX on 2022-10-28 19:01:22. //------------------------------------------------------------------------------ diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 9006b18..61e54f3 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842adc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048002135 -386100207c7f1b78 -6000000048001b4d +6000000048002139 +7fc3f3787c7f1b78 +6000000048001b59 7fe3fb78382100b0 -000000004800283c -0000018001000000 +000000004800285c +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842ad283c4c0001 +3842ad203c4c0001 7d6000267c0802a6 -9161000848002775 -48001b49f821fed1 +9161000848002799 +48001b55f821fed1 3c62ffff60000000 -4bffff4138637af0 +4bffff3938637b18 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b10 -3c62ffff4bffff1d -38637b307bff0020 -7c0004ac4bffff0d +63ff000838637b38 +3c62ffff4bffff15 +38637b587bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b48 +4bfffee938637b70 4d80000073e90002 3c62ffff41820010 -4bfffed938637b50 +4bfffed138637b78 4e00000073e90004 3c62ffff41820010 -4bfffec138637b58 +4bfffeb938637b80 4d00000073e90008 3c62ffff41820010 -4bfffea938637b60 +4bfffea138637b88 4182001073e90010 -38637b703c62ffff -73ff01004bfffe95 +38637b983c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637b80 -3b7b7b883f62ffff -4bfffe717f63db78 +4bfffe7938637ba8 +3b7b7bb03f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637b90 +4bfffe4138637bb8 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637ba8 +4bfffe1938637bd0 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637bc07884b282 -3d20c0004bfffdfd +38637be87884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637bd87c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c00 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637bf8 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c2057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c185784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c4057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c38 -7f40efaa7c0004ac +4bfffc8138637c60 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c503c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637c783c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637c607bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637c803c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c48 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637d90 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048001865 -38637db03c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847c983c62ffff -4bfffb0938637ca8 -6000000048000c3d -3c82ffff4bffff54 -38847c983c62ffff -4bfffae938637ca8 -6000000048000c1d -3c62ffff4bffff80 -4bfffad138637cc8 -38a000403c9ef000 -3861007078840020 -60000000480017ed -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637c883be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637cb838847ca8 +48000ccd4bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637cd8 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637c703c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637cf0 +38a000403c9af000 +7884002038610070 +6000000048001819 +e92100703d400002 614a464c3c62ffff -794a83e438637ce0 +794a83e438637d08 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d003c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d283c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637d6088810070 +38637d8888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d183ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637db8 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048001771 +38637dd83c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d403b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d40 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637d68 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480022507d638120 -38a000383c9ef000 -386100b078840020 -6000000048001705 +480022547d638120 +38a000383c9ff000 +788400207f23cb78 +60000000480016f1 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -60000000480016bd -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +60000000480016a9 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,7 +742,7 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -3842a6e83c4c0001 +3842a6c03c4c0001 4182006828030002 4182003028030003 4082007c28030001 @@ -815,26 +820,26 @@ ebe100b8eb8100c0 614a100c39200000 000000004bffffd4 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -7c0802a63842a444 -60e700033ce08020 -78e7002039200000 -f821ffa148001e99 -3941001f7c7d1b78 -7d0a4a143bc10020 -7d4903a639400004 +7c0802a63842a41c +f821ffa148001ead +392000003cc08020 +7c7d1b7860c60003 +78c6002038e1001f +3bc1002039400004 +7d4903a67d074a14 788407e0788af862 -7c8438387c8400d0 +7c8430387c8400d0 7d4453787c8a5278 4200ffe49d480001 2829001039290004 -3d40c8004082ffc4 +3d40c8004082ffc8 614a100c39200000 7c0004ac794a0020 3d40c8007d20572a @@ -843,11 +848,11 @@ f821ffa148001e99 4bfffc8938600009 4bffff2d3860000f 3cc0c8003d20c800 -60c6107461291014 -792900207fcaf378 +612910147fcaf378 +7929002060c61074 38a0000478c60020 -7ca903a638eaffff -8ca7000139000000 +3900000038eaffff +8ca700017ca903a6 7ca82b787905400c 7c0004ac4200fff4 392900187ca04f2a @@ -862,7 +867,7 @@ f821ffa148001e99 57e3063e38800017 4bfffc2d3fe0c800 3860000f63ff082c -7bff00204bfffe89 +4bfffe857bff0020 7c60fe2a7c0004ac 4bfffe055463063e 7c60fe2a7c0004ac @@ -879,17 +884,17 @@ f821ffa148001e99 3be100303860000b 3860000f4bfffb65 3ce0c8004bfffe09 -60e710183d60c800 -3c6033333c005555 -616b10783d800f0f -78e7002038800000 -211d000138a00000 -6063333360005555 -796b0020618c0f0f +3c0055553d60c800 +3d800f0f3c603333 +38a0000038800000 +60e71018211d0001 +60005555616b1078 +618c0f0f60633333 +796b002078e70020 7d203e2a7c0004ac 792900203ba00004 -38c100347fa903a6 -9d26ffff39400004 +3940000438c10034 +9d26ffff7fa903a6 7929c202394affff 392000044200fff4 7d2452147d2903a6 @@ -906,18 +911,18 @@ f821ffa148001e99 552906be7d293214 394a00017ca54a14 38e700184200ff9c -7c2758003bde0004 -4082ff5438840004 +388400043bde0004 +4082ff547c275800 78a3002038210060 -0000000048001c48 +0000000048001c4c 0000038001000000 -3842a1783c4c0001 -48001bcd7c0802a6 -7c7f1b78f821ff61 -4bfffb213b800000 +3842a1503c4c0001 +48001bd17c0802a6 +3b800000f821ff61 +4bfffb217c7f1b78 7fe3fb783880002a -388000544bfffd15 -7c7e1b783bbc0001 +4bfffd113bbc0001 +7c7e1b7838800054 4bfffd017fe3fb78 2c0300007c63f214 2c1d00204182001c @@ -925,9 +930,9 @@ f821ffa148001e99 4bfffb2d7fbceb78 7f9de3784bffffc0 3b5c00047fe3fb78 -7fe3fb784bfffb19 -4bfffb0d7f5bd378 -3bc0ffff7fe3fb78 +4bfffb153bc0ffff +7f5bd3787fe3fb78 +7fe3fb784bfffb09 7fe3fb784bfffb01 3880002a4bfffaf9 4bfffca17fe3fb78 @@ -941,590 +946,587 @@ f821ffa148001e99 4bffffb84bfffab1 3ba0ffff3b800020 2c1effff4bffff80 -2c1a001f4082001c -418100083bc00000 -3b9c000523da001f -2c1dffff7fdee214 -3c62ffff4082001c -4bfff2a138637dc8 -382100a060000000 -7cbdf05048001b00 -7ca50e707c9df214 -789cfee27ca50194 -7ca507b43c62ffff -38637dd87f84e378 -4bfff2693bc00008 -7fe3fb7860000000 -4bfff9d93ba00000 -4bfffb9538600064 -4082003c7c1ce800 -7fe3fb783880002a -388000544bfffbbd -7fe3fb787c7d1b78 -7c63ea144bfffbad -4182ff882c030000 -2c1e00003bdeffff -4bffff784082ffb4 -3bbd00017fe3fb78 -386000644bfff9d1 -4bffffac4bfffb41 -0100000000000000 -3c4c000100000780 -3d20c80038429fa4 -7929002061291000 -7d404e2a7c0004ac -4d820020280a000e -3940000e7c0802a6 -f821ffa1f8010010 -7d404f2a7c0004ac +23da001f40820018 +3b9c00052c1a001f +7fdee2147fc0f05e +4082001c2c1dffff 38637df03c62ffff -600000004bfff1a5 -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -3d20c80038429f3c -7929002061291000 -7d404e2a7c0004ac -4d820020280a0001 -394000017c0802a6 +600000004bfff27d +48001b08382100a0 +7c9df2147cbdf050 +3bc000083c62ffff +7ca501947ca50e70 +38637e00789cfee2 +7ca507b47f84e378 +600000004bfff245 +3ba000007fe3fb78 +386000644bfff9dd +7c1ce8004bfffb99 +3880002a4082003c +4bfffbc17fe3fb78 +7c7d1b7838800054 +4bfffbb17fe3fb78 +2c0300007c63ea14 +3bdeffff4182ff88 +4082ffb42c1e0000 +7fe3fb784bffff78 +4bfff9d53bbd0001 +4bfffb4538600064 +000000004bffffac +0000078001000000 +38429f803c4c0001 +612910003d20c800 +7c0004ac79290020 +280a000e7d404e2a +7c0802a64d820020 f821ffa1f8010010 -7d404f2a7c0004ac -38637e183c62ffff -600000004bfff13d -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429ed4 -39297e403d22ffff -f821ff01480018f5 -3f00c8003f80c800 -3e62ffff3e82ffff -639c08043f22ffff -3e42ffff63180820 -3b4000013ba00000 -3ae00000f9210060 -3a737e583a947e50 -7b9c00203b397b88 -3a527e607b180020 -7fb0eb787ba307e0 -7f56e8304bfff8c5 +7c0004ac3940000e +3c62ffff7d404f2a +4bfff18138637e18 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429f183c4c0001 +612910003d20c800 +7c0004ac79290020 +280a00017d404e2a +7c0802a64d820020 +f821ffa1f8010010 +7c0004ac39400001 +3c62ffff7d404f2a +4bfff11938637e40 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429eb03c4c0001 +480019057c0802a6 +3f80c800f821ff01 +3ba000003f00c800 +3ae000003b400001 +3e82ffff3d22ffff +3f22ffff3e62ffff +63180820639c0804 +39297e683e42ffff +3a737e803a947e78 +7b9c00203b397bb0 +3a527e887b180020 +7ba307e0f9210060 +7f56e8307fb0eb78 3a2000003be00000 7fbe07b439e00000 -7de507b4e8610060 -39c000207fc4f378 -4bfff0813b600000 -7fc3f37860000000 -3880002a4bfff7f5 -4bfff9e97fc3f378 -7c751b7838800054 -4bfff9d97fc3f378 -7c6400347c63aa14 -7e83a37821230080 -548a60265484d97e -7d2952147c8407b4 -4bfff0317f7b4a14 +e86100604bfff8b5 +7fc4f3787de507b4 +3b60000039c00020 +600000004bfff05d +4bfff7f97fc3f378 +7fc3f3783880002a +388000544bfff9ed +7fc3f3787c751b78 +7c63aa144bfff9dd +212300807c640034 +5484d97e7e83a378 +7c8407b4548a6026 +7f7b4a147d295214 +600000004bfff00d +4bfff7f57fc3f378 +4082ffac35ceffff +4bffeff17e639b78 7fc3f37860000000 -35ceffff4bfff7f1 -7e639b784082ffac -600000004bfff015 -4bfffc557fc3f378 -4bfff0017f23cb78 -7c11d84060000000 -7dff7b784080000c -2c0f00077f71db78 -7c0004ac4182002c -7c0004ac7ec0e72a -7c0004ac7f40c72a -39ef00017ee0e72a -3ba000014bffff30 -7fe507b44bffff08 -7e4393787fc4f378 -4bffefa97bff0020 -7a0307e060000000 -393f00014bfff7b5 -420000287d2903a6 -4bfffbd57fc3f378 -4bffef817f23cb78 -2c1d000060000000 -382101004182ffb4 -7c0004ac480017ac -7c0004ac7ec0e72a -7c0004ac7f40c72a -4bffffc07ee0e72a -0100000000000000 -3c4c000100001280 -7c0802a638429cfc -f821ffa1f8010010 -386000004bfffd4d -386000004bfff6a5 -386000014bfff735 -386000014bfff695 -3c62ffff4bfff725 -4bffef0138637e78 -4bfffde960000000 -382100604bfffd7d -e801001038600001 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429c8c -6129082c3d20c800 -480016cd79290020 -3b000002f821ff51 -7f004f2a7c0004ac -3b2000033d20c800 -7929002061290830 -7f204f2a7c0004ac -3c62ffff3fc0c800 -38637e883c804000 -4bffee7963de0800 -3b80000160000000 -7bde00204bfffc8d -7f80f72a7c0004ac -3be00000386003e8 -7c0004ac4bfff799 -386003e87fe0f72a -4bfff7853f60c800 -7c0004ac7b7b0020 -3f40c8007fe0df2a -7b5a0020635a0004 -7fe0d72a7c0004ac -63bd100c3fa0c800 -7c0004ac7bbd0020 -3fc0c8007fe0ef2a -7bde002063de1010 +7f23cb784bfffc59 +600000004bffefdd +4080000c7c11d840 +7f71db787dff7b78 +4182002c2c0f0007 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +4bffff3039ef0001 +4bffff083ba00001 +7fc4f3787fe507b4 +7bff00207e439378 +600000004bffef85 +4bfff7b97a0307e0 +7d2903a6393f0001 +7fc3f37842000028 +7f23cb784bfffbd9 +600000004bffef5d +4182ffb42c1d0000 +480017b438210100 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +000000004bffffc0 +0000128001000000 +38429cd83c4c0001 +f80100107c0802a6 +4bfffd4df821ffa1 +4bfff6a938600000 +4bfff73938600000 +4bfff69938600001 +4bfff72938600001 +38637ea03c62ffff +600000004bffeedd +4bfffd7d4bfffde9 +3860000138210060 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429c683c4c0001 +480016e17c0802a6 +3d20c800f821ff51 +6129082c3b000002 +7c0004ac79290020 +3d20c8007f004f2a +612908303b200003 +7c0004ac79290020 +3fc0c8007f204f2a +3c8040003c62ffff +38637eb03b800001 +4bffee5163de0800 +7bde002060000000 +7c0004ac4bfffc89 +386003e87f80f72a +4bfff79d3be00000 7fe0f72a7c0004ac -3920000c3ee0c800 -7af7002062f71000 -7d20bf2a7c0004ac -6063c35038600000 -7c0004ac4bfff719 -7c0004ac7fe0ef2a -3920000e7fe0f72a -7d20bf2a7c0004ac -4bfff6f538602710 -7c0004ac39200200 -7c0004ac7d20ef2a -3860000f7f00f72a -7c0004ac4bfff42d -7c0004ac7fe0ef2a -3860000f7f20f72a -392000064bfff415 +3f60c800386003e8 +7b7b00204bfff789 +7fe0df2a7c0004ac +635a00043f40c800 +7c0004ac7b5a0020 +3fa0c8007fe0d72a +7bbd002063bd100c +7fe0ef2a7c0004ac +63de10103fc0c800 +7c0004ac7bde0020 +3ee0c8007fe0f72a +62f710003920000c +7c0004ac7af70020 +386000007d20bf2a +4bfff71d6063c350 +7fe0ef2a7c0004ac +7fe0f72a7c0004ac +7c0004ac3920000e +386027107d20bf2a +392002004bfff6f9 7d20ef2a7c0004ac -7f80f72a7c0004ac -4bfff3f93860000f -7c0004ac39200930 +7f00f72a7c0004ac +4bfff4313860000f +7fe0ef2a7c0004ac +7f20f72a7c0004ac +4bfff4193860000f +7c0004ac39200006 7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff3dd -392004004bfff681 +3860000f7f80f72a +392009304bfff3fd 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff3b938600003 -4bfff65d386000c8 -4bfffb994bfffddd -3c6040003c800020 -60000000480006e9 -408200242c030000 -7c0004ac7c691b78 -7c0004ac7f80d72a -382100b07f80df2a -4800153c7d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bfff3e13860000f +4bfff685386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff3bd +4bfffddd4bfff661 +3c8000204bfffb99 +480006e13c604000 +2c03000060000000 +7c691b7840820024 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000980 -7c0802a638429a5c -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffec7938637ea8 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637eb03c62ffff -600000004bffec3d -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ec07ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b4382100b0 +38c0000048001544 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000098001000000 +38429a383c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ed03c62ffff +600000004bffec55 +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ed0 -0100000000000000 -3c4c000100000080 -7c0802a63842998c -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffec1938637ed8 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637ee8 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ee078c60020 +38637ef87ca54b92 +000000004bffffa4 +0000008001000000 +384299683c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffeb9d -4bfffef97fe3fb78 -38637ef03c62ffff -600000004bffeb85 -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -384298e83c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffeb7938637f08 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffeb6138637f18 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384298c4 +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffeb59 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffeb09 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffeb3d42000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffeaed7fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384297d83c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187ef87bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637ef8 -3c62ffff4bfffde5 -4bffe9a138637b88 -4bffea0560000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a6384297b4 +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f20 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f20 +38637bb03c62ffff +600000004bffe97d +600000004bffe9e9 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f08 -3c62ffff4bfffd8d -4bffe94938637b88 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f08 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384296183c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f30 +38637bb03c62ffff +600000004bffe925 +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f307ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a6384295f4 +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f183c62ffff -4bffe8197cbc2b78 -3c62ffff60000000 -4092000c38637f30 -38637f403c62ffff -600000004bffe7fd -4bfffb597fc3f378 -38637f503c62ffff -600000004bffe7e5 -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f402e3b0000 +600000004bffe7f5 38637f583c62ffff -4bffe7617f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffe74938637f68 +3c62ffff4092000c +4bffe7d938637f68 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffe7c138637f78 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8005f57d3602a6 +7929002078ea0020 +639ce1003c62ffff +38637f807d295050 +7f9c4b927f9ee1d2 +600000004bffe73d +4bfffabd7f83e378 +38637f903c62ffff +600000004bffe725 +38637bb03c62ffff +600000004bffe715 +600000004bffe781 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4005f5 +3c62ffff79290020 +7d29e050614ae100 +7fde51d238637f98 +4bffe6797fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffe66138637f90 3c62ffff60000000 -4bffe73938637b88 -4bffe79d60000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f70 -600000004bffe69d -4bfff9f97fc3f378 -38637f683c62ffff -600000004bffe685 -38637b883c62ffff -600000004bffe675 -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384293e03c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffe65138637bb0 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384293c4 +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f807fc4f378 -600000004bffe5ed -4bfff9497fe3fb78 -38637f503c62ffff +7c641b787f9c205e +38637fa83c62ffff 600000004bffe5d5 +4bfff9557fe3fb78 +38637f783c62ffff +600000004bffe5bd 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffe58938637f90 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fa838800000 -600000004bffe55d -7be5f0823c62ffff -38637fc07fc4f378 -600000004bffe545 -38637fd83c62ffff -600000004bffe535 -3821008038600000 -48000d987c6307b4 -38637fe83c62ffff -600000004bffe515 -4bffffe038600001 -0100000000000000 -3c4c000100000480 -60000000384292b4 -6000000089228068 -2c09000039428060 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228060 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428060 -4e8000207d2057ea +4bffe57138637fb8 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fd0 +4bffe54978a5f082 +3c62ffff60000000 +7fc4f3787be5f082 +4bffe53138637fe8 +6000000060000000 +4bffe52138628000 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffe50138628010 +3860000160000000 +000000004bffffe0 +0000048001000000 +384292a03c4c0001 +6000000060000000 +3942808889228090 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e922808860000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94280885469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842922c -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384291cc -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428060 -9942806860000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942806060000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228068 -3920ff806108200c -7c0004ac79080020 -e92280607d2047aa -7d404faa7c0004ac -794ac202e9228060 -7c0004ac39290004 -e92280607d404faa -3929000c39400003 +384292183c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384291b83c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f942808860000000 +6000000039400000 +3d40001c99428090 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf9428088 +7d495392614a2000 +600000004182ffa0 +9922809039200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace9228088 +e92280887d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228060 +39400003e9228088 +7c0004ac3929000c +e92280887d404faa +7c0004ac39290010 +e92280887d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228060 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 -0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +000000004e800020 +0000000000000000 +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428e94 -f821ffa1480008e9 +7c0802a638428e84 +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1536,36 +1538,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428dc4 -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428db4 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428d483c4c0001 -3d22ffff7c0802a6 -2b860010e9297ff8 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428d383c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922800060000000 +2b8600107caa2b78 +f9210020e9228020 +e922802860000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -1573,253 +1575,256 @@ e922800060000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428c54 -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b7488 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428c483c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b7494 +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028018 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c676443cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028040 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a7654 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942801860000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280187aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028040 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028040 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2801038610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280387de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1870,15 +1875,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 0453ea2..0bf0d54 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:06:57 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:20 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [14:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -69,1941 +69,2065 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; -wire iodelay_clk; -wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [14:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [14:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [14:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [14:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [14:0] litedramcore_master_p2_address = 15'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [14:0] litedramcore_master_p3_address = 15'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [14:0] litedramcore_dfi_p2_address = 15'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [14:0] litedramcore_dfi_p3_address = 15'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [14:0] litedramcore_nop_a = 15'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [14:0] array_muxed15 = 15'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [14:0] array_muxed22 = 15'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg rst_1 = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire reset; +reg power_down = 1'd0; +wire locked; +wire clkin; +wire clkout0; +wire clkout_buf0; +wire clkout1; +wire clkout_buf1; +wire clkout2; +wire clkout_buf2; +wire clkout3; +wire clkout_buf3; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +reg a7ddrphy_wlevel_strobe_re = 1'd0; +wire a7ddrphy_wlevel_strobe_r; +reg a7ddrphy_wlevel_strobe_we = 1'd0; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg a7ddrphy_rdly_dq_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_r; +reg a7ddrphy_rdly_dq_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_inc_re = 1'd0; +wire a7ddrphy_rdly_dq_inc_r; +reg a7ddrphy_rdly_dq_inc_we = 1'd0; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_r; +reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_r; +reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [14:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [14:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [14:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [14:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +wire [2:0] a7ddrphy_pads_ba; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip21; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip31; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [14:0] litedramcore_master_p2_address = 15'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [14:0] litedramcore_master_p3_address = 15'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p2_address; +wire [2:0] litedramcore_csr_dfi_p2_bank; +reg litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg litedramcore_csr_dfi_p2_we_n = 1'd1; +wire litedramcore_csr_dfi_p2_cke; +wire litedramcore_csr_dfi_p2_odt; +wire litedramcore_csr_dfi_p2_reset_n; +reg litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p2_wrdata; +wire litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; +wire litedramcore_csr_dfi_p2_rddata_en; +reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; +reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p3_address; +wire [2:0] litedramcore_csr_dfi_p3_bank; +reg litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg litedramcore_csr_dfi_p3_we_n = 1'd1; +wire litedramcore_csr_dfi_p3_cke; +wire litedramcore_csr_dfi_p3_odt; +wire litedramcore_csr_dfi_p3_reset_n; +reg litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p3_wrdata; +wire litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; +wire litedramcore_csr_dfi_p3_rddata_en; +reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; +reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; +reg litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg litedramcore_ext_dfi_p2_we_n = 1'd1; +reg litedramcore_ext_dfi_p2_cke = 1'd0; +reg litedramcore_ext_dfi_p2_odt = 1'd0; +reg litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; +reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; +reg litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg litedramcore_ext_dfi_p3_we_n = 1'd1; +reg litedramcore_ext_dfi_p3_cke = 1'd0; +reg litedramcore_ext_dfi_p3_odt = 1'd0; +reg litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; +reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_phaseinjector2_csrfield_cs; +wire litedramcore_phaseinjector2_csrfield_we; +wire litedramcore_phaseinjector2_csrfield_cas; +wire litedramcore_phaseinjector2_csrfield_ras; +wire litedramcore_phaseinjector2_csrfield_wren; +wire litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +reg litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_r; +reg litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; +wire litedramcore_phaseinjector2_rddata_we; +reg litedramcore_phaseinjector2_rddata_re = 1'd0; +wire litedramcore_phaseinjector3_csrfield_cs; +wire litedramcore_phaseinjector3_csrfield_we; +wire litedramcore_phaseinjector3_csrfield_cas; +wire litedramcore_phaseinjector3_csrfield_ras; +wire litedramcore_phaseinjector3_csrfield_wren; +wire litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +reg litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_r; +reg litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; +wire litedramcore_phaseinjector3_rddata_we; +reg litedramcore_phaseinjector3_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [14:0] litedramcore_dfi_p2_address = 15'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [14:0] litedramcore_dfi_p3_address = 15'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +wire [1:0] litedramcore_rdcmdphase; +wire [1:0] litedramcore_wrcmdphase; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_rst0_re = 1'd0; +wire csrbank1_rst0_r; +reg csrbank1_rst0_we = 1'd0; +wire csrbank1_rst0_w; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_r; +reg csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_w; +reg csrbank1_wlevel_en0_re = 1'd0; +wire csrbank1_wlevel_en0_r; +reg csrbank1_wlevel_en0_we = 1'd0; +wire csrbank1_wlevel_en0_w; +reg csrbank1_rdphase0_re = 1'd0; +wire [1:0] csrbank1_rdphase0_r; +reg csrbank1_rdphase0_we = 1'd0; +wire [1:0] csrbank1_rdphase0_w; +reg csrbank1_wrphase0_re = 1'd0; +wire [1:0] csrbank1_wrphase0_r; +reg csrbank1_wrphase0_we = 1'd0; +wire [1:0] csrbank1_wrphase0_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +reg csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +reg csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_w; +reg csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_r; +reg csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_w; +reg csrbank2_dfii_pi2_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address0_r; +reg csrbank2_dfii_pi2_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi2_address0_w; +reg csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +reg csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; +reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +reg csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +reg csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_w; +reg csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_r; +reg csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_w; +reg csrbank2_dfii_pi3_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address0_r; +reg csrbank2_dfii_pi3_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi3_address0_w; +reg csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +reg csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; +reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +reg csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +reg csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_reset0; +wire litedramcore_reset1; +wire litedramcore_reset2; +wire litedramcore_reset3; +wire litedramcore_reset4; +wire litedramcore_reset5; +wire litedramcore_reset6; +wire litedramcore_reset7; +wire litedramcore_pll_fb; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [14:0] rhs_array_muxed1 = 15'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [14:0] rhs_array_muxed7 = 15'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [21:0] rhs_array_muxed24 = 22'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [21:0] rhs_array_muxed27 = 22'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [21:0] rhs_array_muxed30 = 22'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [21:0] rhs_array_muxed33 = 22'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [14:0] array_muxed1 = 15'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [14:0] array_muxed8 = 15'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [14:0] array_muxed15 = 15'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [14:0] array_muxed22 = 15'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2047,144 +2171,144 @@ assign ddram_ba = a7ddrphy_pads_ba; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); @@ -2192,1074 +2316,1074 @@ assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7d assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) - 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) - 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) - 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) - 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) - 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) - 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) - 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) - 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) - 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) - 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) - 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) - 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) - 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) - 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) - 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) - 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) - 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) - 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) - 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) - 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) - 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) - 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) - 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) - 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) - 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) - 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) - 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) - 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) - 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) - 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) - 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) - 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) - 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) - 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) - 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) - 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -3390,892 +3514,892 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end + litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; - end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; - end - end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; - end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; - end - end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; - end - end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; - end - end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; - end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; - end - end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end - end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; - end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; - end - end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; - end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; - end - end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; - end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; - end - end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; - end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; - end - end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; - end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; - end - end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; - end - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; - end - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; - end - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - litedramcore_master_p3_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; - end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; - end - end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; - end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; - end - end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; - end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; - end - end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; - end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; - end - end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end -end -always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; - end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; - end - end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; - end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; - end - end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end - end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end - end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end - end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end - end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; - end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; - end - end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; - end - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; - end - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; - end - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + end else begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; + end + end else begin + litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + end else begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + end + end else begin + litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end + end else begin + litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end + end else begin + litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end + end else begin + litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end + end else begin + litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + end else begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + end + end else begin + litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + end else begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + end + end else begin + litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + end + end else begin + litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + end else begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + end + end else begin + litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + end + end else begin + litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end + end else begin + litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end + end else begin + litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end + end else begin + litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end + end else begin + litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end + end else begin + litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end + end else begin + litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end + end else begin + litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + end else begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + end + end else begin + litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + end + end else begin + litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + end else begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + end + end else begin + litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + end + end else begin + litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + end + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + end + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + end + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -4290,36 +4414,36 @@ assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -4328,36 +4452,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -4366,36 +4490,36 @@ assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_ assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); - end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + end else begin + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); - end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + end else begin + litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); - end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + end else begin + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; @@ -4404,36 +4528,36 @@ assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_ assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); - end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + end else begin + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); - end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + end else begin + litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); - end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + end else begin + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; @@ -4511,4590 +4635,4686 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase end assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); @@ -9127,15 +9347,15 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9145,106 +9365,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9254,22 +9474,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -9286,473 +9506,473 @@ assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -9798,26 +10018,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -9829,129 +10049,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -9967,201 +10187,201 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); - end + csrbank1_rst0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; - end + csrbank1_rst0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_re <= interface1_bank_bus_we; + end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; - end + csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); - end + csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); - end + csrbank1_wlevel_en0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; - end + csrbank1_wlevel_en0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; - end + a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; - end + csrbank1_rdphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_rdphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; - end + csrbank1_wrphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_wrphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_rst0_w = a7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10172,328 +10392,328 @@ assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -10563,1194 +10783,1194 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 15'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 15'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 22'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 22'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 22'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 22'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 15'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 15'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 22'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 22'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 22'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 22'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 15'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 15'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 15'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 15'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); @@ -11763,2132 +11983,2132 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); - end else begin - ic_reset <= 1'd0; - end - if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; - end + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); + end else begin + ic_reset <= 1'd0; + end + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; + end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; - end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; - end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; - end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; - end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; - end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; - end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; - end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; - end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; - end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; - end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; - end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; - end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; - end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; - end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; - end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; - end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; - end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; - end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; - end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; - end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; - end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; - end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; - end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; - end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; - end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; - end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; - end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; - end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; - end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; - end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; - end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; - end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; - end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; - end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; - end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; - end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; - end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 10'd781; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd55)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; - end - endcase - end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; - end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; - end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; - end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; - end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; - end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; - end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; - end - 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; - end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; - end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; - end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; - end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; - end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; - end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; - end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; - end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; - if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 15'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 15'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 15'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 15'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 15'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine0_row <= 15'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine1_row <= 15'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine2_row <= 15'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine3_row <= 15'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine4_row <= 15'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine5_row <= 15'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine6_row <= 15'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine7_row <= 15'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if (litedramcore_csr_dfi_p2_rddata_valid) begin + litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + end + if (litedramcore_csr_dfi_p3_rddata_valid) begin + litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd55)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_rst0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + end + endcase + end + if (csrbank1_rst0_re) begin + a7ddrphy_rst_storage <= csrbank1_rst0_r; + end + a7ddrphy_rst_re <= csrbank1_rst0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + end + a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; + if (csrbank1_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + end + a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; + litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + if (sys_rst) begin + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 32'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 32'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_rddata_status <= 32'd0; + litedramcore_phaseinjector2_rddata_re <= 1'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_rddata_status <= 32'd0; + litedramcore_phaseinjector3_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 15'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 15'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 15'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -15833,14 +16053,14 @@ IOBUF IOBUF_15( reg [24:0] storage[0:15]; reg [24:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -15851,14 +16071,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [24:0] storage_1[0:15]; reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -15869,14 +16089,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [24:0] storage_2[0:15]; reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -15887,14 +16107,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [24:0] storage_3[0:15]; reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -15905,14 +16125,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [24:0] storage_4[0:15]; reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -15923,14 +16143,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [24:0] storage_5[0:15]; reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -15941,14 +16161,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [24:0] storage_6[0:15]; reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -15959,14 +16179,14 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [24:0] storage_7[0:15]; reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( @@ -16060,7 +16280,8 @@ PLLE2_ADV #( .LOCKED(locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), @@ -16070,7 +16291,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), @@ -16080,7 +16302,8 @@ PLLE2_ADV #( .Q(iodelay_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), @@ -16090,7 +16313,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), @@ -16100,7 +16324,8 @@ PLLE2_ADV #( .Q(sys_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), @@ -16110,7 +16335,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), @@ -16120,7 +16346,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), @@ -16130,7 +16357,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), @@ -16143,5 +16371,5 @@ PLLE2_ADV #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:06:57. +// Auto-Generated by LiteX on 2022-10-28 19:01:20. //------------------------------------------------------------------------------ diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.init b/litedram/generated/orangecrab-85-0.2/litedram_core.init index cb505da..2a3035b 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.init +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842acc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -600000004800204d -386100207c7f1b78 -6000000048001a65 +6000000048002051 +7fc3f3787c7f1b78 +6000000048001a71 7fe3fb78382100b0 -0000000048002754 -0000018001000000 +0000000048002774 +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842ac283c4c0001 +3842ac203c4c0001 7d6000267c0802a6 -916100084800268d -48001a61f821fed1 +91610008480026b1 +48001a6df821fed1 3c62ffff60000000 -4bffff4138637b08 +4bffff3938637b30 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b28 -3c62ffff4bffff1d -38637b487bff0020 -7c0004ac4bffff0d +63ff000838637b50 +3c62ffff4bffff15 +38637b707bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b60 +4bfffee938637b88 4d80000073e90002 3c62ffff41820010 -4bfffed938637b68 +4bfffed138637b90 4e00000073e90004 3c62ffff41820010 -4bfffec138637b70 +4bfffeb938637b98 4d00000073e90008 3c62ffff41820010 -4bfffea938637b78 +4bfffea138637ba0 4182001073e90010 -38637b883c62ffff -73ff01004bfffe95 +38637bb03c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637b98 -3b7b7ba03f62ffff -4bfffe717f63db78 +4bfffe7938637bc0 +3b7b7bc83f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637ba8 +4bfffe4138637bd0 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637bc0 +4bfffe1938637be8 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637bd87884b282 -3d20c0004bfffdfd +38637c007884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637bf07c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c18 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637c10 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c3857d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c305784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c5857a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c50 -7f40efaa7c0004ac +4bfffc8138637c78 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c683c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637c903c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637c787bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637c983c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c60 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637da8 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -600000004800177d -38637dc83c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847cb03c62ffff -4bfffb0938637cc0 -6000000048000ba9 -3c82ffff4bffff54 -38847cb03c62ffff -4bfffae938637cc0 -6000000048000b89 -3c62ffff4bffff80 -4bfffad138637ce0 -38a000403c9ef000 -3861007078840020 -6000000048001705 -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637ca03be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637cd038847cc0 +48000c394bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637cf0 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637c883c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637d08 +38a000403c9af000 +7884002038610070 +6000000048001731 +e92100703d400002 614a464c3c62ffff -794a83e438637cf8 +794a83e438637d20 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d183c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d403c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637d7888810070 +38637da088810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d303ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637dd0 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048001689 +38637df03c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d583b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d58 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637d80 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480021687d638120 -38a000383c9ef000 -386100b078840020 -600000004800161d +4800216c7d638120 +38a000383c9ff000 +788400207f23cb78 +6000000048001609 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -60000000480015d5 -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +60000000480015c1 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -770,30 +775,30 @@ ebe100b8eb8100c0 7c0004ac39400000 4e8000207d404f2a 0000000000000000 -2c03000000000000 -3929000178690020 -3920000140800008 +7869002000000000 +394000012c030000 +7d2a481e39290001 3929ffff2c290001 600000004d820020 000000004bfffff0 0000000000000000 -3842a4a83c4c0001 -392000087c0802a6 -3d0080207d2903a6 -7908002061080003 -f821ffa148001f0d -3b81001f7c7f1b78 -7889f8627f8ae378 +3842a4803c4c0001 +48001f257c0802a6 +39200008f821ffa1 +7d2903a63d008020 +610800033b81001f +7f8ae3787c7f1b78 +7889f86279080020 7c8400d0788407e0 7c894a787c844038 9d2a00017d244b78 392000084200ffe4 -7d2903a63d008020 -610800033ba10027 -3bc000087faaeb78 +3ba100273d008020 +7d2903a63bc00008 +7faaeb7861080003 7889f86279080020 -7c8400d0788407e0 -7c8440383bdeffff +3bdeffff788407e0 +7c8440387c8400d0 7d244b787c894a78 4200ffe09d2a0001 392000003d40c800 @@ -811,7 +816,7 @@ f821ffa148001f0d 794a0020614a1014 7fc0572a7c0004ac 3901002338e00004 -394000047ce903a6 +7ce903a639400004 394affff8ce80001 7ce93b787927400c 3d00c8004200fff0 @@ -857,17 +862,17 @@ f821ffa148001f0d 4bfffc193bc10030 4bfffd593860000f 3c80c8003d20c800 -3c0055556129101c -3d800f0f3ca03333 -38e100206084103c +3ca033333c005555 +38e100203d800f0f 3860000038c00000 -217f000179290020 -60a5333360005555 -78840020618c0f0f +6084103c6129101c +60005555217f0001 +618c0f0f60a53333 +7884002079290020 7d004e2a7c0004ac 790800203b800004 -3ba100347f8903a6 -9d1dffff39400004 +394000043ba10034 +9d1dffff7f8903a6 7908c202394affff 392900044200fff4 7d204e2a7c0004ac @@ -893,609 +898,606 @@ f821ffa148001f0d 712900017d29fc30 3863000140820008 7863002038210060 -38c0000148001bdc +38c0000148001be0 000000004bffff10 0000048001000000 -3842a0f03c4c0001 -48001b617c0802a6 -7c7f1b78f821ff71 -4bfffaed3bc00000 +3842a0c83c4c0001 +48001b657c0802a6 +3ba00000f821ff71 +4bfffaed7c7f1b78 7fe3fb783880002a -388000544bfffc29 -7c7d1b783b9e0001 +4bfffc253b9d0001 +7c7e1b7838800054 4bfffc157fe3fb78 -2c0300007c63ea14 +2c0300007c63f214 2c1c00084182001c 7fe3fb7841820074 -4bfffb0d7f9ee378 -7fdcf3784bffffc0 -3b7e00017fe3fb78 -3ba0ffff4bfffaf9 +4bfffb0d7f9de378 +7fbceb784bffffc0 +3b7d00017fe3fb78 +4bfffaf53bc0ffff 7fe3fb783880002a 388000544bfffbd1 7fe3fb787c7a1b78 7c63d2144bfffbc1 418200102c030000 -408200082c1dffff -3b7b00017f7ddb78 +408200082c1effff +3b7b00017f7edb78 4181001c2c1b0007 4bfffaad7fe3fb78 -3bc000084bffffb8 +3ba000084bffffb8 4bffff9c3b80ffff -4082001c2c1dffff -3ba000002c1e0006 -23be000641810008 -7fbdf2143bde0002 -4082001c2c1cffff -38637de03c62ffff -600000004bfff335 -48001ab038210090 -7c9cea147cbce850 -7ca501947ca50e70 -3c62ffff789bff62 -7f64db787ca507b4 -3bc0000838637df0 -600000004bfff2fd -3ba000007fe3fb78 -386000644bfff9c1 -7c1be8004bfffac5 -3880002a4082003c -4bfffaed7fe3fb78 -7c7d1b7838800054 -4bfffadd7fe3fb78 -2c0300007c63ea14 -3bdeffff4182ff88 -4082ffb42c1e0000 -7fe3fb784bffff78 -4bfff9cd3bbd0001 -4bfffa7138600064 -000000004bffffac -0000068001000000 -38429f383c4c0001 -612910003d20c800 -7c0004ac79290020 -280a000e7d404e2a -7c0802a64d820020 -f80100103940000e -7c0004acf821ffa1 -3c62ffff7d404f2a -4bfff23938637e08 -3821006060000000 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -38429ed03c4c0001 -612910003d20c800 -7c0004ac79290020 -280a00017d404e2a -7c0802a64d820020 -f801001039400001 -7c0004acf821ffa1 -3c62ffff7d404f2a -4bfff1d138637e30 -3821006060000000 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -38429e683c4c0001 -3d22ffff7c0802a6 -480018a139297e58 -3f80c800f821ff01 -3e82ffff3f00c800 -3f22ffff3e62ffff -63180810639c0800 -3ba000003e42ffff -f92100603b400001 -3a947e683ae00000 -3b397ba03a737e70 +408200182c1effff +2c1d000623dd0006 +7fc0f05e3bbd0002 +2c1cffff7fdeea14 +3c62ffff4082001c +4bfff31138637e08 +3821009060000000 +7cbcf05048001ab8 +3c62ffff7c9cf214 +7ca50e703bc00008 +789bff627ca50194 +7f64db7838637e18 +4bfff2d97ca507b4 +7fe3fb7860000000 +4bfff9c53ba00000 +4bfffac938600064 +4082003c7c1be800 +7fe3fb783880002a +388000544bfffaf1 +7fe3fb787c7d1b78 +7c63ea144bfffae1 +4182ff882c030000 +2c1e00003bdeffff +4bffff784082ffb4 +3bbd00017fe3fb78 +386000644bfff9d1 +4bffffac4bfffa75 +0100000000000000 +3c4c000100000680 +3d20c80038429f14 +7929002061291000 +7d404e2a7c0004ac +4d820020280a000e +f80100107c0802a6 +3940000ef821ffa1 +7d404f2a7c0004ac +38637e303c62ffff +600000004bfff215 +e801001038210060 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +3d20c80038429eac +7929002061291000 +7d404e2a7c0004ac +4d820020280a0001 +f80100107c0802a6 +39400001f821ffa1 +7d404f2a7c0004ac +38637e583c62ffff +600000004bfff1ad +e801001038210060 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +7c0802a638429e44 +f821ff01480018b1 +3f00c8003f80c800 +3b4000013ba00000 +3d22ffff3ae00000 +3e62ffff3e82ffff +639c08003f22ffff +3e42ffff63180810 +3a947e9039297e80 +3b397bc83a737e98 7b1800207b9c0020 -7ba307e03a527e78 -4bfff8d57fb0eb78 +f92100603a527ea0 +7fb0eb787ba307e0 3be000007f56e830 39e000003a200000 -e86100607fbe07b4 -7fc4f3787de507b4 -3b60000039c00008 -600000004bfff115 -4bfff7dd7fc3f378 -7fc3f3783880002a -388000544bfff919 -7fc3f3787c751b78 -7c63aa144bfff909 -212300807c640034 -5484d97e7e83a378 -7c8407b4548a502a -7f7b4a147d295214 -600000004bfff0c5 -4bfff7ed7fc3f378 -4082ffac35ceffff -4bfff0a97e639b78 +4bfff8c57fbe07b4 +7de507b4e8610060 +39c000087fc4f378 +4bfff0f13b600000 7fc3f37860000000 -7f23cb784bfffc71 -600000004bfff095 -4080000c7c11d840 -7f71db787dff7b78 -4182002c2c0f0003 -7ec0e72a7c0004ac -7f40c72a7c0004ac -7ee0e72a7c0004ac -4bffff3039ef0001 -4bffff083ba00001 -7fc4f3787fe507b4 -7bff00207e439378 -600000004bfff03d -4bfff7c57a0307e0 -7d2903a6393f0001 -7fc3f37842000028 -7f23cb784bfffbf1 -600000004bfff015 -4182ffb42c1d0000 -4800175838210100 -7ec0e72a7c0004ac -7f40c72a7c0004ac -7ee0e72a7c0004ac -000000004bffffc0 -0000128001000000 -38429c903c4c0001 -f80100107c0802a6 -4bfffd4df821ffa1 -4bfff68d38600000 -4bfff74538600000 -4bfff67d38600001 -4bfff73538600001 -38637e903c62ffff -600000004bffef95 -4bfffd7d4bfffde9 -3860000138210060 -7c0803a6e8010010 -000000004e800020 -0000008001000000 -38429c203c4c0001 -3c62ffff7c0802a6 -38637ea03c804000 -f821ff7148001685 -3be000003f60c800 -4bffef397b7b0020 -4bfffcbd60000000 -7fe0df2a7c0004ac -635a00043f40c800 -7c0004ac7b5a0020 -3fa0c8007fe0d72a -7bbd002063bd100c -7fe0ef2a7c0004ac -63de10103fc0c800 -7c0004ac7bde0020 -3f80c8007fe0f72a -639c10003920000c -7c0004ac7b9c0020 -386000007d20e72a -4bfff6a96063c350 -7fe0ef2a7c0004ac +3880002a4bfff7e1 +4bfff91d7fc3f378 +7c751b7838800054 +4bfff90d7fc3f378 +7c6400347c63aa14 +7e83a37821230080 +548a502a5484d97e +7d2952147c8407b4 +4bfff0a17f7b4a14 +7fc3f37860000000 +35ceffff4bfff7f1 +7e639b784082ffac +600000004bfff085 +4bfffc757fc3f378 +4bfff0717f23cb78 +7c11d84060000000 +7dff7b784080000c +2c0f00037f71db78 +7c0004ac4182002c +7c0004ac7ec0e72a +7c0004ac7f40c72a +39ef00017ee0e72a +3ba000014bffff30 +7fe507b44bffff08 +7e4393787fc4f378 +4bfff0197bff0020 +7a0307e060000000 +393f00014bfff7c9 +420000287d2903a6 +4bfffbf57fc3f378 +4bffeff17f23cb78 +2c1d000060000000 +382101004182ffb4 +7c0004ac48001760 +7c0004ac7ec0e72a +7c0004ac7f40c72a +4bffffc07ee0e72a +0100000000000000 +3c4c000100001280 +7c0802a638429c6c +f821ffa1f8010010 +386000004bfffd4d +386000004bfff691 +386000014bfff749 +386000014bfff681 +3c62ffff4bfff739 +4bffef7138637eb8 +4bfffde960000000 +382100604bfffd7d +e801001038600001 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +7c0802a638429bfc +f821ff7148001699 +3f60c8003c804000 +3c62ffff3be00000 +38637ec87b7b0020 +600000004bffef15 +7c0004ac4bfffcbd +3f40c8007fe0df2a +7b5a0020635a0004 +7fe0d72a7c0004ac +63bd100c3fa0c800 +7c0004ac7bbd0020 +3fc0c8007fe0ef2a +7bde002063de1010 7fe0f72a7c0004ac -7c0004ac3920000e -386027107d20e72a -392002004bfff685 -7d20ef2a7c0004ac -7c0004ac39200002 -3860000f7d20f72a -7c0004ac4bfff51d -392000037fe0ef2a +3920000c3f80c800 +7b9c0020639c1000 +7d20e72a7c0004ac +6063c35038600000 +7c0004ac4bfff6ad +7c0004ac7fe0ef2a +3920000e7fe0f72a +7d20e72a7c0004ac +4bfff68938602710 +7c0004ac39200200 +392000027d20ef2a 7d20f72a7c0004ac -4bfff5013860000f -7c0004ac39200006 -3b8000017d20ef2a -7f80f72a7c0004ac -4bfff4e13860000f -7c0004ac39200320 -7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff4c5 -392004004bfff605 +4bfff5213860000f +7fe0ef2a7c0004ac +7c0004ac39200003 +3860000f7d20f72a +392000064bfff505 +7d20ef2a7c0004ac +7c0004ac3b800001 +3860000f7f80f72a +392003204bfff4e5 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff4a138600003 -4bfff5e1386000c8 -4bfffbed4bfffe31 -3c6040003c800020 -60000000480006e9 -408200242c030000 -7c0004ac7c691b78 -7c0004ac7f80d72a -382100907f80df2a -480015487d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bfff4c93860000f +4bfff609386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff4a5 +4bfffe314bfff5e5 +3c8000204bfffbed +480006e13c604000 +2c03000060000000 +7c691b7840820024 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000680 -7c0802a638429a44 -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffed6138637ec0 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637ec83c62ffff -600000004bffed25 -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ed87ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b438210090 +38c0000048001550 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000068001000000 +38429a203c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ee83c62ffff +600000004bffed3d +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ee8 -0100000000000000 -3c4c000100000080 -7c0802a638429974 -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffed0138637ef0 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637f00 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ef878c60020 +38637f107ca54b92 +000000004bffffa4 +0000008001000000 +384299503c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffec85 -4bfffef97fe3fb78 -38637f083c62ffff -600000004bffec6d -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -384298d03c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffec6138637f20 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffec4938637f30 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384298ac +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffec41 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffebf1 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffec2542000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffebd57fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384297c03c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187f107bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637f10 -3c62ffff4bfffde5 -4bffea8938637ba0 -4bffeaed60000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a63842979c +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f38 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f38 +38637bc83c62ffff +600000004bffea65 +600000004bffead1 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f20 -3c62ffff4bfffd8d -4bffea3138637ba0 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f20 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384296003c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f48 +38637bc83c62ffff +600000004bffea0d +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f487ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a6384295dc +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f303c62ffff -4bffe9017cbc2b78 -3c62ffff60000000 -4092000c38637f48 -38637f583c62ffff -600000004bffe8e5 -4bfffb597fc3f378 -38637f683c62ffff -600000004bffe8cd -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8002dc -79290020639c6c00 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f582e3b0000 +600000004bffe8dd 38637f703c62ffff -4bffe8497f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffe83138637f80 +3c62ffff4092000c +4bffe8c138637f80 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffe8a938637f90 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8002dc7d3602a6 +7929002078ea0020 +639c6c003c62ffff +38637f987d295050 +7f9c4b927f9ee1d2 +600000004bffe825 +4bfffabd7f83e378 +38637fa83c62ffff +600000004bffe80d +38637bc83c62ffff +600000004bffe7fd +600000004bffe869 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4002dc +3c62ffff79290020 +7d29e050614a6c00 +7fde51d238637fb0 +4bffe7617fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffe74938637fa8 3c62ffff60000000 -4bffe82138637ba0 -4bffe88560000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4002dc7d3602a6 -614a6c007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f88 -600000004bffe785 -4bfff9f97fc3f378 -38637f803c62ffff -600000004bffe76d -38637ba03c62ffff -600000004bffe75d -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384293c83c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffe73938637bc8 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384293ac +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f987fc4f378 -600000004bffe6d5 -4bfff9497fe3fb78 -38637f683c62ffff +7c641b787f9c205e +38637fc03c62ffff 600000004bffe6bd +4bfff9557fe3fb78 +38637f903c62ffff +600000004bffe6a5 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffe67138637fa8 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fc038800000 -600000004bffe645 -7be5f0823c62ffff -38637fd87fc4f378 -600000004bffe62d -38637ff03c62ffff -600000004bffe61d -3821008038600000 -48000d987c6307b4 -3862800060000000 -600000004bffe5fd -4bffffe038600001 -0100000000000000 -3c4c000100000480 -600000003842929c -6000000089228080 -2c09000039428078 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228078 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428078 -4e8000207d2057ea +4bffe65938637fd0 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fe8 +4bffe63178a5f082 +6000000060000000 +7fc4f3787be5f082 +4bffe61938628000 +6000000060000000 +4bffe60938628018 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffe5e938628028 +3860000160000000 +000000004bffffe0 +0000048001000000 +384292883c4c0001 +6000000060000000 +394280a0892280a8 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e92280a060000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94280a05469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a638429214 -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384291b4 -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428078 -9942808060000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942807860000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228080 -3920ff806108200c -7c0004ac79080020 -e92280787d2047aa -7d404faa7c0004ac -794ac202e9228078 -7c0004ac39290004 -e92280787d404faa -3929000c39400003 +384292003c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384291a03c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f94280a060000000 +6000000039400000 +3d40001c994280a8 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf94280a0 +7d495392614a2000 +600000004182ffa0 +992280a839200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace92280a0 +e92280a07d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228078 +39400003e92280a0 +7c0004ac3929000c +e92280a07d404faa +7c0004ac39290010 +e92280a07d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228078 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 +000000004e800020 0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428e7c -f821ffa1480008e9 +7c0802a638428e6c +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1507,36 +1509,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428dac -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428d9c +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428d303c4c0001 -600000007c0802a6 -2b860010e9228010 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428d203c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922801860000000 +2b8600107caa2b78 +f9210020e9228038 +e922804060000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -1544,253 +1546,256 @@ e922801860000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428c3c -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b74a0 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428c303c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b74ac +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028030 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c6765c3cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028058 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a766c +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942803060000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280307aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028058 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028058 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2802838610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280507de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1841,15 +1846,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/orangecrab-85-0.2/litedram_core.v b/litedram/generated/orangecrab-85-0.2/litedram_core.v index cdebb1b..3bd3682 100644 --- a/litedram/generated/orangecrab-85-0.2/litedram_core.v +++ b/litedram/generated/orangecrab-85-0.2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : LFE5U-85F-8MG285C -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:07:03 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:26 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [14:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [1:0] ddram_dm, - input wire [15:0] ddram_dq, - input wire [1:0] ddram_dqs_p, - input wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - input wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [24:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [14:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + input wire [15:0] ddram_dq, + input wire [1:0] ddram_dqs_p, + input wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + input wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [24:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -69,1709 +69,1805 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg crg_rst = 1'd0; -wire init_clk; -wire init_rst; -wire por_clk; -wire sys_clk; -wire sys_rst; -wire sys2x_clk; -wire sys2x_rst; -wire sys2x_i_clk; -wire crg_stop; -wire crg_reset0; -reg [15:0] crg_por_count = 16'd65535; -wire crg_por_done; -wire crg_sys2x_clk_ecsout; -wire crg_reset1; -wire crg_locked; -reg crg_stdby = 1'd0; -wire crg_clkin; -wire crg_clkout0; -wire crg_clkout1; -wire ddrphy_pause0; -wire ddrphy_stop0; -wire ddrphy_delay0; -wire ddrphy_reset0; -wire ddrphy_new_lock; -reg ddrphy_update = 1'd0; -reg ddrphy_stop1 = 1'd0; -reg ddrphy_freeze = 1'd0; -reg ddrphy_pause1 = 1'd0; -reg ddrphy_reset1 = 1'd0; -wire ddrphy_lock0; -wire ddrphy_delay1; -wire ddrphy_lock1; -reg ddrphy_lock_d = 1'd0; -reg [6:0] ddrphy_counter = 7'd0; -reg [1:0] ddrphy_dly_sel_storage = 2'd0; -reg ddrphy_dly_sel_re = 1'd0; -reg ddrphy_rdly_dq_rst_re = 1'd0; -wire ddrphy_rdly_dq_rst_r; -reg ddrphy_rdly_dq_rst_we = 1'd0; -reg ddrphy_rdly_dq_rst_w = 1'd0; -reg ddrphy_rdly_dq_inc_re = 1'd0; -wire ddrphy_rdly_dq_inc_r; -reg ddrphy_rdly_dq_inc_we = 1'd0; -reg ddrphy_rdly_dq_inc_w = 1'd0; -reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire ddrphy_rdly_dq_bitslip_rst_r; -reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg ddrphy_rdly_dq_bitslip_re = 1'd0; -wire ddrphy_rdly_dq_bitslip_r; -reg ddrphy_rdly_dq_bitslip_we = 1'd0; -reg ddrphy_rdly_dq_bitslip_w = 1'd0; -reg ddrphy_burstdet_clr_re = 1'd0; -wire ddrphy_burstdet_clr_r; -reg ddrphy_burstdet_clr_we = 1'd0; -reg ddrphy_burstdet_clr_w = 1'd0; -reg [1:0] ddrphy_burstdet_seen_status = 2'd0; -wire ddrphy_burstdet_seen_we; -reg ddrphy_burstdet_seen_re = 1'd0; -wire [1:0] ddrphy_datavalid; -wire [14:0] ddrphy_dfi_p0_address; -wire [2:0] ddrphy_dfi_p0_bank; -wire ddrphy_dfi_p0_cas_n; -wire ddrphy_dfi_p0_cs_n; -wire ddrphy_dfi_p0_ras_n; -wire ddrphy_dfi_p0_we_n; -wire ddrphy_dfi_p0_cke; -wire ddrphy_dfi_p0_odt; -wire ddrphy_dfi_p0_reset_n; -wire ddrphy_dfi_p0_act_n; -wire [63:0] ddrphy_dfi_p0_wrdata; -wire ddrphy_dfi_p0_wrdata_en; -wire [7:0] ddrphy_dfi_p0_wrdata_mask; -wire ddrphy_dfi_p0_rddata_en; -reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; -wire ddrphy_dfi_p0_rddata_valid; -wire [14:0] ddrphy_dfi_p1_address; -wire [2:0] ddrphy_dfi_p1_bank; -wire ddrphy_dfi_p1_cas_n; -wire ddrphy_dfi_p1_cs_n; -wire ddrphy_dfi_p1_ras_n; -wire ddrphy_dfi_p1_we_n; -wire ddrphy_dfi_p1_cke; -wire ddrphy_dfi_p1_odt; -wire ddrphy_dfi_p1_reset_n; -wire ddrphy_dfi_p1_act_n; -wire [63:0] ddrphy_dfi_p1_wrdata; -wire ddrphy_dfi_p1_wrdata_en; -wire [7:0] ddrphy_dfi_p1_wrdata_mask; -wire ddrphy_dfi_p1_rddata_en; -reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; -wire ddrphy_dfi_p1_rddata_valid; -wire ddrphy_bl8_chunk; -wire ddrphy_pad_oddrx2f0; -wire ddrphy_pad_oddrx2f1; -wire ddrphy_pad_oddrx2f2; -wire ddrphy_pad_oddrx2f3; -wire ddrphy_pad_oddrx2f4; -wire ddrphy_pad_oddrx2f5; -wire ddrphy_pad_oddrx2f6; -wire ddrphy_pad_oddrx2f7; -wire ddrphy_pad_oddrx2f8; -wire ddrphy_pad_oddrx2f9; -wire ddrphy_pad_oddrx2f10; -wire ddrphy_pad_oddrx2f11; -wire ddrphy_pad_oddrx2f12; -wire ddrphy_pad_oddrx2f13; -wire ddrphy_pad_oddrx2f14; -wire ddrphy_pad_oddrx2f15; -wire ddrphy_pad_oddrx2f16; -wire ddrphy_pad_oddrx2f17; -wire ddrphy_pad_oddrx2f18; -wire ddrphy_pad_oddrx2f19; -wire ddrphy_pad_oddrx2f20; -wire ddrphy_pad_oddrx2f21; -wire ddrphy_pad_oddrx2f22; -wire ddrphy_pad_oddrx2f23; -wire ddrphy_pad_oddrx2f24; -wire ddrphy_pad_oddrx2f25; -wire ddrphy_dq_oe; -wire ddrphy_dqs_re; -wire ddrphy_dqs_oe; -wire ddrphy_dqs_postamble; -wire ddrphy_dqs_preamble; -wire ddrphy_dqs_i0; -wire ddrphy_dqsr900; -wire ddrphy_dqsw2700; -wire ddrphy_dqsw0; -wire [2:0] ddrphy_rdpntr0; -wire [2:0] ddrphy_wrpntr0; -reg [2:0] ddrphy_rdly0 = 3'd0; -wire ddrphy_burstdet0; -reg ddrphy_burstdet_d0 = 1'd0; -wire ddrphy_dqs0; -wire ddrphy_dqs_oe_n0; -reg [7:0] ddrphy_dm_o_data0 = 8'd0; -reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; -reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; -wire ddrphy_dq_o0; -wire ddrphy_dq_i0; -wire ddrphy_dq_oe_n0; -wire ddrphy_dq_i_delayed0; -wire [7:0] ddrphy_dq_i_data0; -reg [7:0] ddrphy_dq_o_data0 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; -wire [3:0] ddrphy_bitslip0_i; -reg [3:0] ddrphy_bitslip0_o = 4'd0; -reg [1:0] ddrphy_bitslip0_value = 2'd0; -reg [7:0] ddrphy_bitslip0_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; -wire ddrphy_dq_o1; -wire ddrphy_dq_i1; -wire ddrphy_dq_oe_n1; -wire ddrphy_dq_i_delayed1; -wire [7:0] ddrphy_dq_i_data1; -reg [7:0] ddrphy_dq_o_data1 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; -wire [3:0] ddrphy_bitslip1_i; -reg [3:0] ddrphy_bitslip1_o = 4'd0; -reg [1:0] ddrphy_bitslip1_value = 2'd0; -reg [7:0] ddrphy_bitslip1_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; -wire ddrphy_dq_o2; -wire ddrphy_dq_i2; -wire ddrphy_dq_oe_n2; -wire ddrphy_dq_i_delayed2; -wire [7:0] ddrphy_dq_i_data2; -reg [7:0] ddrphy_dq_o_data2 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; -wire [3:0] ddrphy_bitslip2_i; -reg [3:0] ddrphy_bitslip2_o = 4'd0; -reg [1:0] ddrphy_bitslip2_value = 2'd0; -reg [7:0] ddrphy_bitslip2_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; -wire ddrphy_dq_o3; -wire ddrphy_dq_i3; -wire ddrphy_dq_oe_n3; -wire ddrphy_dq_i_delayed3; -wire [7:0] ddrphy_dq_i_data3; -reg [7:0] ddrphy_dq_o_data3 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; -wire [3:0] ddrphy_bitslip3_i; -reg [3:0] ddrphy_bitslip3_o = 4'd0; -reg [1:0] ddrphy_bitslip3_value = 2'd0; -reg [7:0] ddrphy_bitslip3_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; -wire ddrphy_dq_o4; -wire ddrphy_dq_i4; -wire ddrphy_dq_oe_n4; -wire ddrphy_dq_i_delayed4; -wire [7:0] ddrphy_dq_i_data4; -reg [7:0] ddrphy_dq_o_data4 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; -wire [3:0] ddrphy_bitslip4_i; -reg [3:0] ddrphy_bitslip4_o = 4'd0; -reg [1:0] ddrphy_bitslip4_value = 2'd0; -reg [7:0] ddrphy_bitslip4_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; -wire ddrphy_dq_o5; -wire ddrphy_dq_i5; -wire ddrphy_dq_oe_n5; -wire ddrphy_dq_i_delayed5; -wire [7:0] ddrphy_dq_i_data5; -reg [7:0] ddrphy_dq_o_data5 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; -wire [3:0] ddrphy_bitslip5_i; -reg [3:0] ddrphy_bitslip5_o = 4'd0; -reg [1:0] ddrphy_bitslip5_value = 2'd0; -reg [7:0] ddrphy_bitslip5_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; -wire ddrphy_dq_o6; -wire ddrphy_dq_i6; -wire ddrphy_dq_oe_n6; -wire ddrphy_dq_i_delayed6; -wire [7:0] ddrphy_dq_i_data6; -reg [7:0] ddrphy_dq_o_data6 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; -wire [3:0] ddrphy_bitslip6_i; -reg [3:0] ddrphy_bitslip6_o = 4'd0; -reg [1:0] ddrphy_bitslip6_value = 2'd0; -reg [7:0] ddrphy_bitslip6_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; -wire ddrphy_dq_o7; -wire ddrphy_dq_i7; -wire ddrphy_dq_oe_n7; -wire ddrphy_dq_i_delayed7; -wire [7:0] ddrphy_dq_i_data7; -reg [7:0] ddrphy_dq_o_data7 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; -wire [3:0] ddrphy_bitslip7_i; -reg [3:0] ddrphy_bitslip7_o = 4'd0; -reg [1:0] ddrphy_bitslip7_value = 2'd0; -reg [7:0] ddrphy_bitslip7_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; -wire ddrphy_dqs_i1; -wire ddrphy_dqsr901; -wire ddrphy_dqsw2701; -wire ddrphy_dqsw1; -wire [2:0] ddrphy_rdpntr1; -wire [2:0] ddrphy_wrpntr1; -reg [2:0] ddrphy_rdly1 = 3'd0; -wire ddrphy_burstdet1; -reg ddrphy_burstdet_d1 = 1'd0; -wire ddrphy_dqs1; -wire ddrphy_dqs_oe_n1; -reg [7:0] ddrphy_dm_o_data1 = 8'd0; -reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; -reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; -wire ddrphy_dq_o8; -wire ddrphy_dq_i8; -wire ddrphy_dq_oe_n8; -wire ddrphy_dq_i_delayed8; -wire [7:0] ddrphy_dq_i_data8; -reg [7:0] ddrphy_dq_o_data8 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; -wire [3:0] ddrphy_bitslip8_i; -reg [3:0] ddrphy_bitslip8_o = 4'd0; -reg [1:0] ddrphy_bitslip8_value = 2'd0; -reg [7:0] ddrphy_bitslip8_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; -wire ddrphy_dq_o9; -wire ddrphy_dq_i9; -wire ddrphy_dq_oe_n9; -wire ddrphy_dq_i_delayed9; -wire [7:0] ddrphy_dq_i_data9; -reg [7:0] ddrphy_dq_o_data9 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; -wire [3:0] ddrphy_bitslip9_i; -reg [3:0] ddrphy_bitslip9_o = 4'd0; -reg [1:0] ddrphy_bitslip9_value = 2'd0; -reg [7:0] ddrphy_bitslip9_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; -wire ddrphy_dq_o10; -wire ddrphy_dq_i10; -wire ddrphy_dq_oe_n10; -wire ddrphy_dq_i_delayed10; -wire [7:0] ddrphy_dq_i_data10; -reg [7:0] ddrphy_dq_o_data10 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; -wire [3:0] ddrphy_bitslip10_i; -reg [3:0] ddrphy_bitslip10_o = 4'd0; -reg [1:0] ddrphy_bitslip10_value = 2'd0; -reg [7:0] ddrphy_bitslip10_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; -wire ddrphy_dq_o11; -wire ddrphy_dq_i11; -wire ddrphy_dq_oe_n11; -wire ddrphy_dq_i_delayed11; -wire [7:0] ddrphy_dq_i_data11; -reg [7:0] ddrphy_dq_o_data11 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; -wire [3:0] ddrphy_bitslip11_i; -reg [3:0] ddrphy_bitslip11_o = 4'd0; -reg [1:0] ddrphy_bitslip11_value = 2'd0; -reg [7:0] ddrphy_bitslip11_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; -wire ddrphy_dq_o12; -wire ddrphy_dq_i12; -wire ddrphy_dq_oe_n12; -wire ddrphy_dq_i_delayed12; -wire [7:0] ddrphy_dq_i_data12; -reg [7:0] ddrphy_dq_o_data12 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; -wire [3:0] ddrphy_bitslip12_i; -reg [3:0] ddrphy_bitslip12_o = 4'd0; -reg [1:0] ddrphy_bitslip12_value = 2'd0; -reg [7:0] ddrphy_bitslip12_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; -wire ddrphy_dq_o13; -wire ddrphy_dq_i13; -wire ddrphy_dq_oe_n13; -wire ddrphy_dq_i_delayed13; -wire [7:0] ddrphy_dq_i_data13; -reg [7:0] ddrphy_dq_o_data13 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; -wire [3:0] ddrphy_bitslip13_i; -reg [3:0] ddrphy_bitslip13_o = 4'd0; -reg [1:0] ddrphy_bitslip13_value = 2'd0; -reg [7:0] ddrphy_bitslip13_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; -wire ddrphy_dq_o14; -wire ddrphy_dq_i14; -wire ddrphy_dq_oe_n14; -wire ddrphy_dq_i_delayed14; -wire [7:0] ddrphy_dq_i_data14; -reg [7:0] ddrphy_dq_o_data14 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; -wire [3:0] ddrphy_bitslip14_i; -reg [3:0] ddrphy_bitslip14_o = 4'd0; -reg [1:0] ddrphy_bitslip14_value = 2'd0; -reg [7:0] ddrphy_bitslip14_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; -wire ddrphy_dq_o15; -wire ddrphy_dq_i15; -wire ddrphy_dq_oe_n15; -wire ddrphy_dq_i_delayed15; -wire [7:0] ddrphy_dq_i_data15; -reg [7:0] ddrphy_dq_o_data15 = 8'd0; -reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; -reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; -wire [3:0] ddrphy_bitslip15_i; -reg [3:0] ddrphy_bitslip15_o = 4'd0; -reg [1:0] ddrphy_bitslip15_value = 2'd0; -reg [7:0] ddrphy_bitslip15_r = 8'd0; -reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; -reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; -reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; -reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; -wire [14:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [63:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [7:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [63:0] litedramcore_slave_p0_rddata = 64'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [63:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [7:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [63:0] litedramcore_slave_p1_rddata = 64'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_master_p0_address = 15'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [63:0] litedramcore_master_p0_wrdata = 64'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [14:0] litedramcore_master_p1_address = 15'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [63:0] litedramcore_master_p1_wrdata = 64'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -wire [14:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [14:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [21:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [21:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [21:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [21:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [21:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [21:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [21:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [21:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [14:0] litedramcore_dfi_p0_address = 15'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [14:0] litedramcore_dfi_p1_address = 15'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [63:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [7:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [63:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [14:0] litedramcore_cmd_payload_a = 15'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [8:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [8:0] litedramcore_timer_count1 = 9'd374; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [6:0] litedramcore_sequencer_counter = 7'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [25:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [5:0] litedramcore_zqcs_executer_counter = 6'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [21:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine0_row = 15'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; -wire litedramcore_bankmachine0_trascon_valid; -reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [21:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine1_row = 15'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; -wire litedramcore_bankmachine1_trascon_valid; -reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [21:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine2_row = 15'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; -wire litedramcore_bankmachine2_trascon_valid; -reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [21:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine3_row = 15'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; -wire litedramcore_bankmachine3_trascon_valid; -reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [21:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine4_row = 15'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; -wire litedramcore_bankmachine4_trascon_valid; -reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [21:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine5_row = 15'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; -wire litedramcore_bankmachine5_trascon_valid; -reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [21:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine6_row = 15'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; -wire litedramcore_bankmachine6_trascon_valid; -reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [21:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0; -reg [14:0] litedramcore_bankmachine7_row = 15'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; -wire litedramcore_bankmachine7_trascon_valid; -reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [14:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [14:0] litedramcore_nop_a = 15'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -wire litedramcore_trrdcon_valid; -reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -reg litedramcore_tfawcon_ready = 1'd1; -wire [1:0] litedramcore_tfawcon_count; -reg [2:0] litedramcore_tfawcon_window = 3'd0; -wire litedramcore_tccdcon_valid; -reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [24:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_burstdet_seen_re = 1'd0; -wire [1:0] csrbank1_burstdet_seen_r; -reg csrbank1_burstdet_seen_we = 1'd0; -wire [1:0] csrbank1_burstdet_seen_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_r; -reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata1_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_r; -reg csrbank2_dfii_pi0_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata1_w; -reg csrbank2_dfii_pi0_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_r; -reg csrbank2_dfii_pi0_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata0_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [14:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_r; -reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata1_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata1_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_r; -reg csrbank2_dfii_pi1_rddata1_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata1_w; -reg csrbank2_dfii_pi1_rddata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_r; -reg csrbank2_dfii_pi1_rddata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata0_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_litedramecp5ddrphycrg_ecp5pll; -wire litedramcore_litedramecp5ddrphycrg_locked; -reg [1:0] litedramcore_litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0; -reg [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0; -reg [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0; -reg [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_litedramcore_roundrobin0_request; -wire litedramcore_litedramcore_roundrobin0_grant; -wire litedramcore_litedramcore_roundrobin0_ce; -wire litedramcore_litedramcore_roundrobin1_request; -wire litedramcore_litedramcore_roundrobin1_grant; -wire litedramcore_litedramcore_roundrobin1_ce; -wire litedramcore_litedramcore_roundrobin2_request; -wire litedramcore_litedramcore_roundrobin2_grant; -wire litedramcore_litedramcore_roundrobin2_ce; -wire litedramcore_litedramcore_roundrobin3_request; -wire litedramcore_litedramcore_roundrobin3_grant; -wire litedramcore_litedramcore_roundrobin3_ce; -wire litedramcore_litedramcore_roundrobin4_request; -wire litedramcore_litedramcore_roundrobin4_grant; -wire litedramcore_litedramcore_roundrobin4_ce; -wire litedramcore_litedramcore_roundrobin5_request; -wire litedramcore_litedramcore_roundrobin5_grant; -wire litedramcore_litedramcore_roundrobin5_ce; -wire litedramcore_litedramcore_roundrobin6_request; -wire litedramcore_litedramcore_roundrobin6_grant; -wire litedramcore_litedramcore_roundrobin6_ce; -wire litedramcore_litedramcore_roundrobin7_request; -wire litedramcore_litedramcore_roundrobin7_grant; -wire litedramcore_litedramcore_roundrobin7_ce; -reg litedramcore_litedramcore_locked0 = 1'd0; -reg litedramcore_litedramcore_locked1 = 1'd0; -reg litedramcore_litedramcore_locked2 = 1'd0; -reg litedramcore_litedramcore_locked3 = 1'd0; -reg litedramcore_litedramcore_locked4 = 1'd0; -reg litedramcore_litedramcore_locked5 = 1'd0; -reg litedramcore_litedramcore_locked6 = 1'd0; -reg litedramcore_litedramcore_locked7 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0; -reg litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0; -reg litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [14:0] rhs_array_muxed1 = 15'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [14:0] rhs_array_muxed7 = 15'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [21:0] rhs_array_muxed12 = 22'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [21:0] rhs_array_muxed15 = 22'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [21:0] rhs_array_muxed18 = 22'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [21:0] rhs_array_muxed21 = 22'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [21:0] rhs_array_muxed24 = 22'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [21:0] rhs_array_muxed27 = 22'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [21:0] rhs_array_muxed30 = 22'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [21:0] rhs_array_muxed33 = 22'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [14:0] array_muxed1 = 15'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [14:0] array_muxed8 = 15'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -wire latticeecp5asyncresetsynchronizerimpl0_rst1; -wire latticeecp5asyncresetsynchronizerimpl0_expr; -wire latticeecp5asyncresetsynchronizerimpl1_rst1; -wire latticeecp5asyncresetsynchronizerimpl2_rst1; -wire latticeecp5asyncresetsynchronizerimpl3_rst1; -reg regs0 = 1'd0; -reg regs1 = 1'd0; +reg crg_rst = 1'd0; +wire init_clk; +wire init_rst; +wire por_clk; +wire sys_clk; +wire sys_rst; +wire sys2x_clk; +wire sys2x_rst; +wire sys2x_i_clk; +wire crg_stop; +wire crg_reset0; +reg [15:0] crg_por_count = 16'd65535; +wire crg_por_done; +wire crg_sys2x_clk_ecsout; +wire crg_reset1; +wire crg_locked; +reg crg_stdby = 1'd0; +wire crg_clkin; +wire crg_clkout0; +wire crg_clkout1; +wire ddrphy_pause0; +wire ddrphy_stop0; +wire ddrphy_delay0; +wire ddrphy_reset0; +wire ddrphy_new_lock; +reg ddrphy_update = 1'd0; +reg ddrphy_stop1 = 1'd0; +reg ddrphy_freeze = 1'd0; +reg ddrphy_pause1 = 1'd0; +reg ddrphy_reset1 = 1'd0; +wire ddrphy_lock0; +wire ddrphy_delay1; +wire ddrphy_lock1; +reg ddrphy_lock_d = 1'd0; +reg [6:0] ddrphy_counter = 7'd0; +reg [1:0] ddrphy_dly_sel_storage = 2'd0; +reg ddrphy_dly_sel_re = 1'd0; +reg ddrphy_rdly_dq_rst_re = 1'd0; +wire ddrphy_rdly_dq_rst_r; +reg ddrphy_rdly_dq_rst_we = 1'd0; +reg ddrphy_rdly_dq_rst_w = 1'd0; +reg ddrphy_rdly_dq_inc_re = 1'd0; +wire ddrphy_rdly_dq_inc_r; +reg ddrphy_rdly_dq_inc_we = 1'd0; +reg ddrphy_rdly_dq_inc_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_rst_r; +reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg ddrphy_rdly_dq_bitslip_re = 1'd0; +wire ddrphy_rdly_dq_bitslip_r; +reg ddrphy_rdly_dq_bitslip_we = 1'd0; +reg ddrphy_rdly_dq_bitslip_w = 1'd0; +reg ddrphy_burstdet_clr_re = 1'd0; +wire ddrphy_burstdet_clr_r; +reg ddrphy_burstdet_clr_we = 1'd0; +reg ddrphy_burstdet_clr_w = 1'd0; +reg [1:0] ddrphy_burstdet_seen_status = 2'd0; +wire ddrphy_burstdet_seen_we; +reg ddrphy_burstdet_seen_re = 1'd0; +wire [1:0] ddrphy_datavalid; +wire [14:0] ddrphy_dfi_p0_address; +wire [2:0] ddrphy_dfi_p0_bank; +wire ddrphy_dfi_p0_cas_n; +wire ddrphy_dfi_p0_cs_n; +wire ddrphy_dfi_p0_ras_n; +wire ddrphy_dfi_p0_we_n; +wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_reset_n; +wire ddrphy_dfi_p0_act_n; +wire [63:0] ddrphy_dfi_p0_wrdata; +wire ddrphy_dfi_p0_wrdata_en; +wire [7:0] ddrphy_dfi_p0_wrdata_mask; +wire ddrphy_dfi_p0_rddata_en; +reg [63:0] ddrphy_dfi_p0_rddata = 64'd0; +wire ddrphy_dfi_p0_rddata_valid; +wire [14:0] ddrphy_dfi_p1_address; +wire [2:0] ddrphy_dfi_p1_bank; +wire ddrphy_dfi_p1_cas_n; +wire ddrphy_dfi_p1_cs_n; +wire ddrphy_dfi_p1_ras_n; +wire ddrphy_dfi_p1_we_n; +wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_reset_n; +wire ddrphy_dfi_p1_act_n; +wire [63:0] ddrphy_dfi_p1_wrdata; +wire ddrphy_dfi_p1_wrdata_en; +wire [7:0] ddrphy_dfi_p1_wrdata_mask; +wire ddrphy_dfi_p1_rddata_en; +reg [63:0] ddrphy_dfi_p1_rddata = 64'd0; +wire ddrphy_dfi_p1_rddata_valid; +wire ddrphy_bl8_chunk; +wire ddrphy_pad_oddrx2f0; +wire ddrphy_pad_oddrx2f1; +wire ddrphy_pad_oddrx2f2; +wire ddrphy_pad_oddrx2f3; +wire ddrphy_pad_oddrx2f4; +wire ddrphy_pad_oddrx2f5; +wire ddrphy_pad_oddrx2f6; +wire ddrphy_pad_oddrx2f7; +wire ddrphy_pad_oddrx2f8; +wire ddrphy_pad_oddrx2f9; +wire ddrphy_pad_oddrx2f10; +wire ddrphy_pad_oddrx2f11; +wire ddrphy_pad_oddrx2f12; +wire ddrphy_pad_oddrx2f13; +wire ddrphy_pad_oddrx2f14; +wire ddrphy_pad_oddrx2f15; +wire ddrphy_pad_oddrx2f16; +wire ddrphy_pad_oddrx2f17; +wire ddrphy_pad_oddrx2f18; +wire ddrphy_pad_oddrx2f19; +wire ddrphy_pad_oddrx2f20; +wire ddrphy_pad_oddrx2f21; +wire ddrphy_pad_oddrx2f22; +wire ddrphy_pad_oddrx2f23; +wire ddrphy_pad_oddrx2f24; +wire ddrphy_pad_oddrx2f25; +wire ddrphy_dq_oe; +wire ddrphy_dqs_re; +wire ddrphy_dqs_oe; +wire ddrphy_dqs_postamble; +wire ddrphy_dqs_preamble; +wire ddrphy_dqs_i0; +wire ddrphy_dqsr900; +wire ddrphy_dqsw2700; +wire ddrphy_dqsw0; +wire [2:0] ddrphy_rdpntr0; +wire [2:0] ddrphy_wrpntr0; +reg [2:0] ddrphy_rdly0 = 3'd0; +wire ddrphy_burstdet0; +reg ddrphy_burstdet_d0 = 1'd0; +wire ddrphy_dqs0; +wire ddrphy_dqs_oe_n0; +reg [7:0] ddrphy_dm_o_data0 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d0 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0; +wire ddrphy_dq_o0; +wire ddrphy_dq_i0; +wire ddrphy_dq_oe_n0; +wire ddrphy_dq_i_delayed0; +wire [7:0] ddrphy_dq_i_data0; +reg [7:0] ddrphy_dq_o_data0 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d0 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0; +wire [3:0] ddrphy_bitslip0_i; +reg [3:0] ddrphy_bitslip0_o = 4'd0; +reg [1:0] ddrphy_bitslip0_value = 2'd0; +reg [7:0] ddrphy_bitslip0_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0; +wire ddrphy_dq_o1; +wire ddrphy_dq_i1; +wire ddrphy_dq_oe_n1; +wire ddrphy_dq_i_delayed1; +wire [7:0] ddrphy_dq_i_data1; +reg [7:0] ddrphy_dq_o_data1 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0; +wire [3:0] ddrphy_bitslip1_i; +reg [3:0] ddrphy_bitslip1_o = 4'd0; +reg [1:0] ddrphy_bitslip1_value = 2'd0; +reg [7:0] ddrphy_bitslip1_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0; +wire ddrphy_dq_o2; +wire ddrphy_dq_i2; +wire ddrphy_dq_oe_n2; +wire ddrphy_dq_i_delayed2; +wire [7:0] ddrphy_dq_i_data2; +reg [7:0] ddrphy_dq_o_data2 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d2 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0; +wire [3:0] ddrphy_bitslip2_i; +reg [3:0] ddrphy_bitslip2_o = 4'd0; +reg [1:0] ddrphy_bitslip2_value = 2'd0; +reg [7:0] ddrphy_bitslip2_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0; +wire ddrphy_dq_o3; +wire ddrphy_dq_i3; +wire ddrphy_dq_oe_n3; +wire ddrphy_dq_i_delayed3; +wire [7:0] ddrphy_dq_i_data3; +reg [7:0] ddrphy_dq_o_data3 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d3 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0; +wire [3:0] ddrphy_bitslip3_i; +reg [3:0] ddrphy_bitslip3_o = 4'd0; +reg [1:0] ddrphy_bitslip3_value = 2'd0; +reg [7:0] ddrphy_bitslip3_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0; +wire ddrphy_dq_o4; +wire ddrphy_dq_i4; +wire ddrphy_dq_oe_n4; +wire ddrphy_dq_i_delayed4; +wire [7:0] ddrphy_dq_i_data4; +reg [7:0] ddrphy_dq_o_data4 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d4 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0; +wire [3:0] ddrphy_bitslip4_i; +reg [3:0] ddrphy_bitslip4_o = 4'd0; +reg [1:0] ddrphy_bitslip4_value = 2'd0; +reg [7:0] ddrphy_bitslip4_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0; +wire ddrphy_dq_o5; +wire ddrphy_dq_i5; +wire ddrphy_dq_oe_n5; +wire ddrphy_dq_i_delayed5; +wire [7:0] ddrphy_dq_i_data5; +reg [7:0] ddrphy_dq_o_data5 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d5 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0; +wire [3:0] ddrphy_bitslip5_i; +reg [3:0] ddrphy_bitslip5_o = 4'd0; +reg [1:0] ddrphy_bitslip5_value = 2'd0; +reg [7:0] ddrphy_bitslip5_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0; +wire ddrphy_dq_o6; +wire ddrphy_dq_i6; +wire ddrphy_dq_oe_n6; +wire ddrphy_dq_i_delayed6; +wire [7:0] ddrphy_dq_i_data6; +reg [7:0] ddrphy_dq_o_data6 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d6 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0; +wire [3:0] ddrphy_bitslip6_i; +reg [3:0] ddrphy_bitslip6_o = 4'd0; +reg [1:0] ddrphy_bitslip6_value = 2'd0; +reg [7:0] ddrphy_bitslip6_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0; +wire ddrphy_dq_o7; +wire ddrphy_dq_i7; +wire ddrphy_dq_oe_n7; +wire ddrphy_dq_i_delayed7; +wire [7:0] ddrphy_dq_i_data7; +reg [7:0] ddrphy_dq_o_data7 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d7 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0; +wire [3:0] ddrphy_bitslip7_i; +reg [3:0] ddrphy_bitslip7_o = 4'd0; +reg [1:0] ddrphy_bitslip7_value = 2'd0; +reg [7:0] ddrphy_bitslip7_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0; +wire ddrphy_dqs_i1; +wire ddrphy_dqsr901; +wire ddrphy_dqsw2701; +wire ddrphy_dqsw1; +wire [2:0] ddrphy_rdpntr1; +wire [2:0] ddrphy_wrpntr1; +reg [2:0] ddrphy_rdly1 = 3'd0; +wire ddrphy_burstdet1; +reg ddrphy_burstdet_d1 = 1'd0; +wire ddrphy_dqs1; +wire ddrphy_dqs_oe_n1; +reg [7:0] ddrphy_dm_o_data1 = 8'd0; +reg [7:0] ddrphy_dm_o_data_d1 = 8'd0; +reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0; +wire ddrphy_dq_o8; +wire ddrphy_dq_i8; +wire ddrphy_dq_oe_n8; +wire ddrphy_dq_i_delayed8; +wire [7:0] ddrphy_dq_i_data8; +reg [7:0] ddrphy_dq_o_data8 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d8 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0; +wire [3:0] ddrphy_bitslip8_i; +reg [3:0] ddrphy_bitslip8_o = 4'd0; +reg [1:0] ddrphy_bitslip8_value = 2'd0; +reg [7:0] ddrphy_bitslip8_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0; +wire ddrphy_dq_o9; +wire ddrphy_dq_i9; +wire ddrphy_dq_oe_n9; +wire ddrphy_dq_i_delayed9; +wire [7:0] ddrphy_dq_i_data9; +reg [7:0] ddrphy_dq_o_data9 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d9 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0; +wire [3:0] ddrphy_bitslip9_i; +reg [3:0] ddrphy_bitslip9_o = 4'd0; +reg [1:0] ddrphy_bitslip9_value = 2'd0; +reg [7:0] ddrphy_bitslip9_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0; +wire ddrphy_dq_o10; +wire ddrphy_dq_i10; +wire ddrphy_dq_oe_n10; +wire ddrphy_dq_i_delayed10; +wire [7:0] ddrphy_dq_i_data10; +reg [7:0] ddrphy_dq_o_data10 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d10 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0; +wire [3:0] ddrphy_bitslip10_i; +reg [3:0] ddrphy_bitslip10_o = 4'd0; +reg [1:0] ddrphy_bitslip10_value = 2'd0; +reg [7:0] ddrphy_bitslip10_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0; +wire ddrphy_dq_o11; +wire ddrphy_dq_i11; +wire ddrphy_dq_oe_n11; +wire ddrphy_dq_i_delayed11; +wire [7:0] ddrphy_dq_i_data11; +reg [7:0] ddrphy_dq_o_data11 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d11 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0; +wire [3:0] ddrphy_bitslip11_i; +reg [3:0] ddrphy_bitslip11_o = 4'd0; +reg [1:0] ddrphy_bitslip11_value = 2'd0; +reg [7:0] ddrphy_bitslip11_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0; +wire ddrphy_dq_o12; +wire ddrphy_dq_i12; +wire ddrphy_dq_oe_n12; +wire ddrphy_dq_i_delayed12; +wire [7:0] ddrphy_dq_i_data12; +reg [7:0] ddrphy_dq_o_data12 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d12 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0; +wire [3:0] ddrphy_bitslip12_i; +reg [3:0] ddrphy_bitslip12_o = 4'd0; +reg [1:0] ddrphy_bitslip12_value = 2'd0; +reg [7:0] ddrphy_bitslip12_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0; +wire ddrphy_dq_o13; +wire ddrphy_dq_i13; +wire ddrphy_dq_oe_n13; +wire ddrphy_dq_i_delayed13; +wire [7:0] ddrphy_dq_i_data13; +reg [7:0] ddrphy_dq_o_data13 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d13 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0; +wire [3:0] ddrphy_bitslip13_i; +reg [3:0] ddrphy_bitslip13_o = 4'd0; +reg [1:0] ddrphy_bitslip13_value = 2'd0; +reg [7:0] ddrphy_bitslip13_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0; +wire ddrphy_dq_o14; +wire ddrphy_dq_i14; +wire ddrphy_dq_oe_n14; +wire ddrphy_dq_i_delayed14; +wire [7:0] ddrphy_dq_i_data14; +reg [7:0] ddrphy_dq_o_data14 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d14 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0; +wire [3:0] ddrphy_bitslip14_i; +reg [3:0] ddrphy_bitslip14_o = 4'd0; +reg [1:0] ddrphy_bitslip14_value = 2'd0; +reg [7:0] ddrphy_bitslip14_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0; +wire ddrphy_dq_o15; +wire ddrphy_dq_i15; +wire ddrphy_dq_oe_n15; +wire ddrphy_dq_i_delayed15; +wire [7:0] ddrphy_dq_i_data15; +reg [7:0] ddrphy_dq_o_data15 = 8'd0; +reg [7:0] ddrphy_dq_o_data_d15 = 8'd0; +reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0; +wire [3:0] ddrphy_bitslip15_i; +reg [3:0] ddrphy_bitslip15_o = 4'd0; +reg [1:0] ddrphy_bitslip15_value = 2'd0; +reg [7:0] ddrphy_bitslip15_r = 8'd0; +reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0; +reg ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline8 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline9 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline10 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline11 = 1'd0; +reg ddrphy_rddata_en_tappeddelayline12 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0; +reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0; +wire [14:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [63:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [7:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [63:0] litedramcore_slave_p0_rddata = 64'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [63:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [7:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [63:0] litedramcore_slave_p1_rddata = 64'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +reg [14:0] litedramcore_master_p0_address = 15'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [63:0] litedramcore_master_p0_wrdata = 64'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [14:0] litedramcore_master_p1_address = 15'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [63:0] litedramcore_master_p1_wrdata = 64'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +wire [14:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [14:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [63:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [21:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [21:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [21:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [21:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [21:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [21:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [21:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [21:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [14:0] litedramcore_dfi_p0_address = 15'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [14:0] litedramcore_dfi_p1_address = 15'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [63:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [7:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [63:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [14:0] litedramcore_cmd_payload_a = 15'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [8:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [8:0] litedramcore_timer_count1 = 9'd374; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [6:0] litedramcore_sequencer_counter = 7'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [25:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [5:0] litedramcore_zqcs_executer_counter = 6'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [21:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [24:0] litedramcore_bankmachine0_syncfifo0_din; +wire [24:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [24:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [24:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [21:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine0_row = 15'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0; +wire litedramcore_bankmachine0_trascon_valid; +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [21:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [24:0] litedramcore_bankmachine1_syncfifo1_din; +wire [24:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [24:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [24:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [21:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine1_row = 15'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0; +wire litedramcore_bankmachine1_trascon_valid; +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [21:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [24:0] litedramcore_bankmachine2_syncfifo2_din; +wire [24:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [24:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [24:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [21:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine2_row = 15'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0; +wire litedramcore_bankmachine2_trascon_valid; +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [21:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [24:0] litedramcore_bankmachine3_syncfifo3_din; +wire [24:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [24:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [24:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [21:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine3_row = 15'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0; +wire litedramcore_bankmachine3_trascon_valid; +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [21:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [24:0] litedramcore_bankmachine4_syncfifo4_din; +wire [24:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [24:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [24:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [21:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine4_row = 15'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0; +wire litedramcore_bankmachine4_trascon_valid; +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [21:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [24:0] litedramcore_bankmachine5_syncfifo5_din; +wire [24:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [24:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [24:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [21:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine5_row = 15'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0; +wire litedramcore_bankmachine5_trascon_valid; +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [21:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [24:0] litedramcore_bankmachine6_syncfifo6_din; +wire [24:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [24:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [24:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [21:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine6_row = 15'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0; +wire litedramcore_bankmachine6_trascon_valid; +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [21:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [24:0] litedramcore_bankmachine7_syncfifo7_din; +wire [24:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [24:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [24:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [24:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [21:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0; +reg [14:0] litedramcore_bankmachine7_row = 15'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0; +wire litedramcore_bankmachine7_trascon_valid; +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [14:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [14:0] litedramcore_nop_a = 15'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +wire litedramcore_trrdcon_valid; +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +reg litedramcore_tfawcon_ready = 1'd1; +wire [1:0] litedramcore_tfawcon_count; +reg [2:0] litedramcore_tfawcon_window = 3'd0; +wire litedramcore_tccdcon_valid; +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [24:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_burstdet_seen_re = 1'd0; +wire [1:0] csrbank1_burstdet_seen_r; +reg csrbank1_burstdet_seen_we = 1'd0; +wire [1:0] csrbank1_burstdet_seen_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_r; +reg csrbank2_dfii_pi0_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata1_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_r; +reg csrbank2_dfii_pi0_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata1_w; +reg csrbank2_dfii_pi0_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_r; +reg csrbank2_dfii_pi0_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata0_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [14:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_r; +reg csrbank2_dfii_pi1_wrdata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata1_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata1_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_r; +reg csrbank2_dfii_pi1_rddata1_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata1_w; +reg csrbank2_dfii_pi1_rddata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_r; +reg csrbank2_dfii_pi1_rddata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata0_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_litedramecp5ddrphycrg_ecp5pll; +wire litedramcore_litedramecp5ddrphycrg_locked; +reg [1:0] litedramcore_litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0; +reg [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0; +reg [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0; +reg [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_litedramcore_roundrobin0_request; +wire litedramcore_litedramcore_roundrobin0_grant; +wire litedramcore_litedramcore_roundrobin0_ce; +wire litedramcore_litedramcore_roundrobin1_request; +wire litedramcore_litedramcore_roundrobin1_grant; +wire litedramcore_litedramcore_roundrobin1_ce; +wire litedramcore_litedramcore_roundrobin2_request; +wire litedramcore_litedramcore_roundrobin2_grant; +wire litedramcore_litedramcore_roundrobin2_ce; +wire litedramcore_litedramcore_roundrobin3_request; +wire litedramcore_litedramcore_roundrobin3_grant; +wire litedramcore_litedramcore_roundrobin3_ce; +wire litedramcore_litedramcore_roundrobin4_request; +wire litedramcore_litedramcore_roundrobin4_grant; +wire litedramcore_litedramcore_roundrobin4_ce; +wire litedramcore_litedramcore_roundrobin5_request; +wire litedramcore_litedramcore_roundrobin5_grant; +wire litedramcore_litedramcore_roundrobin5_ce; +wire litedramcore_litedramcore_roundrobin6_request; +wire litedramcore_litedramcore_roundrobin6_grant; +wire litedramcore_litedramcore_roundrobin6_ce; +wire litedramcore_litedramcore_roundrobin7_request; +wire litedramcore_litedramcore_roundrobin7_grant; +wire litedramcore_litedramcore_roundrobin7_ce; +reg litedramcore_litedramcore_locked0 = 1'd0; +reg litedramcore_litedramcore_locked1 = 1'd0; +reg litedramcore_litedramcore_locked2 = 1'd0; +reg litedramcore_litedramcore_locked3 = 1'd0; +reg litedramcore_litedramcore_locked4 = 1'd0; +reg litedramcore_litedramcore_locked5 = 1'd0; +reg litedramcore_litedramcore_locked6 = 1'd0; +reg litedramcore_litedramcore_locked7 = 1'd0; +reg litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0; +reg litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0; +reg litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [14:0] rhs_array_muxed1 = 15'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [14:0] rhs_array_muxed7 = 15'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [21:0] rhs_array_muxed12 = 22'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [21:0] rhs_array_muxed15 = 22'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [21:0] rhs_array_muxed18 = 22'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [21:0] rhs_array_muxed21 = 22'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [21:0] rhs_array_muxed24 = 22'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [21:0] rhs_array_muxed27 = 22'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [21:0] rhs_array_muxed30 = 22'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [21:0] rhs_array_muxed33 = 22'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [14:0] array_muxed1 = 15'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [14:0] array_muxed8 = 15'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +wire latticeecp5asyncresetsynchronizerimpl0_rst1; +wire latticeecp5asyncresetsynchronizerimpl0_expr; +wire latticeecp5asyncresetsynchronizerimpl1_rst1; +wire latticeecp5asyncresetsynchronizerimpl2_rst1; +wire latticeecp5asyncresetsynchronizerimpl3_rst1; +reg regs0 = 1'd0; +reg regs1 = 1'd0; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -1815,351 +1911,351 @@ assign sys2x_i_clk = crg_clkout0; assign init_clk = crg_clkout1; assign crg_locked = (litedramcore_litedramecp5ddrphycrg_locked & (~crg_reset1)); always @(*) begin - ddrphy_dm_o_data0 <= 8'd0; - ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1]; - ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[3]; - ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[5]; - ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[7]; - ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1]; - ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[3]; - ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[5]; - ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[7]; -end -always @(*) begin - ddrphy_dq_o_data0 <= 8'd0; - ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0]; - ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16]; - ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32]; - ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48]; - ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0]; - ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16]; - ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32]; - ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48]; + ddrphy_dm_o_data0 <= 8'd0; + ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1]; + ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[3]; + ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[5]; + ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[7]; + ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1]; + ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[3]; + ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[5]; + ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[7]; +end +always @(*) begin + ddrphy_dq_o_data0 <= 8'd0; + ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0]; + ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16]; + ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32]; + ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48]; + ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0]; + ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16]; + ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32]; + ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48]; end assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0}; always @(*) begin - ddrphy_dfi_p0_rddata <= 64'd0; - ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0]; - ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1]; - ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2]; - ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3]; - ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0]; - ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1]; - ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2]; - ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3]; - ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0]; - ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1]; - ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2]; - ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3]; - ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0]; - ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1]; - ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2]; - ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3]; - ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0]; - ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1]; - ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2]; - ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3]; - ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0]; - ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1]; - ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2]; - ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3]; - ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0]; - ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1]; - ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2]; - ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3]; - ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0]; - ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1]; - ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2]; - ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3]; - ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0]; - ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1]; - ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2]; - ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3]; - ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0]; - ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1]; - ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2]; - ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3]; - ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0]; - ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1]; - ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2]; - ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3]; - ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0]; - ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1]; - ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2]; - ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3]; - ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0]; - ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1]; - ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2]; - ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3]; - ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0]; - ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1]; - ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2]; - ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3]; - ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0]; - ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1]; - ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2]; - ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3]; - ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0]; - ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1]; - ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2]; - ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3]; -end -always @(*) begin - ddrphy_dfi_p1_rddata <= 64'd0; - ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4]; - ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5]; - ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6]; - ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7]; - ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4]; - ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5]; - ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6]; - ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7]; - ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4]; - ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5]; - ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6]; - ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7]; - ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4]; - ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5]; - ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6]; - ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7]; - ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4]; - ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5]; - ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6]; - ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7]; - ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4]; - ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5]; - ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6]; - ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7]; - ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4]; - ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5]; - ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6]; - ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7]; - ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4]; - ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5]; - ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6]; - ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7]; - ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4]; - ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5]; - ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6]; - ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7]; - ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4]; - ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5]; - ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6]; - ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7]; - ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4]; - ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5]; - ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6]; - ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7]; - ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4]; - ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5]; - ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6]; - ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7]; - ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4]; - ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5]; - ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6]; - ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7]; - ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4]; - ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5]; - ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6]; - ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7]; - ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4]; - ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5]; - ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6]; - ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7]; - ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4]; - ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5]; - ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6]; - ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7]; -end -always @(*) begin - ddrphy_dq_o_data1 <= 8'd0; - ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1]; - ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17]; - ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33]; - ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49]; - ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1]; - ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17]; - ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33]; - ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49]; + ddrphy_dfi_p0_rddata <= 64'd0; + ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0]; + ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1]; + ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2]; + ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3]; + ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0]; + ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1]; + ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2]; + ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3]; + ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0]; + ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1]; + ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2]; + ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3]; + ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0]; + ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1]; + ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2]; + ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3]; + ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0]; + ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1]; + ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2]; + ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3]; + ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0]; + ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1]; + ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2]; + ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3]; + ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0]; + ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1]; + ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2]; + ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3]; + ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0]; + ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1]; + ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2]; + ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3]; + ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0]; + ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1]; + ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2]; + ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3]; + ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0]; + ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1]; + ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2]; + ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3]; + ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0]; + ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1]; + ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2]; + ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3]; + ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0]; + ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1]; + ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2]; + ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3]; + ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0]; + ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1]; + ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2]; + ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3]; + ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0]; + ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1]; + ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2]; + ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3]; + ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0]; + ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1]; + ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2]; + ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3]; + ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0]; + ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1]; + ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2]; + ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3]; +end +always @(*) begin + ddrphy_dfi_p1_rddata <= 64'd0; + ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4]; + ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5]; + ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6]; + ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7]; + ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4]; + ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5]; + ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6]; + ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7]; + ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4]; + ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5]; + ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6]; + ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7]; + ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4]; + ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5]; + ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6]; + ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7]; + ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4]; + ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5]; + ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6]; + ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7]; + ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4]; + ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5]; + ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6]; + ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7]; + ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4]; + ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5]; + ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6]; + ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7]; + ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4]; + ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5]; + ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6]; + ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7]; + ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4]; + ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5]; + ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6]; + ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7]; + ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4]; + ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5]; + ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6]; + ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7]; + ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4]; + ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5]; + ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6]; + ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7]; + ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4]; + ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5]; + ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6]; + ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7]; + ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4]; + ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5]; + ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6]; + ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7]; + ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4]; + ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5]; + ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6]; + ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7]; + ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4]; + ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5]; + ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6]; + ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7]; + ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4]; + ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5]; + ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6]; + ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7]; +end +always @(*) begin + ddrphy_dq_o_data1 <= 8'd0; + ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1]; + ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17]; + ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33]; + ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49]; + ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1]; + ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17]; + ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33]; + ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49]; end assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1}; always @(*) begin - ddrphy_dq_o_data2 <= 8'd0; - ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2]; - ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18]; - ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34]; - ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50]; - ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2]; - ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18]; - ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34]; - ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50]; + ddrphy_dq_o_data2 <= 8'd0; + ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2]; + ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18]; + ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34]; + ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50]; + ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2]; + ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18]; + ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34]; + ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50]; end assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2}; always @(*) begin - ddrphy_dq_o_data3 <= 8'd0; - ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3]; - ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19]; - ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35]; - ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51]; - ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3]; - ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19]; - ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35]; - ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51]; + ddrphy_dq_o_data3 <= 8'd0; + ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3]; + ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19]; + ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35]; + ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51]; + ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3]; + ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19]; + ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35]; + ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51]; end assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3}; always @(*) begin - ddrphy_dq_o_data4 <= 8'd0; - ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4]; - ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20]; - ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36]; - ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52]; - ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4]; - ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20]; - ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36]; - ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52]; + ddrphy_dq_o_data4 <= 8'd0; + ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4]; + ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20]; + ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36]; + ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52]; + ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4]; + ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20]; + ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36]; + ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52]; end assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4}; always @(*) begin - ddrphy_dq_o_data5 <= 8'd0; - ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5]; - ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21]; - ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37]; - ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53]; - ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5]; - ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21]; - ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37]; - ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53]; + ddrphy_dq_o_data5 <= 8'd0; + ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5]; + ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21]; + ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37]; + ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53]; + ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5]; + ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21]; + ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37]; + ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53]; end assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5}; always @(*) begin - ddrphy_dq_o_data6 <= 8'd0; - ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6]; - ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22]; - ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38]; - ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54]; - ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6]; - ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22]; - ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38]; - ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54]; + ddrphy_dq_o_data6 <= 8'd0; + ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6]; + ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22]; + ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38]; + ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54]; + ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6]; + ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22]; + ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38]; + ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54]; end assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6}; always @(*) begin - ddrphy_dq_o_data7 <= 8'd0; - ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7]; - ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23]; - ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39]; - ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55]; - ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7]; - ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23]; - ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39]; - ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55]; + ddrphy_dq_o_data7 <= 8'd0; + ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7]; + ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23]; + ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39]; + ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55]; + ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7]; + ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23]; + ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39]; + ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55]; end assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7}; always @(*) begin - ddrphy_dm_o_data1 <= 8'd0; - ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0]; - ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[2]; - ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[4]; - ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[6]; - ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0]; - ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[2]; - ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[4]; - ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[6]; -end -always @(*) begin - ddrphy_dq_o_data8 <= 8'd0; - ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8]; - ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24]; - ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40]; - ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56]; - ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8]; - ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24]; - ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40]; - ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56]; + ddrphy_dm_o_data1 <= 8'd0; + ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0]; + ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[2]; + ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[4]; + ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[6]; + ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0]; + ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[2]; + ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[4]; + ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[6]; +end +always @(*) begin + ddrphy_dq_o_data8 <= 8'd0; + ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8]; + ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24]; + ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40]; + ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56]; + ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8]; + ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24]; + ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40]; + ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56]; end assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8}; always @(*) begin - ddrphy_dq_o_data9 <= 8'd0; - ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9]; - ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25]; - ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41]; - ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57]; - ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9]; - ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25]; - ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41]; - ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57]; + ddrphy_dq_o_data9 <= 8'd0; + ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9]; + ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25]; + ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41]; + ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57]; + ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9]; + ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25]; + ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41]; + ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57]; end assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9}; always @(*) begin - ddrphy_dq_o_data10 <= 8'd0; - ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10]; - ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26]; - ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42]; - ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58]; - ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10]; - ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26]; - ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42]; - ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58]; + ddrphy_dq_o_data10 <= 8'd0; + ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10]; + ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26]; + ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42]; + ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58]; + ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10]; + ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26]; + ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42]; + ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58]; end assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10}; always @(*) begin - ddrphy_dq_o_data11 <= 8'd0; - ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11]; - ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27]; - ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43]; - ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59]; - ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11]; - ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27]; - ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43]; - ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59]; + ddrphy_dq_o_data11 <= 8'd0; + ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11]; + ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27]; + ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43]; + ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59]; + ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11]; + ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27]; + ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43]; + ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59]; end assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11}; always @(*) begin - ddrphy_dq_o_data12 <= 8'd0; - ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12]; - ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28]; - ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44]; - ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60]; - ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12]; - ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28]; - ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44]; - ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60]; + ddrphy_dq_o_data12 <= 8'd0; + ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12]; + ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28]; + ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44]; + ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60]; + ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12]; + ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28]; + ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44]; + ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60]; end assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12}; always @(*) begin - ddrphy_dq_o_data13 <= 8'd0; - ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13]; - ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29]; - ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45]; - ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61]; - ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13]; - ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29]; - ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45]; - ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61]; + ddrphy_dq_o_data13 <= 8'd0; + ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13]; + ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29]; + ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45]; + ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61]; + ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13]; + ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29]; + ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45]; + ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61]; end assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13}; always @(*) begin - ddrphy_dq_o_data14 <= 8'd0; - ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14]; - ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30]; - ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46]; - ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62]; - ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14]; - ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30]; - ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46]; - ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62]; + ddrphy_dq_o_data14 <= 8'd0; + ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14]; + ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30]; + ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46]; + ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62]; + ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14]; + ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30]; + ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46]; + ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62]; end assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14}; always @(*) begin - ddrphy_dq_o_data15 <= 8'd0; - ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15]; - ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31]; - ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47]; - ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63]; - ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15]; - ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31]; - ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47]; - ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63]; + ddrphy_dq_o_data15 <= 8'd0; + ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15]; + ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31]; + ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47]; + ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63]; + ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15]; + ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31]; + ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47]; + ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63]; end assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15}; assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12; @@ -2176,276 +2272,276 @@ assign ddrphy_stop0 = ddrphy_stop1; assign ddrphy_delay0 = ddrphy_delay1; assign ddrphy_reset0 = ddrphy_reset1; always @(*) begin - ddrphy_bitslip0_o <= 4'd0; - case (ddrphy_bitslip0_value) - 1'd0: begin - ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip1_o <= 4'd0; - case (ddrphy_bitslip1_value) - 1'd0: begin - ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip2_o <= 4'd0; - case (ddrphy_bitslip2_value) - 1'd0: begin - ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip3_o <= 4'd0; - case (ddrphy_bitslip3_value) - 1'd0: begin - ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip4_o <= 4'd0; - case (ddrphy_bitslip4_value) - 1'd0: begin - ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip5_o <= 4'd0; - case (ddrphy_bitslip5_value) - 1'd0: begin - ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip6_o <= 4'd0; - case (ddrphy_bitslip6_value) - 1'd0: begin - ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip7_o <= 4'd0; - case (ddrphy_bitslip7_value) - 1'd0: begin - ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip8_o <= 4'd0; - case (ddrphy_bitslip8_value) - 1'd0: begin - ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip9_o <= 4'd0; - case (ddrphy_bitslip9_value) - 1'd0: begin - ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip10_o <= 4'd0; - case (ddrphy_bitslip10_value) - 1'd0: begin - ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip11_o <= 4'd0; - case (ddrphy_bitslip11_value) - 1'd0: begin - ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip12_o <= 4'd0; - case (ddrphy_bitslip12_value) - 1'd0: begin - ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip13_o <= 4'd0; - case (ddrphy_bitslip13_value) - 1'd0: begin - ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip14_o <= 4'd0; - case (ddrphy_bitslip14_value) - 1'd0: begin - ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3]; - end - endcase -end -always @(*) begin - ddrphy_bitslip15_o <= 4'd0; - case (ddrphy_bitslip15_value) - 1'd0: begin - ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0]; - end - 1'd1: begin - ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1]; - end - 2'd2: begin - ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2]; - end - 2'd3: begin - ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3]; - end - endcase + ddrphy_bitslip0_o <= 4'd0; + case (ddrphy_bitslip0_value) + 1'd0: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip1_o <= 4'd0; + case (ddrphy_bitslip1_value) + 1'd0: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip2_o <= 4'd0; + case (ddrphy_bitslip2_value) + 1'd0: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip3_o <= 4'd0; + case (ddrphy_bitslip3_value) + 1'd0: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip4_o <= 4'd0; + case (ddrphy_bitslip4_value) + 1'd0: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip5_o <= 4'd0; + case (ddrphy_bitslip5_value) + 1'd0: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip6_o <= 4'd0; + case (ddrphy_bitslip6_value) + 1'd0: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip7_o <= 4'd0; + case (ddrphy_bitslip7_value) + 1'd0: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip8_o <= 4'd0; + case (ddrphy_bitslip8_value) + 1'd0: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip9_o <= 4'd0; + case (ddrphy_bitslip9_value) + 1'd0: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip10_o <= 4'd0; + case (ddrphy_bitslip10_value) + 1'd0: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip11_o <= 4'd0; + case (ddrphy_bitslip11_value) + 1'd0: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip12_o <= 4'd0; + case (ddrphy_bitslip12_value) + 1'd0: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip13_o <= 4'd0; + case (ddrphy_bitslip13_value) + 1'd0: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip14_o <= 4'd0; + case (ddrphy_bitslip14_value) + 1'd0: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3]; + end + endcase +end +always @(*) begin + ddrphy_bitslip15_o <= 4'd0; + case (ddrphy_bitslip15_value) + 1'd0: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0]; + end + 1'd1: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1]; + end + 2'd2: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2]; + end + 2'd3: begin + ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3]; + end + endcase end assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -2512,448 +2608,448 @@ assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 8'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 64'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 64'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 15'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 8'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata <= 64'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 64'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 15'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -2962,36 +3058,36 @@ assign litedramcore_csr_dfi_p1_odt = litedramcore_odt; assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -3000,36 +3096,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -3107,4126 +3203,4222 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_litedramcore_refresher_next_state <= 2'd0; - litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state; - case (litedramcore_litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]); + litedramcore_litedramcore_refresher_next_state <= 2'd0; + litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state; + case (litedramcore_litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine0_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_litedramcore_bankmachine0_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine1_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_litedramcore_bankmachine1_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine2_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_litedramcore_bankmachine2_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine3_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_litedramcore_bankmachine3_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine4_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_litedramcore_bankmachine4_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine5_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_litedramcore_bankmachine5_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine6_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_litedramcore_bankmachine6_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 15'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 15'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd0; - litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd6; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd6: begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_litedramcore_bankmachine7_next_state <= 3'd0; + litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_litedramcore_bankmachine7_next_state <= 3'd6; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd6: begin + litedramcore_litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase end assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); @@ -7253,15 +7445,15 @@ assign {litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_i assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -7271,106 +7463,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -7380,22 +7572,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -7406,506 +7598,506 @@ assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]); always @(*) begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd11; - end - 4'd11: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd12; - end - 4'd12: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd13; - end - 4'd13: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd14; - end - 4'd14: begin - litedramcore_litedramcore_multiplexer_next_state <= 4'd15; - end - 4'd15: begin - litedramcore_litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if (1'd0) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if (1'd1) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if (1'd0) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if (1'd1) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd0) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if (1'd0) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd1) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - 4'd11: begin - end - 4'd12: begin - end - 4'd13: begin - end - 4'd14: begin - end - 4'd15: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase + litedramcore_litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd11; + end + 4'd11: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd12; + end + 4'd12: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd13; + end + 4'd13: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd14; + end + 4'd14: begin + litedramcore_litedramcore_multiplexer_next_state <= 4'd15; + end + 4'd15: begin + litedramcore_litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if (1'd1) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if (1'd1) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd0) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd1) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + 4'd12: begin + end + 4'd13: begin + end + 4'd14: begin + end + 4'd15: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase end assign litedramcore_litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -7951,26 +8143,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_litedramcore_roundro assign user_port_wdata_ready = litedramcore_litedramcore_new_master_wdata_ready3; assign user_port_rdata_valid = litedramcore_litedramcore_new_master_rdata_valid13; always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_litedramcore_new_master_wdata_ready3}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_litedramcore_new_master_wdata_ready3}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_litedramcore_new_master_wdata_ready3}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_litedramcore_roundrobin0_grant = 1'd0; @@ -7982,129 +8174,129 @@ assign litedramcore_litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -8120,123 +8312,123 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end always @(*) begin - ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end always @(*) begin - ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0]; always @(*) begin - ddrphy_burstdet_clr_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_re <= interface1_bank_bus_we; - end + ddrphy_burstdet_clr_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_re <= interface1_bank_bus_we; + end end always @(*) begin - ddrphy_burstdet_clr_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); - end + ddrphy_burstdet_clr_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we); + end end assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_burstdet_seen_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); - end + csrbank1_burstdet_seen_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_burstdet_seen_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_burstdet_seen_re <= interface1_bank_bus_we; - end + csrbank1_burstdet_seen_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_burstdet_seen_re <= interface1_bank_bus_we; + end end assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0]; assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0]; @@ -8244,224 +8436,224 @@ assign ddrphy_burstdet_seen_we = csrbank1_burstdet_seen_we; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_wrdata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata1_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata1_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata1_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_rddata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we; + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -8511,956 +8703,956 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 15'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 15'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 22'd0; - case (litedramcore_litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 22'd0; - case (litedramcore_litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 22'd0; - case (litedramcore_litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 22'd0; - case (litedramcore_litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 15'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 15'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 22'd0; + case (litedramcore_litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 22'd0; + case (litedramcore_litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 22'd0; + case (litedramcore_litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 22'd0; + case (litedramcore_litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 22'd0; - case (litedramcore_litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 22'd0; - case (litedramcore_litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 22'd0; - case (litedramcore_litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 22'd0; - case (litedramcore_litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 15'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 15'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 22'd0; + case (litedramcore_litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 22'd0; + case (litedramcore_litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 22'd0; + case (litedramcore_litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 22'd0; + case (litedramcore_litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 15'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 15'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign ddrphy_lock1 = regs1; @@ -9470,2155 +9662,2155 @@ assign ddrphy_lock1 = regs1; //------------------------------------------------------------------------------ always @(posedge init_clk) begin - ddrphy_lock_d <= ddrphy_lock1; - if ((ddrphy_counter == 4'd8)) begin - ddrphy_freeze <= 1'd1; - end - if ((ddrphy_counter == 5'd16)) begin - ddrphy_stop1 <= 1'd1; - end - if ((ddrphy_counter == 5'd24)) begin - ddrphy_reset1 <= 1'd1; - end - if ((ddrphy_counter == 6'd32)) begin - ddrphy_reset1 <= 1'd0; - end - if ((ddrphy_counter == 6'd40)) begin - ddrphy_stop1 <= 1'd0; - end - if ((ddrphy_counter == 6'd48)) begin - ddrphy_freeze <= 1'd0; - end - if ((ddrphy_counter == 6'd56)) begin - ddrphy_pause1 <= 1'd1; - end - if ((ddrphy_counter == 7'd64)) begin - ddrphy_update <= 1'd1; - end - if ((ddrphy_counter == 7'd72)) begin - ddrphy_update <= 1'd0; - end - if ((ddrphy_counter == 7'd80)) begin - ddrphy_pause1 <= 1'd0; - end - if ((ddrphy_counter == 7'd80)) begin - ddrphy_counter <= 1'd0; - end else begin - if ((ddrphy_counter != 1'd0)) begin - ddrphy_counter <= (ddrphy_counter + 1'd1); - end else begin - if (ddrphy_new_lock) begin - ddrphy_counter <= 1'd1; - end - end - end - if (init_rst) begin - ddrphy_update <= 1'd0; - ddrphy_stop1 <= 1'd0; - ddrphy_freeze <= 1'd0; - ddrphy_pause1 <= 1'd0; - ddrphy_reset1 <= 1'd0; - ddrphy_lock_d <= 1'd0; - ddrphy_counter <= 7'd0; - end - regs0 <= ddrphy_lock0; - regs1 <= regs0; + ddrphy_lock_d <= ddrphy_lock1; + if ((ddrphy_counter == 4'd8)) begin + ddrphy_freeze <= 1'd1; + end + if ((ddrphy_counter == 5'd16)) begin + ddrphy_stop1 <= 1'd1; + end + if ((ddrphy_counter == 5'd24)) begin + ddrphy_reset1 <= 1'd1; + end + if ((ddrphy_counter == 6'd32)) begin + ddrphy_reset1 <= 1'd0; + end + if ((ddrphy_counter == 6'd40)) begin + ddrphy_stop1 <= 1'd0; + end + if ((ddrphy_counter == 6'd48)) begin + ddrphy_freeze <= 1'd0; + end + if ((ddrphy_counter == 6'd56)) begin + ddrphy_pause1 <= 1'd1; + end + if ((ddrphy_counter == 7'd64)) begin + ddrphy_update <= 1'd1; + end + if ((ddrphy_counter == 7'd72)) begin + ddrphy_update <= 1'd0; + end + if ((ddrphy_counter == 7'd80)) begin + ddrphy_pause1 <= 1'd0; + end + if ((ddrphy_counter == 7'd80)) begin + ddrphy_counter <= 1'd0; + end else begin + if ((ddrphy_counter != 1'd0)) begin + ddrphy_counter <= (ddrphy_counter + 1'd1); + end else begin + if (ddrphy_new_lock) begin + ddrphy_counter <= 1'd1; + end + end + end + if (init_rst) begin + ddrphy_update <= 1'd0; + ddrphy_stop1 <= 1'd0; + ddrphy_freeze <= 1'd0; + ddrphy_pause1 <= 1'd0; + ddrphy_reset1 <= 1'd0; + ddrphy_lock_d <= 1'd0; + ddrphy_counter <= 7'd0; + end + regs0 <= ddrphy_lock0; + regs1 <= regs0; end always @(posedge por_clk) begin - if ((~crg_por_done)) begin - crg_por_count <= (crg_por_count - 1'd1); - end + if ((~crg_por_done)) begin + crg_por_count <= (crg_por_count - 1'd1); + end end always @(posedge sys_clk) begin - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin - ddrphy_rdly0 <= 1'd0; - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin - ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1); - end - ddrphy_burstdet_d0 <= ddrphy_burstdet0; - if (ddrphy_burstdet_clr_re) begin - ddrphy_burstdet_seen_status[0] <= 1'd0; - end - if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin - ddrphy_burstdet_seen_status[0] <= 1'd1; - end - ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0]; - end - 1'd1: begin - ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4]; - end - endcase - ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o; - ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o; - ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o; - ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o; - ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o; - ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o; - ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o; - ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin - ddrphy_rdly1 <= 1'd0; - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin - ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1); - end - ddrphy_burstdet_d1 <= ddrphy_burstdet1; - if (ddrphy_burstdet_clr_re) begin - ddrphy_burstdet_seen_status[1] <= 1'd0; - end - if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin - ddrphy_burstdet_seen_status[1] <= 1'd1; - end - ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0]; - end - 1'd1: begin - ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4]; - end - endcase - ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o; - ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o; - ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o; - ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o; - ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o; - ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o; - ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o; - ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15; - case (ddrphy_bl8_chunk) - 1'd0: begin - ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0]; - end - 1'd1: begin - ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4]; - end - endcase - ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip0_value <= 1'd0; - end - ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip1_value <= 1'd0; - end - ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip2_value <= 1'd0; - end - ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip3_value <= 1'd0; - end - ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip4_value <= 1'd0; - end - ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip5_value <= 1'd0; - end - ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip6_value <= 1'd0; - end - ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]}; - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip7_value <= 1'd0; - end - ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip8_value <= 1'd0; - end - ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip9_value <= 1'd0; - end - ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip10_value <= 1'd0; - end - ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip11_value <= 1'd0; - end - ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip12_value <= 1'd0; - end - ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip13_value <= 1'd0; - end - ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip14_value <= 1'd0; - end - ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]}; - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin - ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1); - end - if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin - ddrphy_bitslip15_value <= 1'd0; - end - ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]}; - ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en); - ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0; - ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1; - ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2; - ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3; - ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4; - ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5; - ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6; - ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7; - ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8; - ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9; - ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10; - ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11; - ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en); - ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0; - ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1; - ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2; - ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3; - ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4; - ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 9'd374; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd2)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 7'd106)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 7'd106)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 26'd47999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd2)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 6'd34)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 6'd34)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd6; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 2'd2; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd6; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state; - litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0; - litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1; - litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2; - litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0; - litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1; - litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2; - litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3; - litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4; - litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5; - litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6; - litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7; - litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8; - litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9; - litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10; - litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11; - litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w; - end - endcase - end - if (csrbank1_dly_sel0_re) begin - ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; - end - ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata1_re) begin - litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; - end - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata1_re) begin - litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; - end - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; - if (sys_rst) begin - ddrphy_dly_sel_storage <= 2'd0; - ddrphy_dly_sel_re <= 1'd0; - ddrphy_burstdet_seen_status <= 2'd0; - ddrphy_burstdet_seen_re <= 1'd0; - ddrphy_rdly0 <= 3'd0; - ddrphy_burstdet_d0 <= 1'd0; - ddrphy_dm_o_data_d0 <= 8'd0; - ddrphy_dm_o_data_muxed0 <= 4'd0; - ddrphy_dq_o_data_d0 <= 8'd0; - ddrphy_dq_o_data_muxed0 <= 4'd0; - ddrphy_bitslip0_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d0 <= 4'd0; - ddrphy_dq_o_data_d1 <= 8'd0; - ddrphy_dq_o_data_muxed1 <= 4'd0; - ddrphy_bitslip1_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d1 <= 4'd0; - ddrphy_dq_o_data_d2 <= 8'd0; - ddrphy_dq_o_data_muxed2 <= 4'd0; - ddrphy_bitslip2_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d2 <= 4'd0; - ddrphy_dq_o_data_d3 <= 8'd0; - ddrphy_dq_o_data_muxed3 <= 4'd0; - ddrphy_bitslip3_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d3 <= 4'd0; - ddrphy_dq_o_data_d4 <= 8'd0; - ddrphy_dq_o_data_muxed4 <= 4'd0; - ddrphy_bitslip4_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d4 <= 4'd0; - ddrphy_dq_o_data_d5 <= 8'd0; - ddrphy_dq_o_data_muxed5 <= 4'd0; - ddrphy_bitslip5_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d5 <= 4'd0; - ddrphy_dq_o_data_d6 <= 8'd0; - ddrphy_dq_o_data_muxed6 <= 4'd0; - ddrphy_bitslip6_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d6 <= 4'd0; - ddrphy_dq_o_data_d7 <= 8'd0; - ddrphy_dq_o_data_muxed7 <= 4'd0; - ddrphy_bitslip7_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d7 <= 4'd0; - ddrphy_rdly1 <= 3'd0; - ddrphy_burstdet_d1 <= 1'd0; - ddrphy_dm_o_data_d1 <= 8'd0; - ddrphy_dm_o_data_muxed1 <= 4'd0; - ddrphy_dq_o_data_d8 <= 8'd0; - ddrphy_dq_o_data_muxed8 <= 4'd0; - ddrphy_bitslip8_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d8 <= 4'd0; - ddrphy_dq_o_data_d9 <= 8'd0; - ddrphy_dq_o_data_muxed9 <= 4'd0; - ddrphy_bitslip9_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d9 <= 4'd0; - ddrphy_dq_o_data_d10 <= 8'd0; - ddrphy_dq_o_data_muxed10 <= 4'd0; - ddrphy_bitslip10_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d10 <= 4'd0; - ddrphy_dq_o_data_d11 <= 8'd0; - ddrphy_dq_o_data_muxed11 <= 4'd0; - ddrphy_bitslip11_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d11 <= 4'd0; - ddrphy_dq_o_data_d12 <= 8'd0; - ddrphy_dq_o_data_muxed12 <= 4'd0; - ddrphy_bitslip12_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d12 <= 4'd0; - ddrphy_dq_o_data_d13 <= 8'd0; - ddrphy_dq_o_data_muxed13 <= 4'd0; - ddrphy_bitslip13_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d13 <= 4'd0; - ddrphy_dq_o_data_d14 <= 8'd0; - ddrphy_dq_o_data_muxed14 <= 4'd0; - ddrphy_bitslip14_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d14 <= 4'd0; - ddrphy_dq_o_data_d15 <= 8'd0; - ddrphy_dq_o_data_muxed15 <= 4'd0; - ddrphy_bitslip15_value <= 2'd0; - ddrphy_dq_i_bitslip_o_d15 <= 4'd0; - ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - ddrphy_rddata_en_tappeddelayline8 <= 1'd0; - ddrphy_rddata_en_tappeddelayline9 <= 1'd0; - ddrphy_rddata_en_tappeddelayline10 <= 1'd0; - ddrphy_rddata_en_tappeddelayline11 <= 1'd0; - ddrphy_rddata_en_tappeddelayline12 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline3 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline4 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline5 <= 1'd0; - ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 64'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 64'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 15'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 15'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 15'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 9'd374; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 7'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 26'd47999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 6'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine0_row <= 15'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 2'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 2'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine1_row <= 15'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 2'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 2'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine2_row <= 15'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 2'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 2'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine3_row <= 15'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 2'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 2'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine4_row <= 15'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 2'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 2'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine5_row <= 15'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 2'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 2'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine6_row <= 15'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 2'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 2'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0; - litedramcore_bankmachine7_row <= 15'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 2'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 2'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 3'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_litedramcore_refresher_state <= 2'd0; - litedramcore_litedramcore_bankmachine0_state <= 3'd0; - litedramcore_litedramcore_bankmachine1_state <= 3'd0; - litedramcore_litedramcore_bankmachine2_state <= 3'd0; - litedramcore_litedramcore_bankmachine3_state <= 3'd0; - litedramcore_litedramcore_bankmachine4_state <= 3'd0; - litedramcore_litedramcore_bankmachine5_state <= 3'd0; - litedramcore_litedramcore_bankmachine6_state <= 3'd0; - litedramcore_litedramcore_bankmachine7_state <= 3'd0; - litedramcore_litedramcore_multiplexer_state <= 4'd0; - litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0; - litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0; - litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0; - litedramcore_state <= 2'd0; - end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly0 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1); + end + ddrphy_burstdet_d0 <= ddrphy_burstdet0; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[0] <= 1'd0; + end + if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin + ddrphy_burstdet_seen_status[0] <= 1'd1; + end + ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4]; + end + endcase + ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o; + ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o; + ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o; + ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o; + ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o; + ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o; + ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o; + ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin + ddrphy_rdly1 <= 1'd0; + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin + ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1); + end + ddrphy_burstdet_d1 <= ddrphy_burstdet1; + if (ddrphy_burstdet_clr_re) begin + ddrphy_burstdet_seen_status[1] <= 1'd0; + end + if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin + ddrphy_burstdet_seen_status[1] <= 1'd1; + end + ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0]; + end + 1'd1: begin + ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4]; + end + endcase + ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o; + ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o; + ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o; + ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o; + ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o; + ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o; + ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o; + ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15; + case (ddrphy_bl8_chunk) + 1'd0: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0]; + end + 1'd1: begin + ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4]; + end + endcase + ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip0_value <= 1'd0; + end + ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip1_value <= 1'd0; + end + ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip2_value <= 1'd0; + end + ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip3_value <= 1'd0; + end + ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip4_value <= 1'd0; + end + ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip5_value <= 1'd0; + end + ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip6_value <= 1'd0; + end + ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]}; + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip7_value <= 1'd0; + end + ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip8_value <= 1'd0; + end + ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip9_value <= 1'd0; + end + ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip10_value <= 1'd0; + end + ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip11_value <= 1'd0; + end + ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip12_value <= 1'd0; + end + ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip13_value <= 1'd0; + end + ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip14_value <= 1'd0; + end + ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]}; + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin + ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1); + end + if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin + ddrphy_bitslip15_value <= 1'd0; + end + ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]}; + ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en); + ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0; + ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1; + ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2; + ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3; + ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4; + ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5; + ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6; + ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7; + ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8; + ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9; + ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10; + ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11; + ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en); + ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0; + ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1; + ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2; + ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3; + ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4; + ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 9'd374; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd2)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 7'd106)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 7'd106)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 26'd47999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd2)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 6'd34)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 6'd34)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd6; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 2'd2; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd6; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state; + litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0; + litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1; + litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2; + litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0; + litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1; + litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2; + litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3; + litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4; + litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5; + litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6; + litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7; + litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8; + litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9; + litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10; + litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11; + litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w; + end + endcase + end + if (csrbank1_dly_sel0_re) begin + ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata1_re) begin + litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r; + end + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata1_re) begin + litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r; + end + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re; + if (sys_rst) begin + ddrphy_dly_sel_storage <= 2'd0; + ddrphy_dly_sel_re <= 1'd0; + ddrphy_burstdet_seen_status <= 2'd0; + ddrphy_burstdet_seen_re <= 1'd0; + ddrphy_rdly0 <= 3'd0; + ddrphy_burstdet_d0 <= 1'd0; + ddrphy_dm_o_data_d0 <= 8'd0; + ddrphy_dm_o_data_muxed0 <= 4'd0; + ddrphy_dq_o_data_d0 <= 8'd0; + ddrphy_dq_o_data_muxed0 <= 4'd0; + ddrphy_bitslip0_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d0 <= 4'd0; + ddrphy_dq_o_data_d1 <= 8'd0; + ddrphy_dq_o_data_muxed1 <= 4'd0; + ddrphy_bitslip1_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d1 <= 4'd0; + ddrphy_dq_o_data_d2 <= 8'd0; + ddrphy_dq_o_data_muxed2 <= 4'd0; + ddrphy_bitslip2_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d2 <= 4'd0; + ddrphy_dq_o_data_d3 <= 8'd0; + ddrphy_dq_o_data_muxed3 <= 4'd0; + ddrphy_bitslip3_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d3 <= 4'd0; + ddrphy_dq_o_data_d4 <= 8'd0; + ddrphy_dq_o_data_muxed4 <= 4'd0; + ddrphy_bitslip4_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d4 <= 4'd0; + ddrphy_dq_o_data_d5 <= 8'd0; + ddrphy_dq_o_data_muxed5 <= 4'd0; + ddrphy_bitslip5_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d5 <= 4'd0; + ddrphy_dq_o_data_d6 <= 8'd0; + ddrphy_dq_o_data_muxed6 <= 4'd0; + ddrphy_bitslip6_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d6 <= 4'd0; + ddrphy_dq_o_data_d7 <= 8'd0; + ddrphy_dq_o_data_muxed7 <= 4'd0; + ddrphy_bitslip7_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d7 <= 4'd0; + ddrphy_rdly1 <= 3'd0; + ddrphy_burstdet_d1 <= 1'd0; + ddrphy_dm_o_data_d1 <= 8'd0; + ddrphy_dm_o_data_muxed1 <= 4'd0; + ddrphy_dq_o_data_d8 <= 8'd0; + ddrphy_dq_o_data_muxed8 <= 4'd0; + ddrphy_bitslip8_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d8 <= 4'd0; + ddrphy_dq_o_data_d9 <= 8'd0; + ddrphy_dq_o_data_muxed9 <= 4'd0; + ddrphy_bitslip9_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d9 <= 4'd0; + ddrphy_dq_o_data_d10 <= 8'd0; + ddrphy_dq_o_data_muxed10 <= 4'd0; + ddrphy_bitslip10_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d10 <= 4'd0; + ddrphy_dq_o_data_d11 <= 8'd0; + ddrphy_dq_o_data_muxed11 <= 4'd0; + ddrphy_bitslip11_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d11 <= 4'd0; + ddrphy_dq_o_data_d12 <= 8'd0; + ddrphy_dq_o_data_muxed12 <= 4'd0; + ddrphy_bitslip12_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d12 <= 4'd0; + ddrphy_dq_o_data_d13 <= 8'd0; + ddrphy_dq_o_data_muxed13 <= 4'd0; + ddrphy_bitslip13_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d13 <= 4'd0; + ddrphy_dq_o_data_d14 <= 8'd0; + ddrphy_dq_o_data_muxed14 <= 4'd0; + ddrphy_bitslip14_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d14 <= 4'd0; + ddrphy_dq_o_data_d15 <= 8'd0; + ddrphy_dq_o_data_muxed15 <= 4'd0; + ddrphy_bitslip15_value <= 2'd0; + ddrphy_dq_i_bitslip_o_d15 <= 4'd0; + ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + ddrphy_rddata_en_tappeddelayline8 <= 1'd0; + ddrphy_rddata_en_tappeddelayline9 <= 1'd0; + ddrphy_rddata_en_tappeddelayline10 <= 1'd0; + ddrphy_rddata_en_tappeddelayline11 <= 1'd0; + ddrphy_rddata_en_tappeddelayline12 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline3 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline4 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline5 <= 1'd0; + ddrphy_wrdata_en_tappeddelayline6 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 64'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 64'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 15'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 15'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 15'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 9'd374; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 7'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 26'd47999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 6'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine0_row <= 15'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 2'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 2'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine1_row <= 15'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 2'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 2'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine2_row <= 15'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 2'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 2'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine3_row <= 15'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 2'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 2'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine4_row <= 15'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 2'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 2'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine5_row <= 15'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 2'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 2'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine6_row <= 15'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 2'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 2'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0; + litedramcore_bankmachine7_row <= 15'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 2'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 2'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 3'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_litedramcore_refresher_state <= 2'd0; + litedramcore_litedramcore_bankmachine0_state <= 3'd0; + litedramcore_litedramcore_bankmachine1_state <= 3'd0; + litedramcore_litedramcore_bankmachine2_state <= 3'd0; + litedramcore_litedramcore_bankmachine3_state <= 3'd0; + litedramcore_litedramcore_bankmachine4_state <= 3'd0; + litedramcore_litedramcore_bankmachine5_state <= 3'd0; + litedramcore_litedramcore_bankmachine6_state <= 3'd0; + litedramcore_litedramcore_bankmachine7_state <= 3'd0; + litedramcore_litedramcore_multiplexer_state <= 4'd0; + litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0; + litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0; + litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -13024,14 +13216,14 @@ TSHX2DQA TSHX2DQA_15( reg [24:0] storage[0:15]; reg [24:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -13042,14 +13234,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [24:0] storage_1[0:15]; reg [24:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -13060,14 +13252,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [24:0] storage_2[0:15]; reg [24:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -13078,14 +13270,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [24:0] storage_3[0:15]; reg [24:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -13096,14 +13288,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [24:0] storage_4[0:15]; reg [24:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -13114,14 +13306,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [24:0] storage_5[0:15]; reg [24:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -13132,14 +13324,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [24:0] storage_6[0:15]; reg [24:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -13150,17 +13342,18 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [24:0] storage_7[0:15]; reg [24:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; -(* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #( +(* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) +EHXPLLL #( .CLKFB_DIV(4'd10), .CLKI_DIV(1'd1), .CLKOP_CPHASE(3'd4), @@ -13407,5 +13600,5 @@ TRELLIS_IO #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:07:03. +// Auto-Generated by LiteX on 2022-10-28 19:01:26. //------------------------------------------------------------------------------ diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init index c3dd752..71d4b3f 100644 --- a/litedram/generated/sim/litedram_core.init +++ b/litedram/generated/sim/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842a3c4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048001781 -386100207c7f1b78 -6000000048001199 +6000000048001789 +7fc3f3787c7f1b78 +60000000480011a9 7fe3fb78382100b0 -0000000048001e88 -0000018001000000 +0000000048001eac +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842a3283c4c0001 +3842a3203c4c0001 7d6000267c0802a6 -9161000848001dc1 -48001195f821fed1 +9161000848001de9 +480011a5f821fed1 3c62ffff60000000 -4bffff4138637b38 +4bffff3938637b68 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b58 -3c62ffff4bffff1d -38637b787bff0020 -7c0004ac4bffff0d +63ff000838637b88 +3c62ffff4bffff15 +38637ba87bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b90 +4bfffee938637bc0 4d80000073e90002 3c62ffff41820010 -4bfffed938637b98 +4bfffed138637bc8 4e00000073e90004 3c62ffff41820010 -4bfffec138637ba0 +4bfffeb938637bd0 4d00000073e90008 3c62ffff41820010 -4bfffea938637ba8 +4bfffea138637bd8 4182001073e90010 -38637bb83c62ffff -73ff01004bfffe95 +38637be83c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637bc8 -3b7b7bd03f62ffff -4bfffe717f63db78 +4bfffe7938637bf8 +3b7b7c003f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637bd8 +4bfffe4138637c08 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637bf0 +4bfffe1938637c20 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637c087884b282 -3d20c0004bfffdfd +38637c387884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637c207c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c50 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637c40 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c7057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c605784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c9057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c80 -7f40efaa7c0004ac +4bfffc8138637cb0 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c983c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637cc83c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637ca87bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637cc83c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c90 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637dd8 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048000eb1 -38637df83c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847ce03c62ffff -4bfffb0938637cf0 -60000000480002e5 -3c82ffff4bffff54 -38847ce03c62ffff -4bfffae938637cf0 -60000000480002c5 -3c62ffff4bffff80 -4bfffad138637d10 -38a000403c9ef000 -3861007078840020 -6000000048000e39 -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637cd83be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637d0838847cf8 +480003794bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637d28 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637cc03c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637d40 +38a000403c9af000 +7884002038610070 +6000000048000e69 +e92100703d400002 614a464c3c62ffff -794a83e438637d28 +794a83e438637d58 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d483c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d783c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637da888810070 +38637dd888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d603ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637e08 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048000dc1 +38637e283c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d903b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d88 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637db8 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -4800189c7d638120 -38a000383c9ef000 -386100b078840020 -6000000048000d51 +480018a47d638120 +38a000383c9ff000 +788400207f23cb78 +6000000048000d41 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -6000000048000d09 -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +6000000048000cf9 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,45 +742,45 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -3d20c80038429cb4 +3d20c80038429c8c 7929002061290800 7d404e2a7c0004ac 4d820020280a000e -3940000e7c0802a6 -f821ffa1f8010010 +f80100107c0802a6 +3940000ef821ffa1 7d404f2a7c0004ac -38637e103c62ffff -600000004bfff8b5 +38637e403c62ffff +600000004bfff88d e801001038210060 4e8000207c0803a6 0100000000000000 3c4c000100000080 -3d20c80038429c4c +3d20c80038429c24 7929002061290800 7d404e2a7c0004ac 4d820020280a0001 -394000017c0802a6 -f821ffa1f8010010 +f80100107c0802a6 +39400001f821ffa1 7d404f2a7c0004ac -38637e383c62ffff -600000004bfff84d +38637e683c62ffff +600000004bfff825 e801001038210060 4e8000207c0803a6 0100000000000000 3c4c000100000080 -7c0802a638429be4 -3c8040003c62ffff -4800167d38637e60 -3f60c800f821ff71 -7b7b00203be00000 -600000004bfff7fd +7c0802a638429bbc +f821ff7148001691 +3f60c8003c804000 +3c62ffff3be00000 +38637e907b7b0020 +600000004bfff7d5 7c0004ac4bffff05 3f40c8007fe0df2a 7b5a0020635a0004 @@ -816,12 +821,12 @@ e801001038210060 386000c84bfffd65 4bfffe394bfffd99 3c60400038800400 -60000000480006e9 +60000000480006e1 408200242c030000 7c0004ac7c691b78 7c0004ac7f80d72a 382100907f80df2a -480015447d2307b4 +4800154c7d2307b4 38a0000038c00000 3c60400038800400 6000000048000471 @@ -829,43 +834,43 @@ e801001038210060 4bffffd039200001 0100000000000000 3c4c000100000680 -7c0802a638429a0c -f8010010282303ff -41810028f821ffa1 +7c0802a6384299e4 +f821ffa1f8010010 +41810028282303ff 3c62ffff7c641b78 -4bfff62938637e80 +4bfff60138637eb0 3821006060000000 7c0803a6e8010010 3d2000104e800020 408000287c234840 39200066786505a0 -7864b2827ca54b92 -38637e883c62ffff -600000004bfff5ed +3c62ffff7864b282 +38637eb87ca54b92 +600000004bfff5c5 3d2040004bffffc4 7c23484078646502 7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637e987ca92b92 +38a0006678895564 +3c62ffff7d291850 +38637ec87ca92b92 786317824bffffc8 7865556439200066 7c641b787ca52050 7ca54b923c62ffff -4bffffa438637ea8 +4bffffa438637ed8 0100000000000000 3c4c000100000080 -7c0802a63842993c -7cc42a14fbe1fff8 +7c0802a638429914 +f8010010fbe1fff8 +7cc42a14f821ff91 7c8523787cbf2b78 3c62ffff7c641b78 -38637eb878c60020 -f821ff91f8010010 -600000004bfff54d +38637ee878c60020 +600000004bfff525 4bfffef97fe3fb78 -38637ec83c62ffff -600000004bfff535 -4800140c38210070 +38637ef83c62ffff +600000004bfff50d +4800141438210070 0100000000000000 2c24000000000180 7869f84241820024 @@ -875,30 +880,30 @@ f821ff91f8010010 386300014e800020 000000004bfffff4 0000000000000000 -384298983c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001335614aaaaa -7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bfff509 +384298703c4c0001 +4800134d7c0802a6 +3d40aaaaf821ffc1 +7c7f1b7878840764 +7c691b787c7d1b78 +7f832214614aaaaa +390400017884f082 +420000807d0903a6 +600000004bfff4e9 3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 +3bc000007feafb78 +6108aaaa7929f082 +7d2903a639290001 7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 +7feafb783d005555 +610855557929f082 +7d2903a639290001 7fffe05042000058 -600000004bfff4b9 -3d2055557bfff082 -61295555395f0001 +600000004bfff499 +7bfff0823d205555 +395f000161295555 420000407d4903a6 7fc307b438210040 -91490000480012e8 +91490000480012f0 4bffff7839290004 7c094000812a0000 3bde000141820008 @@ -909,36 +914,36 @@ f821ff91f8010010 3bbd00043bde0001 000000004bffffac 0000048001000000 -384297883c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff414800120d +384297603c4c0001 +7d6000267c0802a6 +916100084800121d +2e260000f821ff41 7cba2b787c7f1b78 789cf0827cde3378 81260004419200c0 2c09000082e60000 3f02ffff40820044 3b6000013ba00000 -3b187ed07bf90020 +3b187f007bf90020 4082009c7c3ce840 7b8510283c62ffff -7be4002038637ed0 +38637f007be40020 3c62ffff4bfffde5 -4bfff35138637bd0 -4bfff3b560000000 -2d97000060000000 -3ba000007ffbfb78 -3b2000003ac00001 +4bfff32938637c00 +4bfff39560000000 +7ffbfb7860000000 +3ac000013ba00000 +2d9700003b200000 7c3de0407bf50020 408200847fb8eb78 418200282c170000 7b0510283c62ffff -7be4002038637ee0 +38637f107be40020 3c62ffff4bfffd8d -4bfff2f938637bd0 +4bfff2d138637c00 382100c060000000 816100087f2307b4 -480011887d618120 +480011907d618120 4bffff503ae00001 7f44d3787b630020 7ba917644bfffdb5 @@ -953,156 +958,154 @@ f821ff414800120d 4182003c7c032040 419200343b390001 2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 +e8de001041820028 +788400207d8903a6 +f84100187b630020 e84100184e800421 4082ff582c030000 4082001c73187fff 3c62ffff418e0018 7ea4ab787ba51028 -4bfffcb138637ee0 +4bfffcb138637f10 3b7b00043bbd0001 000000004bfffef4 00000b8003000000 -384295c83c4c0001 -7c0802a67d708026 -4800106591610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 -7c9e23787c7f1b78 -7c641b787fa3ea14 -38637ef03c62ffff -4bfff1c97cbc2b78 +384295a03c4c0001 +7d7080267c0802a6 +4800106d91610008 +3ba4ffe0f821ff71 +7c7f1b787cdb3378 +7c641b787c9e2378 +7fa3ea147cbc2b78 +2e3b00003c62ffff +4bfff1a138637f20 3c62ffff60000000 -4092000c38637f08 -38637f183c62ffff -600000004bfff1ad +4092000c38637f38 +38637f483c62ffff +600000004bfff185 4bfffb597fc3f378 -38637f283c62ffff -600000004bfff195 +38637f583c62ffff +600000004bfff16d 408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 +7d3fe8507cf602a6 +38bd002038df0020 3900ffff7feafb78 -4081000839290001 -2c29000139200001 +7c2628407929d942 +3929000138c00001 +2c2900017d26485e 3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 +394a0020f90a0008 +f90afff8f90afff0 7d3602a64082ffe4 78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 -38637f303c62ffff -4bfff1117f9c4b92 +3c62ffff79290020 +7d295050639ce100 +7f9ee1d238637f60 +4bfff0e97f9c4b92 7f83e37860000000 3c62ffff4bfffabd -4bfff0f938637f40 +4bfff0d138637f70 3c62ffff60000000 -4bfff0e938637bd0 -4bfff14d60000000 +4bfff0c138637c00 +4bfff12d60000000 7f9602a660000000 7d3fe85040920048 3bbd0020395f0020 7c2ae8407929d942 -4081000839290001 -2c29000139200001 +3929000139400001 +2c2900017d2a485e 3929ffffe95f0000 e95f0010e95f0008 3bff0020e95f0018 4800001c4082ffe4 394000007bdbe8c2 -3ba000007f7adb78 +7f7adb783ba00000 4082006c7c1dd000 3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f48 -600000004bfff04d -4bfff9f97fc3f378 -38637f403c62ffff -600000004bfff035 -38637bd03c62ffff +792900207b9c0020 +614ae1003c62ffff +38637f787d29e050 +7fde4b927fde51d2 600000004bfff025 +4bfff9f97fc3f378 +38637f703c62ffff +600000004bfff00d +38637c003c62ffff +600000004bffeffd 8161000838210090 -48000ecc7d708120 +48000ed47d708120 794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 +4bfffae93bbd0001 +7c6a1b787d23da16 7d3f482a79291f48 -000000004bffff68 +000000004bffff70 0000068003000000 -384293903c4c0001 -282402007c0802a6 -f821ff8148000e39 -7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f587fc4f378 -600000004bffef9d -4bfff9497fe3fb78 -38637f283c62ffff -600000004bffef85 -7fc3f3787f84e378 -38c000004bfffaa1 -7fe4fb7838a00001 -7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff4182007c -7fa4eb787b85f882 -4bffef3938637f68 -283f008060000000 -408100087fe5fb78 -3c62ffff38a00080 -3880000078a5f082 -4bffef1138637f80 +384293703c4c0001 +48000e4d7c0802a6 +3b800200f821ff81 +7c7e1b7828240200 +7f9c205e7c9f2378 +3c62ffff7c641b78 +4bffef8138637f88 +7fe3fb7860000000 +3c62ffff4bfff955 +4bffef6938637f58 +7f84e37860000000 +4bfffaad7fc3f378 +38a0000138c00000 +7c7d1b787fe4fb78 +4bfffba57fc3f378 +2c0900007d23ea14 +7c7e1b784182007c +7b85f8823c62ffff +38637f987fa4eb78 +600000004bffef1d +38a00080283f0080 +388000003c62ffff +38637fb07ca5f85e +4bffeef978a5f082 3c62ffff60000000 7fc4f3787be5f082 -4bffeef938637f98 +4bffeee138637fc8 3c62ffff60000000 -4bffeee938637fb0 +4bffeed138637fe0 3860000060000000 7c6307b438210080 -3c62ffff48000d98 -4bffeec938637fc0 +3c62ffff48000db0 +4bffeeb138637ff0 3860000160000000 000000004bffffe0 0000048001000000 -384292683c4c0001 -8922804060000000 -3942803860000000 +384292503c4c0001 +6000000060000000 +3942806889228070 418200302c090000 39290014e92a0000 7d204eaa7c0004ac 4182ffec71290020 -e922803860000000 +e922806860000000 7c604faa7c0004ac e92a00004e800020 7c0004ac39290010 712900087d204eea -5469063e4082ffec -e942803860000000 +600000004082ffec +e94280685469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -384291e03c4c0001 -fbe1fff87c0802a6 -3be3fffffbc1fff0 -f821ffd1f8010010 +384291c83c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 2c1e00008fdf0001 3821003040820010 -48000cd038600000 +48000ce838600000 4082000c2c1e000a 4bffff3d3860000d 4bffff357fc307b4 000000004bffffd0 0000028001000000 -384291803c4c0001 +384291683c4c0001 612900203d20c000 7c0004ac79290020 3d40c0007d204eea @@ -1111,9 +1114,9 @@ f821ffd1f8010010 714a00207d4056ea 614a20003d40c000 40820040794a0020 -f942803860000000 +f942806860000000 6000000039400000 -3d40001c99428040 +3d40001c99428070 7d295392614a2000 614a20183d40c000 3929ffff794a0020 @@ -1121,23 +1124,23 @@ f942803860000000 3d00c0004e800020 7908002061080040 7d0046ea7c0004ac -60000000790807e3 -3d40001cf9428038 +790807e360000000 +3d40001cf9428068 7d495392614a2000 600000004182ffa0 -9922804039200001 -6108200c3d00c000 -790800203920ff80 +9922807039200001 +3920ff803d00c000 +790800206108200c 7d2047aa7c0004ac -7c0004ace9228038 -e92280387d404faa +7c0004ace9228068 +e92280687d404faa 39290004794ac202 7d404faa7c0004ac -39400003e9228038 +39400003e9228068 7c0004ac3929000c -e92280387d404faa +e92280687d404faa 7c0004ac39290010 -e92280387d404faa +e92280687d404faa 3929000839400007 7d404faa7c0004ac 000000004e800020 @@ -1146,8 +1149,8 @@ e92280387d404faa 7d2903a639290001 78a9072442000028 3905000178a50760 -7d0903a67d434a14 -392000007c844a14 +7c844a147d434a14 +7d0903a639200000 4e80002042000018 7d23512a7d24502a 4bffffcc394a0008 @@ -1181,310 +1184,313 @@ f924000039290001 38a0000a2c0a0030 8949000140820010 4182ffb82c0a0078 -4800004838600000 +4800004438600000 4082fff42c050010 4bffffec38a00010 54e7063e38eaffd0 -4181003c28070009 +4181003828070009 7d2a07343929ffd0 4c8000207c0a2800 -7c6519d239080001 -f90400007d290734 -e90400007c691a14 -714900ff89480000 -4e8000204082ffc0 -54e7063e38eaff9f -4181000c28070019 -4bffffb83929ffa9 -554a063e394affbf -4d810020280a0019 -4bffffa03929ffc9 -0000000000000000 -3923ff9f00000000 -4181000828090019 -7c6307b43863ffe0 -000000004e800020 +390800017d290734 +f904000010651a73 +89480000e9040000 +4082ffc4714900ff +38eaff9f4e800020 +2807001954e7063e +3929ffa94181000c +394affbf4bffffbc +280a0019554a063e +3929ffc94d810020 +000000004bffffa4 +0000000000000000 +280900193923ff9f +3863ffe041810008 +4e8000207c6307b4 0000000000000000 -38428e483c4c0001 -480008e97c0802a6 -7c7e1b78f821ffa1 -7ca32b787cfd3b78 -38a0000a7c9c2378 -eb3e000038800000 +3c4c000100000000 +7c0802a638428e34 +f821ffa148000905 +7cfd3b787c7e1b78 +7c9c23787ca32b78 +3880000038a0000a 7d1b43787cdf3378 -4bfffe597d3a4b78 -2b9d001060000000 -2c3f000039400000 -2c0a00004082005c -3940000140820008 -7c0350007d4ad214 -7d2350504081003c -792900207d2948f8 -7d2903a639290001 -7d594850e93e0000 -408000187c2ae040 -e93e00009b690000 -f93e000039290001 -382100604200ffe0 -409e00104800089c -394a00017bffe102 -7fffeb924bffff94 -000000004bfffff4 -0000078001000000 -38428d783c4c0001 -480008217c0802a6 -eb630000f821ffb1 -7c9c23787c7f1b78 -3bc000007cbd2b78 -4bfffd717fa3eb78 -7c3e184060000000 -e93f000040800014 -7c2ae0407d5b4850 -382100504180000c -7d5df0ae4800082c -994900003bde0001 -39290001e93f0000 -4bffffbcf93f0000 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 +4082005c2c3f0000 +408200082c0a0000 +7d4ad21439400001 +4081003c7c035000 +7d2948f87d235050 +3929000179290020 +e93e00007d2903a6 +7c2ae0407d594850 +9b69000040800018 +39290001e93e0000 +4200ffe0f93e0000 +480008b838210060 +7bffe102409e0010 +4bffff94394a0001 +4bfffff47fffeb92 0100000000000000 -3c4c000100000580 -7c0802a638428cfc -e9297fd03d22ffff -7d7080262b860010 -916100087caa2b78 -f821ffa148000789 -7cbe2b787c7c1b78 -3be000007cdd3378 -3d22fffff9210020 -f9210028e9297fd8 -408200342c2a0000 -408200082c1f0000 -7fff07b43be00001 -7c3f20402e270000 -408100303b7fffff -8161000838210060 -4800077c7d708120 -794ae102409e0010 -4bffffbc3bff0001 -4bfffff47d4aeb92 -7f5eeb927f5ed378 -7d29f0507d3ae9d2 -886900207d214a14 -5463063e41920010 -600000004bfffdd5 -e93c00007c3df040 -3b7bffff7c69d9ae -e93c00004081ffc8 +3c4c000100000780 +7c0802a638428d64 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 +408000147c3e1840 +7d5b4850e93f0000 +4180000c7c2ae040 +4800084838210050 +3bde00017d5df0ae +e93f000099490000 +f93f000039290001 +000000004bffffbc +0000058001000000 +38428ce83c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 +7cdd33787cbe2b78 +2b8600107caa2b78 +f9210020e9228000 +e922800860000000 +2c2a0000f9210028 +2c1f000040820034 +3be0000140820008 +2e2700007fff07b4 +3b7fffff7c3f2040 +3821006040810030 +7d70812081610008 +409e00104800079c +3bff0001794ae102 +7d4aeb924bffffbc +7d3e4b784bfffff4 +7d214a147d3eea12 +4192001088690020 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc f93c00007d29fa14 -000000004bffff90 -0000068003000000 -38428c083c4c0001 -4800067d7c0802a6 -7c7d1b79f821ff01 +000000004bffff94 +0000058003000000 +38428bf83c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 38600000f8610060 2c24000041820014 3b6100403bc4ffff -382101004082013c -4800069c7c6307b4 +3821011040820144 +480006bc7c6307b4 390500012c0a0025 -38e0000040820620 +38e0000040820640 894500007cbc2b78 38a500017ce93b78 7d47d9ae889c0001 5488063e39470001 -418201cc2c080064 +418201dc2c080064 4181002c28080078 4181002c28080068 -418201302c080058 +418201382c080058 4181008828080058 -418200c02c080025 -418201182c08004f +418200c82c080025 +418201202c08004f 4bffffa438e70001 550b063e3904ff97 4181ffec280b000f -396b74d43d62ffff -7d0b42aa790815a8 +790815a83d62ffff +7d0b42aa396b74e4 7d0903a67d085a14 -000001644e800420 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -0000006cffffffcc -ffffffcc000000cc -000000b8ffffffcc +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc 00000048ffffffcc ffffffccffffffcc -2c08006300000150 -390100204bffff84 -7d4852147d4a07b4 -3929000239000075 -39410020990a0020 -480000947d2907b4 -7d4a07b439010020 -3900006f7d485214 -393f00014bffffdc +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 +7d2907b439290002 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 f9210060991f0000 8925000038bc0002 712a00ffebe10060 4182000c7c7df850 -4180febc7c23f040 +4180feb47c23f040 993f000039200000 -390100204bfffea4 -7d4852147d4a07b4 -4bffff9039000073 -7d4a07b439010020 -390000707d485214 -38e100204bffff7c -7d4752147d4a07b4 -7d2907b439290002 -7cea3b78990a0020 -394000007d2a4a14 -3a4600087f23f050 -3a60003099490020 -892100413ac10042 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 712900fd3929ffd2 -40820458eb060000 -3e02ffff5669063e -3aa000043a800000 -3ae00000f9210068 -3a107ff03a200000 -39010020480001a4 -7d4852147d4a07b4 -4bfffef839000078 -7d4a07b439010020 -392900027d485214 -988a00207d2907b4 -4bffff7c7d0a4378 -38f600012c08004f -3949ffa8418201dc -280600225546063e -3cc2ffff418103b8 -794a15a838c67690 -7d4a32147d4652aa -4e8004207d4903a6 -0000039800000158 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000026800000398 -000003980000008c -0000039800000398 -0000008c0000037c -0000039800000398 -0000039800000364 -000001ac00000398 -0000039800000204 -000002ac00000398 -0000008c00000398 -0000039800000398 -000003980000015c -2c080075000003bc -7d214a147ae90020 -7f1ac37839400000 -4182004499490020 -3920000156aa1838 -7d295036394affff -4182002c7f094839 -3d42ffff3920002d -7f5800d0394a7ff0 -392e0001992e0000 -7aa91e68f9210060 -7f5a48387d2a482a -38e0000ae8810060 -38a100207f46d378 -5668063e39200000 -7c9f205038610060 -4bfffa257c84c850 -7a8707e0e8810060 -7f45d37838c0000a -7c84c8507c9f2050 -4bfffb5138610060 -893600003ad60001 -712800ffe9c10060 -7f5f705041820010 -4181fe7c7c39d040 -4bfffd7c7e469378 -7ae900203a800001 -38e00010e9010068 -7c9ac8507d214a14 -3861006038a10020 -7aa91e689a290020 -392000007dd0482a -7dc673787f0e7038 -e88100604bfff9a1 -38c000107a8707e0 -7dc573787c9f2050 -7ae900204bffff7c -7d214a1439400000 -7c9ac85038e00008 -994900205668063e -7aa91e683d42ffff -38a10020394a7ff0 -7dca482a38610060 -7f0e703839200000 -4bfff9457dc67378 -7a8707e0e8810060 -7c9f205038c00008 -7ae900204bffffa4 -7d214a1439400000 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028020 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a76a4 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 +3920002d4182002c +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028020 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028020 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 7f06c37838e00010 -9949002039000020 -3920000238a10020 -386100607c9ac850 -e88100604bfff901 -386100603ca2ffff -7c9f205038a57fe8 -4bfff9b57c84c850 -7a8707e0e8810060 -7f05c37838c00010 -4bfffec07c9f2050 -394000007ae90020 -390000207d214a14 -38c0000138e0000a -38a1002099490020 -7c9ac85039200000 -4bfff89d38610060 -9b090000e9210060 -f921006039290001 -7ae900204bfffe88 -7d214a1439400000 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 +60000000e8810060 +38a280187de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d +392900019b090000 +4bfffec8f9210060 +38e000007ae90020 3880000038a0000a -9949002038610020 -600000004bfff6f5 -7f03c3787c6f1b78 -600000004bfff6bd -408100647c2f1840 -7f5ac8507d0ef850 -7c6378507d08ca14 -7c6e1a142c280000 -38e0002039400000 -408200083b5a0001 -2c3a00013b400001 -408200143b5affff -41820024714a0001 -4800001cf9c10060 -39ce000198ee0000 -7c23704039400001 -f86100604082ffd4 -7f05c378e8810060 -7c9f205038610060 -4bfff8a57c84c850 -893600014bfffdd0 -2c09006c3aa00008 -7cf63b784082fdc0 -893600014bfffdb8 -2c0900683aa00002 -7cf63b784082fda8 -4bfffd9c3aa00001 +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 +386100607f05c378 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e 554a063e3949ffd0 -4181fd8c280a0009 +4181fdc8280a0009 3af700017aea0020 992a00207d415214 -3aa000084bfffd78 -3a6000204bfffd70 -4bfffba43ac10041 +3a8000204bfffdb4 +4bfffb883b210041 3bff0001993f0000 fbe100607d054378 -000000004bfffaf4 +000000004bfffadc 0000128001000000 f9e1ff78f9c1ff70 fa21ff88fa01ff80 @@ -1559,15 +1565,15 @@ ebe1fff8e8010010 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v index f7462d1..71c1017 100644 --- a/litedram/generated/sim/litedram_core.v +++ b/litedram/generated/sim/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:07:04 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:27 //------------------------------------------------------------------------------ @@ -18,34 +18,34 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire sim_trace, - input wire clk, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire sim_trace, + input wire clk, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -53,1887 +53,1983 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -wire sys_clk; -wire sys_rst; -wire por_clk; -reg soc_int_rst = 1'd1; -wire [13:0] soc_ddrphy_dfi_p0_address; -wire [2:0] soc_ddrphy_dfi_p0_bank; -wire soc_ddrphy_dfi_p0_cas_n; -wire soc_ddrphy_dfi_p0_cs_n; -wire soc_ddrphy_dfi_p0_ras_n; -wire soc_ddrphy_dfi_p0_we_n; -wire soc_ddrphy_dfi_p0_cke; -wire soc_ddrphy_dfi_p0_odt; -wire soc_ddrphy_dfi_p0_reset_n; -wire soc_ddrphy_dfi_p0_act_n; -wire [31:0] soc_ddrphy_dfi_p0_wrdata; -wire soc_ddrphy_dfi_p0_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; -wire soc_ddrphy_dfi_p0_rddata_en; -wire [31:0] soc_ddrphy_dfi_p0_rddata; -wire soc_ddrphy_dfi_p0_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p1_address; -wire [2:0] soc_ddrphy_dfi_p1_bank; -wire soc_ddrphy_dfi_p1_cas_n; -wire soc_ddrphy_dfi_p1_cs_n; -wire soc_ddrphy_dfi_p1_ras_n; -wire soc_ddrphy_dfi_p1_we_n; -wire soc_ddrphy_dfi_p1_cke; -wire soc_ddrphy_dfi_p1_odt; -wire soc_ddrphy_dfi_p1_reset_n; -wire soc_ddrphy_dfi_p1_act_n; -wire [31:0] soc_ddrphy_dfi_p1_wrdata; -wire soc_ddrphy_dfi_p1_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; -wire soc_ddrphy_dfi_p1_rddata_en; -wire [31:0] soc_ddrphy_dfi_p1_rddata; -wire soc_ddrphy_dfi_p1_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p2_address; -wire [2:0] soc_ddrphy_dfi_p2_bank; -wire soc_ddrphy_dfi_p2_cas_n; -wire soc_ddrphy_dfi_p2_cs_n; -wire soc_ddrphy_dfi_p2_ras_n; -wire soc_ddrphy_dfi_p2_we_n; -wire soc_ddrphy_dfi_p2_cke; -wire soc_ddrphy_dfi_p2_odt; -wire soc_ddrphy_dfi_p2_reset_n; -wire soc_ddrphy_dfi_p2_act_n; -wire [31:0] soc_ddrphy_dfi_p2_wrdata; -wire soc_ddrphy_dfi_p2_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; -wire soc_ddrphy_dfi_p2_rddata_en; -wire [31:0] soc_ddrphy_dfi_p2_rddata; -wire soc_ddrphy_dfi_p2_rddata_valid; -wire [13:0] soc_ddrphy_dfi_p3_address; -wire [2:0] soc_ddrphy_dfi_p3_bank; -wire soc_ddrphy_dfi_p3_cas_n; -wire soc_ddrphy_dfi_p3_cs_n; -wire soc_ddrphy_dfi_p3_ras_n; -wire soc_ddrphy_dfi_p3_we_n; -wire soc_ddrphy_dfi_p3_cke; -wire soc_ddrphy_dfi_p3_odt; -wire soc_ddrphy_dfi_p3_reset_n; -wire soc_ddrphy_dfi_p3_act_n; -wire [31:0] soc_ddrphy_dfi_p3_wrdata; -wire soc_ddrphy_dfi_p3_wrdata_en; -wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; -wire soc_ddrphy_dfi_p3_rddata_en; -wire [31:0] soc_ddrphy_dfi_p3_rddata; -wire soc_ddrphy_dfi_p3_rddata_valid; -reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel0_write = 1'd0; -reg soc_ddrphy_dfiphasemodel0_read = 1'd0; -reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel1_write = 1'd0; -reg soc_ddrphy_dfiphasemodel1_read = 1'd0; -reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel2_write = 1'd0; -reg soc_ddrphy_dfiphasemodel2_read = 1'd0; -reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; -reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; -reg soc_ddrphy_dfiphasemodel3_write = 1'd0; -reg soc_ddrphy_dfiphasemodel3_read = 1'd0; -reg soc_ddrphy_bankmodel0_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; -reg soc_ddrphy_bankmodel0_precharge = 1'd0; -wire soc_ddrphy_bankmodel0_write; -wire [9:0] soc_ddrphy_bankmodel0_write_col; -wire [127:0] soc_ddrphy_bankmodel0_write_data; -wire [15:0] soc_ddrphy_bankmodel0_write_mask; -reg soc_ddrphy_bankmodel0_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; -reg soc_ddrphy_bankmodel0_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel0_wraddr; -wire [20:0] soc_ddrphy_bankmodel0_rdaddr; -reg soc_ddrphy_bankmodel1_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; -reg soc_ddrphy_bankmodel1_precharge = 1'd0; -wire soc_ddrphy_bankmodel1_write; -wire [9:0] soc_ddrphy_bankmodel1_write_col; -wire [127:0] soc_ddrphy_bankmodel1_write_data; -wire [15:0] soc_ddrphy_bankmodel1_write_mask; -reg soc_ddrphy_bankmodel1_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; -reg soc_ddrphy_bankmodel1_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel1_wraddr; -wire [20:0] soc_ddrphy_bankmodel1_rdaddr; -reg soc_ddrphy_bankmodel2_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; -reg soc_ddrphy_bankmodel2_precharge = 1'd0; -wire soc_ddrphy_bankmodel2_write; -wire [9:0] soc_ddrphy_bankmodel2_write_col; -wire [127:0] soc_ddrphy_bankmodel2_write_data; -wire [15:0] soc_ddrphy_bankmodel2_write_mask; -reg soc_ddrphy_bankmodel2_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; -reg soc_ddrphy_bankmodel2_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel2_wraddr; -wire [20:0] soc_ddrphy_bankmodel2_rdaddr; -reg soc_ddrphy_bankmodel3_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; -reg soc_ddrphy_bankmodel3_precharge = 1'd0; -wire soc_ddrphy_bankmodel3_write; -wire [9:0] soc_ddrphy_bankmodel3_write_col; -wire [127:0] soc_ddrphy_bankmodel3_write_data; -wire [15:0] soc_ddrphy_bankmodel3_write_mask; -reg soc_ddrphy_bankmodel3_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; -reg soc_ddrphy_bankmodel3_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel3_wraddr; -wire [20:0] soc_ddrphy_bankmodel3_rdaddr; -reg soc_ddrphy_bankmodel4_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; -reg soc_ddrphy_bankmodel4_precharge = 1'd0; -wire soc_ddrphy_bankmodel4_write; -wire [9:0] soc_ddrphy_bankmodel4_write_col; -wire [127:0] soc_ddrphy_bankmodel4_write_data; -wire [15:0] soc_ddrphy_bankmodel4_write_mask; -reg soc_ddrphy_bankmodel4_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; -reg soc_ddrphy_bankmodel4_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel4_wraddr; -wire [20:0] soc_ddrphy_bankmodel4_rdaddr; -reg soc_ddrphy_bankmodel5_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; -reg soc_ddrphy_bankmodel5_precharge = 1'd0; -wire soc_ddrphy_bankmodel5_write; -wire [9:0] soc_ddrphy_bankmodel5_write_col; -wire [127:0] soc_ddrphy_bankmodel5_write_data; -wire [15:0] soc_ddrphy_bankmodel5_write_mask; -reg soc_ddrphy_bankmodel5_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; -reg soc_ddrphy_bankmodel5_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel5_wraddr; -wire [20:0] soc_ddrphy_bankmodel5_rdaddr; -reg soc_ddrphy_bankmodel6_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; -reg soc_ddrphy_bankmodel6_precharge = 1'd0; -wire soc_ddrphy_bankmodel6_write; -wire [9:0] soc_ddrphy_bankmodel6_write_col; -wire [127:0] soc_ddrphy_bankmodel6_write_data; -wire [15:0] soc_ddrphy_bankmodel6_write_mask; -reg soc_ddrphy_bankmodel6_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; -reg soc_ddrphy_bankmodel6_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel6_wraddr; -wire [20:0] soc_ddrphy_bankmodel6_rdaddr; -reg soc_ddrphy_bankmodel7_activate = 1'd0; -reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; -reg soc_ddrphy_bankmodel7_precharge = 1'd0; -wire soc_ddrphy_bankmodel7_write; -wire [9:0] soc_ddrphy_bankmodel7_write_col; -wire [127:0] soc_ddrphy_bankmodel7_write_data; -wire [15:0] soc_ddrphy_bankmodel7_write_mask; -reg soc_ddrphy_bankmodel7_read = 1'd0; -reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; -reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; -reg soc_ddrphy_bankmodel7_active = 1'd0; -reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; -reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; -reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; -reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; -reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; -wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; -wire [20:0] soc_ddrphy_bankmodel7_wraddr; -wire [20:0] soc_ddrphy_bankmodel7_rdaddr; -reg [3:0] soc_ddrphy_activates0 = 4'd0; -reg [3:0] soc_ddrphy_precharges0 = 4'd0; -reg soc_ddrphy_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_writes0 = 4'd0; -reg soc_ddrphy_new_bank_write0 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; -reg [3:0] soc_ddrphy_reads0 = 4'd0; -reg [3:0] soc_ddrphy_activates1 = 4'd0; -reg [3:0] soc_ddrphy_precharges1 = 4'd0; -reg soc_ddrphy_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_writes1 = 4'd0; -reg soc_ddrphy_new_bank_write1 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; -reg [3:0] soc_ddrphy_reads1 = 4'd0; -reg [3:0] soc_ddrphy_activates2 = 4'd0; -reg [3:0] soc_ddrphy_precharges2 = 4'd0; -reg soc_ddrphy_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_writes2 = 4'd0; -reg soc_ddrphy_new_bank_write2 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; -reg [3:0] soc_ddrphy_reads2 = 4'd0; -reg [3:0] soc_ddrphy_activates3 = 4'd0; -reg [3:0] soc_ddrphy_precharges3 = 4'd0; -reg soc_ddrphy_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_writes3 = 4'd0; -reg soc_ddrphy_new_bank_write3 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; -reg [3:0] soc_ddrphy_reads3 = 4'd0; -reg [3:0] soc_ddrphy_activates4 = 4'd0; -reg [3:0] soc_ddrphy_precharges4 = 4'd0; -reg soc_ddrphy_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_writes4 = 4'd0; -reg soc_ddrphy_new_bank_write4 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; -reg [3:0] soc_ddrphy_reads4 = 4'd0; -reg [3:0] soc_ddrphy_activates5 = 4'd0; -reg [3:0] soc_ddrphy_precharges5 = 4'd0; -reg soc_ddrphy_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_writes5 = 4'd0; -reg soc_ddrphy_new_bank_write5 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; -reg [3:0] soc_ddrphy_reads5 = 4'd0; -reg [3:0] soc_ddrphy_activates6 = 4'd0; -reg [3:0] soc_ddrphy_precharges6 = 4'd0; -reg soc_ddrphy_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_writes6 = 4'd0; -reg soc_ddrphy_new_bank_write6 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; -reg [3:0] soc_ddrphy_reads6 = 4'd0; -reg [3:0] soc_ddrphy_activates7 = 4'd0; -reg [3:0] soc_ddrphy_precharges7 = 4'd0; -reg soc_ddrphy_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_writes7 = 4'd0; -reg soc_ddrphy_new_bank_write7 = 1'd0; -reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; -reg [3:0] soc_ddrphy_reads7 = 4'd0; -wire soc_ddrphy_banks_read; -wire [127:0] soc_ddrphy_banks_read_data; -reg soc_ddrphy_new_banks_read0 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; -reg soc_ddrphy_new_banks_read1 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; -reg soc_ddrphy_new_banks_read2 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; -reg soc_ddrphy_new_banks_read3 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; -reg soc_ddrphy_new_banks_read4 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; -reg soc_ddrphy_new_banks_read5 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; -reg soc_ddrphy_new_banks_read6 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; -reg soc_ddrphy_new_banks_read7 = 1'd0; -reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; -wire [13:0] soc_litedramcore_slave_p0_address; -wire [2:0] soc_litedramcore_slave_p0_bank; -wire soc_litedramcore_slave_p0_cas_n; -wire soc_litedramcore_slave_p0_cs_n; -wire soc_litedramcore_slave_p0_ras_n; -wire soc_litedramcore_slave_p0_we_n; -wire soc_litedramcore_slave_p0_cke; -wire soc_litedramcore_slave_p0_odt; -wire soc_litedramcore_slave_p0_reset_n; -wire soc_litedramcore_slave_p0_act_n; -wire [31:0] soc_litedramcore_slave_p0_wrdata; -wire soc_litedramcore_slave_p0_wrdata_en; -wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; -wire soc_litedramcore_slave_p0_rddata_en; -reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; -reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p1_address; -wire [2:0] soc_litedramcore_slave_p1_bank; -wire soc_litedramcore_slave_p1_cas_n; -wire soc_litedramcore_slave_p1_cs_n; -wire soc_litedramcore_slave_p1_ras_n; -wire soc_litedramcore_slave_p1_we_n; -wire soc_litedramcore_slave_p1_cke; -wire soc_litedramcore_slave_p1_odt; -wire soc_litedramcore_slave_p1_reset_n; -wire soc_litedramcore_slave_p1_act_n; -wire [31:0] soc_litedramcore_slave_p1_wrdata; -wire soc_litedramcore_slave_p1_wrdata_en; -wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; -wire soc_litedramcore_slave_p1_rddata_en; -reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; -reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p2_address; -wire [2:0] soc_litedramcore_slave_p2_bank; -wire soc_litedramcore_slave_p2_cas_n; -wire soc_litedramcore_slave_p2_cs_n; -wire soc_litedramcore_slave_p2_ras_n; -wire soc_litedramcore_slave_p2_we_n; -wire soc_litedramcore_slave_p2_cke; -wire soc_litedramcore_slave_p2_odt; -wire soc_litedramcore_slave_p2_reset_n; -wire soc_litedramcore_slave_p2_act_n; -wire [31:0] soc_litedramcore_slave_p2_wrdata; -wire soc_litedramcore_slave_p2_wrdata_en; -wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; -wire soc_litedramcore_slave_p2_rddata_en; -reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; -reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_slave_p3_address; -wire [2:0] soc_litedramcore_slave_p3_bank; -wire soc_litedramcore_slave_p3_cas_n; -wire soc_litedramcore_slave_p3_cs_n; -wire soc_litedramcore_slave_p3_ras_n; -wire soc_litedramcore_slave_p3_we_n; -wire soc_litedramcore_slave_p3_cke; -wire soc_litedramcore_slave_p3_odt; -wire soc_litedramcore_slave_p3_reset_n; -wire soc_litedramcore_slave_p3_act_n; -wire [31:0] soc_litedramcore_slave_p3_wrdata; -wire soc_litedramcore_slave_p3_wrdata_en; -wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; -wire soc_litedramcore_slave_p3_rddata_en; -reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; -reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_master_p0_address = 14'd0; -reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; -reg soc_litedramcore_master_p0_cas_n = 1'd1; -reg soc_litedramcore_master_p0_cs_n = 1'd1; -reg soc_litedramcore_master_p0_ras_n = 1'd1; -reg soc_litedramcore_master_p0_we_n = 1'd1; -reg soc_litedramcore_master_p0_cke = 1'd0; -reg soc_litedramcore_master_p0_odt = 1'd0; -reg soc_litedramcore_master_p0_reset_n = 1'd0; -reg soc_litedramcore_master_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; -reg soc_litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p0_rddata; -wire soc_litedramcore_master_p0_rddata_valid; -reg [13:0] soc_litedramcore_master_p1_address = 14'd0; -reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; -reg soc_litedramcore_master_p1_cas_n = 1'd1; -reg soc_litedramcore_master_p1_cs_n = 1'd1; -reg soc_litedramcore_master_p1_ras_n = 1'd1; -reg soc_litedramcore_master_p1_we_n = 1'd1; -reg soc_litedramcore_master_p1_cke = 1'd0; -reg soc_litedramcore_master_p1_odt = 1'd0; -reg soc_litedramcore_master_p1_reset_n = 1'd0; -reg soc_litedramcore_master_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; -reg soc_litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p1_rddata; -wire soc_litedramcore_master_p1_rddata_valid; -reg [13:0] soc_litedramcore_master_p2_address = 14'd0; -reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; -reg soc_litedramcore_master_p2_cas_n = 1'd1; -reg soc_litedramcore_master_p2_cs_n = 1'd1; -reg soc_litedramcore_master_p2_ras_n = 1'd1; -reg soc_litedramcore_master_p2_we_n = 1'd1; -reg soc_litedramcore_master_p2_cke = 1'd0; -reg soc_litedramcore_master_p2_odt = 1'd0; -reg soc_litedramcore_master_p2_reset_n = 1'd0; -reg soc_litedramcore_master_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; -reg soc_litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p2_rddata; -wire soc_litedramcore_master_p2_rddata_valid; -reg [13:0] soc_litedramcore_master_p3_address = 14'd0; -reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; -reg soc_litedramcore_master_p3_cas_n = 1'd1; -reg soc_litedramcore_master_p3_cs_n = 1'd1; -reg soc_litedramcore_master_p3_ras_n = 1'd1; -reg soc_litedramcore_master_p3_we_n = 1'd1; -reg soc_litedramcore_master_p3_cke = 1'd0; -reg soc_litedramcore_master_p3_odt = 1'd0; -reg soc_litedramcore_master_p3_reset_n = 1'd0; -reg soc_litedramcore_master_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; -reg soc_litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_master_p3_rddata; -wire soc_litedramcore_master_p3_rddata_valid; -wire [13:0] soc_litedramcore_csr_dfi_p0_address; -wire [2:0] soc_litedramcore_csr_dfi_p0_bank; -reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p0_cke; -wire soc_litedramcore_csr_dfi_p0_odt; -wire soc_litedramcore_csr_dfi_p0_reset_n; -reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata; -wire soc_litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask; -wire soc_litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p1_address; -wire [2:0] soc_litedramcore_csr_dfi_p1_bank; -reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p1_cke; -wire soc_litedramcore_csr_dfi_p1_odt; -wire soc_litedramcore_csr_dfi_p1_reset_n; -reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata; -wire soc_litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask; -wire soc_litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p2_address; -wire [2:0] soc_litedramcore_csr_dfi_p2_bank; -reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p2_cke; -wire soc_litedramcore_csr_dfi_p2_odt; -wire soc_litedramcore_csr_dfi_p2_reset_n; -reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata; -wire soc_litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask; -wire soc_litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] soc_litedramcore_csr_dfi_p3_address; -wire [2:0] soc_litedramcore_csr_dfi_p3_bank; -reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_csr_dfi_p3_cke; -wire soc_litedramcore_csr_dfi_p3_odt; -wire soc_litedramcore_csr_dfi_p3_reset_n; -reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata; -wire soc_litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask; -wire soc_litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; -reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p0_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p0_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p1_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p1_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p2_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p2_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0; -reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1; -reg soc_litedramcore_ext_dfi_p3_cke = 1'd0; -reg soc_litedramcore_ext_dfi_p3_odt = 1'd0; -reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0; -reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg soc_litedramcore_ext_dfi_sel = 1'd0; -wire soc_litedramcore_sel; -wire soc_litedramcore_cke; -wire soc_litedramcore_odt; -wire soc_litedramcore_reset_n; -reg [3:0] soc_litedramcore_storage = 4'd1; -reg soc_litedramcore_re = 1'd0; -wire soc_litedramcore_phaseinjector0_csrfield_cs; -wire soc_litedramcore_phaseinjector0_csrfield_we; -wire soc_litedramcore_phaseinjector0_csrfield_cas; -wire soc_litedramcore_phaseinjector0_csrfield_ras; -wire soc_litedramcore_phaseinjector0_csrfield_wren; -wire soc_litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector0_command_re = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector0_command_issue_r; -reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector0_rddata_we; -reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector1_csrfield_cs; -wire soc_litedramcore_phaseinjector1_csrfield_we; -wire soc_litedramcore_phaseinjector1_csrfield_cas; -wire soc_litedramcore_phaseinjector1_csrfield_ras; -wire soc_litedramcore_phaseinjector1_csrfield_wren; -wire soc_litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector1_command_re = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector1_command_issue_r; -reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector1_rddata_we; -reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector2_csrfield_cs; -wire soc_litedramcore_phaseinjector2_csrfield_we; -wire soc_litedramcore_phaseinjector2_csrfield_cas; -wire soc_litedramcore_phaseinjector2_csrfield_ras; -wire soc_litedramcore_phaseinjector2_csrfield_wren; -wire soc_litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector2_command_re = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector2_command_issue_r; -reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector2_rddata_we; -reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; -wire soc_litedramcore_phaseinjector3_csrfield_cs; -wire soc_litedramcore_phaseinjector3_csrfield_we; -wire soc_litedramcore_phaseinjector3_csrfield_cas; -wire soc_litedramcore_phaseinjector3_csrfield_ras; -wire soc_litedramcore_phaseinjector3_csrfield_wren; -wire soc_litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; -reg soc_litedramcore_phaseinjector3_command_re = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire soc_litedramcore_phaseinjector3_command_issue_r; -reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; -reg soc_litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; -wire soc_litedramcore_phaseinjector3_rddata_we; -reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; -wire soc_litedramcore_interface_bank0_valid; -wire soc_litedramcore_interface_bank0_ready; -wire soc_litedramcore_interface_bank0_we; -wire [20:0] soc_litedramcore_interface_bank0_addr; -wire soc_litedramcore_interface_bank0_lock; -wire soc_litedramcore_interface_bank0_wdata_ready; -wire soc_litedramcore_interface_bank0_rdata_valid; -wire soc_litedramcore_interface_bank1_valid; -wire soc_litedramcore_interface_bank1_ready; -wire soc_litedramcore_interface_bank1_we; -wire [20:0] soc_litedramcore_interface_bank1_addr; -wire soc_litedramcore_interface_bank1_lock; -wire soc_litedramcore_interface_bank1_wdata_ready; -wire soc_litedramcore_interface_bank1_rdata_valid; -wire soc_litedramcore_interface_bank2_valid; -wire soc_litedramcore_interface_bank2_ready; -wire soc_litedramcore_interface_bank2_we; -wire [20:0] soc_litedramcore_interface_bank2_addr; -wire soc_litedramcore_interface_bank2_lock; -wire soc_litedramcore_interface_bank2_wdata_ready; -wire soc_litedramcore_interface_bank2_rdata_valid; -wire soc_litedramcore_interface_bank3_valid; -wire soc_litedramcore_interface_bank3_ready; -wire soc_litedramcore_interface_bank3_we; -wire [20:0] soc_litedramcore_interface_bank3_addr; -wire soc_litedramcore_interface_bank3_lock; -wire soc_litedramcore_interface_bank3_wdata_ready; -wire soc_litedramcore_interface_bank3_rdata_valid; -wire soc_litedramcore_interface_bank4_valid; -wire soc_litedramcore_interface_bank4_ready; -wire soc_litedramcore_interface_bank4_we; -wire [20:0] soc_litedramcore_interface_bank4_addr; -wire soc_litedramcore_interface_bank4_lock; -wire soc_litedramcore_interface_bank4_wdata_ready; -wire soc_litedramcore_interface_bank4_rdata_valid; -wire soc_litedramcore_interface_bank5_valid; -wire soc_litedramcore_interface_bank5_ready; -wire soc_litedramcore_interface_bank5_we; -wire [20:0] soc_litedramcore_interface_bank5_addr; -wire soc_litedramcore_interface_bank5_lock; -wire soc_litedramcore_interface_bank5_wdata_ready; -wire soc_litedramcore_interface_bank5_rdata_valid; -wire soc_litedramcore_interface_bank6_valid; -wire soc_litedramcore_interface_bank6_ready; -wire soc_litedramcore_interface_bank6_we; -wire [20:0] soc_litedramcore_interface_bank6_addr; -wire soc_litedramcore_interface_bank6_lock; -wire soc_litedramcore_interface_bank6_wdata_ready; -wire soc_litedramcore_interface_bank6_rdata_valid; -wire soc_litedramcore_interface_bank7_valid; -wire soc_litedramcore_interface_bank7_ready; -wire soc_litedramcore_interface_bank7_we; -wire [20:0] soc_litedramcore_interface_bank7_addr; -wire soc_litedramcore_interface_bank7_lock; -wire soc_litedramcore_interface_bank7_wdata_ready; -wire soc_litedramcore_interface_bank7_rdata_valid; -reg [127:0] soc_litedramcore_interface_wdata = 128'd0; -reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; -wire [127:0] soc_litedramcore_interface_rdata; -reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; -reg soc_litedramcore_dfi_p0_cas_n = 1'd1; -reg soc_litedramcore_dfi_p0_cs_n = 1'd1; -reg soc_litedramcore_dfi_p0_ras_n = 1'd1; -reg soc_litedramcore_dfi_p0_we_n = 1'd1; -wire soc_litedramcore_dfi_p0_cke; -wire soc_litedramcore_dfi_p0_odt; -wire soc_litedramcore_dfi_p0_reset_n; -reg soc_litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p0_wrdata; -reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; -reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p0_rddata; -wire soc_litedramcore_dfi_p0_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; -reg soc_litedramcore_dfi_p1_cas_n = 1'd1; -reg soc_litedramcore_dfi_p1_cs_n = 1'd1; -reg soc_litedramcore_dfi_p1_ras_n = 1'd1; -reg soc_litedramcore_dfi_p1_we_n = 1'd1; -wire soc_litedramcore_dfi_p1_cke; -wire soc_litedramcore_dfi_p1_odt; -wire soc_litedramcore_dfi_p1_reset_n; -reg soc_litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p1_wrdata; -reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; -reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p1_rddata; -wire soc_litedramcore_dfi_p1_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; -reg soc_litedramcore_dfi_p2_cas_n = 1'd1; -reg soc_litedramcore_dfi_p2_cs_n = 1'd1; -reg soc_litedramcore_dfi_p2_ras_n = 1'd1; -reg soc_litedramcore_dfi_p2_we_n = 1'd1; -wire soc_litedramcore_dfi_p2_cke; -wire soc_litedramcore_dfi_p2_odt; -wire soc_litedramcore_dfi_p2_reset_n; -reg soc_litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p2_wrdata; -reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; -reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p2_rddata; -wire soc_litedramcore_dfi_p2_rddata_valid; -reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; -reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; -reg soc_litedramcore_dfi_p3_cas_n = 1'd1; -reg soc_litedramcore_dfi_p3_cs_n = 1'd1; -reg soc_litedramcore_dfi_p3_ras_n = 1'd1; -reg soc_litedramcore_dfi_p3_we_n = 1'd1; -wire soc_litedramcore_dfi_p3_cke; -wire soc_litedramcore_dfi_p3_odt; -wire soc_litedramcore_dfi_p3_reset_n; -reg soc_litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] soc_litedramcore_dfi_p3_wrdata; -reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; -reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] soc_litedramcore_dfi_p3_rddata; -wire soc_litedramcore_dfi_p3_rddata_valid; -reg soc_litedramcore_cmd_valid = 1'd0; -reg soc_litedramcore_cmd_ready = 1'd0; -reg soc_litedramcore_cmd_last = 1'd0; -reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; -reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; -reg soc_litedramcore_cmd_payload_cas = 1'd0; -reg soc_litedramcore_cmd_payload_ras = 1'd0; -reg soc_litedramcore_cmd_payload_we = 1'd0; -reg soc_litedramcore_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_cmd_payload_is_write = 1'd0; -wire soc_litedramcore_wants_refresh; -wire soc_litedramcore_wants_zqcs; -wire soc_litedramcore_timer_wait; -wire soc_litedramcore_timer_done0; -wire [9:0] soc_litedramcore_timer_count0; -wire soc_litedramcore_timer_done1; -reg [9:0] soc_litedramcore_timer_count1 = 10'd781; -wire soc_litedramcore_postponer_req_i; -reg soc_litedramcore_postponer_req_o = 1'd0; -reg soc_litedramcore_postponer_count = 1'd0; -reg soc_litedramcore_sequencer_start0 = 1'd0; -wire soc_litedramcore_sequencer_done0; -wire soc_litedramcore_sequencer_start1; -reg soc_litedramcore_sequencer_done1 = 1'd0; -reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; -reg soc_litedramcore_sequencer_count = 1'd0; -wire soc_litedramcore_zqcs_timer_wait; -wire soc_litedramcore_zqcs_timer_done0; -wire [26:0] soc_litedramcore_zqcs_timer_count0; -wire soc_litedramcore_zqcs_timer_done1; -reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; -reg soc_litedramcore_zqcs_executer_start = 1'd0; -reg soc_litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; -wire soc_litedramcore_bankmachine0_req_valid; -wire soc_litedramcore_bankmachine0_req_ready; -wire soc_litedramcore_bankmachine0_req_we; -wire [20:0] soc_litedramcore_bankmachine0_req_addr; -wire soc_litedramcore_bankmachine0_req_lock; -reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine0_refresh_req; -reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; -reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; -reg soc_litedramcore_bankmachine0_row_opened = 1'd0; -wire soc_litedramcore_bankmachine0_row_hit; -reg soc_litedramcore_bankmachine0_row_open = 1'd0; -reg soc_litedramcore_bankmachine0_row_close = 1'd0; -reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine0_twtpcon_valid; -reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trccon_valid; -reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine0_trascon_valid; -reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine1_req_valid; -wire soc_litedramcore_bankmachine1_req_ready; -wire soc_litedramcore_bankmachine1_req_we; -wire [20:0] soc_litedramcore_bankmachine1_req_addr; -wire soc_litedramcore_bankmachine1_req_lock; -reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine1_refresh_req; -reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; -reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; -reg soc_litedramcore_bankmachine1_row_opened = 1'd0; -wire soc_litedramcore_bankmachine1_row_hit; -reg soc_litedramcore_bankmachine1_row_open = 1'd0; -reg soc_litedramcore_bankmachine1_row_close = 1'd0; -reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine1_twtpcon_valid; -reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trccon_valid; -reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine1_trascon_valid; -reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine2_req_valid; -wire soc_litedramcore_bankmachine2_req_ready; -wire soc_litedramcore_bankmachine2_req_we; -wire [20:0] soc_litedramcore_bankmachine2_req_addr; -wire soc_litedramcore_bankmachine2_req_lock; -reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine2_refresh_req; -reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; -reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; -reg soc_litedramcore_bankmachine2_row_opened = 1'd0; -wire soc_litedramcore_bankmachine2_row_hit; -reg soc_litedramcore_bankmachine2_row_open = 1'd0; -reg soc_litedramcore_bankmachine2_row_close = 1'd0; -reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine2_twtpcon_valid; -reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trccon_valid; -reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine2_trascon_valid; -reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine3_req_valid; -wire soc_litedramcore_bankmachine3_req_ready; -wire soc_litedramcore_bankmachine3_req_we; -wire [20:0] soc_litedramcore_bankmachine3_req_addr; -wire soc_litedramcore_bankmachine3_req_lock; -reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine3_refresh_req; -reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; -reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; -reg soc_litedramcore_bankmachine3_row_opened = 1'd0; -wire soc_litedramcore_bankmachine3_row_hit; -reg soc_litedramcore_bankmachine3_row_open = 1'd0; -reg soc_litedramcore_bankmachine3_row_close = 1'd0; -reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine3_twtpcon_valid; -reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trccon_valid; -reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine3_trascon_valid; -reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine4_req_valid; -wire soc_litedramcore_bankmachine4_req_ready; -wire soc_litedramcore_bankmachine4_req_we; -wire [20:0] soc_litedramcore_bankmachine4_req_addr; -wire soc_litedramcore_bankmachine4_req_lock; -reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine4_refresh_req; -reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; -reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; -reg soc_litedramcore_bankmachine4_row_opened = 1'd0; -wire soc_litedramcore_bankmachine4_row_hit; -reg soc_litedramcore_bankmachine4_row_open = 1'd0; -reg soc_litedramcore_bankmachine4_row_close = 1'd0; -reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine4_twtpcon_valid; -reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trccon_valid; -reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine4_trascon_valid; -reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine5_req_valid; -wire soc_litedramcore_bankmachine5_req_ready; -wire soc_litedramcore_bankmachine5_req_we; -wire [20:0] soc_litedramcore_bankmachine5_req_addr; -wire soc_litedramcore_bankmachine5_req_lock; -reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine5_refresh_req; -reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; -reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; -reg soc_litedramcore_bankmachine5_row_opened = 1'd0; -wire soc_litedramcore_bankmachine5_row_hit; -reg soc_litedramcore_bankmachine5_row_open = 1'd0; -reg soc_litedramcore_bankmachine5_row_close = 1'd0; -reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine5_twtpcon_valid; -reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trccon_valid; -reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine5_trascon_valid; -reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine6_req_valid; -wire soc_litedramcore_bankmachine6_req_ready; -wire soc_litedramcore_bankmachine6_req_we; -wire [20:0] soc_litedramcore_bankmachine6_req_addr; -wire soc_litedramcore_bankmachine6_req_lock; -reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine6_refresh_req; -reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; -reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; -reg soc_litedramcore_bankmachine6_row_opened = 1'd0; -wire soc_litedramcore_bankmachine6_row_hit; -reg soc_litedramcore_bankmachine6_row_open = 1'd0; -reg soc_litedramcore_bankmachine6_row_close = 1'd0; -reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine6_twtpcon_valid; -reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trccon_valid; -reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine6_trascon_valid; -reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; -wire soc_litedramcore_bankmachine7_req_valid; -wire soc_litedramcore_bankmachine7_req_ready; -wire soc_litedramcore_bankmachine7_req_we; -wire [20:0] soc_litedramcore_bankmachine7_req_addr; -wire soc_litedramcore_bankmachine7_req_lock; -reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire soc_litedramcore_bankmachine7_refresh_req; -reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; -reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last; -wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; -reg soc_litedramcore_bankmachine7_row_opened = 1'd0; -wire soc_litedramcore_bankmachine7_row_hit; -reg soc_litedramcore_bankmachine7_row_open = 1'd0; -reg soc_litedramcore_bankmachine7_row_close = 1'd0; -reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire soc_litedramcore_bankmachine7_twtpcon_valid; -reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trccon_valid; -reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; -wire soc_litedramcore_bankmachine7_trascon_valid; -reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; -wire soc_litedramcore_ras_allowed; -wire soc_litedramcore_cas_allowed; -reg soc_litedramcore_choose_cmd_want_reads = 1'd0; -reg soc_litedramcore_choose_cmd_want_writes = 1'd0; -reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; -reg soc_litedramcore_choose_cmd_want_activates = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_valid; -reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; -reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; -wire soc_litedramcore_choose_cmd_cmd_payload_is_read; -wire soc_litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_cmd_request; -reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; -wire soc_litedramcore_choose_cmd_ce; -reg soc_litedramcore_choose_req_want_reads = 1'd0; -reg soc_litedramcore_choose_req_want_writes = 1'd0; -reg soc_litedramcore_choose_req_want_cmds = 1'd0; -reg soc_litedramcore_choose_req_want_activates = 1'd0; -wire soc_litedramcore_choose_req_cmd_valid; -reg soc_litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; -wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; -reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; -wire soc_litedramcore_choose_req_cmd_payload_is_cmd; -wire soc_litedramcore_choose_req_cmd_payload_is_read; -wire soc_litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; -wire [7:0] soc_litedramcore_choose_req_request; -reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; -wire soc_litedramcore_choose_req_ce; -reg [13:0] soc_litedramcore_nop_a = 14'd0; -reg [2:0] soc_litedramcore_nop_ba = 3'd0; -reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; -reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; -reg soc_litedramcore_steerer0 = 1'd1; -reg soc_litedramcore_steerer1 = 1'd1; -reg soc_litedramcore_steerer2 = 1'd1; -reg soc_litedramcore_steerer3 = 1'd1; -reg soc_litedramcore_steerer4 = 1'd1; -reg soc_litedramcore_steerer5 = 1'd1; -reg soc_litedramcore_steerer6 = 1'd1; -reg soc_litedramcore_steerer7 = 1'd1; -wire soc_litedramcore_trrdcon_valid; -reg soc_litedramcore_trrdcon_ready = 1'd0; -reg soc_litedramcore_trrdcon_count = 1'd0; -wire soc_litedramcore_tfawcon_valid; -reg soc_litedramcore_tfawcon_ready = 1'd1; -wire [2:0] soc_litedramcore_tfawcon_count; -reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; -wire soc_litedramcore_tccdcon_valid; -reg soc_litedramcore_tccdcon_ready = 1'd0; -reg soc_litedramcore_tccdcon_count = 1'd0; -wire soc_litedramcore_twtrcon_valid; -reg soc_litedramcore_twtrcon_ready = 1'd0; -reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; -wire soc_litedramcore_read_available; -wire soc_litedramcore_write_available; -reg soc_litedramcore_en0 = 1'd0; -wire soc_litedramcore_max_time0; -reg [4:0] soc_litedramcore_time0 = 5'd0; -reg soc_litedramcore_en1 = 1'd0; -wire soc_litedramcore_max_time1; -reg [3:0] soc_litedramcore_time1 = 4'd0; -wire soc_litedramcore_go_to_refresh; -reg soc_init_done_storage = 1'd0; -reg soc_init_done_re = 1'd0; -reg soc_init_error_storage = 1'd0; -reg soc_init_error_re = 1'd0; -wire [29:0] soc_wb_bus_adr; -wire [31:0] soc_wb_bus_dat_w; -wire [31:0] soc_wb_bus_dat_r; -wire [3:0] soc_wb_bus_sel; -wire soc_wb_bus_cyc; -wire soc_wb_bus_stb; -wire soc_wb_bus_ack; -wire soc_wb_bus_we; -wire [2:0] soc_wb_bus_cti; -wire [1:0] soc_wb_bus_bte; -wire soc_wb_bus_err; -wire soc_user_enable; -wire soc_user_port_cmd_valid; -wire soc_user_port_cmd_ready; -wire soc_user_port_cmd_payload_we; -wire [23:0] soc_user_port_cmd_payload_addr; -wire soc_user_port_wdata_valid; -wire soc_user_port_wdata_ready; -wire [127:0] soc_user_port_wdata_payload_data; -wire [15:0] soc_user_port_wdata_payload_we; -wire soc_user_port_rdata_valid; -wire soc_user_port_rdata_ready; -wire [127:0] soc_user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_dfii_control0_re = 1'd0; -wire [3:0] csrbank1_dfii_control0_r; -reg csrbank1_dfii_control0_we = 1'd0; -wire [3:0] csrbank1_dfii_control0_w; -reg csrbank1_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi0_command0_r; -reg csrbank1_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi0_command0_w; -reg csrbank1_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi0_address0_r; -reg csrbank1_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi0_address0_w; -reg csrbank1_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi0_baddress0_r; -reg csrbank1_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi0_baddress0_w; -reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi0_wrdata0_r; -reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi0_wrdata0_w; -reg csrbank1_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi0_rddata_r; -reg csrbank1_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi0_rddata_w; -reg csrbank1_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi1_command0_r; -reg csrbank1_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi1_command0_w; -reg csrbank1_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi1_address0_r; -reg csrbank1_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi1_address0_w; -reg csrbank1_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi1_baddress0_r; -reg csrbank1_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi1_baddress0_w; -reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi1_wrdata0_r; -reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi1_wrdata0_w; -reg csrbank1_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi1_rddata_r; -reg csrbank1_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi1_rddata_w; -reg csrbank1_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi2_command0_r; -reg csrbank1_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi2_command0_w; -reg csrbank1_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi2_address0_r; -reg csrbank1_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi2_address0_w; -reg csrbank1_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi2_baddress0_r; -reg csrbank1_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi2_baddress0_w; -reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi2_wrdata0_r; -reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi2_wrdata0_w; -reg csrbank1_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi2_rddata_r; -reg csrbank1_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi2_rddata_w; -reg csrbank1_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank1_dfii_pi3_command0_r; -reg csrbank1_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank1_dfii_pi3_command0_w; -reg csrbank1_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank1_dfii_pi3_address0_r; -reg csrbank1_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank1_dfii_pi3_address0_w; -reg csrbank1_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank1_dfii_pi3_baddress0_r; -reg csrbank1_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank1_dfii_pi3_baddress0_w; -reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank1_dfii_pi3_wrdata0_r; -reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank1_dfii_pi3_wrdata0_w; -reg csrbank1_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank1_dfii_pi3_rddata_r; -reg csrbank1_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank1_dfii_pi3_rddata_w; -wire csrbank1_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -wire [24:0] slice_proxy0; -wire [24:0] slice_proxy1; -wire [24:0] slice_proxy2; -wire [24:0] slice_proxy3; -wire [24:0] slice_proxy4; -wire [24:0] slice_proxy5; -wire [24:0] slice_proxy6; -wire [24:0] slice_proxy7; -wire [24:0] slice_proxy8; -wire [24:0] slice_proxy9; -wire [24:0] slice_proxy10; -wire [24:0] slice_proxy11; -wire [24:0] slice_proxy12; -wire [24:0] slice_proxy13; -wire [24:0] slice_proxy14; -wire [24:0] slice_proxy15; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; +wire sys_clk; +wire sys_rst; +wire por_clk; +reg soc_int_rst = 1'd1; +wire [13:0] soc_ddrphy_dfi_p0_address; +wire [2:0] soc_ddrphy_dfi_p0_bank; +wire soc_ddrphy_dfi_p0_cas_n; +wire soc_ddrphy_dfi_p0_cs_n; +wire soc_ddrphy_dfi_p0_ras_n; +wire soc_ddrphy_dfi_p0_we_n; +wire soc_ddrphy_dfi_p0_cke; +wire soc_ddrphy_dfi_p0_odt; +wire soc_ddrphy_dfi_p0_reset_n; +wire soc_ddrphy_dfi_p0_act_n; +wire [31:0] soc_ddrphy_dfi_p0_wrdata; +wire soc_ddrphy_dfi_p0_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask; +wire soc_ddrphy_dfi_p0_rddata_en; +wire [31:0] soc_ddrphy_dfi_p0_rddata; +wire soc_ddrphy_dfi_p0_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p1_address; +wire [2:0] soc_ddrphy_dfi_p1_bank; +wire soc_ddrphy_dfi_p1_cas_n; +wire soc_ddrphy_dfi_p1_cs_n; +wire soc_ddrphy_dfi_p1_ras_n; +wire soc_ddrphy_dfi_p1_we_n; +wire soc_ddrphy_dfi_p1_cke; +wire soc_ddrphy_dfi_p1_odt; +wire soc_ddrphy_dfi_p1_reset_n; +wire soc_ddrphy_dfi_p1_act_n; +wire [31:0] soc_ddrphy_dfi_p1_wrdata; +wire soc_ddrphy_dfi_p1_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask; +wire soc_ddrphy_dfi_p1_rddata_en; +wire [31:0] soc_ddrphy_dfi_p1_rddata; +wire soc_ddrphy_dfi_p1_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p2_address; +wire [2:0] soc_ddrphy_dfi_p2_bank; +wire soc_ddrphy_dfi_p2_cas_n; +wire soc_ddrphy_dfi_p2_cs_n; +wire soc_ddrphy_dfi_p2_ras_n; +wire soc_ddrphy_dfi_p2_we_n; +wire soc_ddrphy_dfi_p2_cke; +wire soc_ddrphy_dfi_p2_odt; +wire soc_ddrphy_dfi_p2_reset_n; +wire soc_ddrphy_dfi_p2_act_n; +wire [31:0] soc_ddrphy_dfi_p2_wrdata; +wire soc_ddrphy_dfi_p2_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask; +wire soc_ddrphy_dfi_p2_rddata_en; +wire [31:0] soc_ddrphy_dfi_p2_rddata; +wire soc_ddrphy_dfi_p2_rddata_valid; +wire [13:0] soc_ddrphy_dfi_p3_address; +wire [2:0] soc_ddrphy_dfi_p3_bank; +wire soc_ddrphy_dfi_p3_cas_n; +wire soc_ddrphy_dfi_p3_cs_n; +wire soc_ddrphy_dfi_p3_ras_n; +wire soc_ddrphy_dfi_p3_we_n; +wire soc_ddrphy_dfi_p3_cke; +wire soc_ddrphy_dfi_p3_odt; +wire soc_ddrphy_dfi_p3_reset_n; +wire soc_ddrphy_dfi_p3_act_n; +wire [31:0] soc_ddrphy_dfi_p3_wrdata; +wire soc_ddrphy_dfi_p3_wrdata_en; +wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask; +wire soc_ddrphy_dfi_p3_rddata_en; +wire [31:0] soc_ddrphy_dfi_p3_rddata; +wire soc_ddrphy_dfi_p3_rddata_valid; +reg soc_ddrphy_dfiphasemodel0_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel0_write = 1'd0; +reg soc_ddrphy_dfiphasemodel0_read = 1'd0; +reg soc_ddrphy_dfiphasemodel1_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel1_write = 1'd0; +reg soc_ddrphy_dfiphasemodel1_read = 1'd0; +reg soc_ddrphy_dfiphasemodel2_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel2_write = 1'd0; +reg soc_ddrphy_dfiphasemodel2_read = 1'd0; +reg soc_ddrphy_dfiphasemodel3_activate = 1'd0; +reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0; +reg soc_ddrphy_dfiphasemodel3_write = 1'd0; +reg soc_ddrphy_dfiphasemodel3_read = 1'd0; +reg soc_ddrphy_bankmodel0_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0; +reg soc_ddrphy_bankmodel0_precharge = 1'd0; +wire soc_ddrphy_bankmodel0_write; +wire [9:0] soc_ddrphy_bankmodel0_write_col; +wire [127:0] soc_ddrphy_bankmodel0_write_data; +wire [15:0] soc_ddrphy_bankmodel0_write_mask; +reg soc_ddrphy_bankmodel0_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0; +reg soc_ddrphy_bankmodel0_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel0_wraddr; +wire [20:0] soc_ddrphy_bankmodel0_rdaddr; +reg soc_ddrphy_bankmodel1_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0; +reg soc_ddrphy_bankmodel1_precharge = 1'd0; +wire soc_ddrphy_bankmodel1_write; +wire [9:0] soc_ddrphy_bankmodel1_write_col; +wire [127:0] soc_ddrphy_bankmodel1_write_data; +wire [15:0] soc_ddrphy_bankmodel1_write_mask; +reg soc_ddrphy_bankmodel1_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0; +reg soc_ddrphy_bankmodel1_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel1_wraddr; +wire [20:0] soc_ddrphy_bankmodel1_rdaddr; +reg soc_ddrphy_bankmodel2_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0; +reg soc_ddrphy_bankmodel2_precharge = 1'd0; +wire soc_ddrphy_bankmodel2_write; +wire [9:0] soc_ddrphy_bankmodel2_write_col; +wire [127:0] soc_ddrphy_bankmodel2_write_data; +wire [15:0] soc_ddrphy_bankmodel2_write_mask; +reg soc_ddrphy_bankmodel2_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0; +reg soc_ddrphy_bankmodel2_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel2_wraddr; +wire [20:0] soc_ddrphy_bankmodel2_rdaddr; +reg soc_ddrphy_bankmodel3_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0; +reg soc_ddrphy_bankmodel3_precharge = 1'd0; +wire soc_ddrphy_bankmodel3_write; +wire [9:0] soc_ddrphy_bankmodel3_write_col; +wire [127:0] soc_ddrphy_bankmodel3_write_data; +wire [15:0] soc_ddrphy_bankmodel3_write_mask; +reg soc_ddrphy_bankmodel3_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0; +reg soc_ddrphy_bankmodel3_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel3_wraddr; +wire [20:0] soc_ddrphy_bankmodel3_rdaddr; +reg soc_ddrphy_bankmodel4_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0; +reg soc_ddrphy_bankmodel4_precharge = 1'd0; +wire soc_ddrphy_bankmodel4_write; +wire [9:0] soc_ddrphy_bankmodel4_write_col; +wire [127:0] soc_ddrphy_bankmodel4_write_data; +wire [15:0] soc_ddrphy_bankmodel4_write_mask; +reg soc_ddrphy_bankmodel4_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0; +reg soc_ddrphy_bankmodel4_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel4_wraddr; +wire [20:0] soc_ddrphy_bankmodel4_rdaddr; +reg soc_ddrphy_bankmodel5_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0; +reg soc_ddrphy_bankmodel5_precharge = 1'd0; +wire soc_ddrphy_bankmodel5_write; +wire [9:0] soc_ddrphy_bankmodel5_write_col; +wire [127:0] soc_ddrphy_bankmodel5_write_data; +wire [15:0] soc_ddrphy_bankmodel5_write_mask; +reg soc_ddrphy_bankmodel5_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0; +reg soc_ddrphy_bankmodel5_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel5_wraddr; +wire [20:0] soc_ddrphy_bankmodel5_rdaddr; +reg soc_ddrphy_bankmodel6_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0; +reg soc_ddrphy_bankmodel6_precharge = 1'd0; +wire soc_ddrphy_bankmodel6_write; +wire [9:0] soc_ddrphy_bankmodel6_write_col; +wire [127:0] soc_ddrphy_bankmodel6_write_data; +wire [15:0] soc_ddrphy_bankmodel6_write_mask; +reg soc_ddrphy_bankmodel6_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0; +reg soc_ddrphy_bankmodel6_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel6_wraddr; +wire [20:0] soc_ddrphy_bankmodel6_rdaddr; +reg soc_ddrphy_bankmodel7_activate = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0; +reg soc_ddrphy_bankmodel7_precharge = 1'd0; +wire soc_ddrphy_bankmodel7_write; +wire [9:0] soc_ddrphy_bankmodel7_write_col; +wire [127:0] soc_ddrphy_bankmodel7_write_data; +wire [15:0] soc_ddrphy_bankmodel7_write_mask; +reg soc_ddrphy_bankmodel7_read = 1'd0; +reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0; +reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0; +reg soc_ddrphy_bankmodel7_active = 1'd0; +reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0; +reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r; +reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0; +reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0; +reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0; +wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r; +wire [20:0] soc_ddrphy_bankmodel7_wraddr; +wire [20:0] soc_ddrphy_bankmodel7_rdaddr; +reg [3:0] soc_ddrphy_activates0 = 4'd0; +reg [3:0] soc_ddrphy_precharges0 = 4'd0; +reg soc_ddrphy_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_writes0 = 4'd0; +reg soc_ddrphy_new_bank_write0 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0; +reg [3:0] soc_ddrphy_reads0 = 4'd0; +reg [3:0] soc_ddrphy_activates1 = 4'd0; +reg [3:0] soc_ddrphy_precharges1 = 4'd0; +reg soc_ddrphy_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_writes1 = 4'd0; +reg soc_ddrphy_new_bank_write1 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0; +reg [3:0] soc_ddrphy_reads1 = 4'd0; +reg [3:0] soc_ddrphy_activates2 = 4'd0; +reg [3:0] soc_ddrphy_precharges2 = 4'd0; +reg soc_ddrphy_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_writes2 = 4'd0; +reg soc_ddrphy_new_bank_write2 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0; +reg [3:0] soc_ddrphy_reads2 = 4'd0; +reg [3:0] soc_ddrphy_activates3 = 4'd0; +reg [3:0] soc_ddrphy_precharges3 = 4'd0; +reg soc_ddrphy_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_writes3 = 4'd0; +reg soc_ddrphy_new_bank_write3 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0; +reg [3:0] soc_ddrphy_reads3 = 4'd0; +reg [3:0] soc_ddrphy_activates4 = 4'd0; +reg [3:0] soc_ddrphy_precharges4 = 4'd0; +reg soc_ddrphy_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_writes4 = 4'd0; +reg soc_ddrphy_new_bank_write4 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0; +reg [3:0] soc_ddrphy_reads4 = 4'd0; +reg [3:0] soc_ddrphy_activates5 = 4'd0; +reg [3:0] soc_ddrphy_precharges5 = 4'd0; +reg soc_ddrphy_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_writes5 = 4'd0; +reg soc_ddrphy_new_bank_write5 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0; +reg [3:0] soc_ddrphy_reads5 = 4'd0; +reg [3:0] soc_ddrphy_activates6 = 4'd0; +reg [3:0] soc_ddrphy_precharges6 = 4'd0; +reg soc_ddrphy_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_writes6 = 4'd0; +reg soc_ddrphy_new_bank_write6 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0; +reg [3:0] soc_ddrphy_reads6 = 4'd0; +reg [3:0] soc_ddrphy_activates7 = 4'd0; +reg [3:0] soc_ddrphy_precharges7 = 4'd0; +reg soc_ddrphy_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_writes7 = 4'd0; +reg soc_ddrphy_new_bank_write7 = 1'd0; +reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0; +reg [3:0] soc_ddrphy_reads7 = 4'd0; +wire soc_ddrphy_banks_read; +wire [127:0] soc_ddrphy_banks_read_data; +reg soc_ddrphy_new_banks_read0 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0; +reg soc_ddrphy_new_banks_read1 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0; +reg soc_ddrphy_new_banks_read2 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0; +reg soc_ddrphy_new_banks_read3 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0; +reg soc_ddrphy_new_banks_read4 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0; +reg soc_ddrphy_new_banks_read5 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0; +reg soc_ddrphy_new_banks_read6 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0; +reg soc_ddrphy_new_banks_read7 = 1'd0; +reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0; +wire [13:0] soc_litedramcore_slave_p0_address; +wire [2:0] soc_litedramcore_slave_p0_bank; +wire soc_litedramcore_slave_p0_cas_n; +wire soc_litedramcore_slave_p0_cs_n; +wire soc_litedramcore_slave_p0_ras_n; +wire soc_litedramcore_slave_p0_we_n; +wire soc_litedramcore_slave_p0_cke; +wire soc_litedramcore_slave_p0_odt; +wire soc_litedramcore_slave_p0_reset_n; +wire soc_litedramcore_slave_p0_act_n; +wire [31:0] soc_litedramcore_slave_p0_wrdata; +wire soc_litedramcore_slave_p0_wrdata_en; +wire [3:0] soc_litedramcore_slave_p0_wrdata_mask; +wire soc_litedramcore_slave_p0_rddata_en; +reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0; +reg soc_litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p1_address; +wire [2:0] soc_litedramcore_slave_p1_bank; +wire soc_litedramcore_slave_p1_cas_n; +wire soc_litedramcore_slave_p1_cs_n; +wire soc_litedramcore_slave_p1_ras_n; +wire soc_litedramcore_slave_p1_we_n; +wire soc_litedramcore_slave_p1_cke; +wire soc_litedramcore_slave_p1_odt; +wire soc_litedramcore_slave_p1_reset_n; +wire soc_litedramcore_slave_p1_act_n; +wire [31:0] soc_litedramcore_slave_p1_wrdata; +wire soc_litedramcore_slave_p1_wrdata_en; +wire [3:0] soc_litedramcore_slave_p1_wrdata_mask; +wire soc_litedramcore_slave_p1_rddata_en; +reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0; +reg soc_litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p2_address; +wire [2:0] soc_litedramcore_slave_p2_bank; +wire soc_litedramcore_slave_p2_cas_n; +wire soc_litedramcore_slave_p2_cs_n; +wire soc_litedramcore_slave_p2_ras_n; +wire soc_litedramcore_slave_p2_we_n; +wire soc_litedramcore_slave_p2_cke; +wire soc_litedramcore_slave_p2_odt; +wire soc_litedramcore_slave_p2_reset_n; +wire soc_litedramcore_slave_p2_act_n; +wire [31:0] soc_litedramcore_slave_p2_wrdata; +wire soc_litedramcore_slave_p2_wrdata_en; +wire [3:0] soc_litedramcore_slave_p2_wrdata_mask; +wire soc_litedramcore_slave_p2_rddata_en; +reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0; +reg soc_litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_slave_p3_address; +wire [2:0] soc_litedramcore_slave_p3_bank; +wire soc_litedramcore_slave_p3_cas_n; +wire soc_litedramcore_slave_p3_cs_n; +wire soc_litedramcore_slave_p3_ras_n; +wire soc_litedramcore_slave_p3_we_n; +wire soc_litedramcore_slave_p3_cke; +wire soc_litedramcore_slave_p3_odt; +wire soc_litedramcore_slave_p3_reset_n; +wire soc_litedramcore_slave_p3_act_n; +wire [31:0] soc_litedramcore_slave_p3_wrdata; +wire soc_litedramcore_slave_p3_wrdata_en; +wire [3:0] soc_litedramcore_slave_p3_wrdata_mask; +wire soc_litedramcore_slave_p3_rddata_en; +reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0; +reg soc_litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_master_p0_address = 14'd0; +reg [2:0] soc_litedramcore_master_p0_bank = 3'd0; +reg soc_litedramcore_master_p0_cas_n = 1'd1; +reg soc_litedramcore_master_p0_cs_n = 1'd1; +reg soc_litedramcore_master_p0_ras_n = 1'd1; +reg soc_litedramcore_master_p0_we_n = 1'd1; +reg soc_litedramcore_master_p0_cke = 1'd0; +reg soc_litedramcore_master_p0_odt = 1'd0; +reg soc_litedramcore_master_p0_reset_n = 1'd0; +reg soc_litedramcore_master_p0_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0; +reg soc_litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p0_rddata; +wire soc_litedramcore_master_p0_rddata_valid; +reg [13:0] soc_litedramcore_master_p1_address = 14'd0; +reg [2:0] soc_litedramcore_master_p1_bank = 3'd0; +reg soc_litedramcore_master_p1_cas_n = 1'd1; +reg soc_litedramcore_master_p1_cs_n = 1'd1; +reg soc_litedramcore_master_p1_ras_n = 1'd1; +reg soc_litedramcore_master_p1_we_n = 1'd1; +reg soc_litedramcore_master_p1_cke = 1'd0; +reg soc_litedramcore_master_p1_odt = 1'd0; +reg soc_litedramcore_master_p1_reset_n = 1'd0; +reg soc_litedramcore_master_p1_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0; +reg soc_litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p1_rddata; +wire soc_litedramcore_master_p1_rddata_valid; +reg [13:0] soc_litedramcore_master_p2_address = 14'd0; +reg [2:0] soc_litedramcore_master_p2_bank = 3'd0; +reg soc_litedramcore_master_p2_cas_n = 1'd1; +reg soc_litedramcore_master_p2_cs_n = 1'd1; +reg soc_litedramcore_master_p2_ras_n = 1'd1; +reg soc_litedramcore_master_p2_we_n = 1'd1; +reg soc_litedramcore_master_p2_cke = 1'd0; +reg soc_litedramcore_master_p2_odt = 1'd0; +reg soc_litedramcore_master_p2_reset_n = 1'd0; +reg soc_litedramcore_master_p2_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0; +reg soc_litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p2_rddata; +wire soc_litedramcore_master_p2_rddata_valid; +reg [13:0] soc_litedramcore_master_p3_address = 14'd0; +reg [2:0] soc_litedramcore_master_p3_bank = 3'd0; +reg soc_litedramcore_master_p3_cas_n = 1'd1; +reg soc_litedramcore_master_p3_cs_n = 1'd1; +reg soc_litedramcore_master_p3_ras_n = 1'd1; +reg soc_litedramcore_master_p3_we_n = 1'd1; +reg soc_litedramcore_master_p3_cke = 1'd0; +reg soc_litedramcore_master_p3_odt = 1'd0; +reg soc_litedramcore_master_p3_reset_n = 1'd0; +reg soc_litedramcore_master_p3_act_n = 1'd1; +reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0; +reg soc_litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_master_p3_rddata; +wire soc_litedramcore_master_p3_rddata_valid; +wire [13:0] soc_litedramcore_csr_dfi_p0_address; +wire [2:0] soc_litedramcore_csr_dfi_p0_bank; +reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1; +wire soc_litedramcore_csr_dfi_p0_cke; +wire soc_litedramcore_csr_dfi_p0_odt; +wire soc_litedramcore_csr_dfi_p0_reset_n; +reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata; +wire soc_litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask; +wire soc_litedramcore_csr_dfi_p0_rddata_en; +reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0; +reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_csr_dfi_p1_address; +wire [2:0] soc_litedramcore_csr_dfi_p1_bank; +reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1; +wire soc_litedramcore_csr_dfi_p1_cke; +wire soc_litedramcore_csr_dfi_p1_odt; +wire soc_litedramcore_csr_dfi_p1_reset_n; +reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata; +wire soc_litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask; +wire soc_litedramcore_csr_dfi_p1_rddata_en; +reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0; +reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_csr_dfi_p2_address; +wire [2:0] soc_litedramcore_csr_dfi_p2_bank; +reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1; +wire soc_litedramcore_csr_dfi_p2_cke; +wire soc_litedramcore_csr_dfi_p2_odt; +wire soc_litedramcore_csr_dfi_p2_reset_n; +reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata; +wire soc_litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask; +wire soc_litedramcore_csr_dfi_p2_rddata_en; +reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0; +reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [13:0] soc_litedramcore_csr_dfi_p3_address; +wire [2:0] soc_litedramcore_csr_dfi_p3_bank; +reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1; +wire soc_litedramcore_csr_dfi_p3_cke; +wire soc_litedramcore_csr_dfi_p3_odt; +wire soc_litedramcore_csr_dfi_p3_reset_n; +reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata; +wire soc_litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask; +wire soc_litedramcore_csr_dfi_p3_rddata_en; +reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0; +reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1; +reg soc_litedramcore_ext_dfi_p0_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p0_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1; +reg soc_litedramcore_ext_dfi_p1_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p1_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1; +reg soc_litedramcore_ext_dfi_p2_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p2_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0; +reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1; +reg soc_litedramcore_ext_dfi_p3_cke = 1'd0; +reg soc_litedramcore_ext_dfi_p3_odt = 1'd0; +reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0; +reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg soc_litedramcore_ext_dfi_sel = 1'd0; +wire soc_litedramcore_sel; +wire soc_litedramcore_cke; +wire soc_litedramcore_odt; +wire soc_litedramcore_reset_n; +reg [3:0] soc_litedramcore_storage = 4'd1; +reg soc_litedramcore_re = 1'd0; +wire soc_litedramcore_phaseinjector0_csrfield_cs; +wire soc_litedramcore_phaseinjector0_csrfield_we; +wire soc_litedramcore_phaseinjector0_csrfield_cas; +wire soc_litedramcore_phaseinjector0_csrfield_ras; +wire soc_litedramcore_phaseinjector0_csrfield_wren; +wire soc_litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector0_command_re = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector0_command_issue_r; +reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector0_rddata_we; +reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0; +wire soc_litedramcore_phaseinjector1_csrfield_cs; +wire soc_litedramcore_phaseinjector1_csrfield_we; +wire soc_litedramcore_phaseinjector1_csrfield_cas; +wire soc_litedramcore_phaseinjector1_csrfield_ras; +wire soc_litedramcore_phaseinjector1_csrfield_wren; +wire soc_litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector1_command_re = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector1_command_issue_r; +reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector1_rddata_we; +reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0; +wire soc_litedramcore_phaseinjector2_csrfield_cs; +wire soc_litedramcore_phaseinjector2_csrfield_we; +wire soc_litedramcore_phaseinjector2_csrfield_cas; +wire soc_litedramcore_phaseinjector2_csrfield_ras; +wire soc_litedramcore_phaseinjector2_csrfield_wren; +wire soc_litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector2_command_re = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector2_command_issue_r; +reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector2_rddata_we; +reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0; +wire soc_litedramcore_phaseinjector3_csrfield_cs; +wire soc_litedramcore_phaseinjector3_csrfield_we; +wire soc_litedramcore_phaseinjector3_csrfield_cas; +wire soc_litedramcore_phaseinjector3_csrfield_ras; +wire soc_litedramcore_phaseinjector3_csrfield_wren; +wire soc_litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0; +reg soc_litedramcore_phaseinjector3_command_re = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire soc_litedramcore_phaseinjector3_command_issue_r; +reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0; +reg soc_litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0; +wire soc_litedramcore_phaseinjector3_rddata_we; +reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0; +wire soc_litedramcore_interface_bank0_valid; +wire soc_litedramcore_interface_bank0_ready; +wire soc_litedramcore_interface_bank0_we; +wire [20:0] soc_litedramcore_interface_bank0_addr; +wire soc_litedramcore_interface_bank0_lock; +wire soc_litedramcore_interface_bank0_wdata_ready; +wire soc_litedramcore_interface_bank0_rdata_valid; +wire soc_litedramcore_interface_bank1_valid; +wire soc_litedramcore_interface_bank1_ready; +wire soc_litedramcore_interface_bank1_we; +wire [20:0] soc_litedramcore_interface_bank1_addr; +wire soc_litedramcore_interface_bank1_lock; +wire soc_litedramcore_interface_bank1_wdata_ready; +wire soc_litedramcore_interface_bank1_rdata_valid; +wire soc_litedramcore_interface_bank2_valid; +wire soc_litedramcore_interface_bank2_ready; +wire soc_litedramcore_interface_bank2_we; +wire [20:0] soc_litedramcore_interface_bank2_addr; +wire soc_litedramcore_interface_bank2_lock; +wire soc_litedramcore_interface_bank2_wdata_ready; +wire soc_litedramcore_interface_bank2_rdata_valid; +wire soc_litedramcore_interface_bank3_valid; +wire soc_litedramcore_interface_bank3_ready; +wire soc_litedramcore_interface_bank3_we; +wire [20:0] soc_litedramcore_interface_bank3_addr; +wire soc_litedramcore_interface_bank3_lock; +wire soc_litedramcore_interface_bank3_wdata_ready; +wire soc_litedramcore_interface_bank3_rdata_valid; +wire soc_litedramcore_interface_bank4_valid; +wire soc_litedramcore_interface_bank4_ready; +wire soc_litedramcore_interface_bank4_we; +wire [20:0] soc_litedramcore_interface_bank4_addr; +wire soc_litedramcore_interface_bank4_lock; +wire soc_litedramcore_interface_bank4_wdata_ready; +wire soc_litedramcore_interface_bank4_rdata_valid; +wire soc_litedramcore_interface_bank5_valid; +wire soc_litedramcore_interface_bank5_ready; +wire soc_litedramcore_interface_bank5_we; +wire [20:0] soc_litedramcore_interface_bank5_addr; +wire soc_litedramcore_interface_bank5_lock; +wire soc_litedramcore_interface_bank5_wdata_ready; +wire soc_litedramcore_interface_bank5_rdata_valid; +wire soc_litedramcore_interface_bank6_valid; +wire soc_litedramcore_interface_bank6_ready; +wire soc_litedramcore_interface_bank6_we; +wire [20:0] soc_litedramcore_interface_bank6_addr; +wire soc_litedramcore_interface_bank6_lock; +wire soc_litedramcore_interface_bank6_wdata_ready; +wire soc_litedramcore_interface_bank6_rdata_valid; +wire soc_litedramcore_interface_bank7_valid; +wire soc_litedramcore_interface_bank7_ready; +wire soc_litedramcore_interface_bank7_we; +wire [20:0] soc_litedramcore_interface_bank7_addr; +wire soc_litedramcore_interface_bank7_lock; +wire soc_litedramcore_interface_bank7_wdata_ready; +wire soc_litedramcore_interface_bank7_rdata_valid; +reg [127:0] soc_litedramcore_interface_wdata = 128'd0; +reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0; +wire [127:0] soc_litedramcore_interface_rdata; +reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0; +reg soc_litedramcore_dfi_p0_cas_n = 1'd1; +reg soc_litedramcore_dfi_p0_cs_n = 1'd1; +reg soc_litedramcore_dfi_p0_ras_n = 1'd1; +reg soc_litedramcore_dfi_p0_we_n = 1'd1; +wire soc_litedramcore_dfi_p0_cke; +wire soc_litedramcore_dfi_p0_odt; +wire soc_litedramcore_dfi_p0_reset_n; +reg soc_litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p0_wrdata; +reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask; +reg soc_litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p0_rddata; +wire soc_litedramcore_dfi_p0_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0; +reg soc_litedramcore_dfi_p1_cas_n = 1'd1; +reg soc_litedramcore_dfi_p1_cs_n = 1'd1; +reg soc_litedramcore_dfi_p1_ras_n = 1'd1; +reg soc_litedramcore_dfi_p1_we_n = 1'd1; +wire soc_litedramcore_dfi_p1_cke; +wire soc_litedramcore_dfi_p1_odt; +wire soc_litedramcore_dfi_p1_reset_n; +reg soc_litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p1_wrdata; +reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask; +reg soc_litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p1_rddata; +wire soc_litedramcore_dfi_p1_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0; +reg soc_litedramcore_dfi_p2_cas_n = 1'd1; +reg soc_litedramcore_dfi_p2_cs_n = 1'd1; +reg soc_litedramcore_dfi_p2_ras_n = 1'd1; +reg soc_litedramcore_dfi_p2_we_n = 1'd1; +wire soc_litedramcore_dfi_p2_cke; +wire soc_litedramcore_dfi_p2_odt; +wire soc_litedramcore_dfi_p2_reset_n; +reg soc_litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p2_wrdata; +reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask; +reg soc_litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p2_rddata; +wire soc_litedramcore_dfi_p2_rddata_valid; +reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0; +reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0; +reg soc_litedramcore_dfi_p3_cas_n = 1'd1; +reg soc_litedramcore_dfi_p3_cs_n = 1'd1; +reg soc_litedramcore_dfi_p3_ras_n = 1'd1; +reg soc_litedramcore_dfi_p3_we_n = 1'd1; +wire soc_litedramcore_dfi_p3_cke; +wire soc_litedramcore_dfi_p3_odt; +wire soc_litedramcore_dfi_p3_reset_n; +reg soc_litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] soc_litedramcore_dfi_p3_wrdata; +reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask; +reg soc_litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] soc_litedramcore_dfi_p3_rddata; +wire soc_litedramcore_dfi_p3_rddata_valid; +reg soc_litedramcore_cmd_valid = 1'd0; +reg soc_litedramcore_cmd_ready = 1'd0; +reg soc_litedramcore_cmd_last = 1'd0; +reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0; +reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0; +reg soc_litedramcore_cmd_payload_cas = 1'd0; +reg soc_litedramcore_cmd_payload_ras = 1'd0; +reg soc_litedramcore_cmd_payload_we = 1'd0; +reg soc_litedramcore_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_cmd_payload_is_write = 1'd0; +wire soc_litedramcore_wants_refresh; +wire soc_litedramcore_wants_zqcs; +wire soc_litedramcore_timer_wait; +wire soc_litedramcore_timer_done0; +wire [9:0] soc_litedramcore_timer_count0; +wire soc_litedramcore_timer_done1; +reg [9:0] soc_litedramcore_timer_count1 = 10'd781; +wire soc_litedramcore_postponer_req_i; +reg soc_litedramcore_postponer_req_o = 1'd0; +reg soc_litedramcore_postponer_count = 1'd0; +reg soc_litedramcore_sequencer_start0 = 1'd0; +wire soc_litedramcore_sequencer_done0; +wire soc_litedramcore_sequencer_start1; +reg soc_litedramcore_sequencer_done1 = 1'd0; +reg [5:0] soc_litedramcore_sequencer_counter = 6'd0; +reg soc_litedramcore_sequencer_count = 1'd0; +wire soc_litedramcore_zqcs_timer_wait; +wire soc_litedramcore_zqcs_timer_done0; +wire [26:0] soc_litedramcore_zqcs_timer_count0; +wire soc_litedramcore_zqcs_timer_done1; +reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999; +reg soc_litedramcore_zqcs_executer_start = 1'd0; +reg soc_litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0; +wire soc_litedramcore_bankmachine0_req_valid; +wire soc_litedramcore_bankmachine0_req_ready; +wire soc_litedramcore_bankmachine0_req_we; +wire [20:0] soc_litedramcore_bankmachine0_req_addr; +wire soc_litedramcore_bankmachine0_req_lock; +reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine0_refresh_req; +reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba; +reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine0_sink_valid; +wire soc_litedramcore_bankmachine0_sink_ready; +reg soc_litedramcore_bankmachine0_sink_first = 1'd0; +reg soc_litedramcore_bankmachine0_sink_last = 1'd0; +wire soc_litedramcore_bankmachine0_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_sink_payload_addr; +wire soc_litedramcore_bankmachine0_source_valid; +wire soc_litedramcore_bankmachine0_source_ready; +wire soc_litedramcore_bankmachine0_source_first; +wire soc_litedramcore_bankmachine0_source_last; +wire soc_litedramcore_bankmachine0_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_source_payload_addr; +wire soc_litedramcore_bankmachine0_syncfifo0_we; +wire soc_litedramcore_bankmachine0_syncfifo0_writable; +wire soc_litedramcore_bankmachine0_syncfifo0_re; +wire soc_litedramcore_bankmachine0_syncfifo0_readable; +wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] soc_litedramcore_bankmachine0_level = 5'd0; +reg soc_litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_r; +wire soc_litedramcore_bankmachine0_wrport_we; +wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_w; +wire soc_litedramcore_bankmachine0_do_read; +wire [3:0] soc_litedramcore_bankmachine0_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine0_rdport_dat_r; +wire soc_litedramcore_bankmachine0_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_in_first; +wire soc_litedramcore_bankmachine0_fifo_in_last; +wire soc_litedramcore_bankmachine0_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine0_fifo_out_first; +wire soc_litedramcore_bankmachine0_fifo_out_last; +wire soc_litedramcore_bankmachine0_sink_sink_valid; +wire soc_litedramcore_bankmachine0_sink_sink_ready; +wire soc_litedramcore_bankmachine0_sink_sink_first; +wire soc_litedramcore_bankmachine0_sink_sink_last; +wire soc_litedramcore_bankmachine0_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine0_source_source_valid; +wire soc_litedramcore_bankmachine0_source_source_ready; +wire soc_litedramcore_bankmachine0_source_source_first; +wire soc_litedramcore_bankmachine0_source_source_last; +wire soc_litedramcore_bankmachine0_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine0_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0; +reg soc_litedramcore_bankmachine0_row_opened = 1'd0; +wire soc_litedramcore_bankmachine0_row_hit; +reg soc_litedramcore_bankmachine0_row_open = 1'd0; +reg soc_litedramcore_bankmachine0_row_close = 1'd0; +reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine0_twtpcon_valid; +reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trccon_valid; +reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine0_trascon_valid; +reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine1_req_valid; +wire soc_litedramcore_bankmachine1_req_ready; +wire soc_litedramcore_bankmachine1_req_we; +wire [20:0] soc_litedramcore_bankmachine1_req_addr; +wire soc_litedramcore_bankmachine1_req_lock; +reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine1_refresh_req; +reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba; +reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine1_sink_valid; +wire soc_litedramcore_bankmachine1_sink_ready; +reg soc_litedramcore_bankmachine1_sink_first = 1'd0; +reg soc_litedramcore_bankmachine1_sink_last = 1'd0; +wire soc_litedramcore_bankmachine1_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_sink_payload_addr; +wire soc_litedramcore_bankmachine1_source_valid; +wire soc_litedramcore_bankmachine1_source_ready; +wire soc_litedramcore_bankmachine1_source_first; +wire soc_litedramcore_bankmachine1_source_last; +wire soc_litedramcore_bankmachine1_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_source_payload_addr; +wire soc_litedramcore_bankmachine1_syncfifo1_we; +wire soc_litedramcore_bankmachine1_syncfifo1_writable; +wire soc_litedramcore_bankmachine1_syncfifo1_re; +wire soc_litedramcore_bankmachine1_syncfifo1_readable; +wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] soc_litedramcore_bankmachine1_level = 5'd0; +reg soc_litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_r; +wire soc_litedramcore_bankmachine1_wrport_we; +wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_w; +wire soc_litedramcore_bankmachine1_do_read; +wire [3:0] soc_litedramcore_bankmachine1_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine1_rdport_dat_r; +wire soc_litedramcore_bankmachine1_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_in_first; +wire soc_litedramcore_bankmachine1_fifo_in_last; +wire soc_litedramcore_bankmachine1_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine1_fifo_out_first; +wire soc_litedramcore_bankmachine1_fifo_out_last; +wire soc_litedramcore_bankmachine1_sink_sink_valid; +wire soc_litedramcore_bankmachine1_sink_sink_ready; +wire soc_litedramcore_bankmachine1_sink_sink_first; +wire soc_litedramcore_bankmachine1_sink_sink_last; +wire soc_litedramcore_bankmachine1_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine1_source_source_valid; +wire soc_litedramcore_bankmachine1_source_source_ready; +wire soc_litedramcore_bankmachine1_source_source_first; +wire soc_litedramcore_bankmachine1_source_source_last; +wire soc_litedramcore_bankmachine1_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine1_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0; +reg soc_litedramcore_bankmachine1_row_opened = 1'd0; +wire soc_litedramcore_bankmachine1_row_hit; +reg soc_litedramcore_bankmachine1_row_open = 1'd0; +reg soc_litedramcore_bankmachine1_row_close = 1'd0; +reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine1_twtpcon_valid; +reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trccon_valid; +reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine1_trascon_valid; +reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine2_req_valid; +wire soc_litedramcore_bankmachine2_req_ready; +wire soc_litedramcore_bankmachine2_req_we; +wire [20:0] soc_litedramcore_bankmachine2_req_addr; +wire soc_litedramcore_bankmachine2_req_lock; +reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine2_refresh_req; +reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba; +reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine2_sink_valid; +wire soc_litedramcore_bankmachine2_sink_ready; +reg soc_litedramcore_bankmachine2_sink_first = 1'd0; +reg soc_litedramcore_bankmachine2_sink_last = 1'd0; +wire soc_litedramcore_bankmachine2_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_sink_payload_addr; +wire soc_litedramcore_bankmachine2_source_valid; +wire soc_litedramcore_bankmachine2_source_ready; +wire soc_litedramcore_bankmachine2_source_first; +wire soc_litedramcore_bankmachine2_source_last; +wire soc_litedramcore_bankmachine2_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_source_payload_addr; +wire soc_litedramcore_bankmachine2_syncfifo2_we; +wire soc_litedramcore_bankmachine2_syncfifo2_writable; +wire soc_litedramcore_bankmachine2_syncfifo2_re; +wire soc_litedramcore_bankmachine2_syncfifo2_readable; +wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] soc_litedramcore_bankmachine2_level = 5'd0; +reg soc_litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_r; +wire soc_litedramcore_bankmachine2_wrport_we; +wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_w; +wire soc_litedramcore_bankmachine2_do_read; +wire [3:0] soc_litedramcore_bankmachine2_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine2_rdport_dat_r; +wire soc_litedramcore_bankmachine2_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_in_first; +wire soc_litedramcore_bankmachine2_fifo_in_last; +wire soc_litedramcore_bankmachine2_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine2_fifo_out_first; +wire soc_litedramcore_bankmachine2_fifo_out_last; +wire soc_litedramcore_bankmachine2_sink_sink_valid; +wire soc_litedramcore_bankmachine2_sink_sink_ready; +wire soc_litedramcore_bankmachine2_sink_sink_first; +wire soc_litedramcore_bankmachine2_sink_sink_last; +wire soc_litedramcore_bankmachine2_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine2_source_source_valid; +wire soc_litedramcore_bankmachine2_source_source_ready; +wire soc_litedramcore_bankmachine2_source_source_first; +wire soc_litedramcore_bankmachine2_source_source_last; +wire soc_litedramcore_bankmachine2_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine2_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0; +reg soc_litedramcore_bankmachine2_row_opened = 1'd0; +wire soc_litedramcore_bankmachine2_row_hit; +reg soc_litedramcore_bankmachine2_row_open = 1'd0; +reg soc_litedramcore_bankmachine2_row_close = 1'd0; +reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine2_twtpcon_valid; +reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trccon_valid; +reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine2_trascon_valid; +reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine3_req_valid; +wire soc_litedramcore_bankmachine3_req_ready; +wire soc_litedramcore_bankmachine3_req_we; +wire [20:0] soc_litedramcore_bankmachine3_req_addr; +wire soc_litedramcore_bankmachine3_req_lock; +reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine3_refresh_req; +reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba; +reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine3_sink_valid; +wire soc_litedramcore_bankmachine3_sink_ready; +reg soc_litedramcore_bankmachine3_sink_first = 1'd0; +reg soc_litedramcore_bankmachine3_sink_last = 1'd0; +wire soc_litedramcore_bankmachine3_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_sink_payload_addr; +wire soc_litedramcore_bankmachine3_source_valid; +wire soc_litedramcore_bankmachine3_source_ready; +wire soc_litedramcore_bankmachine3_source_first; +wire soc_litedramcore_bankmachine3_source_last; +wire soc_litedramcore_bankmachine3_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_source_payload_addr; +wire soc_litedramcore_bankmachine3_syncfifo3_we; +wire soc_litedramcore_bankmachine3_syncfifo3_writable; +wire soc_litedramcore_bankmachine3_syncfifo3_re; +wire soc_litedramcore_bankmachine3_syncfifo3_readable; +wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] soc_litedramcore_bankmachine3_level = 5'd0; +reg soc_litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_r; +wire soc_litedramcore_bankmachine3_wrport_we; +wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_w; +wire soc_litedramcore_bankmachine3_do_read; +wire [3:0] soc_litedramcore_bankmachine3_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine3_rdport_dat_r; +wire soc_litedramcore_bankmachine3_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_in_first; +wire soc_litedramcore_bankmachine3_fifo_in_last; +wire soc_litedramcore_bankmachine3_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine3_fifo_out_first; +wire soc_litedramcore_bankmachine3_fifo_out_last; +wire soc_litedramcore_bankmachine3_sink_sink_valid; +wire soc_litedramcore_bankmachine3_sink_sink_ready; +wire soc_litedramcore_bankmachine3_sink_sink_first; +wire soc_litedramcore_bankmachine3_sink_sink_last; +wire soc_litedramcore_bankmachine3_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine3_source_source_valid; +wire soc_litedramcore_bankmachine3_source_source_ready; +wire soc_litedramcore_bankmachine3_source_source_first; +wire soc_litedramcore_bankmachine3_source_source_last; +wire soc_litedramcore_bankmachine3_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine3_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0; +reg soc_litedramcore_bankmachine3_row_opened = 1'd0; +wire soc_litedramcore_bankmachine3_row_hit; +reg soc_litedramcore_bankmachine3_row_open = 1'd0; +reg soc_litedramcore_bankmachine3_row_close = 1'd0; +reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine3_twtpcon_valid; +reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trccon_valid; +reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine3_trascon_valid; +reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine4_req_valid; +wire soc_litedramcore_bankmachine4_req_ready; +wire soc_litedramcore_bankmachine4_req_we; +wire [20:0] soc_litedramcore_bankmachine4_req_addr; +wire soc_litedramcore_bankmachine4_req_lock; +reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine4_refresh_req; +reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba; +reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine4_sink_valid; +wire soc_litedramcore_bankmachine4_sink_ready; +reg soc_litedramcore_bankmachine4_sink_first = 1'd0; +reg soc_litedramcore_bankmachine4_sink_last = 1'd0; +wire soc_litedramcore_bankmachine4_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_sink_payload_addr; +wire soc_litedramcore_bankmachine4_source_valid; +wire soc_litedramcore_bankmachine4_source_ready; +wire soc_litedramcore_bankmachine4_source_first; +wire soc_litedramcore_bankmachine4_source_last; +wire soc_litedramcore_bankmachine4_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_source_payload_addr; +wire soc_litedramcore_bankmachine4_syncfifo4_we; +wire soc_litedramcore_bankmachine4_syncfifo4_writable; +wire soc_litedramcore_bankmachine4_syncfifo4_re; +wire soc_litedramcore_bankmachine4_syncfifo4_readable; +wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] soc_litedramcore_bankmachine4_level = 5'd0; +reg soc_litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_r; +wire soc_litedramcore_bankmachine4_wrport_we; +wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_w; +wire soc_litedramcore_bankmachine4_do_read; +wire [3:0] soc_litedramcore_bankmachine4_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine4_rdport_dat_r; +wire soc_litedramcore_bankmachine4_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_in_first; +wire soc_litedramcore_bankmachine4_fifo_in_last; +wire soc_litedramcore_bankmachine4_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine4_fifo_out_first; +wire soc_litedramcore_bankmachine4_fifo_out_last; +wire soc_litedramcore_bankmachine4_sink_sink_valid; +wire soc_litedramcore_bankmachine4_sink_sink_ready; +wire soc_litedramcore_bankmachine4_sink_sink_first; +wire soc_litedramcore_bankmachine4_sink_sink_last; +wire soc_litedramcore_bankmachine4_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine4_source_source_valid; +wire soc_litedramcore_bankmachine4_source_source_ready; +wire soc_litedramcore_bankmachine4_source_source_first; +wire soc_litedramcore_bankmachine4_source_source_last; +wire soc_litedramcore_bankmachine4_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine4_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0; +reg soc_litedramcore_bankmachine4_row_opened = 1'd0; +wire soc_litedramcore_bankmachine4_row_hit; +reg soc_litedramcore_bankmachine4_row_open = 1'd0; +reg soc_litedramcore_bankmachine4_row_close = 1'd0; +reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine4_twtpcon_valid; +reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trccon_valid; +reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine4_trascon_valid; +reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine5_req_valid; +wire soc_litedramcore_bankmachine5_req_ready; +wire soc_litedramcore_bankmachine5_req_we; +wire [20:0] soc_litedramcore_bankmachine5_req_addr; +wire soc_litedramcore_bankmachine5_req_lock; +reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine5_refresh_req; +reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba; +reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine5_sink_valid; +wire soc_litedramcore_bankmachine5_sink_ready; +reg soc_litedramcore_bankmachine5_sink_first = 1'd0; +reg soc_litedramcore_bankmachine5_sink_last = 1'd0; +wire soc_litedramcore_bankmachine5_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_sink_payload_addr; +wire soc_litedramcore_bankmachine5_source_valid; +wire soc_litedramcore_bankmachine5_source_ready; +wire soc_litedramcore_bankmachine5_source_first; +wire soc_litedramcore_bankmachine5_source_last; +wire soc_litedramcore_bankmachine5_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_source_payload_addr; +wire soc_litedramcore_bankmachine5_syncfifo5_we; +wire soc_litedramcore_bankmachine5_syncfifo5_writable; +wire soc_litedramcore_bankmachine5_syncfifo5_re; +wire soc_litedramcore_bankmachine5_syncfifo5_readable; +wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] soc_litedramcore_bankmachine5_level = 5'd0; +reg soc_litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_r; +wire soc_litedramcore_bankmachine5_wrport_we; +wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_w; +wire soc_litedramcore_bankmachine5_do_read; +wire [3:0] soc_litedramcore_bankmachine5_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine5_rdport_dat_r; +wire soc_litedramcore_bankmachine5_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_in_first; +wire soc_litedramcore_bankmachine5_fifo_in_last; +wire soc_litedramcore_bankmachine5_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine5_fifo_out_first; +wire soc_litedramcore_bankmachine5_fifo_out_last; +wire soc_litedramcore_bankmachine5_sink_sink_valid; +wire soc_litedramcore_bankmachine5_sink_sink_ready; +wire soc_litedramcore_bankmachine5_sink_sink_first; +wire soc_litedramcore_bankmachine5_sink_sink_last; +wire soc_litedramcore_bankmachine5_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine5_source_source_valid; +wire soc_litedramcore_bankmachine5_source_source_ready; +wire soc_litedramcore_bankmachine5_source_source_first; +wire soc_litedramcore_bankmachine5_source_source_last; +wire soc_litedramcore_bankmachine5_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine5_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0; +reg soc_litedramcore_bankmachine5_row_opened = 1'd0; +wire soc_litedramcore_bankmachine5_row_hit; +reg soc_litedramcore_bankmachine5_row_open = 1'd0; +reg soc_litedramcore_bankmachine5_row_close = 1'd0; +reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine5_twtpcon_valid; +reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trccon_valid; +reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine5_trascon_valid; +reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine6_req_valid; +wire soc_litedramcore_bankmachine6_req_ready; +wire soc_litedramcore_bankmachine6_req_we; +wire [20:0] soc_litedramcore_bankmachine6_req_addr; +wire soc_litedramcore_bankmachine6_req_lock; +reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine6_refresh_req; +reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba; +reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine6_sink_valid; +wire soc_litedramcore_bankmachine6_sink_ready; +reg soc_litedramcore_bankmachine6_sink_first = 1'd0; +reg soc_litedramcore_bankmachine6_sink_last = 1'd0; +wire soc_litedramcore_bankmachine6_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_sink_payload_addr; +wire soc_litedramcore_bankmachine6_source_valid; +wire soc_litedramcore_bankmachine6_source_ready; +wire soc_litedramcore_bankmachine6_source_first; +wire soc_litedramcore_bankmachine6_source_last; +wire soc_litedramcore_bankmachine6_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_source_payload_addr; +wire soc_litedramcore_bankmachine6_syncfifo6_we; +wire soc_litedramcore_bankmachine6_syncfifo6_writable; +wire soc_litedramcore_bankmachine6_syncfifo6_re; +wire soc_litedramcore_bankmachine6_syncfifo6_readable; +wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] soc_litedramcore_bankmachine6_level = 5'd0; +reg soc_litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_r; +wire soc_litedramcore_bankmachine6_wrport_we; +wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_w; +wire soc_litedramcore_bankmachine6_do_read; +wire [3:0] soc_litedramcore_bankmachine6_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine6_rdport_dat_r; +wire soc_litedramcore_bankmachine6_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_in_first; +wire soc_litedramcore_bankmachine6_fifo_in_last; +wire soc_litedramcore_bankmachine6_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine6_fifo_out_first; +wire soc_litedramcore_bankmachine6_fifo_out_last; +wire soc_litedramcore_bankmachine6_sink_sink_valid; +wire soc_litedramcore_bankmachine6_sink_sink_ready; +wire soc_litedramcore_bankmachine6_sink_sink_first; +wire soc_litedramcore_bankmachine6_sink_sink_last; +wire soc_litedramcore_bankmachine6_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine6_source_source_valid; +wire soc_litedramcore_bankmachine6_source_source_ready; +wire soc_litedramcore_bankmachine6_source_source_first; +wire soc_litedramcore_bankmachine6_source_source_last; +wire soc_litedramcore_bankmachine6_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine6_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0; +reg soc_litedramcore_bankmachine6_row_opened = 1'd0; +wire soc_litedramcore_bankmachine6_row_hit; +reg soc_litedramcore_bankmachine6_row_open = 1'd0; +reg soc_litedramcore_bankmachine6_row_close = 1'd0; +reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine6_twtpcon_valid; +reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trccon_valid; +reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine6_trascon_valid; +reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0; +wire soc_litedramcore_bankmachine7_req_valid; +wire soc_litedramcore_bankmachine7_req_ready; +wire soc_litedramcore_bankmachine7_req_we; +wire [20:0] soc_litedramcore_bankmachine7_req_addr; +wire soc_litedramcore_bankmachine7_req_lock; +reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire soc_litedramcore_bankmachine7_refresh_req; +reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba; +reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0; +wire soc_litedramcore_bankmachine7_sink_valid; +wire soc_litedramcore_bankmachine7_sink_ready; +reg soc_litedramcore_bankmachine7_sink_first = 1'd0; +reg soc_litedramcore_bankmachine7_sink_last = 1'd0; +wire soc_litedramcore_bankmachine7_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_sink_payload_addr; +wire soc_litedramcore_bankmachine7_source_valid; +wire soc_litedramcore_bankmachine7_source_ready; +wire soc_litedramcore_bankmachine7_source_first; +wire soc_litedramcore_bankmachine7_source_last; +wire soc_litedramcore_bankmachine7_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_source_payload_addr; +wire soc_litedramcore_bankmachine7_syncfifo7_we; +wire soc_litedramcore_bankmachine7_syncfifo7_writable; +wire soc_litedramcore_bankmachine7_syncfifo7_re; +wire soc_litedramcore_bankmachine7_syncfifo7_readable; +wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] soc_litedramcore_bankmachine7_level = 5'd0; +reg soc_litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] soc_litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_r; +wire soc_litedramcore_bankmachine7_wrport_we; +wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_w; +wire soc_litedramcore_bankmachine7_do_read; +wire [3:0] soc_litedramcore_bankmachine7_rdport_adr; +wire [23:0] soc_litedramcore_bankmachine7_rdport_dat_r; +wire soc_litedramcore_bankmachine7_fifo_in_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_in_first; +wire soc_litedramcore_bankmachine7_fifo_in_last; +wire soc_litedramcore_bankmachine7_fifo_out_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr; +wire soc_litedramcore_bankmachine7_fifo_out_first; +wire soc_litedramcore_bankmachine7_fifo_out_last; +wire soc_litedramcore_bankmachine7_sink_sink_valid; +wire soc_litedramcore_bankmachine7_sink_sink_ready; +wire soc_litedramcore_bankmachine7_sink_sink_first; +wire soc_litedramcore_bankmachine7_sink_sink_last; +wire soc_litedramcore_bankmachine7_sink_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr; +wire soc_litedramcore_bankmachine7_source_source_valid; +wire soc_litedramcore_bankmachine7_source_source_ready; +wire soc_litedramcore_bankmachine7_source_source_first; +wire soc_litedramcore_bankmachine7_source_source_last; +wire soc_litedramcore_bankmachine7_source_source_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_valid; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_first; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_last; +wire soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [20:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire soc_litedramcore_bankmachine7_pipe_valid_source_ready; +reg soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [20:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0; +reg soc_litedramcore_bankmachine7_row_opened = 1'd0; +wire soc_litedramcore_bankmachine7_row_hit; +reg soc_litedramcore_bankmachine7_row_open = 1'd0; +reg soc_litedramcore_bankmachine7_row_close = 1'd0; +reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire soc_litedramcore_bankmachine7_twtpcon_valid; +reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trccon_valid; +reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0; +wire soc_litedramcore_bankmachine7_trascon_valid; +reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0; +wire soc_litedramcore_ras_allowed; +wire soc_litedramcore_cas_allowed; +reg soc_litedramcore_choose_cmd_want_reads = 1'd0; +reg soc_litedramcore_choose_cmd_want_writes = 1'd0; +reg soc_litedramcore_choose_cmd_want_cmds = 1'd0; +reg soc_litedramcore_choose_cmd_want_activates = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_valid; +reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba; +reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd; +wire soc_litedramcore_choose_cmd_cmd_payload_is_read; +wire soc_litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_cmd_request; +reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0; +wire soc_litedramcore_choose_cmd_ce; +reg soc_litedramcore_choose_req_want_reads = 1'd0; +reg soc_litedramcore_choose_req_want_writes = 1'd0; +reg soc_litedramcore_choose_req_want_cmds = 1'd0; +reg soc_litedramcore_choose_req_want_activates = 1'd0; +wire soc_litedramcore_choose_req_cmd_valid; +reg soc_litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] soc_litedramcore_choose_req_cmd_payload_a; +wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba; +reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0; +wire soc_litedramcore_choose_req_cmd_payload_is_cmd; +wire soc_litedramcore_choose_req_cmd_payload_is_read; +wire soc_litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] soc_litedramcore_choose_req_valids = 8'd0; +wire [7:0] soc_litedramcore_choose_req_request; +reg [2:0] soc_litedramcore_choose_req_grant = 3'd0; +wire soc_litedramcore_choose_req_ce; +reg [13:0] soc_litedramcore_nop_a = 14'd0; +reg [2:0] soc_litedramcore_nop_ba = 3'd0; +reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0; +reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0; +reg soc_litedramcore_steerer0 = 1'd1; +reg soc_litedramcore_steerer1 = 1'd1; +reg soc_litedramcore_steerer2 = 1'd1; +reg soc_litedramcore_steerer3 = 1'd1; +reg soc_litedramcore_steerer4 = 1'd1; +reg soc_litedramcore_steerer5 = 1'd1; +reg soc_litedramcore_steerer6 = 1'd1; +reg soc_litedramcore_steerer7 = 1'd1; +wire soc_litedramcore_trrdcon_valid; +reg soc_litedramcore_trrdcon_ready = 1'd0; +reg soc_litedramcore_trrdcon_count = 1'd0; +wire soc_litedramcore_tfawcon_valid; +reg soc_litedramcore_tfawcon_ready = 1'd1; +wire [2:0] soc_litedramcore_tfawcon_count; +reg [4:0] soc_litedramcore_tfawcon_window = 5'd0; +wire soc_litedramcore_tccdcon_valid; +reg soc_litedramcore_tccdcon_ready = 1'd0; +reg soc_litedramcore_tccdcon_count = 1'd0; +wire soc_litedramcore_twtrcon_valid; +reg soc_litedramcore_twtrcon_ready = 1'd0; +reg [2:0] soc_litedramcore_twtrcon_count = 3'd0; +wire soc_litedramcore_read_available; +wire soc_litedramcore_write_available; +reg soc_litedramcore_en0 = 1'd0; +wire soc_litedramcore_max_time0; +reg [4:0] soc_litedramcore_time0 = 5'd0; +reg soc_litedramcore_en1 = 1'd0; +wire soc_litedramcore_max_time1; +reg [3:0] soc_litedramcore_time1 = 4'd0; +wire soc_litedramcore_go_to_refresh; +reg soc_init_done_storage = 1'd0; +reg soc_init_done_re = 1'd0; +reg soc_init_error_storage = 1'd0; +reg soc_init_error_re = 1'd0; +wire [29:0] soc_wb_bus_adr; +wire [31:0] soc_wb_bus_dat_w; +wire [31:0] soc_wb_bus_dat_r; +wire [3:0] soc_wb_bus_sel; +wire soc_wb_bus_cyc; +wire soc_wb_bus_stb; +wire soc_wb_bus_ack; +wire soc_wb_bus_we; +wire [2:0] soc_wb_bus_cti; +wire [1:0] soc_wb_bus_bte; +wire soc_wb_bus_err; +wire soc_user_enable; +wire soc_user_port_cmd_valid; +wire soc_user_port_cmd_ready; +wire soc_user_port_cmd_payload_we; +wire [23:0] soc_user_port_cmd_payload_addr; +wire soc_user_port_wdata_valid; +wire soc_user_port_wdata_ready; +wire [127:0] soc_user_port_wdata_payload_data; +wire [15:0] soc_user_port_wdata_payload_we; +wire soc_user_port_rdata_valid; +wire soc_user_port_rdata_ready; +wire [127:0] soc_user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_dfii_control0_re = 1'd0; +wire [3:0] csrbank1_dfii_control0_r; +reg csrbank1_dfii_control0_we = 1'd0; +wire [3:0] csrbank1_dfii_control0_w; +reg csrbank1_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank1_dfii_pi0_command0_r; +reg csrbank1_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank1_dfii_pi0_command0_w; +reg csrbank1_dfii_pi0_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_r; +reg csrbank1_dfii_pi0_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi0_address0_w; +reg csrbank1_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi0_baddress0_r; +reg csrbank1_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi0_baddress0_w; +reg csrbank1_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_r; +reg csrbank1_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_wrdata0_w; +reg csrbank1_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_r; +reg csrbank1_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi0_rddata_w; +reg csrbank1_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank1_dfii_pi1_command0_r; +reg csrbank1_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank1_dfii_pi1_command0_w; +reg csrbank1_dfii_pi1_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_r; +reg csrbank1_dfii_pi1_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi1_address0_w; +reg csrbank1_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi1_baddress0_r; +reg csrbank1_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi1_baddress0_w; +reg csrbank1_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_r; +reg csrbank1_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_wrdata0_w; +reg csrbank1_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_r; +reg csrbank1_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi1_rddata_w; +reg csrbank1_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank1_dfii_pi2_command0_r; +reg csrbank1_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank1_dfii_pi2_command0_w; +reg csrbank1_dfii_pi2_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_r; +reg csrbank1_dfii_pi2_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi2_address0_w; +reg csrbank1_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi2_baddress0_r; +reg csrbank1_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi2_baddress0_w; +reg csrbank1_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_r; +reg csrbank1_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_wrdata0_w; +reg csrbank1_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_r; +reg csrbank1_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi2_rddata_w; +reg csrbank1_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank1_dfii_pi3_command0_r; +reg csrbank1_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank1_dfii_pi3_command0_w; +reg csrbank1_dfii_pi3_address0_re = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_r; +reg csrbank1_dfii_pi3_address0_we = 1'd0; +wire [13:0] csrbank1_dfii_pi3_address0_w; +reg csrbank1_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank1_dfii_pi3_baddress0_r; +reg csrbank1_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank1_dfii_pi3_baddress0_w; +reg csrbank1_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_r; +reg csrbank1_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_wrdata0_w; +reg csrbank1_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_r; +reg csrbank1_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank1_dfii_pi3_rddata_w; +wire csrbank1_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +wire [24:0] slice_proxy0; +wire [24:0] slice_proxy1; +wire [24:0] slice_proxy2; +wire [24:0] slice_proxy3; +wire [24:0] slice_proxy4; +wire [24:0] slice_proxy5; +wire [24:0] slice_proxy6; +wire [24:0] slice_proxy7; +wire [24:0] slice_proxy8; +wire [24:0] slice_proxy9; +wire [24:0] slice_proxy10; +wire [24:0] slice_proxy11; +wire [24:0] slice_proxy12; +wire [24:0] slice_proxy13; +wire [24:0] slice_proxy14; +wire [24:0] slice_proxy15; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -1970,1212 +2066,1212 @@ assign sys_clk = clk; assign por_clk = clk; assign sys_rst = soc_int_rst; always @(*) begin - soc_ddrphy_activates0 <= 4'd0; - soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel0_activate_row <= 14'd0; - case (soc_ddrphy_activates0) - 1'd1: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel0_activate <= 1'd0; - case (soc_ddrphy_activates0) - 1'd1: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0); - end - 2'd2: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0); - end - 3'd4: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0); - end - 4'd8: begin - soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0); - end - endcase -end -always @(*) begin - soc_ddrphy_precharges0 <= 4'd0; - soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel0_precharge <= 1'd0; - case (soc_ddrphy_precharges0) - 1'd1: begin - soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes0 <= 4'd0; - soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write0 <= 1'd0; - case (soc_ddrphy_writes0) - 1'd1: begin - soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0); - end - 2'd2: begin - soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0); - end - 3'd4: begin - soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0); - end - 4'd8: begin - soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col0 <= 10'd0; - case (soc_ddrphy_writes0) - 1'd1: begin - soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_activates0 <= 4'd0; + soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel0_activate_row <= 14'd0; + case (soc_ddrphy_activates0) + 1'd1: begin + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel0_activate <= 1'd0; + case (soc_ddrphy_activates0) + 1'd1: begin + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +always @(*) begin + soc_ddrphy_precharges0 <= 4'd0; + soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel0_precharge <= 1'd0; + case (soc_ddrphy_precharges0) + 1'd1: begin + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes0 <= 4'd0; + soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write0 <= 1'd0; + case (soc_ddrphy_writes0) + 1'd1: begin + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col0 <= 10'd0; + case (soc_ddrphy_writes0) + 1'd1: begin + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0; assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0; always @(*) begin - soc_ddrphy_reads0 <= 4'd0; - soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel0_read <= 1'd0; - case (soc_ddrphy_reads0) - 1'd1: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0); - end - 2'd2: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0); - end - 3'd4: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0); - end - 4'd8: begin - soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel0_read_col <= 10'd0; - case (soc_ddrphy_reads0) - 1'd1: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_activates1 <= 4'd0; - soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel1_activate <= 1'd0; - case (soc_ddrphy_activates1) - 1'd1: begin - soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1); - end - 2'd2: begin - soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1); - end - 3'd4: begin - soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1); - end - 4'd8: begin - soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel1_activate_row <= 14'd0; - case (soc_ddrphy_activates1) - 1'd1: begin - soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges1 <= 4'd0; - soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel1_precharge <= 1'd0; - case (soc_ddrphy_precharges1) - 1'd1: begin - soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes1 <= 4'd0; - soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write1 <= 1'd0; - case (soc_ddrphy_writes1) - 1'd1: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1); - end - 2'd2: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1); - end - 3'd4: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1); - end - 4'd8: begin - soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col1 <= 10'd0; - case (soc_ddrphy_writes1) - 1'd1: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads0 <= 4'd0; + soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel0_read <= 1'd0; + case (soc_ddrphy_reads0) + 1'd1: begin + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel0_read_col <= 10'd0; + case (soc_ddrphy_reads0) + 1'd1: begin + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates1 <= 4'd0; + soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel1_activate <= 1'd0; + case (soc_ddrphy_activates1) + 1'd1: begin + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel1_activate_row <= 14'd0; + case (soc_ddrphy_activates1) + 1'd1: begin + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges1 <= 4'd0; + soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel1_precharge <= 1'd0; + case (soc_ddrphy_precharges1) + 1'd1: begin + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes1 <= 4'd0; + soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write1 <= 1'd0; + case (soc_ddrphy_writes1) + 1'd1: begin + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col1 <= 10'd0; + case (soc_ddrphy_writes1) + 1'd1: begin + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1; assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1; always @(*) begin - soc_ddrphy_reads1 <= 4'd0; - soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel1_read_col <= 10'd0; - case (soc_ddrphy_reads1) - 1'd1: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel1_read <= 1'd0; - case (soc_ddrphy_reads1) - 1'd1: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1); - end - 2'd2: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1); - end - 3'd4: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1); - end - 4'd8: begin - soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1); - end - endcase -end -always @(*) begin - soc_ddrphy_activates2 <= 4'd0; - soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel2_activate <= 1'd0; - case (soc_ddrphy_activates2) - 1'd1: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2); - end - 2'd2: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2); - end - 3'd4: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2); - end - 4'd8: begin - soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel2_activate_row <= 14'd0; - case (soc_ddrphy_activates2) - 1'd1: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges2 <= 4'd0; - soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel2_precharge <= 1'd0; - case (soc_ddrphy_precharges2) - 1'd1: begin - soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes2 <= 4'd0; - soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write_col2 <= 10'd0; - case (soc_ddrphy_writes2) - 1'd1: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write2 <= 1'd0; - case (soc_ddrphy_writes2) - 1'd1: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2); - end - 2'd2: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2); - end - 3'd4: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2); - end - 4'd8: begin - soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2); - end - endcase + soc_ddrphy_reads1 <= 4'd0; + soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel1_read_col <= 10'd0; + case (soc_ddrphy_reads1) + 1'd1: begin + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel1_read <= 1'd0; + case (soc_ddrphy_reads1) + 1'd1: begin + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + soc_ddrphy_activates2 <= 4'd0; + soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel2_activate <= 1'd0; + case (soc_ddrphy_activates2) + 1'd1: begin + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel2_activate_row <= 14'd0; + case (soc_ddrphy_activates2) + 1'd1: begin + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges2 <= 4'd0; + soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel2_precharge <= 1'd0; + case (soc_ddrphy_precharges2) + 1'd1: begin + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes2 <= 4'd0; + soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write_col2 <= 10'd0; + case (soc_ddrphy_writes2) + 1'd1: begin + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write2 <= 1'd0; + case (soc_ddrphy_writes2) + 1'd1: begin + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2); + end + endcase end assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2; assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2; always @(*) begin - soc_ddrphy_reads2 <= 4'd0; - soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel2_read <= 1'd0; - case (soc_ddrphy_reads2) - 1'd1: begin - soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2); - end - 2'd2: begin - soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2); - end - 3'd4: begin - soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2); - end - 4'd8: begin - soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel2_read_col <= 10'd0; - case (soc_ddrphy_reads2) - 1'd1: begin - soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_activates3 <= 4'd0; - soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel3_activate_row <= 14'd0; - case (soc_ddrphy_activates3) - 1'd1: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel3_activate <= 1'd0; - case (soc_ddrphy_activates3) - 1'd1: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3); - end - 2'd2: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3); - end - 3'd4: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3); - end - 4'd8: begin - soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3); - end - endcase -end -always @(*) begin - soc_ddrphy_precharges3 <= 4'd0; - soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel3_precharge <= 1'd0; - case (soc_ddrphy_precharges3) - 1'd1: begin - soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes3 <= 4'd0; - soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write3 <= 1'd0; - case (soc_ddrphy_writes3) - 1'd1: begin - soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3); - end - 2'd2: begin - soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3); - end - 3'd4: begin - soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3); - end - 4'd8: begin - soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col3 <= 10'd0; - case (soc_ddrphy_writes3) - 1'd1: begin - soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads2 <= 4'd0; + soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel2_read <= 1'd0; + case (soc_ddrphy_reads2) + 1'd1: begin + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel2_read_col <= 10'd0; + case (soc_ddrphy_reads2) + 1'd1: begin + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates3 <= 4'd0; + soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel3_activate_row <= 14'd0; + case (soc_ddrphy_activates3) + 1'd1: begin + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel3_activate <= 1'd0; + case (soc_ddrphy_activates3) + 1'd1: begin + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + soc_ddrphy_precharges3 <= 4'd0; + soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel3_precharge <= 1'd0; + case (soc_ddrphy_precharges3) + 1'd1: begin + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes3 <= 4'd0; + soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write3 <= 1'd0; + case (soc_ddrphy_writes3) + 1'd1: begin + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col3 <= 10'd0; + case (soc_ddrphy_writes3) + 1'd1: begin + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3; assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3; always @(*) begin - soc_ddrphy_reads3 <= 4'd0; - soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel3_read <= 1'd0; - case (soc_ddrphy_reads3) - 1'd1: begin - soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3); - end - 2'd2: begin - soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3); - end - 3'd4: begin - soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3); - end - 4'd8: begin - soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel3_read_col <= 10'd0; - case (soc_ddrphy_reads3) - 1'd1: begin - soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_activates4 <= 4'd0; - soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel4_activate <= 1'd0; - case (soc_ddrphy_activates4) - 1'd1: begin - soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4); - end - 2'd2: begin - soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4); - end - 3'd4: begin - soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4); - end - 4'd8: begin - soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel4_activate_row <= 14'd0; - case (soc_ddrphy_activates4) - 1'd1: begin - soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges4 <= 4'd0; - soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel4_precharge <= 1'd0; - case (soc_ddrphy_precharges4) - 1'd1: begin - soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes4 <= 4'd0; - soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write4 <= 1'd0; - case (soc_ddrphy_writes4) - 1'd1: begin - soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4); - end - 2'd2: begin - soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4); - end - 3'd4: begin - soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4); - end - 4'd8: begin - soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col4 <= 10'd0; - case (soc_ddrphy_writes4) - 1'd1: begin - soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads3 <= 4'd0; + soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel3_read <= 1'd0; + case (soc_ddrphy_reads3) + 1'd1: begin + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel3_read_col <= 10'd0; + case (soc_ddrphy_reads3) + 1'd1: begin + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates4 <= 4'd0; + soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel4_activate <= 1'd0; + case (soc_ddrphy_activates4) + 1'd1: begin + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel4_activate_row <= 14'd0; + case (soc_ddrphy_activates4) + 1'd1: begin + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges4 <= 4'd0; + soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel4_precharge <= 1'd0; + case (soc_ddrphy_precharges4) + 1'd1: begin + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes4 <= 4'd0; + soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write4 <= 1'd0; + case (soc_ddrphy_writes4) + 1'd1: begin + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col4 <= 10'd0; + case (soc_ddrphy_writes4) + 1'd1: begin + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4; assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4; always @(*) begin - soc_ddrphy_reads4 <= 4'd0; - soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel4_read <= 1'd0; - case (soc_ddrphy_reads4) - 1'd1: begin - soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4); - end - 2'd2: begin - soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4); - end - 3'd4: begin - soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4); - end - 4'd8: begin - soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel4_read_col <= 10'd0; - case (soc_ddrphy_reads4) - 1'd1: begin - soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_activates5 <= 4'd0; - soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel5_activate <= 1'd0; - case (soc_ddrphy_activates5) - 1'd1: begin - soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5); - end - 2'd2: begin - soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5); - end - 3'd4: begin - soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5); - end - 4'd8: begin - soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel5_activate_row <= 14'd0; - case (soc_ddrphy_activates5) - 1'd1: begin - soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges5 <= 4'd0; - soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel5_precharge <= 1'd0; - case (soc_ddrphy_precharges5) - 1'd1: begin - soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes5 <= 4'd0; - soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write5 <= 1'd0; - case (soc_ddrphy_writes5) - 1'd1: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5); - end - 2'd2: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5); - end - 3'd4: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5); - end - 4'd8: begin - soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col5 <= 10'd0; - case (soc_ddrphy_writes5) - 1'd1: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads4 <= 4'd0; + soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel4_read <= 1'd0; + case (soc_ddrphy_reads4) + 1'd1: begin + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel4_read_col <= 10'd0; + case (soc_ddrphy_reads4) + 1'd1: begin + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates5 <= 4'd0; + soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel5_activate <= 1'd0; + case (soc_ddrphy_activates5) + 1'd1: begin + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel5_activate_row <= 14'd0; + case (soc_ddrphy_activates5) + 1'd1: begin + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges5 <= 4'd0; + soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel5_precharge <= 1'd0; + case (soc_ddrphy_precharges5) + 1'd1: begin + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes5 <= 4'd0; + soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write5 <= 1'd0; + case (soc_ddrphy_writes5) + 1'd1: begin + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col5 <= 10'd0; + case (soc_ddrphy_writes5) + 1'd1: begin + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5; assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5; always @(*) begin - soc_ddrphy_reads5 <= 4'd0; - soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel5_read <= 1'd0; - case (soc_ddrphy_reads5) - 1'd1: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5); - end - 2'd2: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5); - end - 3'd4: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5); - end - 4'd8: begin - soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel5_read_col <= 10'd0; - case (soc_ddrphy_reads5) - 1'd1: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_activates6 <= 4'd0; - soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel6_activate <= 1'd0; - case (soc_ddrphy_activates6) - 1'd1: begin - soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6); - end - 2'd2: begin - soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6); - end - 3'd4: begin - soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6); - end - 4'd8: begin - soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel6_activate_row <= 14'd0; - case (soc_ddrphy_activates6) - 1'd1: begin - soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges6 <= 4'd0; - soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel6_precharge <= 1'd0; - case (soc_ddrphy_precharges6) - 1'd1: begin - soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes6 <= 4'd0; - soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write_col6 <= 10'd0; - case (soc_ddrphy_writes6) - 1'd1: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write6 <= 1'd0; - case (soc_ddrphy_writes6) - 1'd1: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6); - end - 2'd2: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6); - end - 3'd4: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6); - end - 4'd8: begin - soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6); - end - endcase + soc_ddrphy_reads5 <= 4'd0; + soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel5_read <= 1'd0; + case (soc_ddrphy_reads5) + 1'd1: begin + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel5_read_col <= 10'd0; + case (soc_ddrphy_reads5) + 1'd1: begin + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_activates6 <= 4'd0; + soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel6_activate <= 1'd0; + case (soc_ddrphy_activates6) + 1'd1: begin + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel6_activate_row <= 14'd0; + case (soc_ddrphy_activates6) + 1'd1: begin + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges6 <= 4'd0; + soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel6_precharge <= 1'd0; + case (soc_ddrphy_precharges6) + 1'd1: begin + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes6 <= 4'd0; + soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write_col6 <= 10'd0; + case (soc_ddrphy_writes6) + 1'd1: begin + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write6 <= 1'd0; + case (soc_ddrphy_writes6) + 1'd1: begin + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6); + end + endcase end assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6; assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6; always @(*) begin - soc_ddrphy_reads6 <= 4'd0; - soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel6_read_col <= 10'd0; - case (soc_ddrphy_reads6) - 1'd1: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel6_read <= 1'd0; - case (soc_ddrphy_reads6) - 1'd1: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6); - end - 2'd2: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6); - end - 3'd4: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6); - end - 4'd8: begin - soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6); - end - endcase -end -always @(*) begin - soc_ddrphy_activates7 <= 4'd0; - soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate; - soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate; - soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate; - soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate; -end -always @(*) begin - soc_ddrphy_bankmodel7_activate <= 1'd0; - case (soc_ddrphy_activates7) - 1'd1: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7); - end - 2'd2: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7); - end - 3'd4: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7); - end - 4'd8: begin - soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel7_activate_row <= 14'd0; - case (soc_ddrphy_activates7) - 1'd1: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address; - end - endcase -end -always @(*) begin - soc_ddrphy_precharges7 <= 4'd0; - soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge; - soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge; - soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge; - soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge; -end -always @(*) begin - soc_ddrphy_bankmodel7_precharge <= 1'd0; - case (soc_ddrphy_precharges7) - 1'd1: begin - soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); - end - 2'd2: begin - soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); - end - 3'd4: begin - soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); - end - 4'd8: begin - soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); - end - endcase -end -always @(*) begin - soc_ddrphy_writes7 <= 4'd0; - soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write; - soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write; - soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write; - soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write; -end -always @(*) begin - soc_ddrphy_bank_write7 <= 1'd0; - case (soc_ddrphy_writes7) - 1'd1: begin - soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7); - end - 2'd2: begin - soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7); - end - 3'd4: begin - soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7); - end - 4'd8: begin - soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7); - end - endcase -end -always @(*) begin - soc_ddrphy_bank_write_col7 <= 10'd0; - case (soc_ddrphy_writes7) - 1'd1: begin - soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads6 <= 4'd0; + soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel6_read_col <= 10'd0; + case (soc_ddrphy_reads6) + 1'd1: begin + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel6_read <= 1'd0; + case (soc_ddrphy_reads6) + 1'd1: begin + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6); + end + endcase +end +always @(*) begin + soc_ddrphy_activates7 <= 4'd0; + soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate; + soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate; + soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate; + soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + soc_ddrphy_bankmodel7_activate <= 1'd0; + case (soc_ddrphy_activates7) + 1'd1: begin + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel7_activate_row <= 14'd0; + case (soc_ddrphy_activates7) + 1'd1: begin + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + soc_ddrphy_precharges7 <= 4'd0; + soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge; + soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge; + soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge; + soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + soc_ddrphy_bankmodel7_precharge <= 1'd0; + case (soc_ddrphy_precharges7) + 1'd1: begin + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + soc_ddrphy_writes7 <= 4'd0; + soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write; + soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write; + soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write; + soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write; +end +always @(*) begin + soc_ddrphy_bank_write7 <= 1'd0; + case (soc_ddrphy_writes7) + 1'd1: begin + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + soc_ddrphy_bank_write_col7 <= 10'd0; + case (soc_ddrphy_writes7) + 1'd1: begin + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata}; assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask}; assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7; assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7; always @(*) begin - soc_ddrphy_reads7 <= 4'd0; - soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read; - soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read; - soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read; - soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read; -end -always @(*) begin - soc_ddrphy_bankmodel7_read <= 1'd0; - case (soc_ddrphy_reads7) - 1'd1: begin - soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7); - end - 2'd2: begin - soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7); - end - 3'd4: begin - soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7); - end - 4'd8: begin - soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7); - end - endcase -end -always @(*) begin - soc_ddrphy_bankmodel7_read_col <= 10'd0; - case (soc_ddrphy_reads7) - 1'd1: begin - soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address; - end - 2'd2: begin - soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address; - end - 3'd4: begin - soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address; - end - 4'd8: begin - soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address; - end - endcase + soc_ddrphy_reads7 <= 4'd0; + soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read; + soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read; + soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read; + soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read; +end +always @(*) begin + soc_ddrphy_bankmodel7_read <= 1'd0; + case (soc_ddrphy_reads7) + 1'd1: begin + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + soc_ddrphy_bankmodel7_read_col <= 10'd0; + case (soc_ddrphy_reads7) + 1'd1: begin + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address; + end + 2'd2: begin + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address; + end + 3'd4: begin + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address; + end + 4'd8: begin + soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address; + end + endcase end assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read); assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data); @@ -3188,420 +3284,420 @@ assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rd assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7; always @(*) begin - soc_ddrphy_dfiphasemodel0_precharge <= 1'd0; - if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n); - end + soc_ddrphy_dfiphasemodel0_precharge <= 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin + soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel0_activate <= 1'd0; - if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin - soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n; - end + soc_ddrphy_dfiphasemodel0_activate <= 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin + soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel0_write <= 1'd0; - if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin - soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n); - end + soc_ddrphy_dfiphasemodel0_write <= 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin + soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel0_read <= 1'd0; - if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin - soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n; - end + soc_ddrphy_dfiphasemodel0_read <= 1'd0; + if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin + soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel1_activate <= 1'd0; - if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin - soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n; - end + soc_ddrphy_dfiphasemodel1_activate <= 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin + soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel1_precharge <= 1'd0; - if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin - soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n); - end + soc_ddrphy_dfiphasemodel1_precharge <= 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin + soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel1_write <= 1'd0; - if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n); - end + soc_ddrphy_dfiphasemodel1_write <= 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin + soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel1_read <= 1'd0; - if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin - soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n; - end + soc_ddrphy_dfiphasemodel1_read <= 1'd0; + if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin + soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel2_activate <= 1'd0; - if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin - soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n; - end + soc_ddrphy_dfiphasemodel2_activate <= 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin + soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel2_precharge <= 1'd0; - if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin - soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n); - end + soc_ddrphy_dfiphasemodel2_precharge <= 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin + soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel2_read <= 1'd0; - if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n; - end + soc_ddrphy_dfiphasemodel2_read <= 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin + soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel2_write <= 1'd0; - if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin - soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n); - end + soc_ddrphy_dfiphasemodel2_write <= 1'd0; + if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin + soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel3_activate <= 1'd0; - if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n; - end + soc_ddrphy_dfiphasemodel3_activate <= 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin + soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n; + end end always @(*) begin - soc_ddrphy_dfiphasemodel3_precharge <= 1'd0; - if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin - soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n); - end + soc_ddrphy_dfiphasemodel3_precharge <= 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin + soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel3_write <= 1'd0; - if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin - soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n); - end + soc_ddrphy_dfiphasemodel3_write <= 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin + soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n); + end end always @(*) begin - soc_ddrphy_dfiphasemodel3_read <= 1'd0; - if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin - soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n; - end + soc_ddrphy_dfiphasemodel3_read <= 1'd0; + if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin + soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n; + end end assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; always @(*) begin - soc_ddrphy_bankmodel0_read_data <= 128'd0; - if (soc_ddrphy_bankmodel0_active) begin - if (soc_ddrphy_bankmodel0_read) begin - soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r; - end - end + soc_ddrphy_bankmodel0_read_data <= 128'd0; + if (soc_ddrphy_bankmodel0_active) begin + if (soc_ddrphy_bankmodel0_read) begin + soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel0_active) begin - soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr; - end + soc_ddrphy_bankmodel0_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel0_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); - end else begin - soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write; - end - end + soc_ddrphy_bankmodel0_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel0_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask)); + end else begin + soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel0_active) begin - soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data; - end + soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel0_active) begin + soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel0_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel0_active) begin - if (soc_ddrphy_bankmodel0_read) begin - soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr; - end - end + soc_ddrphy_bankmodel0_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel0_active) begin + if (soc_ddrphy_bankmodel0_read) begin + soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr; + end + end end assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; always @(*) begin - soc_ddrphy_bankmodel1_read_data <= 128'd0; - if (soc_ddrphy_bankmodel1_active) begin - if (soc_ddrphy_bankmodel1_read) begin - soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r; - end - end + soc_ddrphy_bankmodel1_read_data <= 128'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel1_active) begin - soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr; - end + soc_ddrphy_bankmodel1_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel1_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); - end else begin - soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write; - end - end + soc_ddrphy_bankmodel1_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask)); + end else begin + soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel1_active) begin - soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data; - end + soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel1_active) begin + soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel1_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel1_active) begin - if (soc_ddrphy_bankmodel1_read) begin - soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr; - end - end + soc_ddrphy_bankmodel1_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel1_active) begin + if (soc_ddrphy_bankmodel1_read) begin + soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr; + end + end end assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; always @(*) begin - soc_ddrphy_bankmodel2_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel2_active) begin - soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr; - end + soc_ddrphy_bankmodel2_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel2_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel2_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); - end else begin - soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write; - end - end + soc_ddrphy_bankmodel2_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel2_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask)); + end else begin + soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel2_active) begin - soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data; - end + soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel2_active) begin + soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel2_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel2_active) begin - if (soc_ddrphy_bankmodel2_read) begin - soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr; - end - end + soc_ddrphy_bankmodel2_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel2_active) begin + if (soc_ddrphy_bankmodel2_read) begin + soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr; + end + end end always @(*) begin - soc_ddrphy_bankmodel2_read_data <= 128'd0; - if (soc_ddrphy_bankmodel2_active) begin - if (soc_ddrphy_bankmodel2_read) begin - soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r; - end - end + soc_ddrphy_bankmodel2_read_data <= 128'd0; + if (soc_ddrphy_bankmodel2_active) begin + if (soc_ddrphy_bankmodel2_read) begin + soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r; + end + end end assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; always @(*) begin - soc_ddrphy_bankmodel3_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel3_active) begin - soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr; - end + soc_ddrphy_bankmodel3_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel3_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel3_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); - end else begin - soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write; - end - end + soc_ddrphy_bankmodel3_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask)); + end else begin + soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel3_active) begin - soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data; - end + soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel3_active) begin + soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel3_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel3_active) begin - if (soc_ddrphy_bankmodel3_read) begin - soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr; - end - end + soc_ddrphy_bankmodel3_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (soc_ddrphy_bankmodel3_read) begin + soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr; + end + end end always @(*) begin - soc_ddrphy_bankmodel3_read_data <= 128'd0; - if (soc_ddrphy_bankmodel3_active) begin - if (soc_ddrphy_bankmodel3_read) begin - soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r; - end - end + soc_ddrphy_bankmodel3_read_data <= 128'd0; + if (soc_ddrphy_bankmodel3_active) begin + if (soc_ddrphy_bankmodel3_read) begin + soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r; + end + end end assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; always @(*) begin - soc_ddrphy_bankmodel4_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel4_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); - end else begin - soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write; - end - end + soc_ddrphy_bankmodel4_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask)); + end else begin + soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel4_active) begin - soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data; - end + soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel4_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel4_active) begin - if (soc_ddrphy_bankmodel4_read) begin - soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr; - end - end + soc_ddrphy_bankmodel4_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr; + end + end end always @(*) begin - soc_ddrphy_bankmodel4_read_data <= 128'd0; - if (soc_ddrphy_bankmodel4_active) begin - if (soc_ddrphy_bankmodel4_read) begin - soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r; - end - end + soc_ddrphy_bankmodel4_read_data <= 128'd0; + if (soc_ddrphy_bankmodel4_active) begin + if (soc_ddrphy_bankmodel4_read) begin + soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel4_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel4_active) begin - soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr; - end + soc_ddrphy_bankmodel4_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel4_active) begin + soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr; + end end assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; always @(*) begin - soc_ddrphy_bankmodel5_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel5_active) begin - if (soc_ddrphy_bankmodel5_read) begin - soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr; - end - end + soc_ddrphy_bankmodel5_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr; + end + end end always @(*) begin - soc_ddrphy_bankmodel5_read_data <= 128'd0; - if (soc_ddrphy_bankmodel5_active) begin - if (soc_ddrphy_bankmodel5_read) begin - soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r; - end - end + soc_ddrphy_bankmodel5_read_data <= 128'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (soc_ddrphy_bankmodel5_read) begin + soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel5_active) begin - soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr; - end + soc_ddrphy_bankmodel5_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel5_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); - end else begin - soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write; - end - end + soc_ddrphy_bankmodel5_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel5_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask)); + end else begin + soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel5_active) begin - soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data; - end + soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel5_active) begin + soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data; + end end assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; always @(*) begin - soc_ddrphy_bankmodel6_read_data <= 128'd0; - if (soc_ddrphy_bankmodel6_active) begin - if (soc_ddrphy_bankmodel6_read) begin - soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r; - end - end + soc_ddrphy_bankmodel6_read_data <= 128'd0; + if (soc_ddrphy_bankmodel6_active) begin + if (soc_ddrphy_bankmodel6_read) begin + soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel6_active) begin - soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr; - end + soc_ddrphy_bankmodel6_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel6_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); - end else begin - soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write; - end - end + soc_ddrphy_bankmodel6_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel6_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask)); + end else begin + soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel6_active) begin - soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data; - end + soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel6_active) begin + soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel6_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel6_active) begin - if (soc_ddrphy_bankmodel6_read) begin - soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr; - end - end + soc_ddrphy_bankmodel6_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel6_active) begin + if (soc_ddrphy_bankmodel6_read) begin + soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr; + end + end end assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; always @(*) begin - soc_ddrphy_bankmodel7_read_data <= 128'd0; - if (soc_ddrphy_bankmodel7_active) begin - if (soc_ddrphy_bankmodel7_read) begin - soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r; - end - end + soc_ddrphy_bankmodel7_read_data <= 128'd0; + if (soc_ddrphy_bankmodel7_active) begin + if (soc_ddrphy_bankmodel7_read) begin + soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r; + end + end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel7_active) begin - soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr; - end + soc_ddrphy_bankmodel7_write_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr; + end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_we <= 16'd0; - if (soc_ddrphy_bankmodel7_active) begin - if (4'd8) begin - soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); - end else begin - soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write; - end - end + soc_ddrphy_bankmodel7_write_port_we <= 16'd0; + if (soc_ddrphy_bankmodel7_active) begin + if (4'd8) begin + soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask)); + end else begin + soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write; + end + end end always @(*) begin - soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0; - if (soc_ddrphy_bankmodel7_active) begin - soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data; - end + soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0; + if (soc_ddrphy_bankmodel7_active) begin + soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data; + end end always @(*) begin - soc_ddrphy_bankmodel7_read_port_adr <= 21'd0; - if (soc_ddrphy_bankmodel7_active) begin - if (soc_ddrphy_bankmodel7_read) begin - soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr; - end - end + soc_ddrphy_bankmodel7_read_port_adr <= 21'd0; + if (soc_ddrphy_bankmodel7_active) begin + if (soc_ddrphy_bankmodel7_read) begin + soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr; + end + end end assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address; assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank; @@ -3732,892 +3828,892 @@ assign soc_litedramcore_slave_p3_rddata_en = soc_litedramcore_dfi_p3_rddata_en; assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata; assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid; always @(*) begin - soc_litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_master_p0_address <= 14'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address; - end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; - end - end else begin - soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - soc_litedramcore_master_p0_bank <= 3'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank; - end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; - end - end else begin - soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - soc_litedramcore_master_p0_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n; - end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; - end - end else begin - soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n; - end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; - end - end else begin - soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n; - end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; - end - end else begin - soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n; - end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; - end - end else begin - soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_cke <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke; - end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; - end - end else begin - soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - soc_litedramcore_master_p0_odt <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt; - end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; - end - end else begin - soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - soc_litedramcore_master_p0_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n; - end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; - end - end else begin - soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n; - end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; - end - end else begin - soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - soc_litedramcore_master_p0_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata; - end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; - end - end else begin - soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - soc_litedramcore_master_p0_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en; - end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; - end - end else begin - soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - soc_litedramcore_master_p0_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; - end - end else begin - soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - soc_litedramcore_master_p0_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en; - end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; - end - end else begin - soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - soc_litedramcore_master_p1_address <= 14'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address; - end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; - end - end else begin - soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - soc_litedramcore_master_p1_bank <= 3'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank; - end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; - end - end else begin - soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - soc_litedramcore_master_p1_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n; - end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; - end - end else begin - soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n; - end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; - end - end else begin - soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n; - end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; - end - end else begin - soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n; - end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; - end - end else begin - soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_cke <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke; - end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; - end - end else begin - soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - soc_litedramcore_master_p1_odt <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt; - end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; - end - end else begin - soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - soc_litedramcore_master_p1_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n; - end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; - end - end else begin - soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n; - end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; - end - end else begin - soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - soc_litedramcore_master_p1_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata; - end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; - end - end else begin - soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - soc_litedramcore_master_p1_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en; - end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; - end - end else begin - soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - soc_litedramcore_master_p1_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; - end - end else begin - soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - soc_litedramcore_master_p1_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en; - end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; - end - end else begin - soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - soc_litedramcore_master_p2_address <= 14'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address; - end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; - end - end else begin - soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - soc_litedramcore_master_p2_bank <= 3'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank; - end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; - end - end else begin - soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - soc_litedramcore_master_p2_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n; - end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; - end - end else begin - soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n; - end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; - end - end else begin - soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n; - end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; - end - end else begin - soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n; - end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; - end - end else begin - soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_cke <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke; - end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; - end - end else begin - soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - soc_litedramcore_master_p2_odt <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt; - end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; - end - end else begin - soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - soc_litedramcore_master_p2_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n; - end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; - end - end else begin - soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n; - end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; - end - end else begin - soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - soc_litedramcore_master_p2_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata; - end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; - end - end else begin - soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - soc_litedramcore_master_p2_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en; - end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; - end - end else begin - soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - soc_litedramcore_master_p2_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; - end - end else begin - soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - soc_litedramcore_master_p2_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en; - end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; - end - end else begin - soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - soc_litedramcore_master_p3_address <= 14'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address; - end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; - end - end else begin - soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - soc_litedramcore_master_p3_bank <= 3'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank; - end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; - end - end else begin - soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - soc_litedramcore_master_p3_cas_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n; - end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; - end - end else begin - soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_cs_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n; - end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; - end - end else begin - soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_ras_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n; - end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; - end - end else begin - soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_we_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n; - end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; - end - end else begin - soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_cke <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke; - end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; - end - end else begin - soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - soc_litedramcore_master_p3_odt <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt; - end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; - end - end else begin - soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - soc_litedramcore_master_p3_reset_n <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n; - end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; - end - end else begin - soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_act_n <= 1'd1; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n; - end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; - end - end else begin - soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - soc_litedramcore_master_p3_wrdata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata; - end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; - end - end else begin - soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - soc_litedramcore_master_p3_wrdata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en; - end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; - end - end else begin - soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - soc_litedramcore_master_p3_wrdata_mask <= 4'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; - end - end else begin - soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - soc_litedramcore_master_p3_rddata_en <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en; - end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; - end - end else begin - soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata; - end -end -always @(*) begin - soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - end else begin - soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p0_rddata <= 32'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - soc_litedramcore_slave_p0_rddata_valid <= 1'd0; - if (soc_litedramcore_sel) begin - if (soc_litedramcore_ext_dfi_sel) begin - end else begin - soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; - end - end else begin - end + soc_litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p1_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p2_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p3_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_master_p0_address <= 14'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address; + end else begin + soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address; + end + end else begin + soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + soc_litedramcore_master_p0_bank <= 3'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank; + end else begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank; + end + end else begin + soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + soc_litedramcore_master_p0_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n; + end else begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n; + end + end else begin + soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n; + end else begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n; + end + end else begin + soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n; + end else begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n; + end + end else begin + soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n; + end else begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n; + end + end else begin + soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_cke <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke; + end else begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke; + end + end else begin + soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + soc_litedramcore_master_p0_odt <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt; + end else begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt; + end + end else begin + soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + soc_litedramcore_master_p0_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n; + end else begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n; + end + end else begin + soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n; + end else begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n; + end + end else begin + soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + soc_litedramcore_master_p0_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata; + end else begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata; + end + end else begin + soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + soc_litedramcore_master_p0_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en; + end else begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en; + end + end else begin + soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + soc_litedramcore_master_p0_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask; + end + end else begin + soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + soc_litedramcore_master_p0_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en; + end else begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en; + end + end else begin + soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + soc_litedramcore_master_p1_address <= 14'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address; + end else begin + soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address; + end + end else begin + soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + soc_litedramcore_master_p1_bank <= 3'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank; + end else begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank; + end + end else begin + soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + soc_litedramcore_master_p1_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n; + end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n; + end + end else begin + soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n; + end else begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n; + end + end else begin + soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n; + end else begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n; + end + end else begin + soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n; + end else begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n; + end + end else begin + soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_cke <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke; + end else begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke; + end + end else begin + soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + soc_litedramcore_master_p1_odt <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt; + end else begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt; + end + end else begin + soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + soc_litedramcore_master_p1_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n; + end else begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n; + end + end else begin + soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n; + end else begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n; + end + end else begin + soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + soc_litedramcore_master_p1_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata; + end else begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata; + end + end else begin + soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + soc_litedramcore_master_p1_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en; + end else begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en; + end + end else begin + soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + soc_litedramcore_master_p1_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask; + end + end else begin + soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + soc_litedramcore_master_p1_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en; + end else begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en; + end + end else begin + soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + soc_litedramcore_master_p2_address <= 14'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address; + end else begin + soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address; + end + end else begin + soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + soc_litedramcore_master_p2_bank <= 3'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank; + end else begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank; + end + end else begin + soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + soc_litedramcore_master_p2_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n; + end else begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n; + end + end else begin + soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n; + end else begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n; + end + end else begin + soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n; + end else begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n; + end + end else begin + soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n; + end else begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n; + end + end else begin + soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_cke <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke; + end else begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke; + end + end else begin + soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + soc_litedramcore_master_p2_odt <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt; + end else begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt; + end + end else begin + soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + soc_litedramcore_master_p2_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n; + end else begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n; + end + end else begin + soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n; + end else begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n; + end + end else begin + soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + soc_litedramcore_master_p2_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata; + end else begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata; + end + end else begin + soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + soc_litedramcore_master_p2_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en; + end else begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en; + end + end else begin + soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + soc_litedramcore_master_p2_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask; + end + end else begin + soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + soc_litedramcore_master_p2_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en; + end else begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en; + end + end else begin + soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + soc_litedramcore_master_p3_address <= 14'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address; + end else begin + soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address; + end + end else begin + soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + soc_litedramcore_master_p3_bank <= 3'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank; + end else begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank; + end + end else begin + soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + soc_litedramcore_master_p3_cas_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n; + end else begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n; + end + end else begin + soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_cs_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n; + end else begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n; + end + end else begin + soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_ras_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n; + end else begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n; + end + end else begin + soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_we_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n; + end else begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n; + end + end else begin + soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_cke <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke; + end else begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke; + end + end else begin + soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + soc_litedramcore_master_p3_odt <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt; + end else begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt; + end + end else begin + soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + soc_litedramcore_master_p3_reset_n <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n; + end else begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n; + end + end else begin + soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_act_n <= 1'd1; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n; + end else begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n; + end + end else begin + soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + soc_litedramcore_master_p3_wrdata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata; + end else begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata; + end + end else begin + soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + soc_litedramcore_master_p3_wrdata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en; + end else begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en; + end + end else begin + soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + soc_litedramcore_master_p3_wrdata_mask <= 4'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask; + end + end else begin + soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + soc_litedramcore_master_p3_rddata_en <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en; + end else begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en; + end + end else begin + soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata; + end +end +always @(*) begin + soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + end else begin + soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p0_rddata <= 32'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + soc_litedramcore_slave_p0_rddata_valid <= 1'd0; + if (soc_litedramcore_sel) begin + if (soc_litedramcore_ext_dfi_sel) begin + end else begin + soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid; + end + end else begin + end end assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke; assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke; @@ -4632,36 +4728,36 @@ assign soc_litedramcore_csr_dfi_p1_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n; assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n; always @(*) begin - soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras); - end else begin - soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras); + end else begin + soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we); - end else begin - soc_litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we); + end else begin + soc_litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector0_command_issue_re) begin - soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector0_command_issue_re) begin + soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage; assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage; @@ -4670,36 +4766,36 @@ assign soc_litedramcore_csr_dfi_p0_rddata_en = (soc_litedramcore_phaseinjector0_ assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage; assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras); - end else begin - soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras); + end else begin + soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we); - end else begin - soc_litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we); + end else begin + soc_litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector1_command_issue_re) begin - soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector1_command_issue_re) begin + soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage; assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage; @@ -4708,36 +4804,36 @@ assign soc_litedramcore_csr_dfi_p1_rddata_en = (soc_litedramcore_phaseinjector1_ assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage; assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end always @(*) begin - soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras); - end else begin - soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras); + end else begin + soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we); - end else begin - soc_litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we); + end else begin + soc_litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector2_command_issue_re) begin - soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector2_command_issue_re) begin + soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage; assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage; @@ -4746,36 +4842,36 @@ assign soc_litedramcore_csr_dfi_p2_rddata_en = (soc_litedramcore_phaseinjector2_ assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage; assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end always @(*) begin - soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras); - end else begin - soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras); + end else begin + soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we); - end else begin - soc_litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we); + end else begin + soc_litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end always @(*) begin - soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (soc_litedramcore_phaseinjector3_command_issue_re) begin - soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas); - end else begin - soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (soc_litedramcore_phaseinjector3_command_issue_re) begin + soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas); + end else begin + soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage; assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage; @@ -4853,4590 +4949,4686 @@ assign soc_litedramcore_zqcs_timer_done1 = (soc_litedramcore_zqcs_timer_count1 = assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1; assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (soc_litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (soc_litedramcore_cmd_ready) begin - soc_litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - soc_litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - soc_litedramcore_cmd_valid <= 1'd1; - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - soc_litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (soc_litedramcore_sequencer_done0) begin - if (soc_litedramcore_wants_zqcs) begin - end else begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (soc_litedramcore_zqcs_executer_done) begin - soc_litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid; -assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); -assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (soc_litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (soc_litedramcore_cmd_ready) begin + soc_litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + soc_litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + soc_litedramcore_cmd_valid <= 1'd1; + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + soc_litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (soc_litedramcore_sequencer_done0) begin + if (soc_litedramcore_wants_zqcs) begin + end else begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (soc_litedramcore_zqcs_executer_done) begin + soc_litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +assign soc_litedramcore_bankmachine0_sink_valid = soc_litedramcore_bankmachine0_req_valid; +assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_sink_ready; +assign soc_litedramcore_bankmachine0_sink_payload_we = soc_litedramcore_bankmachine0_req_we; +assign soc_litedramcore_bankmachine0_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr; +assign soc_litedramcore_bankmachine0_sink_sink_valid = soc_litedramcore_bankmachine0_source_valid; +assign soc_litedramcore_bankmachine0_source_ready = soc_litedramcore_bankmachine0_sink_sink_ready; +assign soc_litedramcore_bankmachine0_sink_sink_first = soc_litedramcore_bankmachine0_source_first; +assign soc_litedramcore_bankmachine0_sink_sink_last = soc_litedramcore_bankmachine0_source_last; +assign soc_litedramcore_bankmachine0_sink_sink_payload_we = soc_litedramcore_bankmachine0_source_payload_we; +assign soc_litedramcore_bankmachine0_sink_sink_payload_addr = soc_litedramcore_bankmachine0_source_payload_addr; +assign soc_litedramcore_bankmachine0_source_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid); +assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_source_valid | soc_litedramcore_bankmachine0_source_source_valid); +assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write); assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open); always @(*) begin - soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - if (soc_litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine0_twtpcon_ready) begin - soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine0_trccon_ready) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine0_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine0_row_opened) begin - if (soc_litedramcore_bankmachine0_row_hit) begin - soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid; -assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); -assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine0_source_valid & soc_litedramcore_bankmachine0_source_source_valid)) begin + if ((soc_litedramcore_bankmachine0_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine0_syncfifo0_din = {soc_litedramcore_bankmachine0_fifo_in_last, soc_litedramcore_bankmachine0_fifo_in_first, soc_litedramcore_bankmachine0_fifo_in_payload_addr, soc_litedramcore_bankmachine0_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout; +assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout; +assign soc_litedramcore_bankmachine0_sink_ready = soc_litedramcore_bankmachine0_syncfifo0_writable; +assign soc_litedramcore_bankmachine0_syncfifo0_we = soc_litedramcore_bankmachine0_sink_valid; +assign soc_litedramcore_bankmachine0_fifo_in_first = soc_litedramcore_bankmachine0_sink_first; +assign soc_litedramcore_bankmachine0_fifo_in_last = soc_litedramcore_bankmachine0_sink_last; +assign soc_litedramcore_bankmachine0_fifo_in_payload_we = soc_litedramcore_bankmachine0_sink_payload_we; +assign soc_litedramcore_bankmachine0_fifo_in_payload_addr = soc_litedramcore_bankmachine0_sink_payload_addr; +assign soc_litedramcore_bankmachine0_source_valid = soc_litedramcore_bankmachine0_syncfifo0_readable; +assign soc_litedramcore_bankmachine0_source_first = soc_litedramcore_bankmachine0_fifo_out_first; +assign soc_litedramcore_bankmachine0_source_last = soc_litedramcore_bankmachine0_fifo_out_last; +assign soc_litedramcore_bankmachine0_source_payload_we = soc_litedramcore_bankmachine0_fifo_out_payload_we; +assign soc_litedramcore_bankmachine0_source_payload_addr = soc_litedramcore_bankmachine0_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine0_syncfifo0_re = soc_litedramcore_bankmachine0_source_ready; +always @(*) begin + soc_litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine0_replace) begin + soc_litedramcore_bankmachine0_wrport_adr <= (soc_litedramcore_bankmachine0_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine0_wrport_adr <= soc_litedramcore_bankmachine0_produce; + end +end +assign soc_litedramcore_bankmachine0_wrport_dat_w = soc_litedramcore_bankmachine0_syncfifo0_din; +assign soc_litedramcore_bankmachine0_wrport_we = (soc_litedramcore_bankmachine0_syncfifo0_we & (soc_litedramcore_bankmachine0_syncfifo0_writable | soc_litedramcore_bankmachine0_replace)); +assign soc_litedramcore_bankmachine0_do_read = (soc_litedramcore_bankmachine0_syncfifo0_readable & soc_litedramcore_bankmachine0_syncfifo0_re); +assign soc_litedramcore_bankmachine0_rdport_adr = soc_litedramcore_bankmachine0_consume; +assign soc_litedramcore_bankmachine0_syncfifo0_dout = soc_litedramcore_bankmachine0_rdport_dat_r; +assign soc_litedramcore_bankmachine0_syncfifo0_writable = (soc_litedramcore_bankmachine0_level != 5'd16); +assign soc_litedramcore_bankmachine0_syncfifo0_readable = (soc_litedramcore_bankmachine0_level != 1'd0); +assign soc_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine0_pipe_valid_sink_valid = soc_litedramcore_bankmachine0_sink_sink_valid; +assign soc_litedramcore_bankmachine0_sink_sink_ready = soc_litedramcore_bankmachine0_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_first = soc_litedramcore_bankmachine0_sink_sink_first; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_last = soc_litedramcore_bankmachine0_sink_sink_last; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine0_sink_sink_payload_we; +assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine0_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine0_source_source_valid = soc_litedramcore_bankmachine0_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine0_pipe_valid_source_ready = soc_litedramcore_bankmachine0_source_source_ready; +assign soc_litedramcore_bankmachine0_source_source_first = soc_litedramcore_bankmachine0_pipe_valid_source_first; +assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankmachine0_pipe_valid_source_last; +assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + if (soc_litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + if (soc_litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine0_twtpcon_ready) begin + soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine0_trccon_ready) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine0_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine0_source_source_valid) begin + if (soc_litedramcore_bankmachine0_row_opened) begin + if (soc_litedramcore_bankmachine0_row_hit) begin + soc_litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid; +assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready; +assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we; +assign soc_litedramcore_bankmachine1_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr; +assign soc_litedramcore_bankmachine1_sink_sink_valid = soc_litedramcore_bankmachine1_source_valid; +assign soc_litedramcore_bankmachine1_source_ready = soc_litedramcore_bankmachine1_sink_sink_ready; +assign soc_litedramcore_bankmachine1_sink_sink_first = soc_litedramcore_bankmachine1_source_first; +assign soc_litedramcore_bankmachine1_sink_sink_last = soc_litedramcore_bankmachine1_source_last; +assign soc_litedramcore_bankmachine1_sink_sink_payload_we = soc_litedramcore_bankmachine1_source_payload_we; +assign soc_litedramcore_bankmachine1_sink_sink_payload_addr = soc_litedramcore_bankmachine1_source_payload_addr; +assign soc_litedramcore_bankmachine1_source_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid); +assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_source_valid | soc_litedramcore_bankmachine1_source_source_valid); +assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write); assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open); always @(*) begin - soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - if (soc_litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine1_twtpcon_ready) begin - soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine1_trccon_ready) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine1_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine1_row_opened) begin - if (soc_litedramcore_bankmachine1_row_hit) begin - soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid; -assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); -assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine1_source_valid & soc_litedramcore_bankmachine1_source_source_valid)) begin + if ((soc_litedramcore_bankmachine1_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine1_syncfifo1_din = {soc_litedramcore_bankmachine1_fifo_in_last, soc_litedramcore_bankmachine1_fifo_in_first, soc_litedramcore_bankmachine1_fifo_in_payload_addr, soc_litedramcore_bankmachine1_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout; +assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout; +assign soc_litedramcore_bankmachine1_sink_ready = soc_litedramcore_bankmachine1_syncfifo1_writable; +assign soc_litedramcore_bankmachine1_syncfifo1_we = soc_litedramcore_bankmachine1_sink_valid; +assign soc_litedramcore_bankmachine1_fifo_in_first = soc_litedramcore_bankmachine1_sink_first; +assign soc_litedramcore_bankmachine1_fifo_in_last = soc_litedramcore_bankmachine1_sink_last; +assign soc_litedramcore_bankmachine1_fifo_in_payload_we = soc_litedramcore_bankmachine1_sink_payload_we; +assign soc_litedramcore_bankmachine1_fifo_in_payload_addr = soc_litedramcore_bankmachine1_sink_payload_addr; +assign soc_litedramcore_bankmachine1_source_valid = soc_litedramcore_bankmachine1_syncfifo1_readable; +assign soc_litedramcore_bankmachine1_source_first = soc_litedramcore_bankmachine1_fifo_out_first; +assign soc_litedramcore_bankmachine1_source_last = soc_litedramcore_bankmachine1_fifo_out_last; +assign soc_litedramcore_bankmachine1_source_payload_we = soc_litedramcore_bankmachine1_fifo_out_payload_we; +assign soc_litedramcore_bankmachine1_source_payload_addr = soc_litedramcore_bankmachine1_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine1_syncfifo1_re = soc_litedramcore_bankmachine1_source_ready; +always @(*) begin + soc_litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine1_replace) begin + soc_litedramcore_bankmachine1_wrport_adr <= (soc_litedramcore_bankmachine1_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine1_wrport_adr <= soc_litedramcore_bankmachine1_produce; + end +end +assign soc_litedramcore_bankmachine1_wrport_dat_w = soc_litedramcore_bankmachine1_syncfifo1_din; +assign soc_litedramcore_bankmachine1_wrport_we = (soc_litedramcore_bankmachine1_syncfifo1_we & (soc_litedramcore_bankmachine1_syncfifo1_writable | soc_litedramcore_bankmachine1_replace)); +assign soc_litedramcore_bankmachine1_do_read = (soc_litedramcore_bankmachine1_syncfifo1_readable & soc_litedramcore_bankmachine1_syncfifo1_re); +assign soc_litedramcore_bankmachine1_rdport_adr = soc_litedramcore_bankmachine1_consume; +assign soc_litedramcore_bankmachine1_syncfifo1_dout = soc_litedramcore_bankmachine1_rdport_dat_r; +assign soc_litedramcore_bankmachine1_syncfifo1_writable = (soc_litedramcore_bankmachine1_level != 5'd16); +assign soc_litedramcore_bankmachine1_syncfifo1_readable = (soc_litedramcore_bankmachine1_level != 1'd0); +assign soc_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine1_pipe_valid_sink_valid = soc_litedramcore_bankmachine1_sink_sink_valid; +assign soc_litedramcore_bankmachine1_sink_sink_ready = soc_litedramcore_bankmachine1_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_first = soc_litedramcore_bankmachine1_sink_sink_first; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_last = soc_litedramcore_bankmachine1_sink_sink_last; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine1_sink_sink_payload_we; +assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine1_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine1_source_source_valid = soc_litedramcore_bankmachine1_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine1_pipe_valid_source_ready = soc_litedramcore_bankmachine1_source_source_ready; +assign soc_litedramcore_bankmachine1_source_source_first = soc_litedramcore_bankmachine1_pipe_valid_source_first; +assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankmachine1_pipe_valid_source_last; +assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + if (soc_litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + if (soc_litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine1_twtpcon_ready) begin + soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine1_trccon_ready) begin + soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine1_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine1_source_source_valid) begin + if (soc_litedramcore_bankmachine1_row_opened) begin + if (soc_litedramcore_bankmachine1_row_hit) begin + soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid; +assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready; +assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we; +assign soc_litedramcore_bankmachine2_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr; +assign soc_litedramcore_bankmachine2_sink_sink_valid = soc_litedramcore_bankmachine2_source_valid; +assign soc_litedramcore_bankmachine2_source_ready = soc_litedramcore_bankmachine2_sink_sink_ready; +assign soc_litedramcore_bankmachine2_sink_sink_first = soc_litedramcore_bankmachine2_source_first; +assign soc_litedramcore_bankmachine2_sink_sink_last = soc_litedramcore_bankmachine2_source_last; +assign soc_litedramcore_bankmachine2_sink_sink_payload_we = soc_litedramcore_bankmachine2_source_payload_we; +assign soc_litedramcore_bankmachine2_sink_sink_payload_addr = soc_litedramcore_bankmachine2_source_payload_addr; +assign soc_litedramcore_bankmachine2_source_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid); +assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_source_valid | soc_litedramcore_bankmachine2_source_source_valid); +assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write); assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open); always @(*) begin - soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - if (soc_litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine2_twtpcon_ready) begin - soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine2_trccon_ready) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine2_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine2_row_opened) begin - if (soc_litedramcore_bankmachine2_row_hit) begin - soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid; -assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); -assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine2_source_valid & soc_litedramcore_bankmachine2_source_source_valid)) begin + if ((soc_litedramcore_bankmachine2_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine2_syncfifo2_din = {soc_litedramcore_bankmachine2_fifo_in_last, soc_litedramcore_bankmachine2_fifo_in_first, soc_litedramcore_bankmachine2_fifo_in_payload_addr, soc_litedramcore_bankmachine2_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout; +assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout; +assign soc_litedramcore_bankmachine2_sink_ready = soc_litedramcore_bankmachine2_syncfifo2_writable; +assign soc_litedramcore_bankmachine2_syncfifo2_we = soc_litedramcore_bankmachine2_sink_valid; +assign soc_litedramcore_bankmachine2_fifo_in_first = soc_litedramcore_bankmachine2_sink_first; +assign soc_litedramcore_bankmachine2_fifo_in_last = soc_litedramcore_bankmachine2_sink_last; +assign soc_litedramcore_bankmachine2_fifo_in_payload_we = soc_litedramcore_bankmachine2_sink_payload_we; +assign soc_litedramcore_bankmachine2_fifo_in_payload_addr = soc_litedramcore_bankmachine2_sink_payload_addr; +assign soc_litedramcore_bankmachine2_source_valid = soc_litedramcore_bankmachine2_syncfifo2_readable; +assign soc_litedramcore_bankmachine2_source_first = soc_litedramcore_bankmachine2_fifo_out_first; +assign soc_litedramcore_bankmachine2_source_last = soc_litedramcore_bankmachine2_fifo_out_last; +assign soc_litedramcore_bankmachine2_source_payload_we = soc_litedramcore_bankmachine2_fifo_out_payload_we; +assign soc_litedramcore_bankmachine2_source_payload_addr = soc_litedramcore_bankmachine2_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine2_syncfifo2_re = soc_litedramcore_bankmachine2_source_ready; +always @(*) begin + soc_litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine2_replace) begin + soc_litedramcore_bankmachine2_wrport_adr <= (soc_litedramcore_bankmachine2_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine2_wrport_adr <= soc_litedramcore_bankmachine2_produce; + end +end +assign soc_litedramcore_bankmachine2_wrport_dat_w = soc_litedramcore_bankmachine2_syncfifo2_din; +assign soc_litedramcore_bankmachine2_wrport_we = (soc_litedramcore_bankmachine2_syncfifo2_we & (soc_litedramcore_bankmachine2_syncfifo2_writable | soc_litedramcore_bankmachine2_replace)); +assign soc_litedramcore_bankmachine2_do_read = (soc_litedramcore_bankmachine2_syncfifo2_readable & soc_litedramcore_bankmachine2_syncfifo2_re); +assign soc_litedramcore_bankmachine2_rdport_adr = soc_litedramcore_bankmachine2_consume; +assign soc_litedramcore_bankmachine2_syncfifo2_dout = soc_litedramcore_bankmachine2_rdport_dat_r; +assign soc_litedramcore_bankmachine2_syncfifo2_writable = (soc_litedramcore_bankmachine2_level != 5'd16); +assign soc_litedramcore_bankmachine2_syncfifo2_readable = (soc_litedramcore_bankmachine2_level != 1'd0); +assign soc_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine2_pipe_valid_sink_valid = soc_litedramcore_bankmachine2_sink_sink_valid; +assign soc_litedramcore_bankmachine2_sink_sink_ready = soc_litedramcore_bankmachine2_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_first = soc_litedramcore_bankmachine2_sink_sink_first; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_last = soc_litedramcore_bankmachine2_sink_sink_last; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine2_sink_sink_payload_we; +assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine2_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine2_source_source_valid = soc_litedramcore_bankmachine2_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine2_pipe_valid_source_ready = soc_litedramcore_bankmachine2_source_source_ready; +assign soc_litedramcore_bankmachine2_source_source_first = soc_litedramcore_bankmachine2_pipe_valid_source_first; +assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankmachine2_pipe_valid_source_last; +assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + if (soc_litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine2_twtpcon_ready) begin + soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine2_trccon_ready) begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine2_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine2_source_source_valid) begin + if (soc_litedramcore_bankmachine2_row_opened) begin + if (soc_litedramcore_bankmachine2_row_hit) begin + if (soc_litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid; +assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready; +assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we; +assign soc_litedramcore_bankmachine3_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr; +assign soc_litedramcore_bankmachine3_sink_sink_valid = soc_litedramcore_bankmachine3_source_valid; +assign soc_litedramcore_bankmachine3_source_ready = soc_litedramcore_bankmachine3_sink_sink_ready; +assign soc_litedramcore_bankmachine3_sink_sink_first = soc_litedramcore_bankmachine3_source_first; +assign soc_litedramcore_bankmachine3_sink_sink_last = soc_litedramcore_bankmachine3_source_last; +assign soc_litedramcore_bankmachine3_sink_sink_payload_we = soc_litedramcore_bankmachine3_source_payload_we; +assign soc_litedramcore_bankmachine3_sink_sink_payload_addr = soc_litedramcore_bankmachine3_source_payload_addr; +assign soc_litedramcore_bankmachine3_source_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid); +assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_source_valid | soc_litedramcore_bankmachine3_source_source_valid); +assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write); assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open); always @(*) begin - soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - if (soc_litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine3_twtpcon_ready) begin - soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine3_trccon_ready) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine3_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine3_row_opened) begin - if (soc_litedramcore_bankmachine3_row_hit) begin - soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid; -assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); -assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine3_source_valid & soc_litedramcore_bankmachine3_source_source_valid)) begin + if ((soc_litedramcore_bankmachine3_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine3_syncfifo3_din = {soc_litedramcore_bankmachine3_fifo_in_last, soc_litedramcore_bankmachine3_fifo_in_first, soc_litedramcore_bankmachine3_fifo_in_payload_addr, soc_litedramcore_bankmachine3_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout; +assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout; +assign soc_litedramcore_bankmachine3_sink_ready = soc_litedramcore_bankmachine3_syncfifo3_writable; +assign soc_litedramcore_bankmachine3_syncfifo3_we = soc_litedramcore_bankmachine3_sink_valid; +assign soc_litedramcore_bankmachine3_fifo_in_first = soc_litedramcore_bankmachine3_sink_first; +assign soc_litedramcore_bankmachine3_fifo_in_last = soc_litedramcore_bankmachine3_sink_last; +assign soc_litedramcore_bankmachine3_fifo_in_payload_we = soc_litedramcore_bankmachine3_sink_payload_we; +assign soc_litedramcore_bankmachine3_fifo_in_payload_addr = soc_litedramcore_bankmachine3_sink_payload_addr; +assign soc_litedramcore_bankmachine3_source_valid = soc_litedramcore_bankmachine3_syncfifo3_readable; +assign soc_litedramcore_bankmachine3_source_first = soc_litedramcore_bankmachine3_fifo_out_first; +assign soc_litedramcore_bankmachine3_source_last = soc_litedramcore_bankmachine3_fifo_out_last; +assign soc_litedramcore_bankmachine3_source_payload_we = soc_litedramcore_bankmachine3_fifo_out_payload_we; +assign soc_litedramcore_bankmachine3_source_payload_addr = soc_litedramcore_bankmachine3_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine3_syncfifo3_re = soc_litedramcore_bankmachine3_source_ready; +always @(*) begin + soc_litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine3_replace) begin + soc_litedramcore_bankmachine3_wrport_adr <= (soc_litedramcore_bankmachine3_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine3_wrport_adr <= soc_litedramcore_bankmachine3_produce; + end +end +assign soc_litedramcore_bankmachine3_wrport_dat_w = soc_litedramcore_bankmachine3_syncfifo3_din; +assign soc_litedramcore_bankmachine3_wrport_we = (soc_litedramcore_bankmachine3_syncfifo3_we & (soc_litedramcore_bankmachine3_syncfifo3_writable | soc_litedramcore_bankmachine3_replace)); +assign soc_litedramcore_bankmachine3_do_read = (soc_litedramcore_bankmachine3_syncfifo3_readable & soc_litedramcore_bankmachine3_syncfifo3_re); +assign soc_litedramcore_bankmachine3_rdport_adr = soc_litedramcore_bankmachine3_consume; +assign soc_litedramcore_bankmachine3_syncfifo3_dout = soc_litedramcore_bankmachine3_rdport_dat_r; +assign soc_litedramcore_bankmachine3_syncfifo3_writable = (soc_litedramcore_bankmachine3_level != 5'd16); +assign soc_litedramcore_bankmachine3_syncfifo3_readable = (soc_litedramcore_bankmachine3_level != 1'd0); +assign soc_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine3_pipe_valid_sink_valid = soc_litedramcore_bankmachine3_sink_sink_valid; +assign soc_litedramcore_bankmachine3_sink_sink_ready = soc_litedramcore_bankmachine3_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_first = soc_litedramcore_bankmachine3_sink_sink_first; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_last = soc_litedramcore_bankmachine3_sink_sink_last; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine3_sink_sink_payload_we; +assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine3_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine3_source_source_valid = soc_litedramcore_bankmachine3_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine3_pipe_valid_source_ready = soc_litedramcore_bankmachine3_source_source_ready; +assign soc_litedramcore_bankmachine3_source_source_first = soc_litedramcore_bankmachine3_pipe_valid_source_first; +assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankmachine3_pipe_valid_source_last; +assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + if (soc_litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine3_twtpcon_ready) begin + soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine3_trccon_ready) begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine3_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine3_source_source_valid) begin + if (soc_litedramcore_bankmachine3_row_opened) begin + if (soc_litedramcore_bankmachine3_row_hit) begin + if (soc_litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid; +assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready; +assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we; +assign soc_litedramcore_bankmachine4_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr; +assign soc_litedramcore_bankmachine4_sink_sink_valid = soc_litedramcore_bankmachine4_source_valid; +assign soc_litedramcore_bankmachine4_source_ready = soc_litedramcore_bankmachine4_sink_sink_ready; +assign soc_litedramcore_bankmachine4_sink_sink_first = soc_litedramcore_bankmachine4_source_first; +assign soc_litedramcore_bankmachine4_sink_sink_last = soc_litedramcore_bankmachine4_source_last; +assign soc_litedramcore_bankmachine4_sink_sink_payload_we = soc_litedramcore_bankmachine4_source_payload_we; +assign soc_litedramcore_bankmachine4_sink_sink_payload_addr = soc_litedramcore_bankmachine4_source_payload_addr; +assign soc_litedramcore_bankmachine4_source_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid); +assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_source_valid | soc_litedramcore_bankmachine4_source_source_valid); +assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write); assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open); always @(*) begin - soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - if (soc_litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine4_twtpcon_ready) begin - soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine4_trccon_ready) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine4_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine4_row_opened) begin - if (soc_litedramcore_bankmachine4_row_hit) begin - soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid; -assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); -assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine4_source_valid & soc_litedramcore_bankmachine4_source_source_valid)) begin + if ((soc_litedramcore_bankmachine4_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine4_syncfifo4_din = {soc_litedramcore_bankmachine4_fifo_in_last, soc_litedramcore_bankmachine4_fifo_in_first, soc_litedramcore_bankmachine4_fifo_in_payload_addr, soc_litedramcore_bankmachine4_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout; +assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout; +assign soc_litedramcore_bankmachine4_sink_ready = soc_litedramcore_bankmachine4_syncfifo4_writable; +assign soc_litedramcore_bankmachine4_syncfifo4_we = soc_litedramcore_bankmachine4_sink_valid; +assign soc_litedramcore_bankmachine4_fifo_in_first = soc_litedramcore_bankmachine4_sink_first; +assign soc_litedramcore_bankmachine4_fifo_in_last = soc_litedramcore_bankmachine4_sink_last; +assign soc_litedramcore_bankmachine4_fifo_in_payload_we = soc_litedramcore_bankmachine4_sink_payload_we; +assign soc_litedramcore_bankmachine4_fifo_in_payload_addr = soc_litedramcore_bankmachine4_sink_payload_addr; +assign soc_litedramcore_bankmachine4_source_valid = soc_litedramcore_bankmachine4_syncfifo4_readable; +assign soc_litedramcore_bankmachine4_source_first = soc_litedramcore_bankmachine4_fifo_out_first; +assign soc_litedramcore_bankmachine4_source_last = soc_litedramcore_bankmachine4_fifo_out_last; +assign soc_litedramcore_bankmachine4_source_payload_we = soc_litedramcore_bankmachine4_fifo_out_payload_we; +assign soc_litedramcore_bankmachine4_source_payload_addr = soc_litedramcore_bankmachine4_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine4_syncfifo4_re = soc_litedramcore_bankmachine4_source_ready; +always @(*) begin + soc_litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine4_replace) begin + soc_litedramcore_bankmachine4_wrport_adr <= (soc_litedramcore_bankmachine4_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine4_wrport_adr <= soc_litedramcore_bankmachine4_produce; + end +end +assign soc_litedramcore_bankmachine4_wrport_dat_w = soc_litedramcore_bankmachine4_syncfifo4_din; +assign soc_litedramcore_bankmachine4_wrport_we = (soc_litedramcore_bankmachine4_syncfifo4_we & (soc_litedramcore_bankmachine4_syncfifo4_writable | soc_litedramcore_bankmachine4_replace)); +assign soc_litedramcore_bankmachine4_do_read = (soc_litedramcore_bankmachine4_syncfifo4_readable & soc_litedramcore_bankmachine4_syncfifo4_re); +assign soc_litedramcore_bankmachine4_rdport_adr = soc_litedramcore_bankmachine4_consume; +assign soc_litedramcore_bankmachine4_syncfifo4_dout = soc_litedramcore_bankmachine4_rdport_dat_r; +assign soc_litedramcore_bankmachine4_syncfifo4_writable = (soc_litedramcore_bankmachine4_level != 5'd16); +assign soc_litedramcore_bankmachine4_syncfifo4_readable = (soc_litedramcore_bankmachine4_level != 1'd0); +assign soc_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine4_pipe_valid_sink_valid = soc_litedramcore_bankmachine4_sink_sink_valid; +assign soc_litedramcore_bankmachine4_sink_sink_ready = soc_litedramcore_bankmachine4_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_first = soc_litedramcore_bankmachine4_sink_sink_first; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_last = soc_litedramcore_bankmachine4_sink_sink_last; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine4_sink_sink_payload_we; +assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine4_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine4_source_source_valid = soc_litedramcore_bankmachine4_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine4_pipe_valid_source_ready = soc_litedramcore_bankmachine4_source_source_ready; +assign soc_litedramcore_bankmachine4_source_source_first = soc_litedramcore_bankmachine4_pipe_valid_source_first; +assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankmachine4_pipe_valid_source_last; +assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + if (soc_litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + if (soc_litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine4_twtpcon_ready) begin + soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine4_trccon_ready) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine4_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine4_source_source_valid) begin + if (soc_litedramcore_bankmachine4_row_opened) begin + if (soc_litedramcore_bankmachine4_row_hit) begin + soc_litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid; +assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready; +assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we; +assign soc_litedramcore_bankmachine5_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr; +assign soc_litedramcore_bankmachine5_sink_sink_valid = soc_litedramcore_bankmachine5_source_valid; +assign soc_litedramcore_bankmachine5_source_ready = soc_litedramcore_bankmachine5_sink_sink_ready; +assign soc_litedramcore_bankmachine5_sink_sink_first = soc_litedramcore_bankmachine5_source_first; +assign soc_litedramcore_bankmachine5_sink_sink_last = soc_litedramcore_bankmachine5_source_last; +assign soc_litedramcore_bankmachine5_sink_sink_payload_we = soc_litedramcore_bankmachine5_source_payload_we; +assign soc_litedramcore_bankmachine5_sink_sink_payload_addr = soc_litedramcore_bankmachine5_source_payload_addr; +assign soc_litedramcore_bankmachine5_source_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid); +assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_source_valid | soc_litedramcore_bankmachine5_source_source_valid); +assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write); assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open); always @(*) begin - soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - if (soc_litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine5_twtpcon_ready) begin - soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine5_trccon_ready) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine5_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine5_row_opened) begin - if (soc_litedramcore_bankmachine5_row_hit) begin - soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid; -assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); -assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine5_source_valid & soc_litedramcore_bankmachine5_source_source_valid)) begin + if ((soc_litedramcore_bankmachine5_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine5_syncfifo5_din = {soc_litedramcore_bankmachine5_fifo_in_last, soc_litedramcore_bankmachine5_fifo_in_first, soc_litedramcore_bankmachine5_fifo_in_payload_addr, soc_litedramcore_bankmachine5_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout; +assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout; +assign soc_litedramcore_bankmachine5_sink_ready = soc_litedramcore_bankmachine5_syncfifo5_writable; +assign soc_litedramcore_bankmachine5_syncfifo5_we = soc_litedramcore_bankmachine5_sink_valid; +assign soc_litedramcore_bankmachine5_fifo_in_first = soc_litedramcore_bankmachine5_sink_first; +assign soc_litedramcore_bankmachine5_fifo_in_last = soc_litedramcore_bankmachine5_sink_last; +assign soc_litedramcore_bankmachine5_fifo_in_payload_we = soc_litedramcore_bankmachine5_sink_payload_we; +assign soc_litedramcore_bankmachine5_fifo_in_payload_addr = soc_litedramcore_bankmachine5_sink_payload_addr; +assign soc_litedramcore_bankmachine5_source_valid = soc_litedramcore_bankmachine5_syncfifo5_readable; +assign soc_litedramcore_bankmachine5_source_first = soc_litedramcore_bankmachine5_fifo_out_first; +assign soc_litedramcore_bankmachine5_source_last = soc_litedramcore_bankmachine5_fifo_out_last; +assign soc_litedramcore_bankmachine5_source_payload_we = soc_litedramcore_bankmachine5_fifo_out_payload_we; +assign soc_litedramcore_bankmachine5_source_payload_addr = soc_litedramcore_bankmachine5_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine5_syncfifo5_re = soc_litedramcore_bankmachine5_source_ready; +always @(*) begin + soc_litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine5_replace) begin + soc_litedramcore_bankmachine5_wrport_adr <= (soc_litedramcore_bankmachine5_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine5_wrport_adr <= soc_litedramcore_bankmachine5_produce; + end +end +assign soc_litedramcore_bankmachine5_wrport_dat_w = soc_litedramcore_bankmachine5_syncfifo5_din; +assign soc_litedramcore_bankmachine5_wrport_we = (soc_litedramcore_bankmachine5_syncfifo5_we & (soc_litedramcore_bankmachine5_syncfifo5_writable | soc_litedramcore_bankmachine5_replace)); +assign soc_litedramcore_bankmachine5_do_read = (soc_litedramcore_bankmachine5_syncfifo5_readable & soc_litedramcore_bankmachine5_syncfifo5_re); +assign soc_litedramcore_bankmachine5_rdport_adr = soc_litedramcore_bankmachine5_consume; +assign soc_litedramcore_bankmachine5_syncfifo5_dout = soc_litedramcore_bankmachine5_rdport_dat_r; +assign soc_litedramcore_bankmachine5_syncfifo5_writable = (soc_litedramcore_bankmachine5_level != 5'd16); +assign soc_litedramcore_bankmachine5_syncfifo5_readable = (soc_litedramcore_bankmachine5_level != 1'd0); +assign soc_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine5_pipe_valid_sink_valid = soc_litedramcore_bankmachine5_sink_sink_valid; +assign soc_litedramcore_bankmachine5_sink_sink_ready = soc_litedramcore_bankmachine5_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_first = soc_litedramcore_bankmachine5_sink_sink_first; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_last = soc_litedramcore_bankmachine5_sink_sink_last; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine5_sink_sink_payload_we; +assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine5_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine5_source_source_valid = soc_litedramcore_bankmachine5_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine5_pipe_valid_source_ready = soc_litedramcore_bankmachine5_source_source_ready; +assign soc_litedramcore_bankmachine5_source_source_first = soc_litedramcore_bankmachine5_pipe_valid_source_first; +assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankmachine5_pipe_valid_source_last; +assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + if (soc_litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + if (soc_litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine5_twtpcon_ready) begin + soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine5_trccon_ready) begin + soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine5_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine5_source_source_valid) begin + if (soc_litedramcore_bankmachine5_row_opened) begin + if (soc_litedramcore_bankmachine5_row_hit) begin + soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid; +assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready; +assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we; +assign soc_litedramcore_bankmachine6_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr; +assign soc_litedramcore_bankmachine6_sink_sink_valid = soc_litedramcore_bankmachine6_source_valid; +assign soc_litedramcore_bankmachine6_source_ready = soc_litedramcore_bankmachine6_sink_sink_ready; +assign soc_litedramcore_bankmachine6_sink_sink_first = soc_litedramcore_bankmachine6_source_first; +assign soc_litedramcore_bankmachine6_sink_sink_last = soc_litedramcore_bankmachine6_source_last; +assign soc_litedramcore_bankmachine6_sink_sink_payload_we = soc_litedramcore_bankmachine6_source_payload_we; +assign soc_litedramcore_bankmachine6_sink_sink_payload_addr = soc_litedramcore_bankmachine6_source_payload_addr; +assign soc_litedramcore_bankmachine6_source_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid); +assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_source_valid | soc_litedramcore_bankmachine6_source_source_valid); +assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write); assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open); always @(*) begin - soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - if (soc_litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine6_twtpcon_ready) begin - soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine6_trccon_ready) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine6_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine6_row_opened) begin - if (soc_litedramcore_bankmachine6_row_hit) begin - soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid; -assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); -assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid); -assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); + soc_litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine6_source_valid & soc_litedramcore_bankmachine6_source_source_valid)) begin + if ((soc_litedramcore_bankmachine6_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine6_syncfifo6_din = {soc_litedramcore_bankmachine6_fifo_in_last, soc_litedramcore_bankmachine6_fifo_in_first, soc_litedramcore_bankmachine6_fifo_in_payload_addr, soc_litedramcore_bankmachine6_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout; +assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout; +assign soc_litedramcore_bankmachine6_sink_ready = soc_litedramcore_bankmachine6_syncfifo6_writable; +assign soc_litedramcore_bankmachine6_syncfifo6_we = soc_litedramcore_bankmachine6_sink_valid; +assign soc_litedramcore_bankmachine6_fifo_in_first = soc_litedramcore_bankmachine6_sink_first; +assign soc_litedramcore_bankmachine6_fifo_in_last = soc_litedramcore_bankmachine6_sink_last; +assign soc_litedramcore_bankmachine6_fifo_in_payload_we = soc_litedramcore_bankmachine6_sink_payload_we; +assign soc_litedramcore_bankmachine6_fifo_in_payload_addr = soc_litedramcore_bankmachine6_sink_payload_addr; +assign soc_litedramcore_bankmachine6_source_valid = soc_litedramcore_bankmachine6_syncfifo6_readable; +assign soc_litedramcore_bankmachine6_source_first = soc_litedramcore_bankmachine6_fifo_out_first; +assign soc_litedramcore_bankmachine6_source_last = soc_litedramcore_bankmachine6_fifo_out_last; +assign soc_litedramcore_bankmachine6_source_payload_we = soc_litedramcore_bankmachine6_fifo_out_payload_we; +assign soc_litedramcore_bankmachine6_source_payload_addr = soc_litedramcore_bankmachine6_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine6_syncfifo6_re = soc_litedramcore_bankmachine6_source_ready; +always @(*) begin + soc_litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine6_replace) begin + soc_litedramcore_bankmachine6_wrport_adr <= (soc_litedramcore_bankmachine6_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine6_wrport_adr <= soc_litedramcore_bankmachine6_produce; + end +end +assign soc_litedramcore_bankmachine6_wrport_dat_w = soc_litedramcore_bankmachine6_syncfifo6_din; +assign soc_litedramcore_bankmachine6_wrport_we = (soc_litedramcore_bankmachine6_syncfifo6_we & (soc_litedramcore_bankmachine6_syncfifo6_writable | soc_litedramcore_bankmachine6_replace)); +assign soc_litedramcore_bankmachine6_do_read = (soc_litedramcore_bankmachine6_syncfifo6_readable & soc_litedramcore_bankmachine6_syncfifo6_re); +assign soc_litedramcore_bankmachine6_rdport_adr = soc_litedramcore_bankmachine6_consume; +assign soc_litedramcore_bankmachine6_syncfifo6_dout = soc_litedramcore_bankmachine6_rdport_dat_r; +assign soc_litedramcore_bankmachine6_syncfifo6_writable = (soc_litedramcore_bankmachine6_level != 5'd16); +assign soc_litedramcore_bankmachine6_syncfifo6_readable = (soc_litedramcore_bankmachine6_level != 1'd0); +assign soc_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine6_pipe_valid_sink_valid = soc_litedramcore_bankmachine6_sink_sink_valid; +assign soc_litedramcore_bankmachine6_sink_sink_ready = soc_litedramcore_bankmachine6_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_bankmachine6_sink_sink_first; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we; +assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready; +assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first; +assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last; +assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + if (soc_litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine6_twtpcon_ready) begin + soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine6_trccon_ready) begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine6_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine6_source_source_valid) begin + if (soc_litedramcore_bankmachine6_row_opened) begin + if (soc_litedramcore_bankmachine6_row_hit) begin + if (soc_litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid; +assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready; +assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we; +assign soc_litedramcore_bankmachine7_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr; +assign soc_litedramcore_bankmachine7_sink_sink_valid = soc_litedramcore_bankmachine7_source_valid; +assign soc_litedramcore_bankmachine7_source_ready = soc_litedramcore_bankmachine7_sink_sink_ready; +assign soc_litedramcore_bankmachine7_sink_sink_first = soc_litedramcore_bankmachine7_source_first; +assign soc_litedramcore_bankmachine7_sink_sink_last = soc_litedramcore_bankmachine7_source_last; +assign soc_litedramcore_bankmachine7_sink_sink_payload_we = soc_litedramcore_bankmachine7_source_payload_we; +assign soc_litedramcore_bankmachine7_sink_sink_payload_addr = soc_litedramcore_bankmachine7_source_payload_addr; +assign soc_litedramcore_bankmachine7_source_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid); +assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_source_valid | soc_litedramcore_bankmachine7_source_source_valid); +assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_source_source_payload_addr[20:7]); assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin - soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end else begin - soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin + soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end else begin + soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write); assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open); always @(*) begin - soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - if (soc_litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~soc_litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - soc_litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (soc_litedramcore_bankmachine7_twtpcon_ready) begin - soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (soc_litedramcore_bankmachine7_trccon_ready) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (soc_litedramcore_bankmachine7_refresh_req) begin - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (soc_litedramcore_bankmachine7_row_opened) begin - if (soc_litedramcore_bankmachine7_row_hit) begin - soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase + soc_litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((soc_litedramcore_bankmachine7_source_valid & soc_litedramcore_bankmachine7_source_source_valid)) begin + if ((soc_litedramcore_bankmachine7_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin + soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign soc_litedramcore_bankmachine7_syncfifo7_din = {soc_litedramcore_bankmachine7_fifo_in_last, soc_litedramcore_bankmachine7_fifo_in_first, soc_litedramcore_bankmachine7_fifo_in_payload_addr, soc_litedramcore_bankmachine7_fifo_in_payload_we}; +assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout; +assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout; +assign soc_litedramcore_bankmachine7_sink_ready = soc_litedramcore_bankmachine7_syncfifo7_writable; +assign soc_litedramcore_bankmachine7_syncfifo7_we = soc_litedramcore_bankmachine7_sink_valid; +assign soc_litedramcore_bankmachine7_fifo_in_first = soc_litedramcore_bankmachine7_sink_first; +assign soc_litedramcore_bankmachine7_fifo_in_last = soc_litedramcore_bankmachine7_sink_last; +assign soc_litedramcore_bankmachine7_fifo_in_payload_we = soc_litedramcore_bankmachine7_sink_payload_we; +assign soc_litedramcore_bankmachine7_fifo_in_payload_addr = soc_litedramcore_bankmachine7_sink_payload_addr; +assign soc_litedramcore_bankmachine7_source_valid = soc_litedramcore_bankmachine7_syncfifo7_readable; +assign soc_litedramcore_bankmachine7_source_first = soc_litedramcore_bankmachine7_fifo_out_first; +assign soc_litedramcore_bankmachine7_source_last = soc_litedramcore_bankmachine7_fifo_out_last; +assign soc_litedramcore_bankmachine7_source_payload_we = soc_litedramcore_bankmachine7_fifo_out_payload_we; +assign soc_litedramcore_bankmachine7_source_payload_addr = soc_litedramcore_bankmachine7_fifo_out_payload_addr; +assign soc_litedramcore_bankmachine7_syncfifo7_re = soc_litedramcore_bankmachine7_source_ready; +always @(*) begin + soc_litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (soc_litedramcore_bankmachine7_replace) begin + soc_litedramcore_bankmachine7_wrport_adr <= (soc_litedramcore_bankmachine7_produce - 1'd1); + end else begin + soc_litedramcore_bankmachine7_wrport_adr <= soc_litedramcore_bankmachine7_produce; + end +end +assign soc_litedramcore_bankmachine7_wrport_dat_w = soc_litedramcore_bankmachine7_syncfifo7_din; +assign soc_litedramcore_bankmachine7_wrport_we = (soc_litedramcore_bankmachine7_syncfifo7_we & (soc_litedramcore_bankmachine7_syncfifo7_writable | soc_litedramcore_bankmachine7_replace)); +assign soc_litedramcore_bankmachine7_do_read = (soc_litedramcore_bankmachine7_syncfifo7_readable & soc_litedramcore_bankmachine7_syncfifo7_re); +assign soc_litedramcore_bankmachine7_rdport_adr = soc_litedramcore_bankmachine7_consume; +assign soc_litedramcore_bankmachine7_syncfifo7_dout = soc_litedramcore_bankmachine7_rdport_dat_r; +assign soc_litedramcore_bankmachine7_syncfifo7_writable = (soc_litedramcore_bankmachine7_level != 5'd16); +assign soc_litedramcore_bankmachine7_syncfifo7_readable = (soc_litedramcore_bankmachine7_level != 1'd0); +assign soc_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready); +assign soc_litedramcore_bankmachine7_pipe_valid_sink_valid = soc_litedramcore_bankmachine7_sink_sink_valid; +assign soc_litedramcore_bankmachine7_sink_sink_ready = soc_litedramcore_bankmachine7_pipe_valid_sink_ready; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_first = soc_litedramcore_bankmachine7_sink_sink_first; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_last = soc_litedramcore_bankmachine7_sink_sink_last; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine7_sink_sink_payload_we; +assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine7_sink_sink_payload_addr; +assign soc_litedramcore_bankmachine7_source_source_valid = soc_litedramcore_bankmachine7_pipe_valid_source_valid; +assign soc_litedramcore_bankmachine7_pipe_valid_source_ready = soc_litedramcore_bankmachine7_source_source_ready; +assign soc_litedramcore_bankmachine7_source_source_first = soc_litedramcore_bankmachine7_pipe_valid_source_first; +assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankmachine7_pipe_valid_source_last; +assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + if (soc_litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~soc_litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + soc_litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (soc_litedramcore_bankmachine7_twtpcon_ready) begin + soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (soc_litedramcore_bankmachine7_trccon_ready) begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (soc_litedramcore_bankmachine7_refresh_req) begin + end else begin + if (soc_litedramcore_bankmachine7_source_source_valid) begin + if (soc_litedramcore_bankmachine7_row_opened) begin + if (soc_litedramcore_bankmachine7_row_hit) begin + if (soc_litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase end assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))); @@ -9467,15 +9659,15 @@ assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we); always @(*) begin - soc_litedramcore_choose_cmd_valids <= 8'd0; - soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); - soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids <= 8'd0; + soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); + soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes)))); end assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids; assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9485,106 +9677,106 @@ assign soc_litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_cmd_cmd_valid) begin - soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_cmd_cmd_valid) begin + soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin - soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin + soc_litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin - soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin + soc_litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin - soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin + soc_litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin - soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin + soc_litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin - soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin + soc_litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin - soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin + soc_litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin - soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin + soc_litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin - soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + soc_litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin + soc_litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid)); always @(*) begin - soc_litedramcore_choose_req_valids <= 8'd0; - soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); - soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids <= 8'd0; + soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); + soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes)))); end assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids; assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9594,22 +9786,22 @@ assign soc_litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (soc_litedramcore_choose_req_cmd_valid) begin - soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + soc_litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (soc_litedramcore_choose_req_cmd_valid) begin + soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid)); assign soc_litedramcore_dfi_p0_reset_n = 1'd1; @@ -9626,473 +9818,473 @@ assign soc_litedramcore_dfi_p3_cke = {1{soc_litedramcore_steerer6}}; assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}}; assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (soc_litedramcore_read_available) begin - if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (soc_litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (soc_litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (soc_litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (soc_litedramcore_write_available) begin - if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (soc_litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - soc_litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); - end else begin - soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - soc_litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - soc_litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel0 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - soc_litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel1 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel1 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel1 <= 2'd2; - end - if (1'd1) begin - soc_litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - soc_litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel2 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - if (1'd1) begin - soc_litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel2 <= 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel2 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - soc_litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - soc_litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - if (1'd1) begin - soc_litedramcore_steerer_sel3 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_steerer_sel3 <= 1'd0; - if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 2'd2; - end - if (1'd0) begin - soc_litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - soc_litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - soc_litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - soc_litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - soc_litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - soc_litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - soc_litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - soc_litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (soc_litedramcore_read_available) begin + if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (soc_litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (soc_litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (soc_litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (soc_litedramcore_write_available) begin + if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (soc_litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + soc_litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed)); + end else begin + soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + soc_litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + soc_litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel0 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel1 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel2 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel2 <= 2'd2; + end + if (1'd1) begin + soc_litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel2 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel2 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + soc_litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + soc_litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_steerer_sel3 <= 1'd0; + if (1'd1) begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_steerer_sel3 <= 1'd0; + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 2'd2; + end + if (1'd0) begin + soc_litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + soc_litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + soc_litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + soc_litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + soc_litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + soc_litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + soc_litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + soc_litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + soc_litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase end assign litedramcore_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock)); @@ -10138,26 +10330,26 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_gran assign soc_user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign soc_user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - soc_litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; - end - default: begin - soc_litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - soc_litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; - end - default: begin - soc_litedramcore_interface_wdata_we <= 1'd0; - end - endcase + soc_litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data; + end + default: begin + soc_litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + soc_litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we; + end + default: begin + soc_litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -10169,129 +10361,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase end assign litedramcore_wishbone_adr = soc_wb_bus_adr; assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w; @@ -10307,357 +10499,357 @@ assign soc_wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_done0_w = soc_init_done_storage; assign csrbank0_init_error0_w = soc_init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; always @(*) begin - csrbank1_dfii_control0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_control0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_control0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_dfii_control0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_control0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dfii_control0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi0_command0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi0_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi0_command0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi0_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we); + end end assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); - end + soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we); + end end always @(*) begin - soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; - end + soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi0_address0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi0_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi0_address0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi0_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi1_command0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi1_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi1_command0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi1_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we; + end end assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; - end + soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we; + end end always @(*) begin - soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); - end + soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi1_address0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi1_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi1_address0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi1_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi2_command0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi2_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi2_command0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin - csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi2_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin + csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we; + end end assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we; - end + soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we; + end end always @(*) begin - soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin - soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we); - end + soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin + soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi2_address0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi2_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi2_address0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin - csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi2_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin + csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin - csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin + csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin - csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin + csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin - csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin + csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; always @(*) begin - csrbank1_dfii_pi3_command0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin - csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi3_command0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi3_command0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin - csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi3_command0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin + csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we); + end end assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; always @(*) begin - soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin - soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we); - end + soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we); + end end always @(*) begin - soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin - soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we; - end + soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin + soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; always @(*) begin - csrbank1_dfii_pi3_address0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi3_address0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi3_address0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin - csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi3_address0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin + csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we; + end end assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; always @(*) begin - csrbank1_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin - csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin + csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin - csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin + csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; always @(*) begin - csrbank1_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin - csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we); - end + csrbank1_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin - csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we; - end + csrbank1_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin + csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we; + end end assign soc_litedramcore_sel = soc_litedramcore_storage[0]; assign soc_litedramcore_cke = soc_litedramcore_storage[1]; @@ -10740,1194 +10932,1194 @@ assign slice_proxy13 = ((soc_ddrphy_bankmodel6_row * 11'd1024) | soc_ddrphy_bank assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col); assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 14'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 14'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 14'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 14'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 21'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 21'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 21'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 21'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= soc_user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= soc_litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 14'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= soc_litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= soc_litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (soc_litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= soc_litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 14'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= soc_litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= soc_litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (soc_litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= soc_litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 14'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= soc_litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= soc_litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (soc_litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= soc_litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 14'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= soc_litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= soc_litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (soc_litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 21'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 21'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 21'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 21'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= soc_user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 14'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= soc_litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (soc_litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 14'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= soc_litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (soc_litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 14'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= soc_litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (soc_litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= soc_litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 14'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= soc_litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= soc_litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (soc_litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write); + end + endcase end @@ -11936,1868 +12128,1868 @@ end //------------------------------------------------------------------------------ always @(posedge por_clk) begin - soc_int_rst <= 1'd0; + soc_int_rst <= 1'd0; end always @(posedge sys_clk) begin - soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0; - soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0; - soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1; - soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1; - soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2; - soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2; - soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3; - soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3; - soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4; - soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4; - soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5; - soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5; - soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6; - soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6; - soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7; - soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7; - soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read; - soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data; - soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0; - soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0; - soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1; - soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1; - soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2; - soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2; - soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3; - soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3; - soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4; - soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4; - soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5; - soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5; - soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6; - soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6; - if (soc_ddrphy_bankmodel0_precharge) begin - soc_ddrphy_bankmodel0_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel0_activate) begin - soc_ddrphy_bankmodel0_active <= 1'd1; - soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row; - end - end - if (soc_ddrphy_bankmodel1_precharge) begin - soc_ddrphy_bankmodel1_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel1_activate) begin - soc_ddrphy_bankmodel1_active <= 1'd1; - soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row; - end - end - if (soc_ddrphy_bankmodel2_precharge) begin - soc_ddrphy_bankmodel2_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel2_activate) begin - soc_ddrphy_bankmodel2_active <= 1'd1; - soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row; - end - end - if (soc_ddrphy_bankmodel3_precharge) begin - soc_ddrphy_bankmodel3_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel3_activate) begin - soc_ddrphy_bankmodel3_active <= 1'd1; - soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row; - end - end - if (soc_ddrphy_bankmodel4_precharge) begin - soc_ddrphy_bankmodel4_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel4_activate) begin - soc_ddrphy_bankmodel4_active <= 1'd1; - soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row; - end - end - if (soc_ddrphy_bankmodel5_precharge) begin - soc_ddrphy_bankmodel5_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel5_activate) begin - soc_ddrphy_bankmodel5_active <= 1'd1; - soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row; - end - end - if (soc_ddrphy_bankmodel6_precharge) begin - soc_ddrphy_bankmodel6_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel6_activate) begin - soc_ddrphy_bankmodel6_active <= 1'd1; - soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row; - end - end - if (soc_ddrphy_bankmodel7_precharge) begin - soc_ddrphy_bankmodel7_active <= 1'd0; - end else begin - if (soc_ddrphy_bankmodel7_activate) begin - soc_ddrphy_bankmodel7_active <= 1'd1; - soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row; - end - end - if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin - soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata; - end - if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin - soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata; - end - if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin - soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata; - end - if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin - soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata; - end - if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin - soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); - end else begin - soc_litedramcore_timer_count1 <= 10'd781; - end - soc_litedramcore_postponer_req_o <= 1'd0; - if (soc_litedramcore_postponer_req_i) begin - soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); - if ((soc_litedramcore_postponer_count == 1'd0)) begin - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_postponer_req_o <= 1'd1; - end - end - if (soc_litedramcore_sequencer_start0) begin - soc_litedramcore_sequencer_count <= 1'd0; - end else begin - if (soc_litedramcore_sequencer_done1) begin - if ((soc_litedramcore_sequencer_count != 1'd0)) begin - soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); - end - end - end - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd1; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd0; - end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd1; - end - if ((soc_litedramcore_sequencer_counter == 6'd35)) begin - soc_litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((soc_litedramcore_sequencer_counter != 1'd0)) begin - soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); - end else begin - if (soc_litedramcore_sequencer_start1) begin - soc_litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin - soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - soc_litedramcore_zqcs_executer_done <= 1'd0; - if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin - soc_litedramcore_cmd_payload_a <= 11'd1024; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd1; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_cmd_payload_a <= 1'd0; - soc_litedramcore_cmd_payload_ba <= 1'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_zqcs_executer_done <= 1'd1; - end - if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin - soc_litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin - soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (soc_litedramcore_zqcs_executer_start) begin - soc_litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (soc_litedramcore_bankmachine0_row_close) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine0_row_open) begin - soc_litedramcore_bankmachine0_row_opened <= 1'd1; - soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first; - soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine0_twtpcon_valid) begin - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin - soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine0_trccon_valid) begin - soc_litedramcore_bankmachine0_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin - soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine0_trascon_valid) begin - soc_litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin - soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (soc_litedramcore_bankmachine1_row_close) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine1_row_open) begin - soc_litedramcore_bankmachine1_row_opened <= 1'd1; - soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first; - soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine1_twtpcon_valid) begin - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin - soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine1_trccon_valid) begin - soc_litedramcore_bankmachine1_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin - soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine1_trascon_valid) begin - soc_litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin - soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (soc_litedramcore_bankmachine2_row_close) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine2_row_open) begin - soc_litedramcore_bankmachine2_row_opened <= 1'd1; - soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first; - soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine2_twtpcon_valid) begin - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin - soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine2_trccon_valid) begin - soc_litedramcore_bankmachine2_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin - soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine2_trascon_valid) begin - soc_litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin - soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (soc_litedramcore_bankmachine3_row_close) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine3_row_open) begin - soc_litedramcore_bankmachine3_row_opened <= 1'd1; - soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first; - soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine3_twtpcon_valid) begin - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin - soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine3_trccon_valid) begin - soc_litedramcore_bankmachine3_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin - soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine3_trascon_valid) begin - soc_litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin - soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (soc_litedramcore_bankmachine4_row_close) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine4_row_open) begin - soc_litedramcore_bankmachine4_row_opened <= 1'd1; - soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first; - soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine4_twtpcon_valid) begin - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin - soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine4_trccon_valid) begin - soc_litedramcore_bankmachine4_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin - soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine4_trascon_valid) begin - soc_litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin - soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (soc_litedramcore_bankmachine5_row_close) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine5_row_open) begin - soc_litedramcore_bankmachine5_row_opened <= 1'd1; - soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first; - soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine5_twtpcon_valid) begin - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin - soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine5_trccon_valid) begin - soc_litedramcore_bankmachine5_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin - soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine5_trascon_valid) begin - soc_litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin - soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (soc_litedramcore_bankmachine6_row_close) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine6_row_open) begin - soc_litedramcore_bankmachine6_row_opened <= 1'd1; - soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first; - soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine6_twtpcon_valid) begin - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin - soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine6_trccon_valid) begin - soc_litedramcore_bankmachine6_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin - soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine6_trascon_valid) begin - soc_litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin - soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (soc_litedramcore_bankmachine7_row_close) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (soc_litedramcore_bankmachine7_row_open) begin - soc_litedramcore_bankmachine7_row_opened <= 1'd1; - soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid; - soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first; - soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (soc_litedramcore_bankmachine7_twtpcon_valid) begin - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin - soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine7_trccon_valid) begin - soc_litedramcore_bankmachine7_trccon_count <= 3'd5; - if (1'd0) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin - soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_bankmachine7_trascon_valid) begin - soc_litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin - soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); - if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin - soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~soc_litedramcore_en0)) begin - soc_litedramcore_time0 <= 5'd31; - end else begin - if ((~soc_litedramcore_max_time0)) begin - soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); - end - end - if ((~soc_litedramcore_en1)) begin - soc_litedramcore_time1 <= 4'd15; - end else begin - if ((~soc_litedramcore_max_time1)) begin - soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); - end - end - if (soc_litedramcore_choose_cmd_ce) begin - case (soc_litedramcore_choose_cmd_grant) - 1'd0: begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (soc_litedramcore_choose_cmd_request[7]) begin - soc_litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (soc_litedramcore_choose_cmd_request[0]) begin - soc_litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_cmd_request[1]) begin - soc_litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_cmd_request[2]) begin - soc_litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_cmd_request[3]) begin - soc_litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_cmd_request[4]) begin - soc_litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_cmd_request[5]) begin - soc_litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_cmd_request[6]) begin - soc_litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (soc_litedramcore_choose_req_ce) begin - case (soc_litedramcore_choose_req_grant) - 1'd0: begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end else begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (soc_litedramcore_choose_req_request[7]) begin - soc_litedramcore_choose_req_grant <= 3'd7; - end else begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (soc_litedramcore_choose_req_request[0]) begin - soc_litedramcore_choose_req_grant <= 1'd0; - end else begin - if (soc_litedramcore_choose_req_request[1]) begin - soc_litedramcore_choose_req_grant <= 1'd1; - end else begin - if (soc_litedramcore_choose_req_request[2]) begin - soc_litedramcore_choose_req_grant <= 2'd2; - end else begin - if (soc_litedramcore_choose_req_request[3]) begin - soc_litedramcore_choose_req_grant <= 2'd3; - end else begin - if (soc_litedramcore_choose_req_request[4]) begin - soc_litedramcore_choose_req_grant <= 3'd4; - end else begin - if (soc_litedramcore_choose_req_request[5]) begin - soc_litedramcore_choose_req_grant <= 3'd5; - end else begin - if (soc_litedramcore_choose_req_request[6]) begin - soc_litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - soc_litedramcore_dfi_p0_cs_n <= 1'd0; - soc_litedramcore_dfi_p0_bank <= array_muxed0; - soc_litedramcore_dfi_p0_address <= array_muxed1; - soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2); - soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3); - soc_litedramcore_dfi_p0_we_n <= (~array_muxed4); - soc_litedramcore_dfi_p0_rddata_en <= array_muxed5; - soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6; - soc_litedramcore_dfi_p1_cs_n <= 1'd0; - soc_litedramcore_dfi_p1_bank <= array_muxed7; - soc_litedramcore_dfi_p1_address <= array_muxed8; - soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9); - soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10); - soc_litedramcore_dfi_p1_we_n <= (~array_muxed11); - soc_litedramcore_dfi_p1_rddata_en <= array_muxed12; - soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13; - soc_litedramcore_dfi_p2_cs_n <= 1'd0; - soc_litedramcore_dfi_p2_bank <= array_muxed14; - soc_litedramcore_dfi_p2_address <= array_muxed15; - soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16); - soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17); - soc_litedramcore_dfi_p2_we_n <= (~array_muxed18); - soc_litedramcore_dfi_p2_rddata_en <= array_muxed19; - soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20; - soc_litedramcore_dfi_p3_cs_n <= 1'd0; - soc_litedramcore_dfi_p3_bank <= array_muxed21; - soc_litedramcore_dfi_p3_address <= array_muxed22; - soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23); - soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24); - soc_litedramcore_dfi_p3_we_n <= (~array_muxed25); - soc_litedramcore_dfi_p3_rddata_en <= array_muxed26; - soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (soc_litedramcore_trrdcon_valid) begin - soc_litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - soc_litedramcore_trrdcon_ready <= 1'd1; - end else begin - soc_litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_trrdcon_ready)) begin - soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); - if ((soc_litedramcore_trrdcon_count == 1'd1)) begin - soc_litedramcore_trrdcon_ready <= 1'd1; - end - end - end - soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; - if ((soc_litedramcore_tfawcon_count < 3'd4)) begin - if ((soc_litedramcore_tfawcon_count == 2'd3)) begin - soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); - end else begin - soc_litedramcore_tfawcon_ready <= 1'd1; - end - end - if (soc_litedramcore_tccdcon_valid) begin - soc_litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - soc_litedramcore_tccdcon_ready <= 1'd1; - end else begin - soc_litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_tccdcon_ready)) begin - soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); - if ((soc_litedramcore_tccdcon_count == 1'd1)) begin - soc_litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (soc_litedramcore_twtrcon_valid) begin - soc_litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end else begin - soc_litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~soc_litedramcore_twtrcon_ready)) begin - soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); - if ((soc_litedramcore_twtrcon_count == 1'd1)) begin - soc_litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - soc_init_done_storage <= csrbank0_init_done0_r; - end - soc_init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - soc_init_error_storage <= csrbank0_init_error0_r; - end - soc_init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; - end - 4'd13: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; - end - 4'd14: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; - end - 4'd15: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; - end - 5'd16: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; - end - 5'd17: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; - end - 5'd18: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; - end - 5'd19: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; - end - 5'd20: begin - interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; - end - 5'd21: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; - end - 5'd22: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; - end - 5'd23: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; - end - 5'd24: begin - interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; - end - endcase - end - if (csrbank1_dfii_control0_re) begin - soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; - end - soc_litedramcore_re <= csrbank1_dfii_control0_re; - if (csrbank1_dfii_pi0_command0_re) begin - soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; - end - soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; - if (csrbank1_dfii_pi0_address0_re) begin - soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; - end - soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; - if (csrbank1_dfii_pi0_baddress0_re) begin - soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; - end - soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; - if (csrbank1_dfii_pi0_wrdata0_re) begin - soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; - end - soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; - soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re; - if (csrbank1_dfii_pi1_command0_re) begin - soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; - end - soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; - if (csrbank1_dfii_pi1_address0_re) begin - soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; - end - soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; - if (csrbank1_dfii_pi1_baddress0_re) begin - soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; - end - soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; - if (csrbank1_dfii_pi1_wrdata0_re) begin - soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; - end - soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; - soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re; - if (csrbank1_dfii_pi2_command0_re) begin - soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; - end - soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; - if (csrbank1_dfii_pi2_address0_re) begin - soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; - end - soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; - if (csrbank1_dfii_pi2_baddress0_re) begin - soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; - end - soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; - if (csrbank1_dfii_pi2_wrdata0_re) begin - soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; - end - soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; - soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re; - if (csrbank1_dfii_pi3_command0_re) begin - soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; - end - soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; - if (csrbank1_dfii_pi3_address0_re) begin - soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; - end - soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; - if (csrbank1_dfii_pi3_baddress0_re) begin - soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; - end - soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; - if (csrbank1_dfii_pi3_wrdata0_re) begin - soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; - end - soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; - soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re; - if (sys_rst) begin - soc_ddrphy_bankmodel0_active <= 1'd0; - soc_ddrphy_bankmodel0_row <= 14'd0; - soc_ddrphy_bankmodel1_active <= 1'd0; - soc_ddrphy_bankmodel1_row <= 14'd0; - soc_ddrphy_bankmodel2_active <= 1'd0; - soc_ddrphy_bankmodel2_row <= 14'd0; - soc_ddrphy_bankmodel3_active <= 1'd0; - soc_ddrphy_bankmodel3_row <= 14'd0; - soc_ddrphy_bankmodel4_active <= 1'd0; - soc_ddrphy_bankmodel4_row <= 14'd0; - soc_ddrphy_bankmodel5_active <= 1'd0; - soc_ddrphy_bankmodel5_row <= 14'd0; - soc_ddrphy_bankmodel6_active <= 1'd0; - soc_ddrphy_bankmodel6_row <= 14'd0; - soc_ddrphy_bankmodel7_active <= 1'd0; - soc_ddrphy_bankmodel7_row <= 14'd0; - soc_ddrphy_new_bank_write0 <= 1'd0; - soc_ddrphy_new_bank_write_col0 <= 10'd0; - soc_ddrphy_new_bank_write1 <= 1'd0; - soc_ddrphy_new_bank_write_col1 <= 10'd0; - soc_ddrphy_new_bank_write2 <= 1'd0; - soc_ddrphy_new_bank_write_col2 <= 10'd0; - soc_ddrphy_new_bank_write3 <= 1'd0; - soc_ddrphy_new_bank_write_col3 <= 10'd0; - soc_ddrphy_new_bank_write4 <= 1'd0; - soc_ddrphy_new_bank_write_col4 <= 10'd0; - soc_ddrphy_new_bank_write5 <= 1'd0; - soc_ddrphy_new_bank_write_col5 <= 10'd0; - soc_ddrphy_new_bank_write6 <= 1'd0; - soc_ddrphy_new_bank_write_col6 <= 10'd0; - soc_ddrphy_new_bank_write7 <= 1'd0; - soc_ddrphy_new_bank_write_col7 <= 10'd0; - soc_ddrphy_new_banks_read0 <= 1'd0; - soc_ddrphy_new_banks_read_data0 <= 128'd0; - soc_ddrphy_new_banks_read1 <= 1'd0; - soc_ddrphy_new_banks_read_data1 <= 128'd0; - soc_ddrphy_new_banks_read2 <= 1'd0; - soc_ddrphy_new_banks_read_data2 <= 128'd0; - soc_ddrphy_new_banks_read3 <= 1'd0; - soc_ddrphy_new_banks_read_data3 <= 128'd0; - soc_ddrphy_new_banks_read4 <= 1'd0; - soc_ddrphy_new_banks_read_data4 <= 128'd0; - soc_ddrphy_new_banks_read5 <= 1'd0; - soc_ddrphy_new_banks_read_data5 <= 128'd0; - soc_ddrphy_new_banks_read6 <= 1'd0; - soc_ddrphy_new_banks_read_data6 <= 128'd0; - soc_ddrphy_new_banks_read7 <= 1'd0; - soc_ddrphy_new_banks_read_data7 <= 128'd0; - soc_litedramcore_storage <= 4'd1; - soc_litedramcore_re <= 1'd0; - soc_litedramcore_phaseinjector0_command_storage <= 6'd0; - soc_litedramcore_phaseinjector0_command_re <= 1'd0; - soc_litedramcore_phaseinjector0_address_re <= 1'd0; - soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector0_rddata_status <= 32'd0; - soc_litedramcore_phaseinjector0_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector1_command_storage <= 6'd0; - soc_litedramcore_phaseinjector1_command_re <= 1'd0; - soc_litedramcore_phaseinjector1_address_re <= 1'd0; - soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector1_rddata_status <= 32'd0; - soc_litedramcore_phaseinjector1_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector2_command_storage <= 6'd0; - soc_litedramcore_phaseinjector2_command_re <= 1'd0; - soc_litedramcore_phaseinjector2_address_re <= 1'd0; - soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector2_rddata_status <= 32'd0; - soc_litedramcore_phaseinjector2_rddata_re <= 1'd0; - soc_litedramcore_phaseinjector3_command_storage <= 6'd0; - soc_litedramcore_phaseinjector3_command_re <= 1'd0; - soc_litedramcore_phaseinjector3_address_re <= 1'd0; - soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; - soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; - soc_litedramcore_phaseinjector3_rddata_status <= 32'd0; - soc_litedramcore_phaseinjector3_rddata_re <= 1'd0; - soc_litedramcore_dfi_p0_address <= 14'd0; - soc_litedramcore_dfi_p0_bank <= 3'd0; - soc_litedramcore_dfi_p0_cas_n <= 1'd1; - soc_litedramcore_dfi_p0_cs_n <= 1'd1; - soc_litedramcore_dfi_p0_ras_n <= 1'd1; - soc_litedramcore_dfi_p0_we_n <= 1'd1; - soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p0_rddata_en <= 1'd0; - soc_litedramcore_dfi_p1_address <= 14'd0; - soc_litedramcore_dfi_p1_bank <= 3'd0; - soc_litedramcore_dfi_p1_cas_n <= 1'd1; - soc_litedramcore_dfi_p1_cs_n <= 1'd1; - soc_litedramcore_dfi_p1_ras_n <= 1'd1; - soc_litedramcore_dfi_p1_we_n <= 1'd1; - soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p1_rddata_en <= 1'd0; - soc_litedramcore_dfi_p2_address <= 14'd0; - soc_litedramcore_dfi_p2_bank <= 3'd0; - soc_litedramcore_dfi_p2_cas_n <= 1'd1; - soc_litedramcore_dfi_p2_cs_n <= 1'd1; - soc_litedramcore_dfi_p2_ras_n <= 1'd1; - soc_litedramcore_dfi_p2_we_n <= 1'd1; - soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p2_rddata_en <= 1'd0; - soc_litedramcore_dfi_p3_address <= 14'd0; - soc_litedramcore_dfi_p3_bank <= 3'd0; - soc_litedramcore_dfi_p3_cas_n <= 1'd1; - soc_litedramcore_dfi_p3_cs_n <= 1'd1; - soc_litedramcore_dfi_p3_ras_n <= 1'd1; - soc_litedramcore_dfi_p3_we_n <= 1'd1; - soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; - soc_litedramcore_dfi_p3_rddata_en <= 1'd0; - soc_litedramcore_cmd_payload_a <= 14'd0; - soc_litedramcore_cmd_payload_ba <= 3'd0; - soc_litedramcore_cmd_payload_cas <= 1'd0; - soc_litedramcore_cmd_payload_ras <= 1'd0; - soc_litedramcore_cmd_payload_we <= 1'd0; - soc_litedramcore_timer_count1 <= 10'd781; - soc_litedramcore_postponer_req_o <= 1'd0; - soc_litedramcore_postponer_count <= 1'd0; - soc_litedramcore_sequencer_done1 <= 1'd0; - soc_litedramcore_sequencer_counter <= 6'd0; - soc_litedramcore_sequencer_count <= 1'd0; - soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; - soc_litedramcore_zqcs_executer_done <= 1'd0; - soc_litedramcore_zqcs_executer_counter <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine0_row <= 14'd0; - soc_litedramcore_bankmachine0_row_opened <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trccon_count <= 3'd0; - soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine0_trascon_count <= 3'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine1_row <= 14'd0; - soc_litedramcore_bankmachine1_row_opened <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trccon_count <= 3'd0; - soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine1_trascon_count <= 3'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine2_row <= 14'd0; - soc_litedramcore_bankmachine2_row_opened <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trccon_count <= 3'd0; - soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine2_trascon_count <= 3'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine3_row <= 14'd0; - soc_litedramcore_bankmachine3_row_opened <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trccon_count <= 3'd0; - soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine3_trascon_count <= 3'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine4_row <= 14'd0; - soc_litedramcore_bankmachine4_row_opened <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trccon_count <= 3'd0; - soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine4_trascon_count <= 3'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine5_row <= 14'd0; - soc_litedramcore_bankmachine5_row_opened <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trccon_count <= 3'd0; - soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine5_trascon_count <= 3'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine6_row <= 14'd0; - soc_litedramcore_bankmachine6_row_opened <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trccon_count <= 3'd0; - soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine6_trascon_count <= 3'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; - soc_litedramcore_bankmachine7_row <= 14'd0; - soc_litedramcore_bankmachine7_row_opened <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; - soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trccon_count <= 3'd0; - soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; - soc_litedramcore_bankmachine7_trascon_count <= 3'd0; - soc_litedramcore_choose_cmd_grant <= 3'd0; - soc_litedramcore_choose_req_grant <= 3'd0; - soc_litedramcore_trrdcon_ready <= 1'd0; - soc_litedramcore_trrdcon_count <= 1'd0; - soc_litedramcore_tfawcon_ready <= 1'd1; - soc_litedramcore_tfawcon_window <= 5'd0; - soc_litedramcore_tccdcon_ready <= 1'd0; - soc_litedramcore_tccdcon_count <= 1'd0; - soc_litedramcore_twtrcon_ready <= 1'd0; - soc_litedramcore_twtrcon_count <= 3'd0; - soc_litedramcore_time0 <= 5'd0; - soc_litedramcore_time1 <= 4'd0; - soc_init_done_storage <= 1'd0; - soc_init_done_re <= 1'd0; - soc_init_error_storage <= 1'd0; - soc_init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0; + soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0; + soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1; + soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1; + soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2; + soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2; + soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3; + soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3; + soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4; + soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4; + soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5; + soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5; + soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6; + soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6; + soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7; + soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7; + soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read; + soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data; + soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0; + soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0; + soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1; + soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1; + soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2; + soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2; + soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3; + soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3; + soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4; + soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4; + soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5; + soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5; + soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6; + soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6; + if (soc_ddrphy_bankmodel0_precharge) begin + soc_ddrphy_bankmodel0_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel0_activate) begin + soc_ddrphy_bankmodel0_active <= 1'd1; + soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row; + end + end + if (soc_ddrphy_bankmodel1_precharge) begin + soc_ddrphy_bankmodel1_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel1_activate) begin + soc_ddrphy_bankmodel1_active <= 1'd1; + soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row; + end + end + if (soc_ddrphy_bankmodel2_precharge) begin + soc_ddrphy_bankmodel2_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel2_activate) begin + soc_ddrphy_bankmodel2_active <= 1'd1; + soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row; + end + end + if (soc_ddrphy_bankmodel3_precharge) begin + soc_ddrphy_bankmodel3_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel3_activate) begin + soc_ddrphy_bankmodel3_active <= 1'd1; + soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row; + end + end + if (soc_ddrphy_bankmodel4_precharge) begin + soc_ddrphy_bankmodel4_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel4_activate) begin + soc_ddrphy_bankmodel4_active <= 1'd1; + soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row; + end + end + if (soc_ddrphy_bankmodel5_precharge) begin + soc_ddrphy_bankmodel5_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel5_activate) begin + soc_ddrphy_bankmodel5_active <= 1'd1; + soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row; + end + end + if (soc_ddrphy_bankmodel6_precharge) begin + soc_ddrphy_bankmodel6_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel6_activate) begin + soc_ddrphy_bankmodel6_active <= 1'd1; + soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row; + end + end + if (soc_ddrphy_bankmodel7_precharge) begin + soc_ddrphy_bankmodel7_active <= 1'd0; + end else begin + if (soc_ddrphy_bankmodel7_activate) begin + soc_ddrphy_bankmodel7_active <= 1'd1; + soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row; + end + end + if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin + soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata; + end + if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin + soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata; + end + if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin + soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata; + end + if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin + soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata; + end + if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin + soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1); + end else begin + soc_litedramcore_timer_count1 <= 10'd781; + end + soc_litedramcore_postponer_req_o <= 1'd0; + if (soc_litedramcore_postponer_req_i) begin + soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1); + if ((soc_litedramcore_postponer_count == 1'd0)) begin + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_postponer_req_o <= 1'd1; + end + end + if (soc_litedramcore_sequencer_start0) begin + soc_litedramcore_sequencer_count <= 1'd0; + end else begin + if (soc_litedramcore_sequencer_done1) begin + if ((soc_litedramcore_sequencer_count != 1'd0)) begin + soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1); + end + end + end + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd1; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd0; + end + if ((soc_litedramcore_sequencer_counter == 6'd35)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd1; + end + if ((soc_litedramcore_sequencer_counter == 6'd35)) begin + soc_litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_sequencer_counter != 1'd0)) begin + soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1); + end else begin + if (soc_litedramcore_sequencer_start1) begin + soc_litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin + soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + soc_litedramcore_zqcs_executer_done <= 1'd0; + if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin + soc_litedramcore_cmd_payload_a <= 11'd1024; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd1; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_cmd_payload_a <= 1'd0; + soc_litedramcore_cmd_payload_ba <= 1'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_zqcs_executer_done <= 1'd1; + end + if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin + soc_litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin + soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (soc_litedramcore_zqcs_executer_start) begin + soc_litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (soc_litedramcore_bankmachine0_row_close) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine0_row_open) begin + soc_litedramcore_bankmachine0_row_opened <= 1'd1; + soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin + soc_litedramcore_bankmachine0_produce <= (soc_litedramcore_bankmachine0_produce + 1'd1); + end + if (soc_litedramcore_bankmachine0_do_read) begin + soc_litedramcore_bankmachine0_consume <= (soc_litedramcore_bankmachine0_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin + if ((~soc_litedramcore_bankmachine0_do_read)) begin + soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine0_do_read) begin + soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine0_pipe_valid_source_valid <= soc_litedramcore_bankmachine0_pipe_valid_sink_valid; + soc_litedramcore_bankmachine0_pipe_valid_source_first <= soc_litedramcore_bankmachine0_pipe_valid_sink_first; + soc_litedramcore_bankmachine0_pipe_valid_source_last <= soc_litedramcore_bankmachine0_pipe_valid_sink_last; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine0_twtpcon_valid) begin + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin + soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trccon_valid) begin + soc_litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin + soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine0_trascon_valid) begin + soc_litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin + soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (soc_litedramcore_bankmachine1_row_close) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine1_row_open) begin + soc_litedramcore_bankmachine1_row_opened <= 1'd1; + soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin + soc_litedramcore_bankmachine1_produce <= (soc_litedramcore_bankmachine1_produce + 1'd1); + end + if (soc_litedramcore_bankmachine1_do_read) begin + soc_litedramcore_bankmachine1_consume <= (soc_litedramcore_bankmachine1_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin + if ((~soc_litedramcore_bankmachine1_do_read)) begin + soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine1_do_read) begin + soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine1_pipe_valid_source_valid <= soc_litedramcore_bankmachine1_pipe_valid_sink_valid; + soc_litedramcore_bankmachine1_pipe_valid_source_first <= soc_litedramcore_bankmachine1_pipe_valid_sink_first; + soc_litedramcore_bankmachine1_pipe_valid_source_last <= soc_litedramcore_bankmachine1_pipe_valid_sink_last; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine1_twtpcon_valid) begin + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin + soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trccon_valid) begin + soc_litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin + soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine1_trascon_valid) begin + soc_litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin + soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (soc_litedramcore_bankmachine2_row_close) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine2_row_open) begin + soc_litedramcore_bankmachine2_row_opened <= 1'd1; + soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin + soc_litedramcore_bankmachine2_produce <= (soc_litedramcore_bankmachine2_produce + 1'd1); + end + if (soc_litedramcore_bankmachine2_do_read) begin + soc_litedramcore_bankmachine2_consume <= (soc_litedramcore_bankmachine2_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin + if ((~soc_litedramcore_bankmachine2_do_read)) begin + soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine2_do_read) begin + soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine2_pipe_valid_source_valid <= soc_litedramcore_bankmachine2_pipe_valid_sink_valid; + soc_litedramcore_bankmachine2_pipe_valid_source_first <= soc_litedramcore_bankmachine2_pipe_valid_sink_first; + soc_litedramcore_bankmachine2_pipe_valid_source_last <= soc_litedramcore_bankmachine2_pipe_valid_sink_last; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine2_twtpcon_valid) begin + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin + soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trccon_valid) begin + soc_litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin + soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine2_trascon_valid) begin + soc_litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin + soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (soc_litedramcore_bankmachine3_row_close) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine3_row_open) begin + soc_litedramcore_bankmachine3_row_opened <= 1'd1; + soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin + soc_litedramcore_bankmachine3_produce <= (soc_litedramcore_bankmachine3_produce + 1'd1); + end + if (soc_litedramcore_bankmachine3_do_read) begin + soc_litedramcore_bankmachine3_consume <= (soc_litedramcore_bankmachine3_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin + if ((~soc_litedramcore_bankmachine3_do_read)) begin + soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine3_do_read) begin + soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine3_pipe_valid_source_valid <= soc_litedramcore_bankmachine3_pipe_valid_sink_valid; + soc_litedramcore_bankmachine3_pipe_valid_source_first <= soc_litedramcore_bankmachine3_pipe_valid_sink_first; + soc_litedramcore_bankmachine3_pipe_valid_source_last <= soc_litedramcore_bankmachine3_pipe_valid_sink_last; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine3_twtpcon_valid) begin + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin + soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trccon_valid) begin + soc_litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin + soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine3_trascon_valid) begin + soc_litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin + soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (soc_litedramcore_bankmachine4_row_close) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine4_row_open) begin + soc_litedramcore_bankmachine4_row_opened <= 1'd1; + soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin + soc_litedramcore_bankmachine4_produce <= (soc_litedramcore_bankmachine4_produce + 1'd1); + end + if (soc_litedramcore_bankmachine4_do_read) begin + soc_litedramcore_bankmachine4_consume <= (soc_litedramcore_bankmachine4_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin + if ((~soc_litedramcore_bankmachine4_do_read)) begin + soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine4_do_read) begin + soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine4_pipe_valid_source_valid <= soc_litedramcore_bankmachine4_pipe_valid_sink_valid; + soc_litedramcore_bankmachine4_pipe_valid_source_first <= soc_litedramcore_bankmachine4_pipe_valid_sink_first; + soc_litedramcore_bankmachine4_pipe_valid_source_last <= soc_litedramcore_bankmachine4_pipe_valid_sink_last; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine4_twtpcon_valid) begin + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin + soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trccon_valid) begin + soc_litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin + soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine4_trascon_valid) begin + soc_litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin + soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (soc_litedramcore_bankmachine5_row_close) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine5_row_open) begin + soc_litedramcore_bankmachine5_row_opened <= 1'd1; + soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin + soc_litedramcore_bankmachine5_produce <= (soc_litedramcore_bankmachine5_produce + 1'd1); + end + if (soc_litedramcore_bankmachine5_do_read) begin + soc_litedramcore_bankmachine5_consume <= (soc_litedramcore_bankmachine5_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin + if ((~soc_litedramcore_bankmachine5_do_read)) begin + soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine5_do_read) begin + soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine5_pipe_valid_source_valid <= soc_litedramcore_bankmachine5_pipe_valid_sink_valid; + soc_litedramcore_bankmachine5_pipe_valid_source_first <= soc_litedramcore_bankmachine5_pipe_valid_sink_first; + soc_litedramcore_bankmachine5_pipe_valid_source_last <= soc_litedramcore_bankmachine5_pipe_valid_sink_last; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine5_twtpcon_valid) begin + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin + soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trccon_valid) begin + soc_litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin + soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine5_trascon_valid) begin + soc_litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin + soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (soc_litedramcore_bankmachine6_row_close) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine6_row_open) begin + soc_litedramcore_bankmachine6_row_opened <= 1'd1; + soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin + soc_litedramcore_bankmachine6_produce <= (soc_litedramcore_bankmachine6_produce + 1'd1); + end + if (soc_litedramcore_bankmachine6_do_read) begin + soc_litedramcore_bankmachine6_consume <= (soc_litedramcore_bankmachine6_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin + if ((~soc_litedramcore_bankmachine6_do_read)) begin + soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine6_do_read) begin + soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine6_pipe_valid_source_valid <= soc_litedramcore_bankmachine6_pipe_valid_sink_valid; + soc_litedramcore_bankmachine6_pipe_valid_source_first <= soc_litedramcore_bankmachine6_pipe_valid_sink_first; + soc_litedramcore_bankmachine6_pipe_valid_source_last <= soc_litedramcore_bankmachine6_pipe_valid_sink_last; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine6_twtpcon_valid) begin + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin + soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trccon_valid) begin + soc_litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin + soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine6_trascon_valid) begin + soc_litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin + soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (soc_litedramcore_bankmachine7_row_close) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (soc_litedramcore_bankmachine7_row_open) begin + soc_litedramcore_bankmachine7_row_opened <= 1'd1; + soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end + end + if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin + soc_litedramcore_bankmachine7_produce <= (soc_litedramcore_bankmachine7_produce + 1'd1); + end + if (soc_litedramcore_bankmachine7_do_read) begin + soc_litedramcore_bankmachine7_consume <= (soc_litedramcore_bankmachine7_consume + 1'd1); + end + if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin + if ((~soc_litedramcore_bankmachine7_do_read)) begin + soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (soc_litedramcore_bankmachine7_do_read) begin + soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready)) begin + soc_litedramcore_bankmachine7_pipe_valid_source_valid <= soc_litedramcore_bankmachine7_pipe_valid_sink_valid; + soc_litedramcore_bankmachine7_pipe_valid_source_first <= soc_litedramcore_bankmachine7_pipe_valid_sink_first; + soc_litedramcore_bankmachine7_pipe_valid_source_last <= soc_litedramcore_bankmachine7_pipe_valid_sink_last; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (soc_litedramcore_bankmachine7_twtpcon_valid) begin + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin + soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trccon_valid) begin + soc_litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin + soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_bankmachine7_trascon_valid) begin + soc_litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin + soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1); + if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin + soc_litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~soc_litedramcore_en0)) begin + soc_litedramcore_time0 <= 5'd31; + end else begin + if ((~soc_litedramcore_max_time0)) begin + soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1); + end + end + if ((~soc_litedramcore_en1)) begin + soc_litedramcore_time1 <= 4'd15; + end else begin + if ((~soc_litedramcore_max_time1)) begin + soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1); + end + end + if (soc_litedramcore_choose_cmd_ce) begin + case (soc_litedramcore_choose_cmd_grant) + 1'd0: begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_cmd_request[7]) begin + soc_litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_cmd_request[0]) begin + soc_litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_cmd_request[1]) begin + soc_litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_cmd_request[2]) begin + soc_litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_cmd_request[3]) begin + soc_litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_cmd_request[4]) begin + soc_litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_cmd_request[5]) begin + soc_litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_cmd_request[6]) begin + soc_litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (soc_litedramcore_choose_req_ce) begin + case (soc_litedramcore_choose_req_grant) + 1'd0: begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end else begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (soc_litedramcore_choose_req_request[7]) begin + soc_litedramcore_choose_req_grant <= 3'd7; + end else begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (soc_litedramcore_choose_req_request[0]) begin + soc_litedramcore_choose_req_grant <= 1'd0; + end else begin + if (soc_litedramcore_choose_req_request[1]) begin + soc_litedramcore_choose_req_grant <= 1'd1; + end else begin + if (soc_litedramcore_choose_req_request[2]) begin + soc_litedramcore_choose_req_grant <= 2'd2; + end else begin + if (soc_litedramcore_choose_req_request[3]) begin + soc_litedramcore_choose_req_grant <= 2'd3; + end else begin + if (soc_litedramcore_choose_req_request[4]) begin + soc_litedramcore_choose_req_grant <= 3'd4; + end else begin + if (soc_litedramcore_choose_req_request[5]) begin + soc_litedramcore_choose_req_grant <= 3'd5; + end else begin + if (soc_litedramcore_choose_req_request[6]) begin + soc_litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + soc_litedramcore_dfi_p0_cs_n <= 1'd0; + soc_litedramcore_dfi_p0_bank <= array_muxed0; + soc_litedramcore_dfi_p0_address <= array_muxed1; + soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2); + soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3); + soc_litedramcore_dfi_p0_we_n <= (~array_muxed4); + soc_litedramcore_dfi_p0_rddata_en <= array_muxed5; + soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6; + soc_litedramcore_dfi_p1_cs_n <= 1'd0; + soc_litedramcore_dfi_p1_bank <= array_muxed7; + soc_litedramcore_dfi_p1_address <= array_muxed8; + soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9); + soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10); + soc_litedramcore_dfi_p1_we_n <= (~array_muxed11); + soc_litedramcore_dfi_p1_rddata_en <= array_muxed12; + soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13; + soc_litedramcore_dfi_p2_cs_n <= 1'd0; + soc_litedramcore_dfi_p2_bank <= array_muxed14; + soc_litedramcore_dfi_p2_address <= array_muxed15; + soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16); + soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17); + soc_litedramcore_dfi_p2_we_n <= (~array_muxed18); + soc_litedramcore_dfi_p2_rddata_en <= array_muxed19; + soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20; + soc_litedramcore_dfi_p3_cs_n <= 1'd0; + soc_litedramcore_dfi_p3_bank <= array_muxed21; + soc_litedramcore_dfi_p3_address <= array_muxed22; + soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23); + soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24); + soc_litedramcore_dfi_p3_we_n <= (~array_muxed25); + soc_litedramcore_dfi_p3_rddata_en <= array_muxed26; + soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (soc_litedramcore_trrdcon_valid) begin + soc_litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end else begin + soc_litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_trrdcon_ready)) begin + soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1); + if ((soc_litedramcore_trrdcon_count == 1'd1)) begin + soc_litedramcore_trrdcon_ready <= 1'd1; + end + end + end + soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid}; + if ((soc_litedramcore_tfawcon_count < 3'd4)) begin + if ((soc_litedramcore_tfawcon_count == 2'd3)) begin + soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid); + end else begin + soc_litedramcore_tfawcon_ready <= 1'd1; + end + end + if (soc_litedramcore_tccdcon_valid) begin + soc_litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end else begin + soc_litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_tccdcon_ready)) begin + soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1); + if ((soc_litedramcore_tccdcon_count == 1'd1)) begin + soc_litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (soc_litedramcore_twtrcon_valid) begin + soc_litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end else begin + soc_litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~soc_litedramcore_twtrcon_ready)) begin + soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1); + if ((soc_litedramcore_twtrcon_count == 1'd1)) begin + soc_litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + soc_init_done_storage <= csrbank0_init_done0_r; + end + soc_init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + soc_init_error_storage <= csrbank0_init_error0_r; + end + soc_init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; + end + 4'd13: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + end + 4'd14: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + end + 5'd16: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; + end + 5'd19: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + end + 5'd20: begin + interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + end + 5'd22: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank1_dfii_control0_re) begin + soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; + end + soc_litedramcore_re <= csrbank1_dfii_control0_re; + if (csrbank1_dfii_pi0_command0_re) begin + soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; + end + soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; + if (csrbank1_dfii_pi0_address0_re) begin + soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; + end + soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; + if (csrbank1_dfii_pi0_baddress0_re) begin + soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; + end + soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; + if (csrbank1_dfii_pi0_wrdata0_re) begin + soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; + end + soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; + soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re; + if (csrbank1_dfii_pi1_command0_re) begin + soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; + end + soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; + if (csrbank1_dfii_pi1_address0_re) begin + soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; + end + soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; + if (csrbank1_dfii_pi1_baddress0_re) begin + soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; + end + soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; + if (csrbank1_dfii_pi1_wrdata0_re) begin + soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; + end + soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; + soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re; + if (csrbank1_dfii_pi2_command0_re) begin + soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; + end + soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; + if (csrbank1_dfii_pi2_address0_re) begin + soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; + end + soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; + if (csrbank1_dfii_pi2_baddress0_re) begin + soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; + end + soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; + if (csrbank1_dfii_pi2_wrdata0_re) begin + soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; + end + soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; + soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re; + if (csrbank1_dfii_pi3_command0_re) begin + soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; + end + soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; + if (csrbank1_dfii_pi3_address0_re) begin + soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; + end + soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; + if (csrbank1_dfii_pi3_baddress0_re) begin + soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; + end + soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; + if (csrbank1_dfii_pi3_wrdata0_re) begin + soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; + end + soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; + soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re; + if (sys_rst) begin + soc_ddrphy_bankmodel0_active <= 1'd0; + soc_ddrphy_bankmodel0_row <= 14'd0; + soc_ddrphy_bankmodel1_active <= 1'd0; + soc_ddrphy_bankmodel1_row <= 14'd0; + soc_ddrphy_bankmodel2_active <= 1'd0; + soc_ddrphy_bankmodel2_row <= 14'd0; + soc_ddrphy_bankmodel3_active <= 1'd0; + soc_ddrphy_bankmodel3_row <= 14'd0; + soc_ddrphy_bankmodel4_active <= 1'd0; + soc_ddrphy_bankmodel4_row <= 14'd0; + soc_ddrphy_bankmodel5_active <= 1'd0; + soc_ddrphy_bankmodel5_row <= 14'd0; + soc_ddrphy_bankmodel6_active <= 1'd0; + soc_ddrphy_bankmodel6_row <= 14'd0; + soc_ddrphy_bankmodel7_active <= 1'd0; + soc_ddrphy_bankmodel7_row <= 14'd0; + soc_ddrphy_new_bank_write0 <= 1'd0; + soc_ddrphy_new_bank_write_col0 <= 10'd0; + soc_ddrphy_new_bank_write1 <= 1'd0; + soc_ddrphy_new_bank_write_col1 <= 10'd0; + soc_ddrphy_new_bank_write2 <= 1'd0; + soc_ddrphy_new_bank_write_col2 <= 10'd0; + soc_ddrphy_new_bank_write3 <= 1'd0; + soc_ddrphy_new_bank_write_col3 <= 10'd0; + soc_ddrphy_new_bank_write4 <= 1'd0; + soc_ddrphy_new_bank_write_col4 <= 10'd0; + soc_ddrphy_new_bank_write5 <= 1'd0; + soc_ddrphy_new_bank_write_col5 <= 10'd0; + soc_ddrphy_new_bank_write6 <= 1'd0; + soc_ddrphy_new_bank_write_col6 <= 10'd0; + soc_ddrphy_new_bank_write7 <= 1'd0; + soc_ddrphy_new_bank_write_col7 <= 10'd0; + soc_ddrphy_new_banks_read0 <= 1'd0; + soc_ddrphy_new_banks_read_data0 <= 128'd0; + soc_ddrphy_new_banks_read1 <= 1'd0; + soc_ddrphy_new_banks_read_data1 <= 128'd0; + soc_ddrphy_new_banks_read2 <= 1'd0; + soc_ddrphy_new_banks_read_data2 <= 128'd0; + soc_ddrphy_new_banks_read3 <= 1'd0; + soc_ddrphy_new_banks_read_data3 <= 128'd0; + soc_ddrphy_new_banks_read4 <= 1'd0; + soc_ddrphy_new_banks_read_data4 <= 128'd0; + soc_ddrphy_new_banks_read5 <= 1'd0; + soc_ddrphy_new_banks_read_data5 <= 128'd0; + soc_ddrphy_new_banks_read6 <= 1'd0; + soc_ddrphy_new_banks_read_data6 <= 128'd0; + soc_ddrphy_new_banks_read7 <= 1'd0; + soc_ddrphy_new_banks_read_data7 <= 128'd0; + soc_litedramcore_storage <= 4'd1; + soc_litedramcore_re <= 1'd0; + soc_litedramcore_phaseinjector0_command_storage <= 6'd0; + soc_litedramcore_phaseinjector0_command_re <= 1'd0; + soc_litedramcore_phaseinjector0_address_re <= 1'd0; + soc_litedramcore_phaseinjector0_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector0_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector0_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector1_command_storage <= 6'd0; + soc_litedramcore_phaseinjector1_command_re <= 1'd0; + soc_litedramcore_phaseinjector1_address_re <= 1'd0; + soc_litedramcore_phaseinjector1_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector1_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector1_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector2_command_storage <= 6'd0; + soc_litedramcore_phaseinjector2_command_re <= 1'd0; + soc_litedramcore_phaseinjector2_address_re <= 1'd0; + soc_litedramcore_phaseinjector2_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector2_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector2_rddata_re <= 1'd0; + soc_litedramcore_phaseinjector3_command_storage <= 6'd0; + soc_litedramcore_phaseinjector3_command_re <= 1'd0; + soc_litedramcore_phaseinjector3_address_re <= 1'd0; + soc_litedramcore_phaseinjector3_baddress_re <= 1'd0; + soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0; + soc_litedramcore_phaseinjector3_rddata_status <= 32'd0; + soc_litedramcore_phaseinjector3_rddata_re <= 1'd0; + soc_litedramcore_dfi_p0_address <= 14'd0; + soc_litedramcore_dfi_p0_bank <= 3'd0; + soc_litedramcore_dfi_p0_cas_n <= 1'd1; + soc_litedramcore_dfi_p0_cs_n <= 1'd1; + soc_litedramcore_dfi_p0_ras_n <= 1'd1; + soc_litedramcore_dfi_p0_we_n <= 1'd1; + soc_litedramcore_dfi_p0_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p0_rddata_en <= 1'd0; + soc_litedramcore_dfi_p1_address <= 14'd0; + soc_litedramcore_dfi_p1_bank <= 3'd0; + soc_litedramcore_dfi_p1_cas_n <= 1'd1; + soc_litedramcore_dfi_p1_cs_n <= 1'd1; + soc_litedramcore_dfi_p1_ras_n <= 1'd1; + soc_litedramcore_dfi_p1_we_n <= 1'd1; + soc_litedramcore_dfi_p1_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p1_rddata_en <= 1'd0; + soc_litedramcore_dfi_p2_address <= 14'd0; + soc_litedramcore_dfi_p2_bank <= 3'd0; + soc_litedramcore_dfi_p2_cas_n <= 1'd1; + soc_litedramcore_dfi_p2_cs_n <= 1'd1; + soc_litedramcore_dfi_p2_ras_n <= 1'd1; + soc_litedramcore_dfi_p2_we_n <= 1'd1; + soc_litedramcore_dfi_p2_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p2_rddata_en <= 1'd0; + soc_litedramcore_dfi_p3_address <= 14'd0; + soc_litedramcore_dfi_p3_bank <= 3'd0; + soc_litedramcore_dfi_p3_cas_n <= 1'd1; + soc_litedramcore_dfi_p3_cs_n <= 1'd1; + soc_litedramcore_dfi_p3_ras_n <= 1'd1; + soc_litedramcore_dfi_p3_we_n <= 1'd1; + soc_litedramcore_dfi_p3_wrdata_en <= 1'd0; + soc_litedramcore_dfi_p3_rddata_en <= 1'd0; + soc_litedramcore_cmd_payload_a <= 14'd0; + soc_litedramcore_cmd_payload_ba <= 3'd0; + soc_litedramcore_cmd_payload_cas <= 1'd0; + soc_litedramcore_cmd_payload_ras <= 1'd0; + soc_litedramcore_cmd_payload_we <= 1'd0; + soc_litedramcore_timer_count1 <= 10'd781; + soc_litedramcore_postponer_req_o <= 1'd0; + soc_litedramcore_postponer_count <= 1'd0; + soc_litedramcore_sequencer_done1 <= 1'd0; + soc_litedramcore_sequencer_counter <= 6'd0; + soc_litedramcore_sequencer_count <= 1'd0; + soc_litedramcore_zqcs_timer_count1 <= 27'd99999999; + soc_litedramcore_zqcs_executer_done <= 1'd0; + soc_litedramcore_zqcs_executer_counter <= 5'd0; + soc_litedramcore_bankmachine0_level <= 5'd0; + soc_litedramcore_bankmachine0_produce <= 4'd0; + soc_litedramcore_bankmachine0_consume <= 4'd0; + soc_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine0_row <= 14'd0; + soc_litedramcore_bankmachine0_row_opened <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine0_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trccon_count <= 3'd0; + soc_litedramcore_bankmachine0_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine0_trascon_count <= 3'd0; + soc_litedramcore_bankmachine1_level <= 5'd0; + soc_litedramcore_bankmachine1_produce <= 4'd0; + soc_litedramcore_bankmachine1_consume <= 4'd0; + soc_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine1_row <= 14'd0; + soc_litedramcore_bankmachine1_row_opened <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine1_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trccon_count <= 3'd0; + soc_litedramcore_bankmachine1_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine1_trascon_count <= 3'd0; + soc_litedramcore_bankmachine2_level <= 5'd0; + soc_litedramcore_bankmachine2_produce <= 4'd0; + soc_litedramcore_bankmachine2_consume <= 4'd0; + soc_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine2_row <= 14'd0; + soc_litedramcore_bankmachine2_row_opened <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine2_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trccon_count <= 3'd0; + soc_litedramcore_bankmachine2_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine2_trascon_count <= 3'd0; + soc_litedramcore_bankmachine3_level <= 5'd0; + soc_litedramcore_bankmachine3_produce <= 4'd0; + soc_litedramcore_bankmachine3_consume <= 4'd0; + soc_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine3_row <= 14'd0; + soc_litedramcore_bankmachine3_row_opened <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine3_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trccon_count <= 3'd0; + soc_litedramcore_bankmachine3_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine3_trascon_count <= 3'd0; + soc_litedramcore_bankmachine4_level <= 5'd0; + soc_litedramcore_bankmachine4_produce <= 4'd0; + soc_litedramcore_bankmachine4_consume <= 4'd0; + soc_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine4_row <= 14'd0; + soc_litedramcore_bankmachine4_row_opened <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine4_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trccon_count <= 3'd0; + soc_litedramcore_bankmachine4_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine4_trascon_count <= 3'd0; + soc_litedramcore_bankmachine5_level <= 5'd0; + soc_litedramcore_bankmachine5_produce <= 4'd0; + soc_litedramcore_bankmachine5_consume <= 4'd0; + soc_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine5_row <= 14'd0; + soc_litedramcore_bankmachine5_row_opened <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine5_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trccon_count <= 3'd0; + soc_litedramcore_bankmachine5_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine5_trascon_count <= 3'd0; + soc_litedramcore_bankmachine6_level <= 5'd0; + soc_litedramcore_bankmachine6_produce <= 4'd0; + soc_litedramcore_bankmachine6_consume <= 4'd0; + soc_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine6_row <= 14'd0; + soc_litedramcore_bankmachine6_row_opened <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine6_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trccon_count <= 3'd0; + soc_litedramcore_bankmachine6_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine6_trascon_count <= 3'd0; + soc_litedramcore_bankmachine7_level <= 5'd0; + soc_litedramcore_bankmachine7_produce <= 4'd0; + soc_litedramcore_bankmachine7_consume <= 4'd0; + soc_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; + soc_litedramcore_bankmachine7_row <= 14'd0; + soc_litedramcore_bankmachine7_row_opened <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0; + soc_litedramcore_bankmachine7_trccon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trccon_count <= 3'd0; + soc_litedramcore_bankmachine7_trascon_ready <= 1'd0; + soc_litedramcore_bankmachine7_trascon_count <= 3'd0; + soc_litedramcore_choose_cmd_grant <= 3'd0; + soc_litedramcore_choose_req_grant <= 3'd0; + soc_litedramcore_trrdcon_ready <= 1'd0; + soc_litedramcore_trrdcon_count <= 1'd0; + soc_litedramcore_tfawcon_ready <= 1'd1; + soc_litedramcore_tfawcon_window <= 5'd0; + soc_litedramcore_tccdcon_ready <= 1'd0; + soc_litedramcore_tccdcon_count <= 1'd0; + soc_litedramcore_twtrcon_ready <= 1'd0; + soc_litedramcore_twtrcon_count <= 3'd0; + soc_litedramcore_time0 <= 5'd0; + soc_litedramcore_time1 <= 4'd0; + soc_init_done_storage <= 1'd0; + soc_init_done_re <= 1'd0; + soc_init_error_storage <= 1'd0; + soc_init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -14197,14 +14389,14 @@ assign soc_ddrphy_bankmodel7_read_port_dat_r = mem_7[soc_ddrphy_bankmodel7_read_ reg [23:0] storage[0:15]; reg [23:0] storage_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine0_wrport_we) + storage[soc_litedramcore_bankmachine0_wrport_adr] <= soc_litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[soc_litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign soc_litedramcore_bankmachine0_rdport_dat_r = storage[soc_litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -14215,14 +14407,14 @@ assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_1[0:15]; reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine1_wrport_we) + storage_1[soc_litedramcore_bankmachine1_wrport_adr] <= soc_litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign soc_litedramcore_bankmachine1_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -14233,14 +14425,14 @@ assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_2[0:15]; reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine2_wrport_we) + storage_2[soc_litedramcore_bankmachine2_wrport_adr] <= soc_litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign soc_litedramcore_bankmachine2_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -14251,14 +14443,14 @@ assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_3[0:15]; reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine3_wrport_we) + storage_3[soc_litedramcore_bankmachine3_wrport_adr] <= soc_litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign soc_litedramcore_bankmachine3_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -14269,14 +14461,14 @@ assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_4[0:15]; reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine4_wrport_we) + storage_4[soc_litedramcore_bankmachine4_wrport_adr] <= soc_litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign soc_litedramcore_bankmachine4_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -14287,14 +14479,14 @@ assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_5[0:15]; reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine5_wrport_we) + storage_5[soc_litedramcore_bankmachine5_wrport_adr] <= soc_litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign soc_litedramcore_bankmachine5_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -14305,14 +14497,14 @@ assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_6[0:15]; reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine6_wrport_we) + storage_6[soc_litedramcore_bankmachine6_wrport_adr] <= soc_litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign soc_litedramcore_bankmachine6_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -14323,18 +14515,18 @@ assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage reg [23:0] storage_7[0:15]; reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin - if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (soc_litedramcore_bankmachine7_wrport_we) + storage_7[soc_litedramcore_bankmachine7_wrport_adr] <= soc_litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign soc_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_rdport_adr]; endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:07:04. +// Auto-Generated by LiteX on 2022-10-28 19:01:27. //------------------------------------------------------------------------------ diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init index 9006b18..61e54f3 100644 --- a/litedram/generated/wukong-v2/litedram_core.init +++ b/litedram/generated/wukong-v2/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421ff00782107c6 3d80000060215f00 798c07c6618c0000 -618c10d8658cff00 +618c10e0658cff00 4e8004217d8903a6 4e8004207c6903a6 0000000000000000 @@ -519,214 +519,219 @@ a64b5a7d14004a39 0000000000000000 3c4c000100000000 7c0802a63842adc4 -f8010010fbe1fff8 -f88100d8f821ff51 -38800080f8a100e0 -f8c100e87c651b78 -38c100d838610020 -f90100f8f8e100f0 +fbe1fff8fbc1fff0 +f821ff51f8010010 +f88100d83bc10020 +f8c100e8f8a100e0 +38c100d87c651b78 +f8e100f038800080 +7fc3f378f90100f8 f9410108f9210100 -6000000048002135 -386100207c7f1b78 -6000000048001b4d +6000000048002139 +7fc3f3787c7f1b78 +6000000048001b59 7fe3fb78382100b0 -000000004800283c -0000018001000000 +000000004800285c +0000028001000000 000000004e800020 0000000000000000 4c00012c7c0007ac 000000004e800020 0000000000000000 -3842ad283c4c0001 +3842ad203c4c0001 7d6000267c0802a6 -9161000848002775 -48001b49f821fed1 +9161000848002799 +48001b55f821fed1 3c62ffff60000000 -4bffff4138637af0 +4bffff3938637b18 788400203c80c000 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637b10 -3c62ffff4bffff1d -38637b307bff0020 -7c0004ac4bffff0d +63ff000838637b38 +3c62ffff4bffff15 +38637b587bff0020 +7c0004ac4bffff05 73e900017fe0feea 3c62ffff41820010 -4bfffef138637b48 +4bfffee938637b70 4d80000073e90002 3c62ffff41820010 -4bfffed938637b50 +4bfffed138637b78 4e00000073e90004 3c62ffff41820010 -4bfffec138637b58 +4bfffeb938637b80 4d00000073e90008 3c62ffff41820010 -4bfffea938637b60 +4bfffea138637b88 4182001073e90010 -38637b703c62ffff -73ff01004bfffe95 +38637b983c62ffff +73ff01004bfffe8d 3c62ffff41820010 -4bfffe8138637b80 -3b7b7b883f62ffff -4bfffe717f63db78 +4bfffe7938637ba8 +3b7b7bb03f62ffff +4bfffe697f63db78 3c80c00041920028 7884002060840010 7c8026ea7c0004ac 7884b5823c62ffff -4bfffe4938637b90 +4bfffe4138637bb8 3c80c000418e004c 7884002060840018 7c8026ea7c0004ac 788460223c62ffff -4bfffe2138637ba8 +4bfffe1938637bd0 608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637bc07884b282 -3d20c0004bfffdfd +38637be87884b282 +3d20c0004bfffdf5 7929002061290020 7d204eea7c0004ac 792906003c80000f -3c62ffff60844240 -38637bd87c892392 -418a02604bfffdcd -63de00383fc0c000 -7c0004ac7bde0020 -3d40c0007fc0f6ea +608442403c62ffff +7c89239238637c00 +418a02bc4bfffdc5 +639c00383f80c000 +7c0004ac7b9c0020 +3d40c0007f80e6ea 614a600439200002 7c0004ac794a0020 3fe0c0007d2057aa 63ff60003920ff9f 7c0004ac7bff0020 7c0004ac7d20ffaa +7c0004ac7fc0feaa 7c0004ac7fa0feaa -7c0004ac7f80feaa -4bfffd257fe0feaa +4bfffd1d7fe0feaa 57e6063e3c62ffff -57a4063e5785063e -57f8063e38637bf8 -7fa9e3784bfffd4d -7d29fb78579a063e -5529063e57b9063e +57c4063e57a5063e +57ba063e57f8063e +38637c2057d9063e +7fc9eb784bfffd3d +5529063e7d29fb78 418201682c090000 -7fbdf8387fbde038 -2c1d00ff57bd063e +7fdef8387fdee838 +2c1e00ff57de063e 2c19000141820154 -2c1a000240820184 -739c00bf41820010 -408201302c1c0020 +2c1a0002408201e0 +73bd00bf41820010 +408201302c1d0020 57ff063e3bffffe8 41810120281f0001 392000353fe0c000 7bff002063ff6000 7d20ffaa7c0004ac -3b4000023fa0c000 -7bbd002063bd6004 -7f40efaa7c0004ac +3b4000023fc0c000 +7bde002063de6004 +7f40f7aa7c0004ac 7d20ffaa7c0004ac -7f80feaa7c0004ac -3c62ffff4bfffc69 -38637c185784063e -738900024bfffc9d +7fa0feaa7c0004ac +3c62ffff4bfffc61 +38637c4057a4063e +73a900024bfffc95 3c62ffff40820090 -4bfffc8938637c38 -7f40efaa7c0004ac +4bfffc8138637c60 +7f40f7aa7c0004ac 7c0004ac39200006 -4bfffc2d7d20ffaa -7f40efaa7c0004ac +4bfffc257d20ffaa +7f40f7aa7c0004ac 7c0004ac39200001 392000007d20ffaa 7d20ffaa7c0004ac -7c0004ac639c0002 -7c0004ac7f80ffaa -4bfffbf57d20efaa -3b4000053b000002 +7c0004ac63bd0002 +7c0004ac7fa0ffaa +3b0000027d20f7aa +3b4000054bfffbe9 7c0004ac7ff9fb78 -7c0004ac7f00efaa +7c0004ac7f00f7aa 7c0004ac7f40cfaa -4bfffbcd7f80feaa -4082ffe0739c0001 -38637c503c62ffff -3d40c0004bfffbfd +4bfffbc57fa0feaa +4082ffe073bd0001 +38637c783c62ffff +3d40c0004bfffbf5 794a0020614a6008 7d20562a7c0004ac 652920005529021e 7c0004ac61291f6b 7f63db787d20572a -3c62ffff4bfffbcd -38637c607bc40020 -4bfffbb97fdaf378 -4bfffbb17f63db78 -419200d0408e0094 -38637c803c62ffff -386000004bfffb9d -2c190020480001a0 -2c1a00ba4082ffbc -2c1800184082ffb4 -3c62ffff4082ffac -4bfffb7138637c48 -7f63db784bffff68 -408e00684bfffb65 -3c62ffff4092ffb8 -4bfffb5138637d90 -38a000003c80ff00 -60a5a00060846000 -3c60400078840020 -6000000048001865 -38637db03c62ffff -4bfffb9d4bfffb25 -3c82ffff4bffff84 -38847c983c62ffff -4bfffb0938637ca8 -6000000048000c3d -3c82ffff4bffff54 -38847c983c62ffff -4bfffae938637ca8 -6000000048000c1d -3c62ffff4bffff80 -4bfffad138637cc8 -38a000403c9ef000 -3861007078840020 -60000000480017ed -3d400002e9210070 +3c62ffff4bfffbc5 +7f9ae3787b840020 +38637c883be00001 +7f63db784bfffbad +418e00384bfffba5 +792900203d20c800 +7d204e2a7c0004ac +408200202c090000 +3c62ffff3c82ffff +38637cb838847ca8 +48000ccd4bfffb75 +3d40c00060000000 +794a0020614a0028 +7d2056ea7c0004ac +792920007929e042 +7d2057ea7c0004ac +3c62ffff4192004c +4bfffb3938637cd8 +4800016438600000 +4082ff602c190020 +4082ff582c1a00ba +4082ff502c180018 +38637c703c62ffff +4bffff0c4bfffb0d +3b4000003be00000 +73ff00014bffff54 +3c62ffff418200a4 +4bfffae938637cf0 +38a000403c9af000 +7884002038610070 +6000000048001819 +e92100703d400002 614a464c3c62ffff -794a83e438637ce0 +794a83e438637d08 614a457f79290600 408200247c295000 2c09000189210075 a121008240820010 -418200442c090015 -38637d003c62ffff -892100774bfffa6d -8901007489410076 -3c62ffff88e10073 +418200802c090015 +38637d283c62ffff +892100774bfffa85 +894100763c62ffff +88e1007389010074 88a1007188c10072 -38637d6088810070 +38637d8888810070 89210075f9210060 -4bfffee04bfffa3d -3f22ffffe9210090 -3b397d183ba00000 -a12100a87fde4a14 +3c62ffff4bfffa55 +4bfffa4938637db8 +38a000003c80ff00 +608460003c604000 +7884002060a5a000 +6000000048001771 +38637dd83c62ffff +4bfffa9d4bfffa1d +ebe100904bfffee0 +3ba000003f02ffff +3b187d403b2100b0 +a12100a87ffafa14 418000347c1d4840 3c62ffff80810088 -4bfffa0938637d40 -e86100884bfffa81 -4182fea02c23ffff +4bfff9e138637d68 +e86100884bfffa61 +4182ff802c23ffff 8161000838210130 -480022507d638120 -38a000383c9ef000 -386100b078840020 -6000000048001705 +480022547d638120 +38a000383c9ff000 +788400207f23cb78 +60000000480016f1 2c090001812100b0 eb6100d040820048 -ebe100b8eb8100c0 -7f23cb787ba40020 +ebc100b8eb8100c0 +7f03c3787ba40020 7b6500207f86e378 -4bfff9a13ffff000 -7b6500207c9fd214 -7f83e37878840020 -60000000480016bd -7fde4a14a12100a6 +4bfff9793fdef000 +7b6500207c9af214 +788400207f83e378 +60000000480016a9 +7fff4a14a12100a6 4bffff583bbd0001 0300000000000000 3d20c80000000880 @@ -737,7 +742,7 @@ ebe100b8eb8100c0 7d20572a7c0004ac 000000004e800020 0000000000000000 -3842a6e83c4c0001 +3842a6c03c4c0001 4182006828030002 4182003028030003 4082007c28030001 @@ -815,26 +820,26 @@ ebe100b8eb8100c0 614a100c39200000 000000004bffffd4 0000000000000000 -786900202c030000 -4080000839290001 -2c29000139200001 +2c03000078690020 +3929000139400001 +2c2900017d2a481e 4d8200203929ffff 4bfffff060000000 0000000000000000 3c4c000100000000 -7c0802a63842a444 -60e700033ce08020 -78e7002039200000 -f821ffa148001e99 -3941001f7c7d1b78 -7d0a4a143bc10020 -7d4903a639400004 +7c0802a63842a41c +f821ffa148001ead +392000003cc08020 +7c7d1b7860c60003 +78c6002038e1001f +3bc1002039400004 +7d4903a67d074a14 788407e0788af862 -7c8438387c8400d0 +7c8430387c8400d0 7d4453787c8a5278 4200ffe49d480001 2829001039290004 -3d40c8004082ffc4 +3d40c8004082ffc8 614a100c39200000 7c0004ac794a0020 3d40c8007d20572a @@ -843,11 +848,11 @@ f821ffa148001e99 4bfffc8938600009 4bffff2d3860000f 3cc0c8003d20c800 -60c6107461291014 -792900207fcaf378 +612910147fcaf378 +7929002060c61074 38a0000478c60020 -7ca903a638eaffff -8ca7000139000000 +3900000038eaffff +8ca700017ca903a6 7ca82b787905400c 7c0004ac4200fff4 392900187ca04f2a @@ -862,7 +867,7 @@ f821ffa148001e99 57e3063e38800017 4bfffc2d3fe0c800 3860000f63ff082c -7bff00204bfffe89 +4bfffe857bff0020 7c60fe2a7c0004ac 4bfffe055463063e 7c60fe2a7c0004ac @@ -879,17 +884,17 @@ f821ffa148001e99 3be100303860000b 3860000f4bfffb65 3ce0c8004bfffe09 -60e710183d60c800 -3c6033333c005555 -616b10783d800f0f -78e7002038800000 -211d000138a00000 -6063333360005555 -796b0020618c0f0f +3c0055553d60c800 +3d800f0f3c603333 +38a0000038800000 +60e71018211d0001 +60005555616b1078 +618c0f0f60633333 +796b002078e70020 7d203e2a7c0004ac 792900203ba00004 -38c100347fa903a6 -9d26ffff39400004 +3940000438c10034 +9d26ffff7fa903a6 7929c202394affff 392000044200fff4 7d2452147d2903a6 @@ -906,18 +911,18 @@ f821ffa148001e99 552906be7d293214 394a00017ca54a14 38e700184200ff9c -7c2758003bde0004 -4082ff5438840004 +388400043bde0004 +4082ff547c275800 78a3002038210060 -0000000048001c48 +0000000048001c4c 0000038001000000 -3842a1783c4c0001 -48001bcd7c0802a6 -7c7f1b78f821ff61 -4bfffb213b800000 +3842a1503c4c0001 +48001bd17c0802a6 +3b800000f821ff61 +4bfffb217c7f1b78 7fe3fb783880002a -388000544bfffd15 -7c7e1b783bbc0001 +4bfffd113bbc0001 +7c7e1b7838800054 4bfffd017fe3fb78 2c0300007c63f214 2c1d00204182001c @@ -925,9 +930,9 @@ f821ffa148001e99 4bfffb2d7fbceb78 7f9de3784bffffc0 3b5c00047fe3fb78 -7fe3fb784bfffb19 -4bfffb0d7f5bd378 -3bc0ffff7fe3fb78 +4bfffb153bc0ffff +7f5bd3787fe3fb78 +7fe3fb784bfffb09 7fe3fb784bfffb01 3880002a4bfffaf9 4bfffca17fe3fb78 @@ -941,590 +946,587 @@ f821ffa148001e99 4bffffb84bfffab1 3ba0ffff3b800020 2c1effff4bffff80 -2c1a001f4082001c -418100083bc00000 -3b9c000523da001f -2c1dffff7fdee214 -3c62ffff4082001c -4bfff2a138637dc8 -382100a060000000 -7cbdf05048001b00 -7ca50e707c9df214 -789cfee27ca50194 -7ca507b43c62ffff -38637dd87f84e378 -4bfff2693bc00008 -7fe3fb7860000000 -4bfff9d93ba00000 -4bfffb9538600064 -4082003c7c1ce800 -7fe3fb783880002a -388000544bfffbbd -7fe3fb787c7d1b78 -7c63ea144bfffbad -4182ff882c030000 -2c1e00003bdeffff -4bffff784082ffb4 -3bbd00017fe3fb78 -386000644bfff9d1 -4bffffac4bfffb41 -0100000000000000 -3c4c000100000780 -3d20c80038429fa4 -7929002061291000 -7d404e2a7c0004ac -4d820020280a000e -3940000e7c0802a6 -f821ffa1f8010010 -7d404f2a7c0004ac +23da001f40820018 +3b9c00052c1a001f +7fdee2147fc0f05e +4082001c2c1dffff 38637df03c62ffff -600000004bfff1a5 -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -3d20c80038429f3c -7929002061291000 -7d404e2a7c0004ac -4d820020280a0001 -394000017c0802a6 +600000004bfff27d +48001b08382100a0 +7c9df2147cbdf050 +3bc000083c62ffff +7ca501947ca50e70 +38637e00789cfee2 +7ca507b47f84e378 +600000004bfff245 +3ba000007fe3fb78 +386000644bfff9dd +7c1ce8004bfffb99 +3880002a4082003c +4bfffbc17fe3fb78 +7c7d1b7838800054 +4bfffbb17fe3fb78 +2c0300007c63ea14 +3bdeffff4182ff88 +4082ffb42c1e0000 +7fe3fb784bffff78 +4bfff9d53bbd0001 +4bfffb4538600064 +000000004bffffac +0000078001000000 +38429f803c4c0001 +612910003d20c800 +7c0004ac79290020 +280a000e7d404e2a +7c0802a64d820020 f821ffa1f8010010 -7d404f2a7c0004ac -38637e183c62ffff -600000004bfff13d -e801001038210060 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429ed4 -39297e403d22ffff -f821ff01480018f5 -3f00c8003f80c800 -3e62ffff3e82ffff -639c08043f22ffff -3e42ffff63180820 -3b4000013ba00000 -3ae00000f9210060 -3a737e583a947e50 -7b9c00203b397b88 -3a527e607b180020 -7fb0eb787ba307e0 -7f56e8304bfff8c5 +7c0004ac3940000e +3c62ffff7d404f2a +4bfff18138637e18 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429f183c4c0001 +612910003d20c800 +7c0004ac79290020 +280a00017d404e2a +7c0802a64d820020 +f821ffa1f8010010 +7c0004ac39400001 +3c62ffff7d404f2a +4bfff11938637e40 +3821006060000000 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429eb03c4c0001 +480019057c0802a6 +3f80c800f821ff01 +3ba000003f00c800 +3ae000003b400001 +3e82ffff3d22ffff +3f22ffff3e62ffff +63180820639c0804 +39297e683e42ffff +3a737e803a947e78 +7b9c00203b397bb0 +3a527e887b180020 +7ba307e0f9210060 +7f56e8307fb0eb78 3a2000003be00000 7fbe07b439e00000 -7de507b4e8610060 -39c000207fc4f378 -4bfff0813b600000 -7fc3f37860000000 -3880002a4bfff7f5 -4bfff9e97fc3f378 -7c751b7838800054 -4bfff9d97fc3f378 -7c6400347c63aa14 -7e83a37821230080 -548a60265484d97e -7d2952147c8407b4 -4bfff0317f7b4a14 +e86100604bfff8b5 +7fc4f3787de507b4 +3b60000039c00020 +600000004bfff05d +4bfff7f97fc3f378 +7fc3f3783880002a +388000544bfff9ed +7fc3f3787c751b78 +7c63aa144bfff9dd +212300807c640034 +5484d97e7e83a378 +7c8407b4548a6026 +7f7b4a147d295214 +600000004bfff00d +4bfff7f57fc3f378 +4082ffac35ceffff +4bffeff17e639b78 7fc3f37860000000 -35ceffff4bfff7f1 -7e639b784082ffac -600000004bfff015 -4bfffc557fc3f378 -4bfff0017f23cb78 -7c11d84060000000 -7dff7b784080000c -2c0f00077f71db78 -7c0004ac4182002c -7c0004ac7ec0e72a -7c0004ac7f40c72a -39ef00017ee0e72a -3ba000014bffff30 -7fe507b44bffff08 -7e4393787fc4f378 -4bffefa97bff0020 -7a0307e060000000 -393f00014bfff7b5 -420000287d2903a6 -4bfffbd57fc3f378 -4bffef817f23cb78 -2c1d000060000000 -382101004182ffb4 -7c0004ac480017ac -7c0004ac7ec0e72a -7c0004ac7f40c72a -4bffffc07ee0e72a -0100000000000000 -3c4c000100001280 -7c0802a638429cfc -f821ffa1f8010010 -386000004bfffd4d -386000004bfff6a5 -386000014bfff735 -386000014bfff695 -3c62ffff4bfff725 -4bffef0138637e78 -4bfffde960000000 -382100604bfffd7d -e801001038600001 -4e8000207c0803a6 -0100000000000000 -3c4c000100000080 -7c0802a638429c8c -6129082c3d20c800 -480016cd79290020 -3b000002f821ff51 -7f004f2a7c0004ac -3b2000033d20c800 -7929002061290830 -7f204f2a7c0004ac -3c62ffff3fc0c800 -38637e883c804000 -4bffee7963de0800 -3b80000160000000 -7bde00204bfffc8d -7f80f72a7c0004ac -3be00000386003e8 -7c0004ac4bfff799 -386003e87fe0f72a -4bfff7853f60c800 -7c0004ac7b7b0020 -3f40c8007fe0df2a -7b5a0020635a0004 -7fe0d72a7c0004ac -63bd100c3fa0c800 -7c0004ac7bbd0020 -3fc0c8007fe0ef2a -7bde002063de1010 +7f23cb784bfffc59 +600000004bffefdd +4080000c7c11d840 +7f71db787dff7b78 +4182002c2c0f0007 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +4bffff3039ef0001 +4bffff083ba00001 +7fc4f3787fe507b4 +7bff00207e439378 +600000004bffef85 +4bfff7b97a0307e0 +7d2903a6393f0001 +7fc3f37842000028 +7f23cb784bfffbd9 +600000004bffef5d +4182ffb42c1d0000 +480017b438210100 +7ec0e72a7c0004ac +7f40c72a7c0004ac +7ee0e72a7c0004ac +000000004bffffc0 +0000128001000000 +38429cd83c4c0001 +f80100107c0802a6 +4bfffd4df821ffa1 +4bfff6a938600000 +4bfff73938600000 +4bfff69938600001 +4bfff72938600001 +38637ea03c62ffff +600000004bffeedd +4bfffd7d4bfffde9 +3860000138210060 +7c0803a6e8010010 +000000004e800020 +0000008001000000 +38429c683c4c0001 +480016e17c0802a6 +3d20c800f821ff51 +6129082c3b000002 +7c0004ac79290020 +3d20c8007f004f2a +612908303b200003 +7c0004ac79290020 +3fc0c8007f204f2a +3c8040003c62ffff +38637eb03b800001 +4bffee5163de0800 +7bde002060000000 +7c0004ac4bfffc89 +386003e87f80f72a +4bfff79d3be00000 7fe0f72a7c0004ac -3920000c3ee0c800 -7af7002062f71000 -7d20bf2a7c0004ac -6063c35038600000 -7c0004ac4bfff719 -7c0004ac7fe0ef2a -3920000e7fe0f72a -7d20bf2a7c0004ac -4bfff6f538602710 -7c0004ac39200200 -7c0004ac7d20ef2a -3860000f7f00f72a -7c0004ac4bfff42d -7c0004ac7fe0ef2a -3860000f7f20f72a -392000064bfff415 +3f60c800386003e8 +7b7b00204bfff789 +7fe0df2a7c0004ac +635a00043f40c800 +7c0004ac7b5a0020 +3fa0c8007fe0d72a +7bbd002063bd100c +7fe0ef2a7c0004ac +63de10103fc0c800 +7c0004ac7bde0020 +3ee0c8007fe0f72a +62f710003920000c +7c0004ac7af70020 +386000007d20bf2a +4bfff71d6063c350 +7fe0ef2a7c0004ac +7fe0f72a7c0004ac +7c0004ac3920000e +386027107d20bf2a +392002004bfff6f9 7d20ef2a7c0004ac -7f80f72a7c0004ac -4bfff3f93860000f -7c0004ac39200930 +7f00f72a7c0004ac +4bfff4313860000f +7fe0ef2a7c0004ac +7f20f72a7c0004ac +4bfff4193860000f +7c0004ac39200006 7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff3dd -392004004bfff681 +3860000f7f80f72a +392009304bfff3fd 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff3b938600003 -4bfff65d386000c8 -4bfffb994bfffddd -3c6040003c800020 -60000000480006e9 -408200242c030000 -7c0004ac7c691b78 -7c0004ac7f80d72a -382100b07f80df2a -4800153c7d2307b4 -38a0000038c00000 -3c6040003c800020 -6000000048000471 +4bfff3e13860000f +4bfff685386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff3bd +4bfffddd4bfff661 +3c8000204bfffb99 +480006e13c604000 +2c03000060000000 +7c691b7840820024 +7f80d72a7c0004ac 7f80df2a7c0004ac -4bffffd039200001 -0100000000000000 -3c4c000100000980 -7c0802a638429a5c -f8010010282303ff -41810028f821ffa1 -3c62ffff7c641b78 -4bffec7938637ea8 -3821006060000000 -7c0803a6e8010010 -3d2000104e800020 -408000287c234840 -39200066786505a0 -7864b2827ca54b92 -38637eb03c62ffff -600000004bffec3d -3d2040004bffffc4 -7c23484078646502 -7863b28240800024 -7d29185078895564 -3c62ffff38a00066 -38637ec07ca92b92 -786317824bffffc8 -7865556439200066 -7c641b787ca52050 +7d2307b4382100b0 +38c0000048001544 +3c80002038a00000 +480004713c604000 +7c0004ac60000000 +392000017f80df2a +000000004bffffd0 +0000098001000000 +38429a383c4c0001 +f80100107c0802a6 +282303fff821ffa1 +7c641b7841810028 +38637ed03c62ffff +600000004bffec55 +e801001038210060 +4e8000207c0803a6 +7c2348403d200010 +786505a040800028 +7864b28239200066 7ca54b923c62ffff -4bffffa438637ed0 -0100000000000000 -3c4c000100000080 -7c0802a63842998c -7cc42a14fbe1fff8 -7c8523787cbf2b78 +4bffec1938637ed8 +4bffffc460000000 +786465023d204000 +408000247c234840 +788955647863b282 +7d29185038a00066 +7ca92b923c62ffff +4bffffc838637ee8 +3920006678631782 +7ca5205078655564 3c62ffff7c641b78 -38637ee078c60020 +38637ef87ca54b92 +000000004bffffa4 +0000008001000000 +384299683c4c0001 +fbe1fff87c0802a6 f821ff91f8010010 -600000004bffeb9d -4bfffef97fe3fb78 -38637ef03c62ffff -600000004bffeb85 -4800141038210070 -0100000000000000 -2c24000000000180 -7869f84241820024 -7c6300d0786307e0 -5463028054630794 -786300207c634a78 -386300014e800020 -000000004bfffff4 -0000000000000000 -384298e83c4c0001 -788407647c0802a6 -7c691b783d40aaaa -48001339614aaaaa +7cbf2b787cc42a14 +7c641b787c852378 +78c600203c62ffff +4bffeb7938637f08 +7fe3fb7860000000 +3c62ffff4bfffef9 +4bffeb6138637f18 +3821007060000000 +0000000048001418 +0000018001000000 +418200242c240000 +786307e07869f842 +546307947c6300d0 +7c634a7854630280 +4e80002078630020 +4bfffff438630001 +0000000000000000 +3c4c000100000000 +7c0802a6384298c4 +f821ffc148001351 +788407643d40aaaa +7c7d1b787c7f1b78 +614aaaaa7c691b78 7884f0827f832214 -39040001f821ffc1 -7d0903a67c7f1b78 -420000807c7d1b78 -600000004bffeb59 -3d00aaaa7d3fe050 -7feafb787929f082 -3bc0000039290001 -6108aaaa7d2903a6 -7d3fe05042000060 -7929f0823d005555 -392900017feafb78 -7d2903a661085555 -7fffe05042000058 -600000004bffeb09 -3d2055557bfff082 -61295555395f0001 -420000407d4903a6 -7fc307b438210040 -91490000480012ec -4bffff7839290004 -7c094000812a0000 +7d0903a639040001 +4bffeb3d42000080 +7d3fe05060000000 +7feafb783d00aaaa +7929f0823bc00000 +392900016108aaaa +420000607d2903a6 +3d0055557d3fe050 +7929f0827feafb78 +3929000161085555 +420000587d2903a6 +4bffeaed7fffe050 +3d20555560000000 +612955557bfff082 +7d4903a6395f0001 +3821004042000040 +480012f47fc307b4 +3929000491490000 +812a00004bffff78 +418200087c094000 +394a00043bde0001 +910a00004bffff8c +4bffffa0394a0004 +7c0a4800815d0000 3bde000141820008 -4bffff8c394a0004 -394a0004910a0000 -815d00004bffffa0 -418200087c0a4800 -3bbd00043bde0001 -000000004bffffac -0000048001000000 -384297d83c4c0001 -7c0802a67d600026 -2e26000091610008 -f821ff4148001211 -7cba2b787c7f1b78 -789cf0827cde3378 -81260004419200c0 -2c09000082e60000 -3f02ffff40820044 -3b6000013ba00000 -3b187ef87bf90020 -4082009c7c3ce840 -7b8510283c62ffff -7be4002038637ef8 -3c62ffff4bfffde5 -4bffe9a138637b88 -4bffea0560000000 -2d97000060000000 +4bffffac3bbd0004 +0100000000000000 +3c4c000100000480 +7c0802a6384297b4 +480012217d600026 +f821ff4191610008 +7c7f1b782e260000 +7cde33787cba2b78 +419200c0789cf082 +82e6000081260004 +408200442c090000 +3ba000003f02ffff +7bf900203b600001 +7c3ce8403b187f20 +3c62ffff4082009c +7be400207b851028 +4bfffde538637f20 +38637bb03c62ffff +600000004bffe97d +600000004bffe9e9 3ba000007ffbfb78 3b2000003ac00001 -7c3de0407bf50020 -408200847fb8eb78 -418200282c170000 -7b0510283c62ffff -7be4002038637f08 -3c62ffff4bfffd8d -4bffe94938637b88 -382100c060000000 -816100087f2307b4 -4800118c7d618120 -4bffff503ae00001 -7f44d3787b630020 -7ba917644bfffdb5 -73a97fff7c7f492e -408200147c7b1b78 -7f24cb787ba51028 -4bfffd317f03c378 -4bffff2c3bbd0001 -7ac300207f44d378 -809b00004bfffd7d -7c761b787c651b78 -4182003c7c032040 -419200343b390001 -2c2c0000e99e0008 -7d8903a641820028 -78840020e8de0010 -7b630020f8410018 -e84100184e800421 -4082ff582c030000 -4082001c73187fff -3c62ffff418e0018 -7ea4ab787ba51028 -4bfffcb138637f08 -3b7b00043bbd0001 -000000004bfffef4 -00000b8003000000 -384296183c4c0001 -7c0802a67d708026 -4800106991610008 -7cdb3378f821ff71 -2e3b00003ba4ffe0 +7bf500202d970000 +7fb8eb787c3de040 +2c17000040820084 +3c62ffff41820028 +7be400207b051028 +4bfffd8d38637f30 +38637bb03c62ffff +600000004bffe925 +7f2307b4382100c0 +7d61812081610008 +3ae0000148001194 +7b6300204bffff50 +4bfffdb57f44d378 +7c7f492e7ba91764 +7c7b1b7873a97fff +7ba5102840820014 +7f03c3787f24cb78 +3bbd00014bfffd31 +7f44d3784bffff2c +4bfffd7d7ac30020 +7c651b78809b0000 +7c0320407c761b78 +3b3900014182003c +e99e000841920034 +418200282c2c0000 +7d8903a6e8de0010 +7b63002078840020 +4e800421f8410018 +2c030000e8410018 +73187fff4082ff58 +418e00184082001c +7ba510283c62ffff +38637f307ea4ab78 +3bbd00014bfffcb1 +4bfffef43b7b0004 +0300000000000000 +3c4c000100000b80 +7c0802a6384295f4 +916100087d708026 +f821ff7148001071 +7cdb33783ba4ffe0 7c9e23787c7f1b78 -7c641b787fa3ea14 -38637f183c62ffff -4bffe8197cbc2b78 -3c62ffff60000000 -4092000c38637f30 -38637f403c62ffff -600000004bffe7fd -4bfffb597fc3f378 -38637f503c62ffff -600000004bffe7e5 -408200a82c3c0000 -38df00207cf602a6 -7c26284038bd0020 -7929d9427d3fe850 -3900ffff7feafb78 -4081000839290001 -2c29000139200001 -3929fffff90a0000 -f90a0010f90a0008 -394a0020f90a0018 -7d3602a64082ffe4 -78ea00203f8005f5 -79290020639ce100 -7d2950507f9ee1d2 +7cbc2b787c641b78 +3c62ffff7fa3ea14 +38637f402e3b0000 +600000004bffe7f5 38637f583c62ffff -4bffe7617f9c4b92 -7f83e37860000000 -3c62ffff4bfffabd -4bffe74938637f68 +3c62ffff4092000c +4bffe7d938637f68 +7fc3f37860000000 +3c62ffff4bfffb59 +4bffe7c138637f78 +2c3c000060000000 +7cf602a6408200a8 +38df00207d3fe850 +7feafb7838bd0020 +7929d9423900ffff +38c000017c262840 +7d26485e39290001 +f90a00002c290001 +f90a00083929ffff +f90afff0394a0020 +4082ffe4f90afff8 +3f8005f57d3602a6 +7929002078ea0020 +639ce1003c62ffff +38637f807d295050 +7f9c4b927f9ee1d2 +600000004bffe73d +4bfffabd7f83e378 +38637f903c62ffff +600000004bffe725 +38637bb03c62ffff +600000004bffe715 +600000004bffe781 +409200487f9602a6 +395f00207d3fe850 +7929d9423bbd0020 +394000017c2ae840 +7d2a485e39290001 +e95f00002c290001 +e95f00083929ffff +e95f0018e95f0010 +4082ffe43bff0020 +7bdbe8c24800001c +3ba0000039400000 +7c1dd0007f7adb78 +7d3602a64082006c +7b9c00203d4005f5 +3c62ffff79290020 +7d29e050614ae100 +7fde51d238637f98 +4bffe6797fde4b92 +7fc3f37860000000 +3c62ffff4bfff9f9 +4bffe66138637f90 3c62ffff60000000 -4bffe73938637b88 -4bffe79d60000000 -7f9602a660000000 -7d3fe85040920048 -3bbd0020395f0020 -7c2ae8407929d942 -4081000839290001 -2c29000139200001 -3929ffffe95f0000 -e95f0010e95f0008 -3bff0020e95f0018 -4800001c4082ffe4 -394000007bdbe8c2 -3ba000007f7adb78 -4082006c7c1dd000 -3d4005f57d3602a6 -614ae1007b9c0020 -7fde51d279290020 -3c62ffff7d29e050 -7fde4b9238637f70 -600000004bffe69d -4bfff9f97fc3f378 -38637f683c62ffff -600000004bffe685 -38637b883c62ffff -600000004bffe675 -8161000838210090 -48000ed07d708120 -794300207fa407b4 -3bbd00014bfffaed -7c6a1b787d23db96 -7d2918507d29d9d6 -7d3f482a79291f48 -000000004bffff68 -0000068003000000 -384293e03c4c0001 -282402007c0802a6 -f821ff8148000e3d +4bffe65138637bb0 +3821009060000000 +7d70812081610008 +7fa407b448000ed8 +3bbd000179430020 +7d23da164bfffae9 +79291f487c6a1b78 +4bffff707d3f482a +0300000000000000 +3c4c000100000680 +7c0802a6384293c4 +f821ff8148000e51 +282402003b800200 7c9f23787c7e1b78 -418100083b800200 -3c62ffff7c9c2378 -38637f807fc4f378 -600000004bffe5ed -4bfff9497fe3fb78 -38637f503c62ffff +7c641b787f9c205e +38637fa83c62ffff 600000004bffe5d5 +4bfff9557fe3fb78 +38637f783c62ffff +600000004bffe5bd 7fc3f3787f84e378 -38c000004bfffaa1 +38c000004bfffaad 7fe4fb7838a00001 7fc3f3787c7d1b78 -7d23ea144bfffb99 -2c0900007c7e1b78 -3c62ffff41820080 +7d23ea144bfffba5 +418200802c090000 +3c62ffff7c7e1b78 7fa4eb787b85f882 -4bffe58938637f90 -283f800060000000 -4081000c7fe5fb78 -54a5042038a0ffff -78a5f0823c62ffff -38637fa838800000 -600000004bffe55d -7be5f0823c62ffff -38637fc07fc4f378 -600000004bffe545 -38637fd83c62ffff -600000004bffe535 -3821008038600000 -48000d987c6307b4 -38637fe83c62ffff -600000004bffe515 -4bffffe038600001 -0100000000000000 -3c4c000100000480 -60000000384292b4 -6000000089228068 -2c09000039428060 -e92a000041820030 -7c0004ac39290014 -712900207d204eaa -600000004182ffec -7c0004ace9228060 -4e8000207c604faa -39290010e92a0000 -7d204eea7c0004ac -4082ffec71290008 -600000005469063e -7c0004ace9428060 -4e8000207d2057ea +4bffe57138637fb8 +38a0ffff60000000 +3c62ffff283f8000 +54a5042038800000 +7ca5f85e38637fd0 +4bffe54978a5f082 +3c62ffff60000000 +7fc4f3787be5f082 +4bffe53138637fe8 +6000000060000000 +4bffe52138628000 +3860000060000000 +7c6307b438210080 +6000000048000db0 +4bffe50138628010 +3860000160000000 +000000004bffffe0 +0000048001000000 +384292a03c4c0001 +6000000060000000 +3942808889228090 +418200302c090000 +39290014e92a0000 +7d204eaa7c0004ac +4182ffec71290020 +e922808860000000 +7c604faa7c0004ac +e92a00004e800020 +7c0004ac39290010 +712900087d204eea +600000004082ffec +e94280885469063e +7d2057ea7c0004ac +000000004e800020 0000000000000000 -3c4c000100000000 -7c0802a63842922c -fbc1fff0fbe1fff8 -f80100103be3ffff -8fdf0001f821ffd1 -408200102c1e0000 -3860000038210030 -2c1e000a48000cd0 -3860000d4082000c -7fc307b44bffff3d -4bffffd04bffff35 -0100000000000000 -3c4c000100000280 -3d20c000384291cc -7929002061290020 -7d204eea7c0004ac -792906003d40c000 -794a0020614a0008 -7d4056ea7c0004ac -3d40c000714a0020 -794a0020614a2000 -6000000040820040 -39400000f9428060 -9942806860000000 -614a20003d40001c -3d40c0007d295392 -794a0020614a2018 -7c0004ac3929ffff -4e8000207d2057ea -610800403d00c000 -7c0004ac79080020 -790807e37d0046ea -f942806060000000 -614a20003d40001c -4182ffa07d495392 -3920000160000000 -3d00c00099228068 -3920ff806108200c -7c0004ac79080020 -e92280607d2047aa -7d404faa7c0004ac -794ac202e9228060 -7c0004ac39290004 -e92280607d404faa -3929000c39400003 +384292183c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be3fffff821ffd1 +2c1e00008fdf0001 +3821003040820010 +48000ce838600000 +4082000c2c1e000a +4bffff3d3860000d +4bffff357fc307b4 +000000004bffffd0 +0000028001000000 +384291b83c4c0001 +612900203d20c000 +7c0004ac79290020 +3d40c0007d204eea +614a000879290600 +7c0004ac794a0020 +714a00207d4056ea +614a20003d40c000 +40820040794a0020 +f942808860000000 +6000000039400000 +3d40001c99428090 +7d295392614a2000 +614a20183d40c000 +3929ffff794a0020 +7d2057ea7c0004ac +3d00c0004e800020 +7908002061080040 +7d0046ea7c0004ac +790807e360000000 +3d40001cf9428088 +7d495392614a2000 +600000004182ffa0 +9922809039200001 +3920ff803d00c000 +790800206108200c +7d2047aa7c0004ac +7c0004ace9228088 +e92280887d404faa +39290004794ac202 7d404faa7c0004ac -39290010e9228060 +39400003e9228088 +7c0004ac3929000c +e92280887d404faa +7c0004ac39290010 +e92280887d404faa +3929000839400007 7d404faa7c0004ac -39400007e9228060 -7c0004ac39290008 -4e8000207d404faa -0000000000000000 -78a9e8c200000000 -3929000139400000 -420000287d2903a6 -78a5076078a90724 -7d434a1439050001 -7c844a147d0903a6 -4200001839200000 -7d24502a4e800020 -394a00087d23512a -7d0448ae4bffffcc -392900017d0a49ae -000000004bffffdc -0000000000000000 -386000007c691b78 -2c0a00007d4918ae -386300014d820020 -000000004bfffff0 -0000000000000000 -408200082c240000 -280500243881fff0 -38600000f8640000 -3d00fffe4d810020 -790883e46108ffff -e92400006108d9ff -280a002089490000 -2c25000040810040 -2c05001041820054 -2c0a003040820064 -894900014082006c -408200602c0a0078 -f924000039290002 -3929000148000054 -4bffffb8f9240000 -714a00017d0a5634 -2c2500004182ffec -38a0000a4082002c -2c0a00304800001c -4082001038a0000a +000000004e800020 +0000000000000000 +3940000078a9e8c2 +7d2903a639290001 +78a9072442000028 +3905000178a50760 +7c844a147d434a14 +7d0903a639200000 +4e80002042000018 +7d23512a7d24502a +4bffffcc394a0008 +7d0a49ae7d0448ae +4bffffdc39290001 +0000000000000000 +7c691b7800000000 +7d4918ae38600000 +4d8200202c0a0000 +4bfffff038630001 +0000000000000000 +2c24000000000000 +3881fff040820008 +f864000028050024 +4d81002038600000 +6108ffff3d00fffe +6108d9ff790883e4 +89490000e9240000 +40810040280a0020 +418200542c250000 +408200642c050010 +4082006c2c0a0030 2c0a007889490001 -386000004182ffb8 -2c05001048000048 -38a000104082fff4 -38eaffd04bffffec -2807000954e7063e -3929ffd04181003c -7c0a28007d2a0734 -390800014c800020 -7d2907347c6519d2 -7c691a14f9040000 +3929000240820060 +48000054f9240000 +f924000039290001 +7d0a56344bffffb8 +4182ffec714a0001 +4082002c2c250000 +4800001c38a0000a +38a0000a2c0a0030 +8949000140820010 +4182ffb82c0a0078 +4800004438600000 +4082fff42c050010 +4bffffec38a00010 +54e7063e38eaffd0 +4181003828070009 +7d2a07343929ffd0 +4c8000207c0a2800 +390800017d290734 +f904000010651a73 89480000e9040000 -4082ffc0714900ff +4082ffc4714900ff 38eaff9f4e800020 2807001954e7063e 3929ffa94181000c -394affbf4bffffb8 +394affbf4bffffbc 280a0019554a063e 3929ffc94d810020 -000000004bffffa0 +000000004bffffa4 0000000000000000 280900193923ff9f 3863ffe041810008 4e8000207c6307b4 0000000000000000 3c4c000100000000 -7c0802a638428e94 -f821ffa1480008e9 +7c0802a638428e84 +f821ffa148000905 7cfd3b787c7e1b78 7c9c23787ca32b78 3880000038a0000a -7cdf3378eb3e0000 -7d3a4b787d1b4378 -600000004bfffe59 -394000002b9d0010 +7d1b43787cdf3378 +7d3a4b78eb3e0000 +600000004bfffe5d +2b9d001039400000 4082005c2c3f0000 408200082c0a0000 7d4ad21439400001 @@ -1536,36 +1538,36 @@ e93e00007d2903a6 9b69000040800018 39290001e93e0000 4200ffe0f93e0000 -4800089c38210060 +480008b838210060 7bffe102409e0010 4bffff94394a0001 4bfffff47fffeb92 0100000000000000 3c4c000100000780 -7c0802a638428dc4 -f821ffb148000821 -7c7f1b78eb630000 -7cbd2b787c9c2378 -7fa3eb783bc00000 -600000004bfffd71 +7c0802a638428db4 +f821ffb14800083d +eb6300003bc00000 +7c9c23787c7f1b78 +7fa3eb787cbd2b78 +600000004bfffd75 408000147c3e1840 7d5b4850e93f0000 4180000c7c2ae040 -4800082c38210050 +4800084838210050 3bde00017d5df0ae e93f000099490000 f93f000039290001 000000004bffffbc 0000058001000000 -38428d483c4c0001 -3d22ffff7c0802a6 -2b860010e9297ff8 -7caa2b787d708026 -4800078991610008 -7c7c1b78f821ffa1 +38428d383c4c0001 +7d7080267c0802a6 +480007b991610008 +3be00000f821ffa1 +7c7c1b7860000000 7cdd33787cbe2b78 -f92100203be00000 -e922800060000000 +2b8600107caa2b78 +f9210020e9228020 +e922802860000000 2c2a0000f9210028 2c1f000040820034 3be0000140820008 @@ -1573,253 +1575,256 @@ e922800060000000 3b7fffff7c3f2040 3821006040810030 7d70812081610008 -409e00104800077c +409e00104800079c 3bff0001794ae102 7d4aeb924bffffbc -7f5ed3784bfffff4 -7d3ae9d27f5eeb92 -7d214a147d29f050 +7d3e4b784bfffff4 +7d214a147d3eea12 4192001088690020 -4bfffdd55463063e -7c3df04060000000 -7c69d9aee93c0000 -4081ffc83b7bffff -7d29fa14e93c0000 -4bffff90f93c0000 -0300000000000000 -3c4c000100000680 -7c0802a638428c54 -f821ff014800067d -f86100607c7d1b79 -4182001438600000 -3bc4ffff2c240000 -4082013c3b610040 -7c6307b438210100 -2c0a00254800069c -4082062039050001 -7cbc2b7838e00000 -7ce93b7889450000 -889c000138a50001 -394700017d47d9ae -2c0800645488063e -28080078418201cc -280800684181002c -2c0800584181002c -2808005841820130 -2c08002541810088 -2c08004f418200c0 -38e7000141820118 -3904ff974bffffa4 -280b000f550b063e -3d62ffff4181ffec -790815a8396b7488 -7d085a147d0b42aa -4e8004207d0903a6 -ffffffcc00000164 +4bfffddd5463063e +e93c000060000000 +7c69d9ae7c3df040 +3b7bffff7d3eeb92 +e93c00004081ffcc +f93c00007d29fa14 +000000004bffff94 +0000058003000000 +38428c483c4c0001 +4800069d7c0802a6 +7c7d1b79f821fef1 +38600000f8610060 +2c24000041820014 +3b6100403bc4ffff +3821011040820144 +480006bc7c6307b4 +390500012c0a0025 +38e0000040820640 +894500007cbc2b78 +38a500017ce93b78 +7d47d9ae889c0001 +5488063e39470001 +418201dc2c080064 +4181002c28080078 +4181002c28080068 +418201382c080058 +4181008828080058 +418200c82c080025 +418201202c08004f +4bffffa438e70001 +550b063e3904ff97 +4181ffec280b000f +790815a83d62ffff +7d0b42aa396b7494 +7d0903a67d085a14 +000001744e800420 ffffffccffffffcc ffffffccffffffcc -000000cc0000006c +00000074ffffffcc +ffffffcc000000d4 +000000c0ffffffcc +00000048ffffffcc ffffffccffffffcc -ffffffcc000000b8 -ffffffcc00000048 -00000150ffffffcc -4bffff842c080063 -7d4a07b439010020 -390000757d485214 -990a002039290002 -7d2907b439410020 -3901002048000094 -7d4852147d4a07b4 -4bffffdc3900006f -991f0000393f0001 -38bc0002f9210060 -ebe1006089250000 -7c7df850712a00ff -7c23f0404182000c -392000004180febc -4bfffea4993f0000 -7d4a07b439010020 -390000737d485214 -390100204bffff90 -7d4852147d4a07b4 -4bffff7c39000070 -7d4a07b438e10020 -392900027d475214 -990a00207d2907b4 -7d2a4a147cea3b78 -7f23f05039400000 -994900203a460008 -3ac100423a600030 -3929ffd289210041 -eb060000712900fd -5669063e40820458 -3a80000060000000 -f92100683aa00004 -3a2000003ae00000 -480001a43a028018 -7d4a07b439010020 -390000787d485214 -390100204bfffef8 -7d4852147d4a07b4 +2c08006300000160 +7d4a07b44bffff84 +38e0007539010020 +98ea00207d485214 7d2907b439290002 -7d0a4378988a0020 -2c08004f4bffff7c -418201dc38f60001 -5546063e3949ffa8 -418103b828060022 -38c676443cc2ffff -7d4652aa794a15a8 -7d4903a67d4a3214 -000001584e800420 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000039800000398 -0000008c00000268 -0000039800000398 -0000037c00000398 -000003980000008c -0000036400000398 -0000039800000398 -00000204000001ac -0000039800000398 -00000398000002ac -000003980000008c -0000015c00000398 -000003bc00000398 -7ae900202c080075 -394000007d214a14 -994900207f1ac378 -56aa183841820044 -394affff39200001 -7f0948397d295036 +392000007d084a14 +4800009c99280020 +390100207d4a07b4 +7d48521438e0006f +393f00014bffffd4 +f9210060991f0000 +8925000038bc0002 +712a00ffebe10060 +4182000c7c7df850 +4180feb47c23f040 +993f000039200000 +7d4a07b44bfffe9c +38e0007339010020 +4bffff887d485214 +390100207d4a07b4 +7d48521438e00070 +392900024bffff74 +7d4a07b438e10020 +7d4752147d2907b4 +392000007ce74a14 +99270020990a0020 +eb06000089210041 +3a4600087f43f050 +3b2100423a800030 +712900fd3929ffd2 +5689063e40820474 +3aa0000060000000 +3ae000003ac00004 +3a6100603a200000 +39210020f9210068 +f92100703a028040 +7d4a07b4480001f8 +38e0007839010020 +4bfffee87d485214 +390100207d4a07b4 +988a00207d485214 +2c06004f4bfffed8 +418201e838b90001 +54e4063e38e9ffa8 +418103dc28040022 +78e715a83d42ffff +7ce43aaa388a7654 +7ce903a67ce72214 +000001344e800420 +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +000003bc000003bc +0000008c00000288 +000003bc000003bc +000003a0000003bc +000003bc0000008c +0000038c000003bc +000003bc000003bc +00000218000001b8 +000003bc000003bc +000003bc000002cc +000003bc0000008c +00000138000003bc +00000398000003bc +2c0600757ae90020 +7f0fc37839400000 +994900207d214a14 +56c7183841820044 +38e7ffff39200001 +7f0948397d293836 3920002d4182002c -3942801860000000 -992e00007f5800d0 -f9210060392e0001 -7d2a482a7aa91e68 -e88100607f5a4838 -7f46d37838e0000a -3920000038a10020 -386100605668063e -7c84c8507c9f2050 -e88100604bfffa25 -38c0000a7a8707e0 -7c9f20507f45d378 -386100607c84c850 -3ad600014bfffb51 -e9c1006089360000 -41820010712800ff -7c39d0407f5f7050 -7e4693784181fe7c -3a8000014bfffd7c -e90100687ae90020 -7d214a1438e00010 -38a100207c9ac850 -9a29002038610060 -7dd0482a7aa91e68 -7f0e703839200000 -4bfff9a17dc67378 -7a8707e0e8810060 -7c9f205038c00010 -4bffff7c7dc57378 -394000007ae90020 -38e000087d214a14 -5668063e7c9ac850 -6000000099490020 -394280187aa91e68 -3861006038a10020 -392000007dca482a -7dc673787f0e7038 -e88100604bfff945 -38c000087a8707e0 -4bffffa47c9f2050 -394000007ae90020 -38e000107d214a14 -390000207f06c378 -38a1002099490020 -7c9ac85039200002 -4bfff90138610060 +7d5800d039080001 +f90100609928ffff +7ac91e6860000000 +7d28482a39028040 +e88100607d4f4838 +38e0000a38610060 +38a100207de67b78 +5688063e39200000 +7c9f2050f8610078 +4bfffa217c84d050 +7aa707e0e8810060 +7de57b7838c0000a +e86100787c9f2050 +4800005c7c84d050 +7ae900203aa00001 +e9010068e8a10070 +7c8fd05038e00010 +7d214a147e639b78 +7ac91e689a290020 +392000007d70482a +7dc673787f0e5838 +e88100604bfff9c5 +38c000107aa707e0 +7e639b787dc57378 +7c84d0507c9f2050 +3b3900014bfffaf1 +e901006089390000 +41820010712600ff +7c3a78407dff4050 +7e4693784181fe1c +7ae900204bfffd20 +3861006039000000 +38a1002038e00008 +7d214a147c8fd050 +99090020f8610078 +7ac91e6860000000 +7d68482a39028040 +5688063e39200000 +7dc673787f0e5838 +e88100604bfff935 +38c000087aa707e0 +7c9f20507dc57378 +7ae900204bffff14 +3861006039000000 +7f06c37838e00010 +38a100207c8fd050 +7c6f1b787d214a14 +3920000299090020 +4bfff8e939000020 60000000e8810060 -38a2801038610060 -7c84c8507c9f2050 -e88100604bfff9b5 -38c000107a8707e0 -7c9f20507f05c378 -7ae900204bfffec0 -7d214a1439400000 -38e0000a39000020 -9949002038c00001 -3920000038a10020 -386100607c9ac850 -e92100604bfff89d +38a280387de37b78 +7c84d0507c9f2050 +e88100604bfff99d +38c000107aa707e0 +7de37b787f05c378 +7c84d0507c9f2050 +7ae900204bffff08 +38e0000a39000000 +38a1002038c00001 +386100607c8fd050 +990900207d214a14 +3900002039200000 +e92100604bfff87d 392900019b090000 -4bfffe88f9210060 -394000007ae90020 -38a0000a7d214a14 -3861002038800000 -4bfff6f599490020 -7c6f1b7860000000 -4bfff6bd7f03c378 -7c2f184060000000 -7d0ef85040810064 -7d08ca147f5ac850 -2c2800007c637850 -394000007c6e1a14 -3b5a000138e00020 -3b40000140820008 -3b5affff2c3a0001 -714a000140820014 -f9c1006041820024 -98ee00004800001c -3940000139ce0001 -4082ffd47c237040 -e8810060f8610060 +4bfffec8f9210060 +38e000007ae90020 +3880000038a0000a +38610020f9010078 +98e900207d214a14 +600000004bfff6d5 +7f03c3787c6e1b78 +600000004bfff69d +408100687c2e1840 +7d4fd050e9010078 +38e000007c637050 +394a000138a00020 +7d281a147cc8f850 +2c2600007cc6d214 +7d46509e38c00001 +394affff2c2a0001 +70e7000140820014 +f901006041820024 +98a800004800001c +38e0000139080001 +4082ffd47c294040 +e8810060f9210060 386100607f05c378 -7c84c8507c9f2050 -4bfffdd04bfff8a5 -3aa0000889360001 -4082fdc02c09006c -4bfffdb87cf63b78 -3aa0000289360001 -4082fda82c090068 -3aa000017cf63b78 -3949ffd04bfffd9c -280a0009554a063e -7aea00204181fd8c -7d4152143af70001 -4bfffd78992a0020 -4bfffd703aa00008 -3ac100413a600020 -993f00004bfffba4 -7d0543783bff0001 -4bfffaf4fbe10060 -0100000000000000 -f9c1ff7000001280 -fa01ff80f9e1ff78 -fa41ff90fa21ff88 -fa81ffa0fa61ff98 -fac1ffb0faa1ffa8 -fb01ffc0fae1ffb8 -fb41ffd0fb21ffc8 -fb81ffe0fb61ffd8 -fbc1fff0fba1ffe8 -f8010010fbe1fff8 -e9c1ff704e800020 -ea01ff80e9e1ff78 -ea41ff90ea21ff88 -ea81ffa0ea61ff98 -eac1ffb0eaa1ffa8 -eb01ffc0eae1ffb8 -eb41ffd0eb21ffc8 -eb81ffe0eb61ffd8 -eba1ffe8e8010010 -ebc1fff07c0803a6 -4e800020ebe1fff8 -e8010010ebc1fff0 -7c0803a6ebe1fff8 -600000004e800020 +7c84d0507c9f2050 +4bfffe084bfff87d +2809006c89390001 +3ac000087f25c89e +893900014bfffdf4 +280900683ac00001 +7f25c89e39200002 +4bfffdd87ed6489e +554a063e3949ffd0 +4181fdc8280a0009 +3af700017aea0020 +992a00207d415214 +3a8000204bfffdb4 +4bfffb883b210041 +3bff0001993f0000 +fbe100607d054378 +000000004bfffadc +0000128001000000 +f9e1ff78f9c1ff70 +fa21ff88fa01ff80 +fa61ff98fa41ff90 +faa1ffa8fa81ffa0 +fae1ffb8fac1ffb0 +fb21ffc8fb01ffc0 +fb61ffd8fb41ffd0 +fba1ffe8fb81ffe0 +fbe1fff8fbc1fff0 +4e800020f8010010 +e9e1ff78e9c1ff70 +ea21ff88ea01ff80 +ea61ff98ea41ff90 +eaa1ffa8ea81ffa0 +eae1ffb8eac1ffb0 +eb21ffc8eb01ffc0 +eb61ffd8eb41ffd0 +e8010010eb81ffe0 +7c0803a6eba1ffe8 +ebe1fff8ebc1fff0 +ebc1fff04e800020 +ebe1fff8e8010010 +4e8000207c0803a6 6d6f636c65570a0a 63694d206f742065 2120747461776f72 @@ -1870,15 +1875,15 @@ e8010010ebc1fff0 203a46464f204853 7479622078257830 00000000000a7365 -20676e69746f6f42 -415242206d6f7266 -0000000a2e2e2e4d -3135636632333936 +2d2d2d2d2d2d2d2d 0000000000000000 4d4152446574694c 6620746c69756220 6574694c206d6f72 0000000a73252058 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d 6620676e69797254 0a2e2e2e6873616c 0000000000000000 diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v index d4db3de..4196f91 100644 --- a/litedram/generated/wukong-v2/litedram_core.v +++ b/litedram/generated/wukong-v2/litedram_core.v @@ -8,8 +8,8 @@ // // Filename : litedram_core.v // Device : -// LiteX sha1 : 6932fc51 -// Date : 2022-08-04 21:07:01 +// LiteX sha1 : -------- +// Date : 2022-10-28 19:01:24 //------------------------------------------------------------------------------ @@ -18,50 +18,50 @@ //------------------------------------------------------------------------------ module litedram_core ( - input wire clk, - input wire rst, - output wire pll_locked, - output wire [13:0] ddram_a, - output wire [2:0] ddram_ba, - output wire ddram_ras_n, - output wire ddram_cas_n, - output wire ddram_we_n, - output wire ddram_cs_n, - output wire [1:0] ddram_dm, - inout wire [15:0] ddram_dq, - inout wire [1:0] ddram_dqs_p, - inout wire [1:0] ddram_dqs_n, - output wire ddram_clk_p, - output wire ddram_clk_n, - output wire ddram_cke, - output wire ddram_odt, - output wire ddram_reset_n, - output wire init_done, - output wire init_error, - input wire [29:0] wb_ctrl_adr, - input wire [31:0] wb_ctrl_dat_w, - output wire [31:0] wb_ctrl_dat_r, - input wire [3:0] wb_ctrl_sel, - input wire wb_ctrl_cyc, - input wire wb_ctrl_stb, - output wire wb_ctrl_ack, - input wire wb_ctrl_we, - input wire [2:0] wb_ctrl_cti, - input wire [1:0] wb_ctrl_bte, - output wire wb_ctrl_err, - output wire user_clk, - output wire user_rst, - input wire user_port_native_0_cmd_valid, - output wire user_port_native_0_cmd_ready, - input wire user_port_native_0_cmd_we, - input wire [23:0] user_port_native_0_cmd_addr, - input wire user_port_native_0_wdata_valid, - output wire user_port_native_0_wdata_ready, - input wire [15:0] user_port_native_0_wdata_we, - input wire [127:0] user_port_native_0_wdata_data, - output wire user_port_native_0_rdata_valid, - input wire user_port_native_0_rdata_ready, - output wire [127:0] user_port_native_0_rdata_data + input wire clk, + input wire rst, + output wire pll_locked, + output wire [13:0] ddram_a, + output wire [2:0] ddram_ba, + output wire ddram_ras_n, + output wire ddram_cas_n, + output wire ddram_we_n, + output wire ddram_cs_n, + output wire [1:0] ddram_dm, + inout wire [15:0] ddram_dq, + inout wire [1:0] ddram_dqs_p, + inout wire [1:0] ddram_dqs_n, + output wire ddram_clk_p, + output wire ddram_clk_n, + output wire ddram_cke, + output wire ddram_odt, + output wire ddram_reset_n, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data ); @@ -69,1941 +69,2065 @@ module litedram_core ( // Signals //------------------------------------------------------------------------------ -reg rst_1 = 1'd0; -wire sys_clk; -wire sys_rst; -wire sys4x_clk; -wire sys4x_dqs_clk; -wire iodelay_clk; -wire iodelay_rst; -wire reset; -reg power_down = 1'd0; -wire locked; -wire clkin; -wire clkout0; -wire clkout_buf0; -wire clkout1; -wire clkout_buf1; -wire clkout2; -wire clkout_buf2; -wire clkout3; -wire clkout_buf3; -reg [3:0] reset_counter = 4'd15; -reg ic_reset = 1'd1; -reg a7ddrphy_rst_storage = 1'd0; -reg a7ddrphy_rst_re = 1'd0; -reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; -reg a7ddrphy_dly_sel_re = 1'd0; -reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; -reg a7ddrphy_half_sys8x_taps_re = 1'd0; -reg a7ddrphy_wlevel_en_storage = 1'd0; -reg a7ddrphy_wlevel_en_re = 1'd0; -reg a7ddrphy_wlevel_strobe_re = 1'd0; -wire a7ddrphy_wlevel_strobe_r; -reg a7ddrphy_wlevel_strobe_we = 1'd0; -reg a7ddrphy_wlevel_strobe_w = 1'd0; -reg a7ddrphy_rdly_dq_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_rst_r; -reg a7ddrphy_rdly_dq_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_inc_re = 1'd0; -wire a7ddrphy_rdly_dq_inc_r; -reg a7ddrphy_rdly_dq_inc_we = 1'd0; -reg a7ddrphy_rdly_dq_inc_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_rst_r; -reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_rdly_dq_bitslip_r; -reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_rst_r; -reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; -wire a7ddrphy_wdly_dq_bitslip_r; -reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; -reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; -reg [1:0] a7ddrphy_rdphase_storage = 2'd2; -reg a7ddrphy_rdphase_re = 1'd0; -reg [1:0] a7ddrphy_wrphase_storage = 2'd3; -reg a7ddrphy_wrphase_re = 1'd0; -wire [13:0] a7ddrphy_dfi_p0_address; -wire [2:0] a7ddrphy_dfi_p0_bank; -wire a7ddrphy_dfi_p0_cas_n; -wire a7ddrphy_dfi_p0_cs_n; -wire a7ddrphy_dfi_p0_ras_n; -wire a7ddrphy_dfi_p0_we_n; -wire a7ddrphy_dfi_p0_cke; -wire a7ddrphy_dfi_p0_odt; -wire a7ddrphy_dfi_p0_reset_n; -wire a7ddrphy_dfi_p0_act_n; -wire [31:0] a7ddrphy_dfi_p0_wrdata; -wire a7ddrphy_dfi_p0_wrdata_en; -wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; -wire a7ddrphy_dfi_p0_rddata_en; -reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; -wire a7ddrphy_dfi_p0_rddata_valid; -wire [13:0] a7ddrphy_dfi_p1_address; -wire [2:0] a7ddrphy_dfi_p1_bank; -wire a7ddrphy_dfi_p1_cas_n; -wire a7ddrphy_dfi_p1_cs_n; -wire a7ddrphy_dfi_p1_ras_n; -wire a7ddrphy_dfi_p1_we_n; -wire a7ddrphy_dfi_p1_cke; -wire a7ddrphy_dfi_p1_odt; -wire a7ddrphy_dfi_p1_reset_n; -wire a7ddrphy_dfi_p1_act_n; -wire [31:0] a7ddrphy_dfi_p1_wrdata; -wire a7ddrphy_dfi_p1_wrdata_en; -wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; -wire a7ddrphy_dfi_p1_rddata_en; -reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; -wire a7ddrphy_dfi_p1_rddata_valid; -wire [13:0] a7ddrphy_dfi_p2_address; -wire [2:0] a7ddrphy_dfi_p2_bank; -wire a7ddrphy_dfi_p2_cas_n; -wire a7ddrphy_dfi_p2_cs_n; -wire a7ddrphy_dfi_p2_ras_n; -wire a7ddrphy_dfi_p2_we_n; -wire a7ddrphy_dfi_p2_cke; -wire a7ddrphy_dfi_p2_odt; -wire a7ddrphy_dfi_p2_reset_n; -wire a7ddrphy_dfi_p2_act_n; -wire [31:0] a7ddrphy_dfi_p2_wrdata; -wire a7ddrphy_dfi_p2_wrdata_en; -wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; -wire a7ddrphy_dfi_p2_rddata_en; -reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; -wire a7ddrphy_dfi_p2_rddata_valid; -wire [13:0] a7ddrphy_dfi_p3_address; -wire [2:0] a7ddrphy_dfi_p3_bank; -wire a7ddrphy_dfi_p3_cas_n; -wire a7ddrphy_dfi_p3_cs_n; -wire a7ddrphy_dfi_p3_ras_n; -wire a7ddrphy_dfi_p3_we_n; -wire a7ddrphy_dfi_p3_cke; -wire a7ddrphy_dfi_p3_odt; -wire a7ddrphy_dfi_p3_reset_n; -wire a7ddrphy_dfi_p3_act_n; -wire [31:0] a7ddrphy_dfi_p3_wrdata; -wire a7ddrphy_dfi_p3_wrdata_en; -wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; -wire a7ddrphy_dfi_p3_rddata_en; -reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; -wire a7ddrphy_dfi_p3_rddata_valid; -wire a7ddrphy_sd_clk_se_nodelay; -wire [2:0] a7ddrphy_pads_ba; -reg a7ddrphy_dqs_oe = 1'd0; -wire a7ddrphy_dqs_preamble; -wire a7ddrphy_dqs_postamble; -wire a7ddrphy_dqs_oe_delay_tappeddelayline; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -reg a7ddrphy_dqspattern0 = 1'd0; -reg a7ddrphy_dqspattern1 = 1'd0; -reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; -reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; -wire a7ddrphy_dqs_o_no_delay0; -wire a7ddrphy_dqs_t0; -reg [7:0] a7ddrphy_bitslip00 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; -wire a7ddrphy0; -wire a7ddrphy_dqs_o_no_delay1; -wire a7ddrphy_dqs_t1; -reg [7:0] a7ddrphy_bitslip10 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; -wire a7ddrphy1; -reg [7:0] a7ddrphy_bitslip01 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; -reg [7:0] a7ddrphy_bitslip11 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; -wire a7ddrphy_dq_oe; -wire a7ddrphy_dq_oe_delay_tappeddelayline; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; -reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; -wire a7ddrphy_dq_o_nodelay0; -wire a7ddrphy_dq_i_nodelay0; -wire a7ddrphy_dq_i_delayed0; -wire a7ddrphy_dq_t0; -reg [7:0] a7ddrphy_bitslip02 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip03; -reg [7:0] a7ddrphy_bitslip04 = 8'd0; -reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay1; -wire a7ddrphy_dq_i_nodelay1; -wire a7ddrphy_dq_i_delayed1; -wire a7ddrphy_dq_t1; -reg [7:0] a7ddrphy_bitslip12 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; -wire [7:0] a7ddrphy_bitslip13; -reg [7:0] a7ddrphy_bitslip14 = 8'd0; -reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; -reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; -wire a7ddrphy_dq_o_nodelay2; -wire a7ddrphy_dq_i_nodelay2; -wire a7ddrphy_dq_i_delayed2; -wire a7ddrphy_dq_t2; -reg [7:0] a7ddrphy_bitslip20 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip21; -reg [7:0] a7ddrphy_bitslip22 = 8'd0; -reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay3; -wire a7ddrphy_dq_i_nodelay3; -wire a7ddrphy_dq_i_delayed3; -wire a7ddrphy_dq_t3; -reg [7:0] a7ddrphy_bitslip30 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip31; -reg [7:0] a7ddrphy_bitslip32 = 8'd0; -reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay4; -wire a7ddrphy_dq_i_nodelay4; -wire a7ddrphy_dq_i_delayed4; -wire a7ddrphy_dq_t4; -reg [7:0] a7ddrphy_bitslip40 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip41; -reg [7:0] a7ddrphy_bitslip42 = 8'd0; -reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay5; -wire a7ddrphy_dq_i_nodelay5; -wire a7ddrphy_dq_i_delayed5; -wire a7ddrphy_dq_t5; -reg [7:0] a7ddrphy_bitslip50 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip51; -reg [7:0] a7ddrphy_bitslip52 = 8'd0; -reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay6; -wire a7ddrphy_dq_i_nodelay6; -wire a7ddrphy_dq_i_delayed6; -wire a7ddrphy_dq_t6; -reg [7:0] a7ddrphy_bitslip60 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip61; -reg [7:0] a7ddrphy_bitslip62 = 8'd0; -reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay7; -wire a7ddrphy_dq_i_nodelay7; -wire a7ddrphy_dq_i_delayed7; -wire a7ddrphy_dq_t7; -reg [7:0] a7ddrphy_bitslip70 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip71; -reg [7:0] a7ddrphy_bitslip72 = 8'd0; -reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay8; -wire a7ddrphy_dq_i_nodelay8; -wire a7ddrphy_dq_i_delayed8; -wire a7ddrphy_dq_t8; -reg [7:0] a7ddrphy_bitslip80 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip81; -reg [7:0] a7ddrphy_bitslip82 = 8'd0; -reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay9; -wire a7ddrphy_dq_i_nodelay9; -wire a7ddrphy_dq_i_delayed9; -wire a7ddrphy_dq_t9; -reg [7:0] a7ddrphy_bitslip90 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip91; -reg [7:0] a7ddrphy_bitslip92 = 8'd0; -reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay10; -wire a7ddrphy_dq_i_nodelay10; -wire a7ddrphy_dq_i_delayed10; -wire a7ddrphy_dq_t10; -reg [7:0] a7ddrphy_bitslip100 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip101; -reg [7:0] a7ddrphy_bitslip102 = 8'd0; -reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay11; -wire a7ddrphy_dq_i_nodelay11; -wire a7ddrphy_dq_i_delayed11; -wire a7ddrphy_dq_t11; -reg [7:0] a7ddrphy_bitslip110 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip111; -reg [7:0] a7ddrphy_bitslip112 = 8'd0; -reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay12; -wire a7ddrphy_dq_i_nodelay12; -wire a7ddrphy_dq_i_delayed12; -wire a7ddrphy_dq_t12; -reg [7:0] a7ddrphy_bitslip120 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip121; -reg [7:0] a7ddrphy_bitslip122 = 8'd0; -reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay13; -wire a7ddrphy_dq_i_nodelay13; -wire a7ddrphy_dq_i_delayed13; -wire a7ddrphy_dq_t13; -reg [7:0] a7ddrphy_bitslip130 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip131; -reg [7:0] a7ddrphy_bitslip132 = 8'd0; -reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay14; -wire a7ddrphy_dq_i_nodelay14; -wire a7ddrphy_dq_i_delayed14; -wire a7ddrphy_dq_t14; -reg [7:0] a7ddrphy_bitslip140 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip141; -reg [7:0] a7ddrphy_bitslip142 = 8'd0; -reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; -wire a7ddrphy_dq_o_nodelay15; -wire a7ddrphy_dq_i_nodelay15; -wire a7ddrphy_dq_i_delayed15; -wire a7ddrphy_dq_t15; -reg [7:0] a7ddrphy_bitslip150 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; -wire [7:0] a7ddrphy_bitslip151; -reg [7:0] a7ddrphy_bitslip152 = 8'd0; -reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; -reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; -reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; -reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; -reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; -wire [13:0] litedramcore_slave_p0_address; -wire [2:0] litedramcore_slave_p0_bank; -wire litedramcore_slave_p0_cas_n; -wire litedramcore_slave_p0_cs_n; -wire litedramcore_slave_p0_ras_n; -wire litedramcore_slave_p0_we_n; -wire litedramcore_slave_p0_cke; -wire litedramcore_slave_p0_odt; -wire litedramcore_slave_p0_reset_n; -wire litedramcore_slave_p0_act_n; -wire [31:0] litedramcore_slave_p0_wrdata; -wire litedramcore_slave_p0_wrdata_en; -wire [3:0] litedramcore_slave_p0_wrdata_mask; -wire litedramcore_slave_p0_rddata_en; -reg [31:0] litedramcore_slave_p0_rddata = 32'd0; -reg litedramcore_slave_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p1_address; -wire [2:0] litedramcore_slave_p1_bank; -wire litedramcore_slave_p1_cas_n; -wire litedramcore_slave_p1_cs_n; -wire litedramcore_slave_p1_ras_n; -wire litedramcore_slave_p1_we_n; -wire litedramcore_slave_p1_cke; -wire litedramcore_slave_p1_odt; -wire litedramcore_slave_p1_reset_n; -wire litedramcore_slave_p1_act_n; -wire [31:0] litedramcore_slave_p1_wrdata; -wire litedramcore_slave_p1_wrdata_en; -wire [3:0] litedramcore_slave_p1_wrdata_mask; -wire litedramcore_slave_p1_rddata_en; -reg [31:0] litedramcore_slave_p1_rddata = 32'd0; -reg litedramcore_slave_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p2_address; -wire [2:0] litedramcore_slave_p2_bank; -wire litedramcore_slave_p2_cas_n; -wire litedramcore_slave_p2_cs_n; -wire litedramcore_slave_p2_ras_n; -wire litedramcore_slave_p2_we_n; -wire litedramcore_slave_p2_cke; -wire litedramcore_slave_p2_odt; -wire litedramcore_slave_p2_reset_n; -wire litedramcore_slave_p2_act_n; -wire [31:0] litedramcore_slave_p2_wrdata; -wire litedramcore_slave_p2_wrdata_en; -wire [3:0] litedramcore_slave_p2_wrdata_mask; -wire litedramcore_slave_p2_rddata_en; -reg [31:0] litedramcore_slave_p2_rddata = 32'd0; -reg litedramcore_slave_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_slave_p3_address; -wire [2:0] litedramcore_slave_p3_bank; -wire litedramcore_slave_p3_cas_n; -wire litedramcore_slave_p3_cs_n; -wire litedramcore_slave_p3_ras_n; -wire litedramcore_slave_p3_we_n; -wire litedramcore_slave_p3_cke; -wire litedramcore_slave_p3_odt; -wire litedramcore_slave_p3_reset_n; -wire litedramcore_slave_p3_act_n; -wire [31:0] litedramcore_slave_p3_wrdata; -wire litedramcore_slave_p3_wrdata_en; -wire [3:0] litedramcore_slave_p3_wrdata_mask; -wire litedramcore_slave_p3_rddata_en; -reg [31:0] litedramcore_slave_p3_rddata = 32'd0; -reg litedramcore_slave_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_master_p0_address = 14'd0; -reg [2:0] litedramcore_master_p0_bank = 3'd0; -reg litedramcore_master_p0_cas_n = 1'd1; -reg litedramcore_master_p0_cs_n = 1'd1; -reg litedramcore_master_p0_ras_n = 1'd1; -reg litedramcore_master_p0_we_n = 1'd1; -reg litedramcore_master_p0_cke = 1'd0; -reg litedramcore_master_p0_odt = 1'd0; -reg litedramcore_master_p0_reset_n = 1'd0; -reg litedramcore_master_p0_act_n = 1'd1; -reg [31:0] litedramcore_master_p0_wrdata = 32'd0; -reg litedramcore_master_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; -reg litedramcore_master_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p0_rddata; -wire litedramcore_master_p0_rddata_valid; -reg [13:0] litedramcore_master_p1_address = 14'd0; -reg [2:0] litedramcore_master_p1_bank = 3'd0; -reg litedramcore_master_p1_cas_n = 1'd1; -reg litedramcore_master_p1_cs_n = 1'd1; -reg litedramcore_master_p1_ras_n = 1'd1; -reg litedramcore_master_p1_we_n = 1'd1; -reg litedramcore_master_p1_cke = 1'd0; -reg litedramcore_master_p1_odt = 1'd0; -reg litedramcore_master_p1_reset_n = 1'd0; -reg litedramcore_master_p1_act_n = 1'd1; -reg [31:0] litedramcore_master_p1_wrdata = 32'd0; -reg litedramcore_master_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; -reg litedramcore_master_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p1_rddata; -wire litedramcore_master_p1_rddata_valid; -reg [13:0] litedramcore_master_p2_address = 14'd0; -reg [2:0] litedramcore_master_p2_bank = 3'd0; -reg litedramcore_master_p2_cas_n = 1'd1; -reg litedramcore_master_p2_cs_n = 1'd1; -reg litedramcore_master_p2_ras_n = 1'd1; -reg litedramcore_master_p2_we_n = 1'd1; -reg litedramcore_master_p2_cke = 1'd0; -reg litedramcore_master_p2_odt = 1'd0; -reg litedramcore_master_p2_reset_n = 1'd0; -reg litedramcore_master_p2_act_n = 1'd1; -reg [31:0] litedramcore_master_p2_wrdata = 32'd0; -reg litedramcore_master_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; -reg litedramcore_master_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p2_rddata; -wire litedramcore_master_p2_rddata_valid; -reg [13:0] litedramcore_master_p3_address = 14'd0; -reg [2:0] litedramcore_master_p3_bank = 3'd0; -reg litedramcore_master_p3_cas_n = 1'd1; -reg litedramcore_master_p3_cs_n = 1'd1; -reg litedramcore_master_p3_ras_n = 1'd1; -reg litedramcore_master_p3_we_n = 1'd1; -reg litedramcore_master_p3_cke = 1'd0; -reg litedramcore_master_p3_odt = 1'd0; -reg litedramcore_master_p3_reset_n = 1'd0; -reg litedramcore_master_p3_act_n = 1'd1; -reg [31:0] litedramcore_master_p3_wrdata = 32'd0; -reg litedramcore_master_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; -reg litedramcore_master_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_master_p3_rddata; -wire litedramcore_master_p3_rddata_valid; -wire [13:0] litedramcore_csr_dfi_p0_address; -wire [2:0] litedramcore_csr_dfi_p0_bank; -reg litedramcore_csr_dfi_p0_cas_n = 1'd1; -reg litedramcore_csr_dfi_p0_cs_n = 1'd1; -reg litedramcore_csr_dfi_p0_ras_n = 1'd1; -reg litedramcore_csr_dfi_p0_we_n = 1'd1; -wire litedramcore_csr_dfi_p0_cke; -wire litedramcore_csr_dfi_p0_odt; -wire litedramcore_csr_dfi_p0_reset_n; -reg litedramcore_csr_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p0_wrdata; -wire litedramcore_csr_dfi_p0_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; -wire litedramcore_csr_dfi_p0_rddata_en; -reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; -reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p1_address; -wire [2:0] litedramcore_csr_dfi_p1_bank; -reg litedramcore_csr_dfi_p1_cas_n = 1'd1; -reg litedramcore_csr_dfi_p1_cs_n = 1'd1; -reg litedramcore_csr_dfi_p1_ras_n = 1'd1; -reg litedramcore_csr_dfi_p1_we_n = 1'd1; -wire litedramcore_csr_dfi_p1_cke; -wire litedramcore_csr_dfi_p1_odt; -wire litedramcore_csr_dfi_p1_reset_n; -reg litedramcore_csr_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p1_wrdata; -wire litedramcore_csr_dfi_p1_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; -wire litedramcore_csr_dfi_p1_rddata_en; -reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; -reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p2_address; -wire [2:0] litedramcore_csr_dfi_p2_bank; -reg litedramcore_csr_dfi_p2_cas_n = 1'd1; -reg litedramcore_csr_dfi_p2_cs_n = 1'd1; -reg litedramcore_csr_dfi_p2_ras_n = 1'd1; -reg litedramcore_csr_dfi_p2_we_n = 1'd1; -wire litedramcore_csr_dfi_p2_cke; -wire litedramcore_csr_dfi_p2_odt; -wire litedramcore_csr_dfi_p2_reset_n; -reg litedramcore_csr_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p2_wrdata; -wire litedramcore_csr_dfi_p2_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; -wire litedramcore_csr_dfi_p2_rddata_en; -reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; -reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; -wire [13:0] litedramcore_csr_dfi_p3_address; -wire [2:0] litedramcore_csr_dfi_p3_bank; -reg litedramcore_csr_dfi_p3_cas_n = 1'd1; -reg litedramcore_csr_dfi_p3_cs_n = 1'd1; -reg litedramcore_csr_dfi_p3_ras_n = 1'd1; -reg litedramcore_csr_dfi_p3_we_n = 1'd1; -wire litedramcore_csr_dfi_p3_cke; -wire litedramcore_csr_dfi_p3_odt; -wire litedramcore_csr_dfi_p3_reset_n; -reg litedramcore_csr_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_csr_dfi_p3_wrdata; -wire litedramcore_csr_dfi_p3_wrdata_en; -wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; -wire litedramcore_csr_dfi_p3_rddata_en; -reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; -reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; -reg litedramcore_ext_dfi_p0_cas_n = 1'd1; -reg litedramcore_ext_dfi_p0_cs_n = 1'd1; -reg litedramcore_ext_dfi_p0_ras_n = 1'd1; -reg litedramcore_ext_dfi_p0_we_n = 1'd1; -reg litedramcore_ext_dfi_p0_cke = 1'd0; -reg litedramcore_ext_dfi_p0_odt = 1'd0; -reg litedramcore_ext_dfi_p0_reset_n = 1'd0; -reg litedramcore_ext_dfi_p0_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; -reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; -reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; -reg litedramcore_ext_dfi_p1_cas_n = 1'd1; -reg litedramcore_ext_dfi_p1_cs_n = 1'd1; -reg litedramcore_ext_dfi_p1_ras_n = 1'd1; -reg litedramcore_ext_dfi_p1_we_n = 1'd1; -reg litedramcore_ext_dfi_p1_cke = 1'd0; -reg litedramcore_ext_dfi_p1_odt = 1'd0; -reg litedramcore_ext_dfi_p1_reset_n = 1'd0; -reg litedramcore_ext_dfi_p1_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; -reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; -reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; -reg litedramcore_ext_dfi_p2_cas_n = 1'd1; -reg litedramcore_ext_dfi_p2_cs_n = 1'd1; -reg litedramcore_ext_dfi_p2_ras_n = 1'd1; -reg litedramcore_ext_dfi_p2_we_n = 1'd1; -reg litedramcore_ext_dfi_p2_cke = 1'd0; -reg litedramcore_ext_dfi_p2_odt = 1'd0; -reg litedramcore_ext_dfi_p2_reset_n = 1'd0; -reg litedramcore_ext_dfi_p2_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; -reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; -reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; -reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; -reg litedramcore_ext_dfi_p3_cas_n = 1'd1; -reg litedramcore_ext_dfi_p3_cs_n = 1'd1; -reg litedramcore_ext_dfi_p3_ras_n = 1'd1; -reg litedramcore_ext_dfi_p3_we_n = 1'd1; -reg litedramcore_ext_dfi_p3_cke = 1'd0; -reg litedramcore_ext_dfi_p3_odt = 1'd0; -reg litedramcore_ext_dfi_p3_reset_n = 1'd0; -reg litedramcore_ext_dfi_p3_act_n = 1'd1; -reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; -reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; -reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; -reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; -reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; -reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; -reg litedramcore_ext_dfi_sel = 1'd0; -wire litedramcore_sel; -wire litedramcore_cke; -wire litedramcore_odt; -wire litedramcore_reset_n; -reg [3:0] litedramcore_storage = 4'd1; -reg litedramcore_re = 1'd0; -wire litedramcore_phaseinjector0_csrfield_cs; -wire litedramcore_phaseinjector0_csrfield_we; -wire litedramcore_phaseinjector0_csrfield_cas; -wire litedramcore_phaseinjector0_csrfield_ras; -wire litedramcore_phaseinjector0_csrfield_wren; -wire litedramcore_phaseinjector0_csrfield_rden; -reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; -reg litedramcore_phaseinjector0_command_re = 1'd0; -reg litedramcore_phaseinjector0_command_issue_re = 1'd0; -wire litedramcore_phaseinjector0_command_issue_r; -reg litedramcore_phaseinjector0_command_issue_we = 1'd0; -reg litedramcore_phaseinjector0_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; -reg litedramcore_phaseinjector0_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; -reg litedramcore_phaseinjector0_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector0_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; -wire litedramcore_phaseinjector0_rddata_we; -reg litedramcore_phaseinjector0_rddata_re = 1'd0; -wire litedramcore_phaseinjector1_csrfield_cs; -wire litedramcore_phaseinjector1_csrfield_we; -wire litedramcore_phaseinjector1_csrfield_cas; -wire litedramcore_phaseinjector1_csrfield_ras; -wire litedramcore_phaseinjector1_csrfield_wren; -wire litedramcore_phaseinjector1_csrfield_rden; -reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; -reg litedramcore_phaseinjector1_command_re = 1'd0; -reg litedramcore_phaseinjector1_command_issue_re = 1'd0; -wire litedramcore_phaseinjector1_command_issue_r; -reg litedramcore_phaseinjector1_command_issue_we = 1'd0; -reg litedramcore_phaseinjector1_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; -reg litedramcore_phaseinjector1_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; -reg litedramcore_phaseinjector1_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector1_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; -wire litedramcore_phaseinjector1_rddata_we; -reg litedramcore_phaseinjector1_rddata_re = 1'd0; -wire litedramcore_phaseinjector2_csrfield_cs; -wire litedramcore_phaseinjector2_csrfield_we; -wire litedramcore_phaseinjector2_csrfield_cas; -wire litedramcore_phaseinjector2_csrfield_ras; -wire litedramcore_phaseinjector2_csrfield_wren; -wire litedramcore_phaseinjector2_csrfield_rden; -reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; -reg litedramcore_phaseinjector2_command_re = 1'd0; -reg litedramcore_phaseinjector2_command_issue_re = 1'd0; -wire litedramcore_phaseinjector2_command_issue_r; -reg litedramcore_phaseinjector2_command_issue_we = 1'd0; -reg litedramcore_phaseinjector2_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; -reg litedramcore_phaseinjector2_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; -reg litedramcore_phaseinjector2_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector2_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; -wire litedramcore_phaseinjector2_rddata_we; -reg litedramcore_phaseinjector2_rddata_re = 1'd0; -wire litedramcore_phaseinjector3_csrfield_cs; -wire litedramcore_phaseinjector3_csrfield_we; -wire litedramcore_phaseinjector3_csrfield_cas; -wire litedramcore_phaseinjector3_csrfield_ras; -wire litedramcore_phaseinjector3_csrfield_wren; -wire litedramcore_phaseinjector3_csrfield_rden; -reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; -reg litedramcore_phaseinjector3_command_re = 1'd0; -reg litedramcore_phaseinjector3_command_issue_re = 1'd0; -wire litedramcore_phaseinjector3_command_issue_r; -reg litedramcore_phaseinjector3_command_issue_we = 1'd0; -reg litedramcore_phaseinjector3_command_issue_w = 1'd0; -reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; -reg litedramcore_phaseinjector3_address_re = 1'd0; -reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; -reg litedramcore_phaseinjector3_baddress_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; -reg litedramcore_phaseinjector3_wrdata_re = 1'd0; -reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; -wire litedramcore_phaseinjector3_rddata_we; -reg litedramcore_phaseinjector3_rddata_re = 1'd0; -wire litedramcore_interface_bank0_valid; -wire litedramcore_interface_bank0_ready; -wire litedramcore_interface_bank0_we; -wire [20:0] litedramcore_interface_bank0_addr; -wire litedramcore_interface_bank0_lock; -wire litedramcore_interface_bank0_wdata_ready; -wire litedramcore_interface_bank0_rdata_valid; -wire litedramcore_interface_bank1_valid; -wire litedramcore_interface_bank1_ready; -wire litedramcore_interface_bank1_we; -wire [20:0] litedramcore_interface_bank1_addr; -wire litedramcore_interface_bank1_lock; -wire litedramcore_interface_bank1_wdata_ready; -wire litedramcore_interface_bank1_rdata_valid; -wire litedramcore_interface_bank2_valid; -wire litedramcore_interface_bank2_ready; -wire litedramcore_interface_bank2_we; -wire [20:0] litedramcore_interface_bank2_addr; -wire litedramcore_interface_bank2_lock; -wire litedramcore_interface_bank2_wdata_ready; -wire litedramcore_interface_bank2_rdata_valid; -wire litedramcore_interface_bank3_valid; -wire litedramcore_interface_bank3_ready; -wire litedramcore_interface_bank3_we; -wire [20:0] litedramcore_interface_bank3_addr; -wire litedramcore_interface_bank3_lock; -wire litedramcore_interface_bank3_wdata_ready; -wire litedramcore_interface_bank3_rdata_valid; -wire litedramcore_interface_bank4_valid; -wire litedramcore_interface_bank4_ready; -wire litedramcore_interface_bank4_we; -wire [20:0] litedramcore_interface_bank4_addr; -wire litedramcore_interface_bank4_lock; -wire litedramcore_interface_bank4_wdata_ready; -wire litedramcore_interface_bank4_rdata_valid; -wire litedramcore_interface_bank5_valid; -wire litedramcore_interface_bank5_ready; -wire litedramcore_interface_bank5_we; -wire [20:0] litedramcore_interface_bank5_addr; -wire litedramcore_interface_bank5_lock; -wire litedramcore_interface_bank5_wdata_ready; -wire litedramcore_interface_bank5_rdata_valid; -wire litedramcore_interface_bank6_valid; -wire litedramcore_interface_bank6_ready; -wire litedramcore_interface_bank6_we; -wire [20:0] litedramcore_interface_bank6_addr; -wire litedramcore_interface_bank6_lock; -wire litedramcore_interface_bank6_wdata_ready; -wire litedramcore_interface_bank6_rdata_valid; -wire litedramcore_interface_bank7_valid; -wire litedramcore_interface_bank7_ready; -wire litedramcore_interface_bank7_we; -wire [20:0] litedramcore_interface_bank7_addr; -wire litedramcore_interface_bank7_lock; -wire litedramcore_interface_bank7_wdata_ready; -wire litedramcore_interface_bank7_rdata_valid; -reg [127:0] litedramcore_interface_wdata = 128'd0; -reg [15:0] litedramcore_interface_wdata_we = 16'd0; -wire [127:0] litedramcore_interface_rdata; -reg [13:0] litedramcore_dfi_p0_address = 14'd0; -reg [2:0] litedramcore_dfi_p0_bank = 3'd0; -reg litedramcore_dfi_p0_cas_n = 1'd1; -reg litedramcore_dfi_p0_cs_n = 1'd1; -reg litedramcore_dfi_p0_ras_n = 1'd1; -reg litedramcore_dfi_p0_we_n = 1'd1; -wire litedramcore_dfi_p0_cke; -wire litedramcore_dfi_p0_odt; -wire litedramcore_dfi_p0_reset_n; -reg litedramcore_dfi_p0_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p0_wrdata; -reg litedramcore_dfi_p0_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p0_wrdata_mask; -reg litedramcore_dfi_p0_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p0_rddata; -wire litedramcore_dfi_p0_rddata_valid; -reg [13:0] litedramcore_dfi_p1_address = 14'd0; -reg [2:0] litedramcore_dfi_p1_bank = 3'd0; -reg litedramcore_dfi_p1_cas_n = 1'd1; -reg litedramcore_dfi_p1_cs_n = 1'd1; -reg litedramcore_dfi_p1_ras_n = 1'd1; -reg litedramcore_dfi_p1_we_n = 1'd1; -wire litedramcore_dfi_p1_cke; -wire litedramcore_dfi_p1_odt; -wire litedramcore_dfi_p1_reset_n; -reg litedramcore_dfi_p1_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p1_wrdata; -reg litedramcore_dfi_p1_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p1_wrdata_mask; -reg litedramcore_dfi_p1_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p1_rddata; -wire litedramcore_dfi_p1_rddata_valid; -reg [13:0] litedramcore_dfi_p2_address = 14'd0; -reg [2:0] litedramcore_dfi_p2_bank = 3'd0; -reg litedramcore_dfi_p2_cas_n = 1'd1; -reg litedramcore_dfi_p2_cs_n = 1'd1; -reg litedramcore_dfi_p2_ras_n = 1'd1; -reg litedramcore_dfi_p2_we_n = 1'd1; -wire litedramcore_dfi_p2_cke; -wire litedramcore_dfi_p2_odt; -wire litedramcore_dfi_p2_reset_n; -reg litedramcore_dfi_p2_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p2_wrdata; -reg litedramcore_dfi_p2_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p2_wrdata_mask; -reg litedramcore_dfi_p2_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p2_rddata; -wire litedramcore_dfi_p2_rddata_valid; -reg [13:0] litedramcore_dfi_p3_address = 14'd0; -reg [2:0] litedramcore_dfi_p3_bank = 3'd0; -reg litedramcore_dfi_p3_cas_n = 1'd1; -reg litedramcore_dfi_p3_cs_n = 1'd1; -reg litedramcore_dfi_p3_ras_n = 1'd1; -reg litedramcore_dfi_p3_we_n = 1'd1; -wire litedramcore_dfi_p3_cke; -wire litedramcore_dfi_p3_odt; -wire litedramcore_dfi_p3_reset_n; -reg litedramcore_dfi_p3_act_n = 1'd1; -wire [31:0] litedramcore_dfi_p3_wrdata; -reg litedramcore_dfi_p3_wrdata_en = 1'd0; -wire [3:0] litedramcore_dfi_p3_wrdata_mask; -reg litedramcore_dfi_p3_rddata_en = 1'd0; -wire [31:0] litedramcore_dfi_p3_rddata; -wire litedramcore_dfi_p3_rddata_valid; -reg litedramcore_cmd_valid = 1'd0; -reg litedramcore_cmd_ready = 1'd0; -reg litedramcore_cmd_last = 1'd0; -reg [13:0] litedramcore_cmd_payload_a = 14'd0; -reg [2:0] litedramcore_cmd_payload_ba = 3'd0; -reg litedramcore_cmd_payload_cas = 1'd0; -reg litedramcore_cmd_payload_ras = 1'd0; -reg litedramcore_cmd_payload_we = 1'd0; -reg litedramcore_cmd_payload_is_read = 1'd0; -reg litedramcore_cmd_payload_is_write = 1'd0; -wire litedramcore_wants_refresh; -wire litedramcore_wants_zqcs; -wire litedramcore_timer_wait; -wire litedramcore_timer_done0; -wire [9:0] litedramcore_timer_count0; -wire litedramcore_timer_done1; -reg [9:0] litedramcore_timer_count1 = 10'd781; -wire litedramcore_postponer_req_i; -reg litedramcore_postponer_req_o = 1'd0; -reg litedramcore_postponer_count = 1'd0; -reg litedramcore_sequencer_start0 = 1'd0; -wire litedramcore_sequencer_done0; -wire litedramcore_sequencer_start1; -reg litedramcore_sequencer_done1 = 1'd0; -reg [5:0] litedramcore_sequencer_counter = 6'd0; -reg litedramcore_sequencer_count = 1'd0; -wire litedramcore_zqcs_timer_wait; -wire litedramcore_zqcs_timer_done0; -wire [26:0] litedramcore_zqcs_timer_count0; -wire litedramcore_zqcs_timer_done1; -reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; -reg litedramcore_zqcs_executer_start = 1'd0; -reg litedramcore_zqcs_executer_done = 1'd0; -reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; -wire litedramcore_bankmachine0_req_valid; -wire litedramcore_bankmachine0_req_ready; -wire litedramcore_bankmachine0_req_we; -wire [20:0] litedramcore_bankmachine0_req_addr; -wire litedramcore_bankmachine0_req_lock; -reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine0_refresh_req; -reg litedramcore_bankmachine0_refresh_gnt = 1'd0; -reg litedramcore_bankmachine0_cmd_valid = 1'd0; -reg litedramcore_bankmachine0_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; -reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine0_auto_precharge = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_valid; -wire litedramcore_bankmachine0_cmd_buffer_sink_ready; -wire litedramcore_bankmachine0_cmd_buffer_sink_first; -wire litedramcore_bankmachine0_cmd_buffer_sink_last; -wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine0_cmd_buffer_source_ready; -reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine0_row = 14'd0; -reg litedramcore_bankmachine0_row_opened = 1'd0; -wire litedramcore_bankmachine0_row_hit; -reg litedramcore_bankmachine0_row_open = 1'd0; -reg litedramcore_bankmachine0_row_close = 1'd0; -reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine0_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; -wire litedramcore_bankmachine0_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; -wire litedramcore_bankmachine0_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; -wire litedramcore_bankmachine1_req_valid; -wire litedramcore_bankmachine1_req_ready; -wire litedramcore_bankmachine1_req_we; -wire [20:0] litedramcore_bankmachine1_req_addr; -wire litedramcore_bankmachine1_req_lock; -reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine1_refresh_req; -reg litedramcore_bankmachine1_refresh_gnt = 1'd0; -reg litedramcore_bankmachine1_cmd_valid = 1'd0; -reg litedramcore_bankmachine1_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; -reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine1_auto_precharge = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_valid; -wire litedramcore_bankmachine1_cmd_buffer_sink_ready; -wire litedramcore_bankmachine1_cmd_buffer_sink_first; -wire litedramcore_bankmachine1_cmd_buffer_sink_last; -wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine1_cmd_buffer_source_ready; -reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine1_row = 14'd0; -reg litedramcore_bankmachine1_row_opened = 1'd0; -wire litedramcore_bankmachine1_row_hit; -reg litedramcore_bankmachine1_row_open = 1'd0; -reg litedramcore_bankmachine1_row_close = 1'd0; -reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine1_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; -wire litedramcore_bankmachine1_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; -wire litedramcore_bankmachine1_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; -wire litedramcore_bankmachine2_req_valid; -wire litedramcore_bankmachine2_req_ready; -wire litedramcore_bankmachine2_req_we; -wire [20:0] litedramcore_bankmachine2_req_addr; -wire litedramcore_bankmachine2_req_lock; -reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine2_refresh_req; -reg litedramcore_bankmachine2_refresh_gnt = 1'd0; -reg litedramcore_bankmachine2_cmd_valid = 1'd0; -reg litedramcore_bankmachine2_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; -reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine2_auto_precharge = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_valid; -wire litedramcore_bankmachine2_cmd_buffer_sink_ready; -wire litedramcore_bankmachine2_cmd_buffer_sink_first; -wire litedramcore_bankmachine2_cmd_buffer_sink_last; -wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine2_cmd_buffer_source_ready; -reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine2_row = 14'd0; -reg litedramcore_bankmachine2_row_opened = 1'd0; -wire litedramcore_bankmachine2_row_hit; -reg litedramcore_bankmachine2_row_open = 1'd0; -reg litedramcore_bankmachine2_row_close = 1'd0; -reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine2_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; -wire litedramcore_bankmachine2_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; -wire litedramcore_bankmachine2_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; -wire litedramcore_bankmachine3_req_valid; -wire litedramcore_bankmachine3_req_ready; -wire litedramcore_bankmachine3_req_we; -wire [20:0] litedramcore_bankmachine3_req_addr; -wire litedramcore_bankmachine3_req_lock; -reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine3_refresh_req; -reg litedramcore_bankmachine3_refresh_gnt = 1'd0; -reg litedramcore_bankmachine3_cmd_valid = 1'd0; -reg litedramcore_bankmachine3_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; -reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine3_auto_precharge = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_valid; -wire litedramcore_bankmachine3_cmd_buffer_sink_ready; -wire litedramcore_bankmachine3_cmd_buffer_sink_first; -wire litedramcore_bankmachine3_cmd_buffer_sink_last; -wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine3_cmd_buffer_source_ready; -reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine3_row = 14'd0; -reg litedramcore_bankmachine3_row_opened = 1'd0; -wire litedramcore_bankmachine3_row_hit; -reg litedramcore_bankmachine3_row_open = 1'd0; -reg litedramcore_bankmachine3_row_close = 1'd0; -reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine3_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; -wire litedramcore_bankmachine3_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; -wire litedramcore_bankmachine3_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; -wire litedramcore_bankmachine4_req_valid; -wire litedramcore_bankmachine4_req_ready; -wire litedramcore_bankmachine4_req_we; -wire [20:0] litedramcore_bankmachine4_req_addr; -wire litedramcore_bankmachine4_req_lock; -reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine4_refresh_req; -reg litedramcore_bankmachine4_refresh_gnt = 1'd0; -reg litedramcore_bankmachine4_cmd_valid = 1'd0; -reg litedramcore_bankmachine4_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; -reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine4_auto_precharge = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_valid; -wire litedramcore_bankmachine4_cmd_buffer_sink_ready; -wire litedramcore_bankmachine4_cmd_buffer_sink_first; -wire litedramcore_bankmachine4_cmd_buffer_sink_last; -wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine4_cmd_buffer_source_ready; -reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine4_row = 14'd0; -reg litedramcore_bankmachine4_row_opened = 1'd0; -wire litedramcore_bankmachine4_row_hit; -reg litedramcore_bankmachine4_row_open = 1'd0; -reg litedramcore_bankmachine4_row_close = 1'd0; -reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine4_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; -wire litedramcore_bankmachine4_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; -wire litedramcore_bankmachine4_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; -wire litedramcore_bankmachine5_req_valid; -wire litedramcore_bankmachine5_req_ready; -wire litedramcore_bankmachine5_req_we; -wire [20:0] litedramcore_bankmachine5_req_addr; -wire litedramcore_bankmachine5_req_lock; -reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine5_refresh_req; -reg litedramcore_bankmachine5_refresh_gnt = 1'd0; -reg litedramcore_bankmachine5_cmd_valid = 1'd0; -reg litedramcore_bankmachine5_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; -reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine5_auto_precharge = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_valid; -wire litedramcore_bankmachine5_cmd_buffer_sink_ready; -wire litedramcore_bankmachine5_cmd_buffer_sink_first; -wire litedramcore_bankmachine5_cmd_buffer_sink_last; -wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine5_cmd_buffer_source_ready; -reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine5_row = 14'd0; -reg litedramcore_bankmachine5_row_opened = 1'd0; -wire litedramcore_bankmachine5_row_hit; -reg litedramcore_bankmachine5_row_open = 1'd0; -reg litedramcore_bankmachine5_row_close = 1'd0; -reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine5_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; -wire litedramcore_bankmachine5_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; -wire litedramcore_bankmachine5_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; -wire litedramcore_bankmachine6_req_valid; -wire litedramcore_bankmachine6_req_ready; -wire litedramcore_bankmachine6_req_we; -wire [20:0] litedramcore_bankmachine6_req_addr; -wire litedramcore_bankmachine6_req_lock; -reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine6_refresh_req; -reg litedramcore_bankmachine6_refresh_gnt = 1'd0; -reg litedramcore_bankmachine6_cmd_valid = 1'd0; -reg litedramcore_bankmachine6_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; -reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine6_auto_precharge = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_valid; -wire litedramcore_bankmachine6_cmd_buffer_sink_ready; -wire litedramcore_bankmachine6_cmd_buffer_sink_first; -wire litedramcore_bankmachine6_cmd_buffer_sink_last; -wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine6_cmd_buffer_source_ready; -reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine6_row = 14'd0; -reg litedramcore_bankmachine6_row_opened = 1'd0; -wire litedramcore_bankmachine6_row_hit; -reg litedramcore_bankmachine6_row_open = 1'd0; -reg litedramcore_bankmachine6_row_close = 1'd0; -reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine6_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; -wire litedramcore_bankmachine6_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; -wire litedramcore_bankmachine6_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; -wire litedramcore_bankmachine7_req_valid; -wire litedramcore_bankmachine7_req_ready; -wire litedramcore_bankmachine7_req_we; -wire [20:0] litedramcore_bankmachine7_req_addr; -wire litedramcore_bankmachine7_req_lock; -reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; -reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; -wire litedramcore_bankmachine7_refresh_req; -reg litedramcore_bankmachine7_refresh_gnt = 1'd0; -reg litedramcore_bankmachine7_cmd_valid = 1'd0; -reg litedramcore_bankmachine7_cmd_ready = 1'd0; -reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; -wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; -reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; -reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; -reg litedramcore_bankmachine7_auto_precharge = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; -reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; -reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; -wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; -wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_valid; -wire litedramcore_bankmachine7_cmd_buffer_sink_ready; -wire litedramcore_bankmachine7_cmd_buffer_sink_first; -wire litedramcore_bankmachine7_cmd_buffer_sink_last; -wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; -wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; -reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; -wire litedramcore_bankmachine7_cmd_buffer_source_ready; -reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; -reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; -reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; -reg [13:0] litedramcore_bankmachine7_row = 14'd0; -reg litedramcore_bankmachine7_row_opened = 1'd0; -wire litedramcore_bankmachine7_row_hit; -reg litedramcore_bankmachine7_row_open = 1'd0; -reg litedramcore_bankmachine7_row_close = 1'd0; -reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; -wire litedramcore_bankmachine7_twtpcon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; -wire litedramcore_bankmachine7_trccon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; -wire litedramcore_bankmachine7_trascon_valid; -(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; -reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; -wire litedramcore_ras_allowed; -wire litedramcore_cas_allowed; -wire [1:0] litedramcore_rdcmdphase; -wire [1:0] litedramcore_wrcmdphase; -reg litedramcore_choose_cmd_want_reads = 1'd0; -reg litedramcore_choose_cmd_want_writes = 1'd0; -reg litedramcore_choose_cmd_want_cmds = 1'd0; -reg litedramcore_choose_cmd_want_activates = 1'd0; -wire litedramcore_choose_cmd_cmd_valid; -reg litedramcore_choose_cmd_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_cmd_cmd_payload_a; -wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; -reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; -reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; -wire litedramcore_choose_cmd_cmd_payload_is_cmd; -wire litedramcore_choose_cmd_cmd_payload_is_read; -wire litedramcore_choose_cmd_cmd_payload_is_write; -reg [7:0] litedramcore_choose_cmd_valids = 8'd0; -wire [7:0] litedramcore_choose_cmd_request; -reg [2:0] litedramcore_choose_cmd_grant = 3'd0; -wire litedramcore_choose_cmd_ce; -reg litedramcore_choose_req_want_reads = 1'd0; -reg litedramcore_choose_req_want_writes = 1'd0; -reg litedramcore_choose_req_want_cmds = 1'd0; -reg litedramcore_choose_req_want_activates = 1'd0; -wire litedramcore_choose_req_cmd_valid; -reg litedramcore_choose_req_cmd_ready = 1'd0; -wire [13:0] litedramcore_choose_req_cmd_payload_a; -wire [2:0] litedramcore_choose_req_cmd_payload_ba; -reg litedramcore_choose_req_cmd_payload_cas = 1'd0; -reg litedramcore_choose_req_cmd_payload_ras = 1'd0; -reg litedramcore_choose_req_cmd_payload_we = 1'd0; -wire litedramcore_choose_req_cmd_payload_is_cmd; -wire litedramcore_choose_req_cmd_payload_is_read; -wire litedramcore_choose_req_cmd_payload_is_write; -reg [7:0] litedramcore_choose_req_valids = 8'd0; -wire [7:0] litedramcore_choose_req_request; -reg [2:0] litedramcore_choose_req_grant = 3'd0; -wire litedramcore_choose_req_ce; -reg [13:0] litedramcore_nop_a = 14'd0; -reg [2:0] litedramcore_nop_ba = 3'd0; -reg [1:0] litedramcore_steerer_sel0 = 2'd0; -reg [1:0] litedramcore_steerer_sel1 = 2'd0; -reg [1:0] litedramcore_steerer_sel2 = 2'd0; -reg [1:0] litedramcore_steerer_sel3 = 2'd0; -reg litedramcore_steerer0 = 1'd1; -reg litedramcore_steerer1 = 1'd1; -reg litedramcore_steerer2 = 1'd1; -reg litedramcore_steerer3 = 1'd1; -reg litedramcore_steerer4 = 1'd1; -reg litedramcore_steerer5 = 1'd1; -reg litedramcore_steerer6 = 1'd1; -reg litedramcore_steerer7 = 1'd1; -wire litedramcore_trrdcon_valid; -(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0; -reg litedramcore_trrdcon_count = 1'd0; -wire litedramcore_tfawcon_valid; -(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1; -wire [2:0] litedramcore_tfawcon_count; -reg [4:0] litedramcore_tfawcon_window = 5'd0; -wire litedramcore_tccdcon_valid; -(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0; -reg litedramcore_tccdcon_count = 1'd0; -wire litedramcore_twtrcon_valid; -(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0; -reg [2:0] litedramcore_twtrcon_count = 3'd0; -wire litedramcore_read_available; -wire litedramcore_write_available; -reg litedramcore_en0 = 1'd0; -wire litedramcore_max_time0; -reg [4:0] litedramcore_time0 = 5'd0; -reg litedramcore_en1 = 1'd0; -wire litedramcore_max_time1; -reg [3:0] litedramcore_time1 = 4'd0; -wire litedramcore_go_to_refresh; -reg init_done_storage = 1'd0; -reg init_done_re = 1'd0; -reg init_error_storage = 1'd0; -reg init_error_re = 1'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -wire user_enable; -wire user_port_cmd_valid; -wire user_port_cmd_ready; -wire user_port_cmd_payload_we; -wire [23:0] user_port_cmd_payload_addr; -wire user_port_wdata_valid; -wire user_port_wdata_ready; -wire [127:0] user_port_wdata_payload_data; -wire [15:0] user_port_wdata_payload_we; -wire user_port_rdata_valid; -wire user_port_rdata_ready; -wire [127:0] user_port_rdata_payload_data; -reg [13:0] litedramcore_adr = 14'd0; -reg litedramcore_we = 1'd0; -reg [31:0] litedramcore_dat_w = 32'd0; -wire [31:0] litedramcore_dat_r; -wire [29:0] litedramcore_wishbone_adr; -wire [31:0] litedramcore_wishbone_dat_w; -reg [31:0] litedramcore_wishbone_dat_r = 32'd0; -wire [3:0] litedramcore_wishbone_sel; -wire litedramcore_wishbone_cyc; -wire litedramcore_wishbone_stb; -reg litedramcore_wishbone_ack = 1'd0; -wire litedramcore_wishbone_we; -wire [2:0] litedramcore_wishbone_cti; -wire [1:0] litedramcore_wishbone_bte; -reg litedramcore_wishbone_err = 1'd0; -wire [13:0] interface0_bank_bus_adr; -wire interface0_bank_bus_we; -wire [31:0] interface0_bank_bus_dat_w; -reg [31:0] interface0_bank_bus_dat_r = 32'd0; -reg csrbank0_init_done0_re = 1'd0; -wire csrbank0_init_done0_r; -reg csrbank0_init_done0_we = 1'd0; -wire csrbank0_init_done0_w; -reg csrbank0_init_error0_re = 1'd0; -wire csrbank0_init_error0_r; -reg csrbank0_init_error0_we = 1'd0; -wire csrbank0_init_error0_w; -wire csrbank0_sel; -wire [13:0] interface1_bank_bus_adr; -wire interface1_bank_bus_we; -wire [31:0] interface1_bank_bus_dat_w; -reg [31:0] interface1_bank_bus_dat_r = 32'd0; -reg csrbank1_rst0_re = 1'd0; -wire csrbank1_rst0_r; -reg csrbank1_rst0_we = 1'd0; -wire csrbank1_rst0_w; -reg csrbank1_dly_sel0_re = 1'd0; -wire [1:0] csrbank1_dly_sel0_r; -reg csrbank1_dly_sel0_we = 1'd0; -wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_half_sys8x_taps0_re = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_r; -reg csrbank1_half_sys8x_taps0_we = 1'd0; -wire [4:0] csrbank1_half_sys8x_taps0_w; -reg csrbank1_wlevel_en0_re = 1'd0; -wire csrbank1_wlevel_en0_r; -reg csrbank1_wlevel_en0_we = 1'd0; -wire csrbank1_wlevel_en0_w; -reg csrbank1_rdphase0_re = 1'd0; -wire [1:0] csrbank1_rdphase0_r; -reg csrbank1_rdphase0_we = 1'd0; -wire [1:0] csrbank1_rdphase0_w; -reg csrbank1_wrphase0_re = 1'd0; -wire [1:0] csrbank1_wrphase0_r; -reg csrbank1_wrphase0_we = 1'd0; -wire [1:0] csrbank1_wrphase0_w; -wire csrbank1_sel; -wire [13:0] interface2_bank_bus_adr; -wire interface2_bank_bus_we; -wire [31:0] interface2_bank_bus_dat_w; -reg [31:0] interface2_bank_bus_dat_r = 32'd0; -reg csrbank2_dfii_control0_re = 1'd0; -wire [3:0] csrbank2_dfii_control0_r; -reg csrbank2_dfii_control0_we = 1'd0; -wire [3:0] csrbank2_dfii_control0_w; -reg csrbank2_dfii_pi0_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_r; -reg csrbank2_dfii_pi0_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi0_command0_w; -reg csrbank2_dfii_pi0_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_r; -reg csrbank2_dfii_pi0_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi0_address0_w; -reg csrbank2_dfii_pi0_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_r; -reg csrbank2_dfii_pi0_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi0_baddress0_w; -reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_r; -reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_wrdata0_w; -reg csrbank2_dfii_pi0_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_r; -reg csrbank2_dfii_pi0_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi0_rddata_w; -reg csrbank2_dfii_pi1_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_r; -reg csrbank2_dfii_pi1_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi1_command0_w; -reg csrbank2_dfii_pi1_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_r; -reg csrbank2_dfii_pi1_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi1_address0_w; -reg csrbank2_dfii_pi1_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_r; -reg csrbank2_dfii_pi1_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi1_baddress0_w; -reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_r; -reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_wrdata0_w; -reg csrbank2_dfii_pi1_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_r; -reg csrbank2_dfii_pi1_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi1_rddata_w; -reg csrbank2_dfii_pi2_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_r; -reg csrbank2_dfii_pi2_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi2_command0_w; -reg csrbank2_dfii_pi2_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_r; -reg csrbank2_dfii_pi2_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi2_address0_w; -reg csrbank2_dfii_pi2_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_r; -reg csrbank2_dfii_pi2_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi2_baddress0_w; -reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_r; -reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_wrdata0_w; -reg csrbank2_dfii_pi2_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_r; -reg csrbank2_dfii_pi2_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi2_rddata_w; -reg csrbank2_dfii_pi3_command0_re = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_r; -reg csrbank2_dfii_pi3_command0_we = 1'd0; -wire [5:0] csrbank2_dfii_pi3_command0_w; -reg csrbank2_dfii_pi3_address0_re = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_r; -reg csrbank2_dfii_pi3_address0_we = 1'd0; -wire [13:0] csrbank2_dfii_pi3_address0_w; -reg csrbank2_dfii_pi3_baddress0_re = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_r; -reg csrbank2_dfii_pi3_baddress0_we = 1'd0; -wire [2:0] csrbank2_dfii_pi3_baddress0_w; -reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_r; -reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_wrdata0_w; -reg csrbank2_dfii_pi3_rddata_re = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_r; -reg csrbank2_dfii_pi3_rddata_we = 1'd0; -wire [31:0] csrbank2_dfii_pi3_rddata_w; -wire csrbank2_sel; -wire [13:0] csr_interconnect_adr; -wire csr_interconnect_we; -wire [31:0] csr_interconnect_dat_w; -wire [31:0] csr_interconnect_dat_r; -wire litedramcore_reset0; -wire litedramcore_reset1; -wire litedramcore_reset2; -wire litedramcore_reset3; -wire litedramcore_reset4; -wire litedramcore_reset5; -wire litedramcore_reset6; -wire litedramcore_reset7; -wire litedramcore_pll_fb; -reg [1:0] litedramcore_refresher_state = 2'd0; -reg [1:0] litedramcore_refresher_next_state = 2'd0; -reg [3:0] litedramcore_bankmachine0_state = 4'd0; -reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_state = 4'd0; -reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_state = 4'd0; -reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_state = 4'd0; -reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_state = 4'd0; -reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_state = 4'd0; -reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_state = 4'd0; -reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_state = 4'd0; -reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; -reg [3:0] litedramcore_multiplexer_state = 4'd0; -reg [3:0] litedramcore_multiplexer_next_state = 4'd0; -wire litedramcore_roundrobin0_request; -wire litedramcore_roundrobin0_grant; -wire litedramcore_roundrobin0_ce; -wire litedramcore_roundrobin1_request; -wire litedramcore_roundrobin1_grant; -wire litedramcore_roundrobin1_ce; -wire litedramcore_roundrobin2_request; -wire litedramcore_roundrobin2_grant; -wire litedramcore_roundrobin2_ce; -wire litedramcore_roundrobin3_request; -wire litedramcore_roundrobin3_grant; -wire litedramcore_roundrobin3_ce; -wire litedramcore_roundrobin4_request; -wire litedramcore_roundrobin4_grant; -wire litedramcore_roundrobin4_ce; -wire litedramcore_roundrobin5_request; -wire litedramcore_roundrobin5_grant; -wire litedramcore_roundrobin5_ce; -wire litedramcore_roundrobin6_request; -wire litedramcore_roundrobin6_grant; -wire litedramcore_roundrobin6_ce; -wire litedramcore_roundrobin7_request; -wire litedramcore_roundrobin7_grant; -wire litedramcore_roundrobin7_ce; -reg litedramcore_locked0 = 1'd0; -reg litedramcore_locked1 = 1'd0; -reg litedramcore_locked2 = 1'd0; -reg litedramcore_locked3 = 1'd0; -reg litedramcore_locked4 = 1'd0; -reg litedramcore_locked5 = 1'd0; -reg litedramcore_locked6 = 1'd0; -reg litedramcore_locked7 = 1'd0; -reg litedramcore_new_master_wdata_ready0 = 1'd0; -reg litedramcore_new_master_wdata_ready1 = 1'd0; -reg litedramcore_new_master_rdata_valid0 = 1'd0; -reg litedramcore_new_master_rdata_valid1 = 1'd0; -reg litedramcore_new_master_rdata_valid2 = 1'd0; -reg litedramcore_new_master_rdata_valid3 = 1'd0; -reg litedramcore_new_master_rdata_valid4 = 1'd0; -reg litedramcore_new_master_rdata_valid5 = 1'd0; -reg litedramcore_new_master_rdata_valid6 = 1'd0; -reg litedramcore_new_master_rdata_valid7 = 1'd0; -reg litedramcore_new_master_rdata_valid8 = 1'd0; -reg [1:0] litedramcore_state = 2'd0; -reg [1:0] litedramcore_next_state = 2'd0; -reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; -reg litedramcore_dat_w_next_value_ce0 = 1'd0; -reg [13:0] litedramcore_adr_next_value1 = 14'd0; -reg litedramcore_adr_next_value_ce1 = 1'd0; -reg litedramcore_we_next_value2 = 1'd0; -reg litedramcore_we_next_value_ce2 = 1'd0; -reg rhs_array_muxed0 = 1'd0; -reg [13:0] rhs_array_muxed1 = 14'd0; -reg [2:0] rhs_array_muxed2 = 3'd0; -reg rhs_array_muxed3 = 1'd0; -reg rhs_array_muxed4 = 1'd0; -reg rhs_array_muxed5 = 1'd0; -reg t_array_muxed0 = 1'd0; -reg t_array_muxed1 = 1'd0; -reg t_array_muxed2 = 1'd0; -reg rhs_array_muxed6 = 1'd0; -reg [13:0] rhs_array_muxed7 = 14'd0; -reg [2:0] rhs_array_muxed8 = 3'd0; -reg rhs_array_muxed9 = 1'd0; -reg rhs_array_muxed10 = 1'd0; -reg rhs_array_muxed11 = 1'd0; -reg t_array_muxed3 = 1'd0; -reg t_array_muxed4 = 1'd0; -reg t_array_muxed5 = 1'd0; -reg [20:0] rhs_array_muxed12 = 21'd0; -reg rhs_array_muxed13 = 1'd0; -reg rhs_array_muxed14 = 1'd0; -reg [20:0] rhs_array_muxed15 = 21'd0; -reg rhs_array_muxed16 = 1'd0; -reg rhs_array_muxed17 = 1'd0; -reg [20:0] rhs_array_muxed18 = 21'd0; -reg rhs_array_muxed19 = 1'd0; -reg rhs_array_muxed20 = 1'd0; -reg [20:0] rhs_array_muxed21 = 21'd0; -reg rhs_array_muxed22 = 1'd0; -reg rhs_array_muxed23 = 1'd0; -reg [20:0] rhs_array_muxed24 = 21'd0; -reg rhs_array_muxed25 = 1'd0; -reg rhs_array_muxed26 = 1'd0; -reg [20:0] rhs_array_muxed27 = 21'd0; -reg rhs_array_muxed28 = 1'd0; -reg rhs_array_muxed29 = 1'd0; -reg [20:0] rhs_array_muxed30 = 21'd0; -reg rhs_array_muxed31 = 1'd0; -reg rhs_array_muxed32 = 1'd0; -reg [20:0] rhs_array_muxed33 = 21'd0; -reg rhs_array_muxed34 = 1'd0; -reg rhs_array_muxed35 = 1'd0; -reg [2:0] array_muxed0 = 3'd0; -reg [13:0] array_muxed1 = 14'd0; -reg array_muxed2 = 1'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg array_muxed6 = 1'd0; -reg [2:0] array_muxed7 = 3'd0; -reg [13:0] array_muxed8 = 14'd0; -reg array_muxed9 = 1'd0; -reg array_muxed10 = 1'd0; -reg array_muxed11 = 1'd0; -reg array_muxed12 = 1'd0; -reg array_muxed13 = 1'd0; -reg [2:0] array_muxed14 = 3'd0; -reg [13:0] array_muxed15 = 14'd0; -reg array_muxed16 = 1'd0; -reg array_muxed17 = 1'd0; -reg array_muxed18 = 1'd0; -reg array_muxed19 = 1'd0; -reg array_muxed20 = 1'd0; -reg [2:0] array_muxed21 = 3'd0; -reg [13:0] array_muxed22 = 14'd0; -reg array_muxed23 = 1'd0; -reg array_muxed24 = 1'd0; -reg array_muxed25 = 1'd0; -reg array_muxed26 = 1'd0; -reg array_muxed27 = 1'd0; -wire xilinxasyncresetsynchronizerimpl0; -wire xilinxasyncresetsynchronizerimpl0_rst_meta; -wire xilinxasyncresetsynchronizerimpl1; -wire xilinxasyncresetsynchronizerimpl1_rst_meta; -wire xilinxasyncresetsynchronizerimpl2; -wire xilinxasyncresetsynchronizerimpl2_rst_meta; -wire xilinxasyncresetsynchronizerimpl2_expr; -wire xilinxasyncresetsynchronizerimpl3; -wire xilinxasyncresetsynchronizerimpl3_rst_meta; -wire xilinxasyncresetsynchronizerimpl3_expr; +reg rst_1 = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire iodelay_clk; +wire iodelay_rst; +wire reset; +reg power_down = 1'd0; +wire locked; +wire clkin; +wire clkout0; +wire clkout_buf0; +wire clkout1; +wire clkout_buf1; +wire clkout2; +wire clkout_buf2; +wire clkout3; +wire clkout_buf3; +reg [3:0] reset_counter = 4'd15; +reg ic_reset = 1'd1; +reg a7ddrphy_rst_storage = 1'd0; +reg a7ddrphy_rst_re = 1'd0; +reg [1:0] a7ddrphy_dly_sel_storage = 2'd0; +reg a7ddrphy_dly_sel_re = 1'd0; +reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8; +reg a7ddrphy_half_sys8x_taps_re = 1'd0; +reg a7ddrphy_wlevel_en_storage = 1'd0; +reg a7ddrphy_wlevel_en_re = 1'd0; +reg a7ddrphy_wlevel_strobe_re = 1'd0; +wire a7ddrphy_wlevel_strobe_r; +reg a7ddrphy_wlevel_strobe_we = 1'd0; +reg a7ddrphy_wlevel_strobe_w = 1'd0; +reg a7ddrphy_rdly_dq_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_rst_r; +reg a7ddrphy_rdly_dq_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_inc_re = 1'd0; +wire a7ddrphy_rdly_dq_inc_r; +reg a7ddrphy_rdly_dq_inc_we = 1'd0; +reg a7ddrphy_rdly_dq_inc_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_rst_r; +reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_rdly_dq_bitslip_r; +reg a7ddrphy_rdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_rdly_dq_bitslip_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_rst_r; +reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_re = 1'd0; +wire a7ddrphy_wdly_dq_bitslip_r; +reg a7ddrphy_wdly_dq_bitslip_we = 1'd0; +reg a7ddrphy_wdly_dq_bitslip_w = 1'd0; +reg [1:0] a7ddrphy_rdphase_storage = 2'd2; +reg a7ddrphy_rdphase_re = 1'd0; +reg [1:0] a7ddrphy_wrphase_storage = 2'd3; +reg a7ddrphy_wrphase_re = 1'd0; +wire [13:0] a7ddrphy_dfi_p0_address; +wire [2:0] a7ddrphy_dfi_p0_bank; +wire a7ddrphy_dfi_p0_cas_n; +wire a7ddrphy_dfi_p0_cs_n; +wire a7ddrphy_dfi_p0_ras_n; +wire a7ddrphy_dfi_p0_we_n; +wire a7ddrphy_dfi_p0_cke; +wire a7ddrphy_dfi_p0_odt; +wire a7ddrphy_dfi_p0_reset_n; +wire a7ddrphy_dfi_p0_act_n; +wire [31:0] a7ddrphy_dfi_p0_wrdata; +wire a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] a7ddrphy_dfi_p0_wrdata_mask; +wire a7ddrphy_dfi_p0_rddata_en; +reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0; +wire a7ddrphy_dfi_p0_rddata_valid; +wire [13:0] a7ddrphy_dfi_p1_address; +wire [2:0] a7ddrphy_dfi_p1_bank; +wire a7ddrphy_dfi_p1_cas_n; +wire a7ddrphy_dfi_p1_cs_n; +wire a7ddrphy_dfi_p1_ras_n; +wire a7ddrphy_dfi_p1_we_n; +wire a7ddrphy_dfi_p1_cke; +wire a7ddrphy_dfi_p1_odt; +wire a7ddrphy_dfi_p1_reset_n; +wire a7ddrphy_dfi_p1_act_n; +wire [31:0] a7ddrphy_dfi_p1_wrdata; +wire a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] a7ddrphy_dfi_p1_wrdata_mask; +wire a7ddrphy_dfi_p1_rddata_en; +reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0; +wire a7ddrphy_dfi_p1_rddata_valid; +wire [13:0] a7ddrphy_dfi_p2_address; +wire [2:0] a7ddrphy_dfi_p2_bank; +wire a7ddrphy_dfi_p2_cas_n; +wire a7ddrphy_dfi_p2_cs_n; +wire a7ddrphy_dfi_p2_ras_n; +wire a7ddrphy_dfi_p2_we_n; +wire a7ddrphy_dfi_p2_cke; +wire a7ddrphy_dfi_p2_odt; +wire a7ddrphy_dfi_p2_reset_n; +wire a7ddrphy_dfi_p2_act_n; +wire [31:0] a7ddrphy_dfi_p2_wrdata; +wire a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] a7ddrphy_dfi_p2_wrdata_mask; +wire a7ddrphy_dfi_p2_rddata_en; +reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0; +wire a7ddrphy_dfi_p2_rddata_valid; +wire [13:0] a7ddrphy_dfi_p3_address; +wire [2:0] a7ddrphy_dfi_p3_bank; +wire a7ddrphy_dfi_p3_cas_n; +wire a7ddrphy_dfi_p3_cs_n; +wire a7ddrphy_dfi_p3_ras_n; +wire a7ddrphy_dfi_p3_we_n; +wire a7ddrphy_dfi_p3_cke; +wire a7ddrphy_dfi_p3_odt; +wire a7ddrphy_dfi_p3_reset_n; +wire a7ddrphy_dfi_p3_act_n; +wire [31:0] a7ddrphy_dfi_p3_wrdata; +wire a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] a7ddrphy_dfi_p3_wrdata_mask; +wire a7ddrphy_dfi_p3_rddata_en; +reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0; +wire a7ddrphy_dfi_p3_rddata_valid; +wire a7ddrphy_sd_clk_se_nodelay; +wire [2:0] a7ddrphy_pads_ba; +reg a7ddrphy_dqs_oe = 1'd0; +wire a7ddrphy_dqs_preamble; +wire a7ddrphy_dqs_postamble; +wire a7ddrphy_dqs_oe_delay_tappeddelayline; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +reg a7ddrphy_dqspattern0 = 1'd0; +reg a7ddrphy_dqspattern1 = 1'd0; +reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0; +reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0; +wire a7ddrphy_dqs_o_no_delay0; +wire a7ddrphy_dqs_t0; +reg [7:0] a7ddrphy_bitslip00 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0; +wire a7ddrphy0; +wire a7ddrphy_dqs_o_no_delay1; +wire a7ddrphy_dqs_t1; +reg [7:0] a7ddrphy_bitslip10 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0; +wire a7ddrphy1; +reg [7:0] a7ddrphy_bitslip01 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0; +reg [7:0] a7ddrphy_bitslip11 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0; +wire a7ddrphy_dq_oe; +wire a7ddrphy_dq_oe_delay_tappeddelayline; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0; +reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0; +wire a7ddrphy_dq_o_nodelay0; +wire a7ddrphy_dq_i_nodelay0; +wire a7ddrphy_dq_i_delayed0; +wire a7ddrphy_dq_t0; +reg [7:0] a7ddrphy_bitslip02 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip03; +reg [7:0] a7ddrphy_bitslip04 = 8'd0; +reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay1; +wire a7ddrphy_dq_i_nodelay1; +wire a7ddrphy_dq_i_delayed1; +wire a7ddrphy_dq_t1; +reg [7:0] a7ddrphy_bitslip12 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0; +wire [7:0] a7ddrphy_bitslip13; +reg [7:0] a7ddrphy_bitslip14 = 8'd0; +reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7; +reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0; +wire a7ddrphy_dq_o_nodelay2; +wire a7ddrphy_dq_i_nodelay2; +wire a7ddrphy_dq_i_delayed2; +wire a7ddrphy_dq_t2; +reg [7:0] a7ddrphy_bitslip20 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip21; +reg [7:0] a7ddrphy_bitslip22 = 8'd0; +reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay3; +wire a7ddrphy_dq_i_nodelay3; +wire a7ddrphy_dq_i_delayed3; +wire a7ddrphy_dq_t3; +reg [7:0] a7ddrphy_bitslip30 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip31; +reg [7:0] a7ddrphy_bitslip32 = 8'd0; +reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay4; +wire a7ddrphy_dq_i_nodelay4; +wire a7ddrphy_dq_i_delayed4; +wire a7ddrphy_dq_t4; +reg [7:0] a7ddrphy_bitslip40 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip41; +reg [7:0] a7ddrphy_bitslip42 = 8'd0; +reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay5; +wire a7ddrphy_dq_i_nodelay5; +wire a7ddrphy_dq_i_delayed5; +wire a7ddrphy_dq_t5; +reg [7:0] a7ddrphy_bitslip50 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip51; +reg [7:0] a7ddrphy_bitslip52 = 8'd0; +reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay6; +wire a7ddrphy_dq_i_nodelay6; +wire a7ddrphy_dq_i_delayed6; +wire a7ddrphy_dq_t6; +reg [7:0] a7ddrphy_bitslip60 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip61; +reg [7:0] a7ddrphy_bitslip62 = 8'd0; +reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay7; +wire a7ddrphy_dq_i_nodelay7; +wire a7ddrphy_dq_i_delayed7; +wire a7ddrphy_dq_t7; +reg [7:0] a7ddrphy_bitslip70 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip71; +reg [7:0] a7ddrphy_bitslip72 = 8'd0; +reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay8; +wire a7ddrphy_dq_i_nodelay8; +wire a7ddrphy_dq_i_delayed8; +wire a7ddrphy_dq_t8; +reg [7:0] a7ddrphy_bitslip80 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip81; +reg [7:0] a7ddrphy_bitslip82 = 8'd0; +reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay9; +wire a7ddrphy_dq_i_nodelay9; +wire a7ddrphy_dq_i_delayed9; +wire a7ddrphy_dq_t9; +reg [7:0] a7ddrphy_bitslip90 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip91; +reg [7:0] a7ddrphy_bitslip92 = 8'd0; +reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay10; +wire a7ddrphy_dq_i_nodelay10; +wire a7ddrphy_dq_i_delayed10; +wire a7ddrphy_dq_t10; +reg [7:0] a7ddrphy_bitslip100 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip101; +reg [7:0] a7ddrphy_bitslip102 = 8'd0; +reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay11; +wire a7ddrphy_dq_i_nodelay11; +wire a7ddrphy_dq_i_delayed11; +wire a7ddrphy_dq_t11; +reg [7:0] a7ddrphy_bitslip110 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip111; +reg [7:0] a7ddrphy_bitslip112 = 8'd0; +reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay12; +wire a7ddrphy_dq_i_nodelay12; +wire a7ddrphy_dq_i_delayed12; +wire a7ddrphy_dq_t12; +reg [7:0] a7ddrphy_bitslip120 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip121; +reg [7:0] a7ddrphy_bitslip122 = 8'd0; +reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay13; +wire a7ddrphy_dq_i_nodelay13; +wire a7ddrphy_dq_i_delayed13; +wire a7ddrphy_dq_t13; +reg [7:0] a7ddrphy_bitslip130 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip131; +reg [7:0] a7ddrphy_bitslip132 = 8'd0; +reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay14; +wire a7ddrphy_dq_i_nodelay14; +wire a7ddrphy_dq_i_delayed14; +wire a7ddrphy_dq_t14; +reg [7:0] a7ddrphy_bitslip140 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip141; +reg [7:0] a7ddrphy_bitslip142 = 8'd0; +reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0; +wire a7ddrphy_dq_o_nodelay15; +wire a7ddrphy_dq_i_nodelay15; +wire a7ddrphy_dq_i_delayed15; +wire a7ddrphy_dq_t15; +reg [7:0] a7ddrphy_bitslip150 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0; +wire [7:0] a7ddrphy_bitslip151; +reg [7:0] a7ddrphy_bitslip152 = 8'd0; +reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7; +reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0; +reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0; +reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0; +reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0; +wire [13:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_master_p0_address = 14'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [13:0] litedramcore_master_p1_address = 14'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [13:0] litedramcore_master_p2_address = 14'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [13:0] litedramcore_master_p3_address = 14'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +wire [13:0] litedramcore_csr_dfi_p0_address; +wire [2:0] litedramcore_csr_dfi_p0_bank; +reg litedramcore_csr_dfi_p0_cas_n = 1'd1; +reg litedramcore_csr_dfi_p0_cs_n = 1'd1; +reg litedramcore_csr_dfi_p0_ras_n = 1'd1; +reg litedramcore_csr_dfi_p0_we_n = 1'd1; +wire litedramcore_csr_dfi_p0_cke; +wire litedramcore_csr_dfi_p0_odt; +wire litedramcore_csr_dfi_p0_reset_n; +reg litedramcore_csr_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p0_wrdata; +wire litedramcore_csr_dfi_p0_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask; +wire litedramcore_csr_dfi_p0_rddata_en; +reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0; +reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p1_address; +wire [2:0] litedramcore_csr_dfi_p1_bank; +reg litedramcore_csr_dfi_p1_cas_n = 1'd1; +reg litedramcore_csr_dfi_p1_cs_n = 1'd1; +reg litedramcore_csr_dfi_p1_ras_n = 1'd1; +reg litedramcore_csr_dfi_p1_we_n = 1'd1; +wire litedramcore_csr_dfi_p1_cke; +wire litedramcore_csr_dfi_p1_odt; +wire litedramcore_csr_dfi_p1_reset_n; +reg litedramcore_csr_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p1_wrdata; +wire litedramcore_csr_dfi_p1_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask; +wire litedramcore_csr_dfi_p1_rddata_en; +reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0; +reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p2_address; +wire [2:0] litedramcore_csr_dfi_p2_bank; +reg litedramcore_csr_dfi_p2_cas_n = 1'd1; +reg litedramcore_csr_dfi_p2_cs_n = 1'd1; +reg litedramcore_csr_dfi_p2_ras_n = 1'd1; +reg litedramcore_csr_dfi_p2_we_n = 1'd1; +wire litedramcore_csr_dfi_p2_cke; +wire litedramcore_csr_dfi_p2_odt; +wire litedramcore_csr_dfi_p2_reset_n; +reg litedramcore_csr_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p2_wrdata; +wire litedramcore_csr_dfi_p2_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask; +wire litedramcore_csr_dfi_p2_rddata_en; +reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0; +reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_csr_dfi_p3_address; +wire [2:0] litedramcore_csr_dfi_p3_bank; +reg litedramcore_csr_dfi_p3_cas_n = 1'd1; +reg litedramcore_csr_dfi_p3_cs_n = 1'd1; +reg litedramcore_csr_dfi_p3_ras_n = 1'd1; +reg litedramcore_csr_dfi_p3_we_n = 1'd1; +wire litedramcore_csr_dfi_p3_cke; +wire litedramcore_csr_dfi_p3_odt; +wire litedramcore_csr_dfi_p3_reset_n; +reg litedramcore_csr_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_csr_dfi_p3_wrdata; +wire litedramcore_csr_dfi_p3_wrdata_en; +wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask; +wire litedramcore_csr_dfi_p3_rddata_en; +reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0; +reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0; +reg litedramcore_ext_dfi_p0_cas_n = 1'd1; +reg litedramcore_ext_dfi_p0_cs_n = 1'd1; +reg litedramcore_ext_dfi_p0_ras_n = 1'd1; +reg litedramcore_ext_dfi_p0_we_n = 1'd1; +reg litedramcore_ext_dfi_p0_cke = 1'd0; +reg litedramcore_ext_dfi_p0_odt = 1'd0; +reg litedramcore_ext_dfi_p0_reset_n = 1'd0; +reg litedramcore_ext_dfi_p0_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0; +reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p0_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0; +reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0; +reg litedramcore_ext_dfi_p1_cas_n = 1'd1; +reg litedramcore_ext_dfi_p1_cs_n = 1'd1; +reg litedramcore_ext_dfi_p1_ras_n = 1'd1; +reg litedramcore_ext_dfi_p1_we_n = 1'd1; +reg litedramcore_ext_dfi_p1_cke = 1'd0; +reg litedramcore_ext_dfi_p1_odt = 1'd0; +reg litedramcore_ext_dfi_p1_reset_n = 1'd0; +reg litedramcore_ext_dfi_p1_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0; +reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p1_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0; +reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0; +reg litedramcore_ext_dfi_p2_cas_n = 1'd1; +reg litedramcore_ext_dfi_p2_cs_n = 1'd1; +reg litedramcore_ext_dfi_p2_ras_n = 1'd1; +reg litedramcore_ext_dfi_p2_we_n = 1'd1; +reg litedramcore_ext_dfi_p2_cke = 1'd0; +reg litedramcore_ext_dfi_p2_odt = 1'd0; +reg litedramcore_ext_dfi_p2_reset_n = 1'd0; +reg litedramcore_ext_dfi_p2_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0; +reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p2_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0; +reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0; +reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0; +reg litedramcore_ext_dfi_p3_cas_n = 1'd1; +reg litedramcore_ext_dfi_p3_cs_n = 1'd1; +reg litedramcore_ext_dfi_p3_ras_n = 1'd1; +reg litedramcore_ext_dfi_p3_we_n = 1'd1; +reg litedramcore_ext_dfi_p3_cke = 1'd0; +reg litedramcore_ext_dfi_p3_odt = 1'd0; +reg litedramcore_ext_dfi_p3_reset_n = 1'd0; +reg litedramcore_ext_dfi_p3_act_n = 1'd1; +reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0; +reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0; +reg litedramcore_ext_dfi_p3_rddata_en = 1'd0; +reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0; +reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0; +reg litedramcore_ext_dfi_sel = 1'd0; +wire litedramcore_sel; +wire litedramcore_cke; +wire litedramcore_odt; +wire litedramcore_reset_n; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +wire litedramcore_phaseinjector0_csrfield_cs; +wire litedramcore_phaseinjector0_csrfield_we; +wire litedramcore_phaseinjector0_csrfield_cas; +wire litedramcore_phaseinjector0_csrfield_ras; +wire litedramcore_phaseinjector0_csrfield_wren; +wire litedramcore_phaseinjector0_csrfield_rden; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +reg litedramcore_phaseinjector0_command_issue_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_r; +reg litedramcore_phaseinjector0_command_issue_we = 1'd0; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0; +wire litedramcore_phaseinjector0_rddata_we; +reg litedramcore_phaseinjector0_rddata_re = 1'd0; +wire litedramcore_phaseinjector1_csrfield_cs; +wire litedramcore_phaseinjector1_csrfield_we; +wire litedramcore_phaseinjector1_csrfield_cas; +wire litedramcore_phaseinjector1_csrfield_ras; +wire litedramcore_phaseinjector1_csrfield_wren; +wire litedramcore_phaseinjector1_csrfield_rden; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +reg litedramcore_phaseinjector1_command_issue_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_r; +reg litedramcore_phaseinjector1_command_issue_we = 1'd0; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0; +wire litedramcore_phaseinjector1_rddata_we; +reg litedramcore_phaseinjector1_rddata_re = 1'd0; +wire litedramcore_phaseinjector2_csrfield_cs; +wire litedramcore_phaseinjector2_csrfield_we; +wire litedramcore_phaseinjector2_csrfield_cas; +wire litedramcore_phaseinjector2_csrfield_ras; +wire litedramcore_phaseinjector2_csrfield_wren; +wire litedramcore_phaseinjector2_csrfield_rden; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +reg litedramcore_phaseinjector2_command_issue_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_r; +reg litedramcore_phaseinjector2_command_issue_we = 1'd0; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0; +wire litedramcore_phaseinjector2_rddata_we; +reg litedramcore_phaseinjector2_rddata_re = 1'd0; +wire litedramcore_phaseinjector3_csrfield_cs; +wire litedramcore_phaseinjector3_csrfield_we; +wire litedramcore_phaseinjector3_csrfield_cas; +wire litedramcore_phaseinjector3_csrfield_ras; +wire litedramcore_phaseinjector3_csrfield_wren; +wire litedramcore_phaseinjector3_csrfield_rden; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +reg litedramcore_phaseinjector3_command_issue_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_r; +reg litedramcore_phaseinjector3_command_issue_we = 1'd0; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0; +wire litedramcore_phaseinjector3_rddata_we; +reg litedramcore_phaseinjector3_rddata_re = 1'd0; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [20:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [20:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [20:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [20:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [20:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [20:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [20:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [20:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [13:0] litedramcore_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [13:0] litedramcore_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [13:0] litedramcore_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [13:0] litedramcore_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [13:0] litedramcore_cmd_payload_a = 14'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [20:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_sink_valid; +wire litedramcore_bankmachine0_sink_ready; +reg litedramcore_bankmachine0_sink_first = 1'd0; +reg litedramcore_bankmachine0_sink_last = 1'd0; +wire litedramcore_bankmachine0_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_sink_payload_addr; +wire litedramcore_bankmachine0_source_valid; +wire litedramcore_bankmachine0_source_ready; +wire litedramcore_bankmachine0_source_first; +wire litedramcore_bankmachine0_source_last; +wire litedramcore_bankmachine0_source_payload_we; +wire [20:0] litedramcore_bankmachine0_source_payload_addr; +wire litedramcore_bankmachine0_syncfifo0_we; +wire litedramcore_bankmachine0_syncfifo0_writable; +wire litedramcore_bankmachine0_syncfifo0_re; +wire litedramcore_bankmachine0_syncfifo0_readable; +wire [23:0] litedramcore_bankmachine0_syncfifo0_din; +wire [23:0] litedramcore_bankmachine0_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_level = 5'd0; +reg litedramcore_bankmachine0_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine0_wrport_dat_r; +wire litedramcore_bankmachine0_wrport_we; +wire [23:0] litedramcore_bankmachine0_wrport_dat_w; +wire litedramcore_bankmachine0_do_read; +wire [3:0] litedramcore_bankmachine0_rdport_adr; +wire [23:0] litedramcore_bankmachine0_rdport_dat_r; +wire litedramcore_bankmachine0_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr; +wire litedramcore_bankmachine0_fifo_in_first; +wire litedramcore_bankmachine0_fifo_in_last; +wire litedramcore_bankmachine0_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr; +wire litedramcore_bankmachine0_fifo_out_first; +wire litedramcore_bankmachine0_fifo_out_last; +wire litedramcore_bankmachine0_sink_sink_valid; +wire litedramcore_bankmachine0_sink_sink_ready; +wire litedramcore_bankmachine0_sink_sink_first; +wire litedramcore_bankmachine0_sink_sink_last; +wire litedramcore_bankmachine0_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr; +wire litedramcore_bankmachine0_source_source_valid; +wire litedramcore_bankmachine0_source_source_ready; +wire litedramcore_bankmachine0_source_source_first; +wire litedramcore_bankmachine0_source_source_last; +wire litedramcore_bankmachine0_source_source_payload_we; +wire [20:0] litedramcore_bankmachine0_source_source_payload_addr; +wire litedramcore_bankmachine0_pipe_valid_sink_valid; +wire litedramcore_bankmachine0_pipe_valid_sink_ready; +wire litedramcore_bankmachine0_pipe_valid_sink_first; +wire litedramcore_bankmachine0_pipe_valid_sink_last; +wire litedramcore_bankmachine0_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine0_pipe_valid_source_ready; +reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine0_row = 14'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [20:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_sink_valid; +wire litedramcore_bankmachine1_sink_ready; +reg litedramcore_bankmachine1_sink_first = 1'd0; +reg litedramcore_bankmachine1_sink_last = 1'd0; +wire litedramcore_bankmachine1_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_sink_payload_addr; +wire litedramcore_bankmachine1_source_valid; +wire litedramcore_bankmachine1_source_ready; +wire litedramcore_bankmachine1_source_first; +wire litedramcore_bankmachine1_source_last; +wire litedramcore_bankmachine1_source_payload_we; +wire [20:0] litedramcore_bankmachine1_source_payload_addr; +wire litedramcore_bankmachine1_syncfifo1_we; +wire litedramcore_bankmachine1_syncfifo1_writable; +wire litedramcore_bankmachine1_syncfifo1_re; +wire litedramcore_bankmachine1_syncfifo1_readable; +wire [23:0] litedramcore_bankmachine1_syncfifo1_din; +wire [23:0] litedramcore_bankmachine1_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_level = 5'd0; +reg litedramcore_bankmachine1_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine1_wrport_dat_r; +wire litedramcore_bankmachine1_wrport_we; +wire [23:0] litedramcore_bankmachine1_wrport_dat_w; +wire litedramcore_bankmachine1_do_read; +wire [3:0] litedramcore_bankmachine1_rdport_adr; +wire [23:0] litedramcore_bankmachine1_rdport_dat_r; +wire litedramcore_bankmachine1_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr; +wire litedramcore_bankmachine1_fifo_in_first; +wire litedramcore_bankmachine1_fifo_in_last; +wire litedramcore_bankmachine1_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr; +wire litedramcore_bankmachine1_fifo_out_first; +wire litedramcore_bankmachine1_fifo_out_last; +wire litedramcore_bankmachine1_sink_sink_valid; +wire litedramcore_bankmachine1_sink_sink_ready; +wire litedramcore_bankmachine1_sink_sink_first; +wire litedramcore_bankmachine1_sink_sink_last; +wire litedramcore_bankmachine1_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr; +wire litedramcore_bankmachine1_source_source_valid; +wire litedramcore_bankmachine1_source_source_ready; +wire litedramcore_bankmachine1_source_source_first; +wire litedramcore_bankmachine1_source_source_last; +wire litedramcore_bankmachine1_source_source_payload_we; +wire [20:0] litedramcore_bankmachine1_source_source_payload_addr; +wire litedramcore_bankmachine1_pipe_valid_sink_valid; +wire litedramcore_bankmachine1_pipe_valid_sink_ready; +wire litedramcore_bankmachine1_pipe_valid_sink_first; +wire litedramcore_bankmachine1_pipe_valid_sink_last; +wire litedramcore_bankmachine1_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine1_pipe_valid_source_ready; +reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine1_row = 14'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [20:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_sink_valid; +wire litedramcore_bankmachine2_sink_ready; +reg litedramcore_bankmachine2_sink_first = 1'd0; +reg litedramcore_bankmachine2_sink_last = 1'd0; +wire litedramcore_bankmachine2_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_sink_payload_addr; +wire litedramcore_bankmachine2_source_valid; +wire litedramcore_bankmachine2_source_ready; +wire litedramcore_bankmachine2_source_first; +wire litedramcore_bankmachine2_source_last; +wire litedramcore_bankmachine2_source_payload_we; +wire [20:0] litedramcore_bankmachine2_source_payload_addr; +wire litedramcore_bankmachine2_syncfifo2_we; +wire litedramcore_bankmachine2_syncfifo2_writable; +wire litedramcore_bankmachine2_syncfifo2_re; +wire litedramcore_bankmachine2_syncfifo2_readable; +wire [23:0] litedramcore_bankmachine2_syncfifo2_din; +wire [23:0] litedramcore_bankmachine2_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_level = 5'd0; +reg litedramcore_bankmachine2_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine2_wrport_dat_r; +wire litedramcore_bankmachine2_wrport_we; +wire [23:0] litedramcore_bankmachine2_wrport_dat_w; +wire litedramcore_bankmachine2_do_read; +wire [3:0] litedramcore_bankmachine2_rdport_adr; +wire [23:0] litedramcore_bankmachine2_rdport_dat_r; +wire litedramcore_bankmachine2_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr; +wire litedramcore_bankmachine2_fifo_in_first; +wire litedramcore_bankmachine2_fifo_in_last; +wire litedramcore_bankmachine2_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr; +wire litedramcore_bankmachine2_fifo_out_first; +wire litedramcore_bankmachine2_fifo_out_last; +wire litedramcore_bankmachine2_sink_sink_valid; +wire litedramcore_bankmachine2_sink_sink_ready; +wire litedramcore_bankmachine2_sink_sink_first; +wire litedramcore_bankmachine2_sink_sink_last; +wire litedramcore_bankmachine2_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr; +wire litedramcore_bankmachine2_source_source_valid; +wire litedramcore_bankmachine2_source_source_ready; +wire litedramcore_bankmachine2_source_source_first; +wire litedramcore_bankmachine2_source_source_last; +wire litedramcore_bankmachine2_source_source_payload_we; +wire [20:0] litedramcore_bankmachine2_source_source_payload_addr; +wire litedramcore_bankmachine2_pipe_valid_sink_valid; +wire litedramcore_bankmachine2_pipe_valid_sink_ready; +wire litedramcore_bankmachine2_pipe_valid_sink_first; +wire litedramcore_bankmachine2_pipe_valid_sink_last; +wire litedramcore_bankmachine2_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine2_pipe_valid_source_ready; +reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine2_row = 14'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [20:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_sink_valid; +wire litedramcore_bankmachine3_sink_ready; +reg litedramcore_bankmachine3_sink_first = 1'd0; +reg litedramcore_bankmachine3_sink_last = 1'd0; +wire litedramcore_bankmachine3_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_sink_payload_addr; +wire litedramcore_bankmachine3_source_valid; +wire litedramcore_bankmachine3_source_ready; +wire litedramcore_bankmachine3_source_first; +wire litedramcore_bankmachine3_source_last; +wire litedramcore_bankmachine3_source_payload_we; +wire [20:0] litedramcore_bankmachine3_source_payload_addr; +wire litedramcore_bankmachine3_syncfifo3_we; +wire litedramcore_bankmachine3_syncfifo3_writable; +wire litedramcore_bankmachine3_syncfifo3_re; +wire litedramcore_bankmachine3_syncfifo3_readable; +wire [23:0] litedramcore_bankmachine3_syncfifo3_din; +wire [23:0] litedramcore_bankmachine3_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_level = 5'd0; +reg litedramcore_bankmachine3_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine3_wrport_dat_r; +wire litedramcore_bankmachine3_wrport_we; +wire [23:0] litedramcore_bankmachine3_wrport_dat_w; +wire litedramcore_bankmachine3_do_read; +wire [3:0] litedramcore_bankmachine3_rdport_adr; +wire [23:0] litedramcore_bankmachine3_rdport_dat_r; +wire litedramcore_bankmachine3_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr; +wire litedramcore_bankmachine3_fifo_in_first; +wire litedramcore_bankmachine3_fifo_in_last; +wire litedramcore_bankmachine3_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr; +wire litedramcore_bankmachine3_fifo_out_first; +wire litedramcore_bankmachine3_fifo_out_last; +wire litedramcore_bankmachine3_sink_sink_valid; +wire litedramcore_bankmachine3_sink_sink_ready; +wire litedramcore_bankmachine3_sink_sink_first; +wire litedramcore_bankmachine3_sink_sink_last; +wire litedramcore_bankmachine3_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr; +wire litedramcore_bankmachine3_source_source_valid; +wire litedramcore_bankmachine3_source_source_ready; +wire litedramcore_bankmachine3_source_source_first; +wire litedramcore_bankmachine3_source_source_last; +wire litedramcore_bankmachine3_source_source_payload_we; +wire [20:0] litedramcore_bankmachine3_source_source_payload_addr; +wire litedramcore_bankmachine3_pipe_valid_sink_valid; +wire litedramcore_bankmachine3_pipe_valid_sink_ready; +wire litedramcore_bankmachine3_pipe_valid_sink_first; +wire litedramcore_bankmachine3_pipe_valid_sink_last; +wire litedramcore_bankmachine3_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine3_pipe_valid_source_ready; +reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine3_row = 14'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [20:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_sink_valid; +wire litedramcore_bankmachine4_sink_ready; +reg litedramcore_bankmachine4_sink_first = 1'd0; +reg litedramcore_bankmachine4_sink_last = 1'd0; +wire litedramcore_bankmachine4_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_sink_payload_addr; +wire litedramcore_bankmachine4_source_valid; +wire litedramcore_bankmachine4_source_ready; +wire litedramcore_bankmachine4_source_first; +wire litedramcore_bankmachine4_source_last; +wire litedramcore_bankmachine4_source_payload_we; +wire [20:0] litedramcore_bankmachine4_source_payload_addr; +wire litedramcore_bankmachine4_syncfifo4_we; +wire litedramcore_bankmachine4_syncfifo4_writable; +wire litedramcore_bankmachine4_syncfifo4_re; +wire litedramcore_bankmachine4_syncfifo4_readable; +wire [23:0] litedramcore_bankmachine4_syncfifo4_din; +wire [23:0] litedramcore_bankmachine4_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_level = 5'd0; +reg litedramcore_bankmachine4_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine4_wrport_dat_r; +wire litedramcore_bankmachine4_wrport_we; +wire [23:0] litedramcore_bankmachine4_wrport_dat_w; +wire litedramcore_bankmachine4_do_read; +wire [3:0] litedramcore_bankmachine4_rdport_adr; +wire [23:0] litedramcore_bankmachine4_rdport_dat_r; +wire litedramcore_bankmachine4_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr; +wire litedramcore_bankmachine4_fifo_in_first; +wire litedramcore_bankmachine4_fifo_in_last; +wire litedramcore_bankmachine4_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr; +wire litedramcore_bankmachine4_fifo_out_first; +wire litedramcore_bankmachine4_fifo_out_last; +wire litedramcore_bankmachine4_sink_sink_valid; +wire litedramcore_bankmachine4_sink_sink_ready; +wire litedramcore_bankmachine4_sink_sink_first; +wire litedramcore_bankmachine4_sink_sink_last; +wire litedramcore_bankmachine4_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr; +wire litedramcore_bankmachine4_source_source_valid; +wire litedramcore_bankmachine4_source_source_ready; +wire litedramcore_bankmachine4_source_source_first; +wire litedramcore_bankmachine4_source_source_last; +wire litedramcore_bankmachine4_source_source_payload_we; +wire [20:0] litedramcore_bankmachine4_source_source_payload_addr; +wire litedramcore_bankmachine4_pipe_valid_sink_valid; +wire litedramcore_bankmachine4_pipe_valid_sink_ready; +wire litedramcore_bankmachine4_pipe_valid_sink_first; +wire litedramcore_bankmachine4_pipe_valid_sink_last; +wire litedramcore_bankmachine4_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine4_pipe_valid_source_ready; +reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine4_row = 14'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [20:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_sink_valid; +wire litedramcore_bankmachine5_sink_ready; +reg litedramcore_bankmachine5_sink_first = 1'd0; +reg litedramcore_bankmachine5_sink_last = 1'd0; +wire litedramcore_bankmachine5_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_sink_payload_addr; +wire litedramcore_bankmachine5_source_valid; +wire litedramcore_bankmachine5_source_ready; +wire litedramcore_bankmachine5_source_first; +wire litedramcore_bankmachine5_source_last; +wire litedramcore_bankmachine5_source_payload_we; +wire [20:0] litedramcore_bankmachine5_source_payload_addr; +wire litedramcore_bankmachine5_syncfifo5_we; +wire litedramcore_bankmachine5_syncfifo5_writable; +wire litedramcore_bankmachine5_syncfifo5_re; +wire litedramcore_bankmachine5_syncfifo5_readable; +wire [23:0] litedramcore_bankmachine5_syncfifo5_din; +wire [23:0] litedramcore_bankmachine5_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_level = 5'd0; +reg litedramcore_bankmachine5_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine5_wrport_dat_r; +wire litedramcore_bankmachine5_wrport_we; +wire [23:0] litedramcore_bankmachine5_wrport_dat_w; +wire litedramcore_bankmachine5_do_read; +wire [3:0] litedramcore_bankmachine5_rdport_adr; +wire [23:0] litedramcore_bankmachine5_rdport_dat_r; +wire litedramcore_bankmachine5_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr; +wire litedramcore_bankmachine5_fifo_in_first; +wire litedramcore_bankmachine5_fifo_in_last; +wire litedramcore_bankmachine5_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr; +wire litedramcore_bankmachine5_fifo_out_first; +wire litedramcore_bankmachine5_fifo_out_last; +wire litedramcore_bankmachine5_sink_sink_valid; +wire litedramcore_bankmachine5_sink_sink_ready; +wire litedramcore_bankmachine5_sink_sink_first; +wire litedramcore_bankmachine5_sink_sink_last; +wire litedramcore_bankmachine5_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr; +wire litedramcore_bankmachine5_source_source_valid; +wire litedramcore_bankmachine5_source_source_ready; +wire litedramcore_bankmachine5_source_source_first; +wire litedramcore_bankmachine5_source_source_last; +wire litedramcore_bankmachine5_source_source_payload_we; +wire [20:0] litedramcore_bankmachine5_source_source_payload_addr; +wire litedramcore_bankmachine5_pipe_valid_sink_valid; +wire litedramcore_bankmachine5_pipe_valid_sink_ready; +wire litedramcore_bankmachine5_pipe_valid_sink_first; +wire litedramcore_bankmachine5_pipe_valid_sink_last; +wire litedramcore_bankmachine5_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine5_pipe_valid_source_ready; +reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine5_row = 14'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [20:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_sink_valid; +wire litedramcore_bankmachine6_sink_ready; +reg litedramcore_bankmachine6_sink_first = 1'd0; +reg litedramcore_bankmachine6_sink_last = 1'd0; +wire litedramcore_bankmachine6_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_sink_payload_addr; +wire litedramcore_bankmachine6_source_valid; +wire litedramcore_bankmachine6_source_ready; +wire litedramcore_bankmachine6_source_first; +wire litedramcore_bankmachine6_source_last; +wire litedramcore_bankmachine6_source_payload_we; +wire [20:0] litedramcore_bankmachine6_source_payload_addr; +wire litedramcore_bankmachine6_syncfifo6_we; +wire litedramcore_bankmachine6_syncfifo6_writable; +wire litedramcore_bankmachine6_syncfifo6_re; +wire litedramcore_bankmachine6_syncfifo6_readable; +wire [23:0] litedramcore_bankmachine6_syncfifo6_din; +wire [23:0] litedramcore_bankmachine6_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_level = 5'd0; +reg litedramcore_bankmachine6_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine6_wrport_dat_r; +wire litedramcore_bankmachine6_wrport_we; +wire [23:0] litedramcore_bankmachine6_wrport_dat_w; +wire litedramcore_bankmachine6_do_read; +wire [3:0] litedramcore_bankmachine6_rdport_adr; +wire [23:0] litedramcore_bankmachine6_rdport_dat_r; +wire litedramcore_bankmachine6_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr; +wire litedramcore_bankmachine6_fifo_in_first; +wire litedramcore_bankmachine6_fifo_in_last; +wire litedramcore_bankmachine6_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr; +wire litedramcore_bankmachine6_fifo_out_first; +wire litedramcore_bankmachine6_fifo_out_last; +wire litedramcore_bankmachine6_sink_sink_valid; +wire litedramcore_bankmachine6_sink_sink_ready; +wire litedramcore_bankmachine6_sink_sink_first; +wire litedramcore_bankmachine6_sink_sink_last; +wire litedramcore_bankmachine6_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr; +wire litedramcore_bankmachine6_source_source_valid; +wire litedramcore_bankmachine6_source_source_ready; +wire litedramcore_bankmachine6_source_source_first; +wire litedramcore_bankmachine6_source_source_last; +wire litedramcore_bankmachine6_source_source_payload_we; +wire [20:0] litedramcore_bankmachine6_source_source_payload_addr; +wire litedramcore_bankmachine6_pipe_valid_sink_valid; +wire litedramcore_bankmachine6_pipe_valid_sink_ready; +wire litedramcore_bankmachine6_pipe_valid_sink_first; +wire litedramcore_bankmachine6_pipe_valid_sink_last; +wire litedramcore_bankmachine6_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine6_pipe_valid_source_ready; +reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine6_row = 14'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [20:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_sink_valid; +wire litedramcore_bankmachine7_sink_ready; +reg litedramcore_bankmachine7_sink_first = 1'd0; +reg litedramcore_bankmachine7_sink_last = 1'd0; +wire litedramcore_bankmachine7_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_sink_payload_addr; +wire litedramcore_bankmachine7_source_valid; +wire litedramcore_bankmachine7_source_ready; +wire litedramcore_bankmachine7_source_first; +wire litedramcore_bankmachine7_source_last; +wire litedramcore_bankmachine7_source_payload_we; +wire [20:0] litedramcore_bankmachine7_source_payload_addr; +wire litedramcore_bankmachine7_syncfifo7_we; +wire litedramcore_bankmachine7_syncfifo7_writable; +wire litedramcore_bankmachine7_syncfifo7_re; +wire litedramcore_bankmachine7_syncfifo7_readable; +wire [23:0] litedramcore_bankmachine7_syncfifo7_din; +wire [23:0] litedramcore_bankmachine7_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_level = 5'd0; +reg litedramcore_bankmachine7_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine7_wrport_dat_r; +wire litedramcore_bankmachine7_wrport_we; +wire [23:0] litedramcore_bankmachine7_wrport_dat_w; +wire litedramcore_bankmachine7_do_read; +wire [3:0] litedramcore_bankmachine7_rdport_adr; +wire [23:0] litedramcore_bankmachine7_rdport_dat_r; +wire litedramcore_bankmachine7_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr; +wire litedramcore_bankmachine7_fifo_in_first; +wire litedramcore_bankmachine7_fifo_in_last; +wire litedramcore_bankmachine7_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr; +wire litedramcore_bankmachine7_fifo_out_first; +wire litedramcore_bankmachine7_fifo_out_last; +wire litedramcore_bankmachine7_sink_sink_valid; +wire litedramcore_bankmachine7_sink_sink_ready; +wire litedramcore_bankmachine7_sink_sink_first; +wire litedramcore_bankmachine7_sink_sink_last; +wire litedramcore_bankmachine7_sink_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr; +wire litedramcore_bankmachine7_source_source_valid; +wire litedramcore_bankmachine7_source_source_ready; +wire litedramcore_bankmachine7_source_source_first; +wire litedramcore_bankmachine7_source_source_last; +wire litedramcore_bankmachine7_source_source_payload_we; +wire [20:0] litedramcore_bankmachine7_source_source_payload_addr; +wire litedramcore_bankmachine7_pipe_valid_sink_valid; +wire litedramcore_bankmachine7_pipe_valid_sink_ready; +wire litedramcore_bankmachine7_pipe_valid_sink_first; +wire litedramcore_bankmachine7_pipe_valid_sink_last; +wire litedramcore_bankmachine7_pipe_valid_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr; +reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0; +wire litedramcore_bankmachine7_pipe_valid_source_ready; +reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0; +reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine7_row = 14'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* dont_touch = "true" *) +reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +wire [1:0] litedramcore_rdcmdphase; +wire [1:0] litedramcore_wrcmdphase; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [13:0] litedramcore_nop_a = 14'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* dont_touch = "true" *) +reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* dont_touch = "true" *) +reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_enable; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [23:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +reg [31:0] litedramcore_dat_w = 32'd0; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +reg [31:0] litedramcore_wishbone_dat_r = 32'd0; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +reg csrbank0_init_done0_re = 1'd0; +wire csrbank0_init_done0_r; +reg csrbank0_init_done0_we = 1'd0; +wire csrbank0_init_done0_w; +reg csrbank0_init_error0_re = 1'd0; +wire csrbank0_init_error0_r; +reg csrbank0_init_error0_we = 1'd0; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +reg csrbank1_rst0_re = 1'd0; +wire csrbank1_rst0_r; +reg csrbank1_rst0_we = 1'd0; +wire csrbank1_rst0_w; +reg csrbank1_dly_sel0_re = 1'd0; +wire [1:0] csrbank1_dly_sel0_r; +reg csrbank1_dly_sel0_we = 1'd0; +wire [1:0] csrbank1_dly_sel0_w; +reg csrbank1_half_sys8x_taps0_re = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_r; +reg csrbank1_half_sys8x_taps0_we = 1'd0; +wire [4:0] csrbank1_half_sys8x_taps0_w; +reg csrbank1_wlevel_en0_re = 1'd0; +wire csrbank1_wlevel_en0_r; +reg csrbank1_wlevel_en0_we = 1'd0; +wire csrbank1_wlevel_en0_w; +reg csrbank1_rdphase0_re = 1'd0; +wire [1:0] csrbank1_rdphase0_r; +reg csrbank1_rdphase0_we = 1'd0; +wire [1:0] csrbank1_rdphase0_w; +reg csrbank1_wrphase0_re = 1'd0; +wire [1:0] csrbank1_wrphase0_r; +reg csrbank1_wrphase0_we = 1'd0; +wire [1:0] csrbank1_wrphase0_w; +wire csrbank1_sel; +wire [13:0] interface2_bank_bus_adr; +wire interface2_bank_bus_we; +wire [31:0] interface2_bank_bus_dat_w; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +reg csrbank2_dfii_control0_re = 1'd0; +wire [3:0] csrbank2_dfii_control0_r; +reg csrbank2_dfii_control0_we = 1'd0; +wire [3:0] csrbank2_dfii_control0_w; +reg csrbank2_dfii_pi0_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_r; +reg csrbank2_dfii_pi0_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi0_command0_w; +reg csrbank2_dfii_pi0_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi0_address0_r; +reg csrbank2_dfii_pi0_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi0_address0_w; +reg csrbank2_dfii_pi0_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_r; +reg csrbank2_dfii_pi0_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi0_baddress0_w; +reg csrbank2_dfii_pi0_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_r; +reg csrbank2_dfii_pi0_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_wrdata0_w; +reg csrbank2_dfii_pi0_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_r; +reg csrbank2_dfii_pi0_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi0_rddata_w; +reg csrbank2_dfii_pi1_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_r; +reg csrbank2_dfii_pi1_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi1_command0_w; +reg csrbank2_dfii_pi1_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi1_address0_r; +reg csrbank2_dfii_pi1_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi1_address0_w; +reg csrbank2_dfii_pi1_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_r; +reg csrbank2_dfii_pi1_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi1_baddress0_w; +reg csrbank2_dfii_pi1_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_r; +reg csrbank2_dfii_pi1_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_wrdata0_w; +reg csrbank2_dfii_pi1_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_r; +reg csrbank2_dfii_pi1_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi1_rddata_w; +reg csrbank2_dfii_pi2_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_r; +reg csrbank2_dfii_pi2_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi2_command0_w; +reg csrbank2_dfii_pi2_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi2_address0_r; +reg csrbank2_dfii_pi2_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi2_address0_w; +reg csrbank2_dfii_pi2_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_r; +reg csrbank2_dfii_pi2_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi2_baddress0_w; +reg csrbank2_dfii_pi2_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_r; +reg csrbank2_dfii_pi2_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_wrdata0_w; +reg csrbank2_dfii_pi2_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_r; +reg csrbank2_dfii_pi2_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi2_rddata_w; +reg csrbank2_dfii_pi3_command0_re = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_r; +reg csrbank2_dfii_pi3_command0_we = 1'd0; +wire [5:0] csrbank2_dfii_pi3_command0_w; +reg csrbank2_dfii_pi3_address0_re = 1'd0; +wire [13:0] csrbank2_dfii_pi3_address0_r; +reg csrbank2_dfii_pi3_address0_we = 1'd0; +wire [13:0] csrbank2_dfii_pi3_address0_w; +reg csrbank2_dfii_pi3_baddress0_re = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_r; +reg csrbank2_dfii_pi3_baddress0_we = 1'd0; +wire [2:0] csrbank2_dfii_pi3_baddress0_w; +reg csrbank2_dfii_pi3_wrdata0_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_r; +reg csrbank2_dfii_pi3_wrdata0_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_wrdata0_w; +reg csrbank2_dfii_pi3_rddata_re = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_r; +reg csrbank2_dfii_pi3_rddata_we = 1'd0; +wire [31:0] csrbank2_dfii_pi3_rddata_w; +wire csrbank2_sel; +wire [13:0] csr_interconnect_adr; +wire csr_interconnect_we; +wire [31:0] csr_interconnect_dat_w; +wire [31:0] csr_interconnect_dat_r; +wire litedramcore_reset0; +wire litedramcore_reset1; +wire litedramcore_reset2; +wire litedramcore_reset3; +wire litedramcore_reset4; +wire litedramcore_reset5; +wire litedramcore_reset6; +wire litedramcore_reset7; +wire litedramcore_pll_fb; +reg [1:0] litedramcore_refresher_state = 2'd0; +reg [1:0] litedramcore_refresher_next_state = 2'd0; +reg [3:0] litedramcore_bankmachine0_state = 4'd0; +reg [3:0] litedramcore_bankmachine0_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_state = 4'd0; +reg [3:0] litedramcore_bankmachine1_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_state = 4'd0; +reg [3:0] litedramcore_bankmachine2_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_state = 4'd0; +reg [3:0] litedramcore_bankmachine3_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_state = 4'd0; +reg [3:0] litedramcore_bankmachine4_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_state = 4'd0; +reg [3:0] litedramcore_bankmachine5_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_state = 4'd0; +reg [3:0] litedramcore_bankmachine6_next_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_state = 4'd0; +reg [3:0] litedramcore_bankmachine7_next_state = 4'd0; +reg [3:0] litedramcore_multiplexer_state = 4'd0; +reg [3:0] litedramcore_multiplexer_next_state = 4'd0; +wire litedramcore_roundrobin0_request; +wire litedramcore_roundrobin0_grant; +wire litedramcore_roundrobin0_ce; +wire litedramcore_roundrobin1_request; +wire litedramcore_roundrobin1_grant; +wire litedramcore_roundrobin1_ce; +wire litedramcore_roundrobin2_request; +wire litedramcore_roundrobin2_grant; +wire litedramcore_roundrobin2_ce; +wire litedramcore_roundrobin3_request; +wire litedramcore_roundrobin3_grant; +wire litedramcore_roundrobin3_ce; +wire litedramcore_roundrobin4_request; +wire litedramcore_roundrobin4_grant; +wire litedramcore_roundrobin4_ce; +wire litedramcore_roundrobin5_request; +wire litedramcore_roundrobin5_grant; +wire litedramcore_roundrobin5_ce; +wire litedramcore_roundrobin6_request; +wire litedramcore_roundrobin6_grant; +wire litedramcore_roundrobin6_ce; +wire litedramcore_roundrobin7_request; +wire litedramcore_roundrobin7_grant; +wire litedramcore_roundrobin7_ce; +reg litedramcore_locked0 = 1'd0; +reg litedramcore_locked1 = 1'd0; +reg litedramcore_locked2 = 1'd0; +reg litedramcore_locked3 = 1'd0; +reg litedramcore_locked4 = 1'd0; +reg litedramcore_locked5 = 1'd0; +reg litedramcore_locked6 = 1'd0; +reg litedramcore_locked7 = 1'd0; +reg litedramcore_new_master_wdata_ready0 = 1'd0; +reg litedramcore_new_master_wdata_ready1 = 1'd0; +reg litedramcore_new_master_rdata_valid0 = 1'd0; +reg litedramcore_new_master_rdata_valid1 = 1'd0; +reg litedramcore_new_master_rdata_valid2 = 1'd0; +reg litedramcore_new_master_rdata_valid3 = 1'd0; +reg litedramcore_new_master_rdata_valid4 = 1'd0; +reg litedramcore_new_master_rdata_valid5 = 1'd0; +reg litedramcore_new_master_rdata_valid6 = 1'd0; +reg litedramcore_new_master_rdata_valid7 = 1'd0; +reg litedramcore_new_master_rdata_valid8 = 1'd0; +reg [1:0] litedramcore_state = 2'd0; +reg [1:0] litedramcore_next_state = 2'd0; +reg [31:0] litedramcore_dat_w_next_value0 = 32'd0; +reg litedramcore_dat_w_next_value_ce0 = 1'd0; +reg [13:0] litedramcore_adr_next_value1 = 14'd0; +reg litedramcore_adr_next_value_ce1 = 1'd0; +reg litedramcore_we_next_value2 = 1'd0; +reg litedramcore_we_next_value_ce2 = 1'd0; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; +wire xilinxasyncresetsynchronizerimpl0; +wire xilinxasyncresetsynchronizerimpl0_rst_meta; +wire xilinxasyncresetsynchronizerimpl1; +wire xilinxasyncresetsynchronizerimpl1_rst_meta; +wire xilinxasyncresetsynchronizerimpl2; +wire xilinxasyncresetsynchronizerimpl2_rst_meta; +wire xilinxasyncresetsynchronizerimpl2_expr; +wire xilinxasyncresetsynchronizerimpl3; +wire xilinxasyncresetsynchronizerimpl3_rst_meta; +wire xilinxasyncresetsynchronizerimpl3_expr; //------------------------------------------------------------------------------ // Combinatorial Logic @@ -2047,144 +2171,144 @@ assign ddram_ba = a7ddrphy_pads_ba; assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble); assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble); always @(*) begin - a7ddrphy_dfi_p0_rddata <= 32'd0; - a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; - a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; - a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; - a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; - a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; - a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; - a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; - a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; - a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; - a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; - a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; - a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; - a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; - a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; - a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; - a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; - a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; - a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; - a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; - a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; - a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; - a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; - a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; - a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; - a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; - a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; - a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; - a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; - a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; - a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; - a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; - a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; -end -always @(*) begin - a7ddrphy_dfi_p1_rddata <= 32'd0; - a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; - a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; - a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; - a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; - a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; - a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; - a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; - a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; - a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; - a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; - a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; - a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; - a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; - a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; - a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; - a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; - a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; - a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; - a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; - a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; - a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; - a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; - a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; - a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; - a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; - a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; - a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; - a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; - a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; - a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; - a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; - a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; -end -always @(*) begin - a7ddrphy_dfi_p2_rddata <= 32'd0; - a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; - a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; - a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; - a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; - a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; - a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; - a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; - a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; - a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; - a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; - a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; - a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; - a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; - a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; - a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; - a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; - a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; - a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; - a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; - a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; - a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; - a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; - a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; - a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; - a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; - a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; - a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; - a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; - a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; - a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; - a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; - a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; -end -always @(*) begin - a7ddrphy_dfi_p3_rddata <= 32'd0; - a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; - a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; - a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; - a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; - a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; - a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; - a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; - a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; - a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; - a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; - a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; - a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; - a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; - a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; - a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; - a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; - a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; - a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; - a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; - a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; - a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; - a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; - a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; - a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; - a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; - a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; - a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; - a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; - a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; - a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; - a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; - a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; + a7ddrphy_dfi_p0_rddata <= 32'd0; + a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0]; + a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1]; + a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0]; + a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1]; + a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0]; + a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1]; + a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0]; + a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1]; + a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0]; + a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1]; + a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0]; + a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1]; + a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0]; + a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1]; + a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0]; + a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1]; + a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0]; + a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1]; + a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0]; + a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1]; + a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0]; + a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1]; + a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0]; + a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1]; + a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0]; + a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1]; + a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0]; + a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1]; + a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0]; + a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1]; + a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0]; + a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1]; +end +always @(*) begin + a7ddrphy_dfi_p1_rddata <= 32'd0; + a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2]; + a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3]; + a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2]; + a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3]; + a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2]; + a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3]; + a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2]; + a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3]; + a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2]; + a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3]; + a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2]; + a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3]; + a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2]; + a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3]; + a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2]; + a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3]; + a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2]; + a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3]; + a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2]; + a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3]; + a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2]; + a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3]; + a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2]; + a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3]; + a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2]; + a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3]; + a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2]; + a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3]; + a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2]; + a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3]; + a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2]; + a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3]; +end +always @(*) begin + a7ddrphy_dfi_p2_rddata <= 32'd0; + a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4]; + a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5]; + a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4]; + a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5]; + a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4]; + a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5]; + a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4]; + a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5]; + a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4]; + a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5]; + a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4]; + a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5]; + a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4]; + a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5]; + a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4]; + a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5]; + a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4]; + a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5]; + a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4]; + a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5]; + a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4]; + a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5]; + a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4]; + a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5]; + a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4]; + a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5]; + a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4]; + a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5]; + a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4]; + a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5]; + a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4]; + a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5]; +end +always @(*) begin + a7ddrphy_dfi_p3_rddata <= 32'd0; + a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6]; + a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7]; + a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6]; + a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7]; + a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6]; + a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7]; + a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6]; + a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7]; + a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6]; + a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7]; + a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6]; + a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7]; + a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6]; + a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7]; + a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6]; + a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7]; + a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6]; + a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7]; + a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6]; + a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7]; + a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6]; + a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7]; + a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6]; + a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7]; + a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6]; + a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7]; + a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6]; + a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7]; + a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6]; + a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7]; + a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6]; + a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7]; end assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); @@ -2192,1074 +2316,1074 @@ assign a7ddrphy_dfi_p2_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7d assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage); assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1; always @(*) begin - a7ddrphy_dqs_oe <= 1'd0; - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqs_oe <= 1'd1; - end else begin - a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; - end + a7ddrphy_dqs_oe <= 1'd0; + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqs_oe <= 1'd1; + end else begin + a7ddrphy_dqs_oe <= a7ddrphy_dq_oe; + end end assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1)); assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1)); always @(*) begin - a7ddrphy_dqspattern_o0 <= 8'd0; - a7ddrphy_dqspattern_o0 <= 7'd85; - if (a7ddrphy_dqspattern0) begin - a7ddrphy_dqspattern_o0 <= 5'd21; - end - if (a7ddrphy_dqspattern1) begin - a7ddrphy_dqspattern_o0 <= 7'd84; - end - if (a7ddrphy_wlevel_en_storage) begin - a7ddrphy_dqspattern_o0 <= 1'd0; - if (a7ddrphy_wlevel_strobe_re) begin - a7ddrphy_dqspattern_o0 <= 1'd1; - end - end -end -always @(*) begin - a7ddrphy_bitslip00 <= 8'd0; - case (a7ddrphy_bitslip0_value0) - 1'd0: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip10 <= 8'd0; - case (a7ddrphy_bitslip1_value0) - 1'd0: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip01 <= 8'd0; - case (a7ddrphy_bitslip0_value1) - 1'd0: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip11 <= 8'd0; - case (a7ddrphy_bitslip1_value1) - 1'd0: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip02 <= 8'd0; - case (a7ddrphy_bitslip0_value2) - 1'd0: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip04 <= 8'd0; - case (a7ddrphy_bitslip0_value3) - 1'd0: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip12 <= 8'd0; - case (a7ddrphy_bitslip1_value2) - 1'd0: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip14 <= 8'd0; - case (a7ddrphy_bitslip1_value3) - 1'd0: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip20 <= 8'd0; - case (a7ddrphy_bitslip2_value0) - 1'd0: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip22 <= 8'd0; - case (a7ddrphy_bitslip2_value1) - 1'd0: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip30 <= 8'd0; - case (a7ddrphy_bitslip3_value0) - 1'd0: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip32 <= 8'd0; - case (a7ddrphy_bitslip3_value1) - 1'd0: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip40 <= 8'd0; - case (a7ddrphy_bitslip4_value0) - 1'd0: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip42 <= 8'd0; - case (a7ddrphy_bitslip4_value1) - 1'd0: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip50 <= 8'd0; - case (a7ddrphy_bitslip5_value0) - 1'd0: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip52 <= 8'd0; - case (a7ddrphy_bitslip5_value1) - 1'd0: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip60 <= 8'd0; - case (a7ddrphy_bitslip6_value0) - 1'd0: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip62 <= 8'd0; - case (a7ddrphy_bitslip6_value1) - 1'd0: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip70 <= 8'd0; - case (a7ddrphy_bitslip7_value0) - 1'd0: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip72 <= 8'd0; - case (a7ddrphy_bitslip7_value1) - 1'd0: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip80 <= 8'd0; - case (a7ddrphy_bitslip8_value0) - 1'd0: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip82 <= 8'd0; - case (a7ddrphy_bitslip8_value1) - 1'd0: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip90 <= 8'd0; - case (a7ddrphy_bitslip9_value0) - 1'd0: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip92 <= 8'd0; - case (a7ddrphy_bitslip9_value1) - 1'd0: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip100 <= 8'd0; - case (a7ddrphy_bitslip10_value0) - 1'd0: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip102 <= 8'd0; - case (a7ddrphy_bitslip10_value1) - 1'd0: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip110 <= 8'd0; - case (a7ddrphy_bitslip11_value0) - 1'd0: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip112 <= 8'd0; - case (a7ddrphy_bitslip11_value1) - 1'd0: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip120 <= 8'd0; - case (a7ddrphy_bitslip12_value0) - 1'd0: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip122 <= 8'd0; - case (a7ddrphy_bitslip12_value1) - 1'd0: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip130 <= 8'd0; - case (a7ddrphy_bitslip13_value0) - 1'd0: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip132 <= 8'd0; - case (a7ddrphy_bitslip13_value1) - 1'd0: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip140 <= 8'd0; - case (a7ddrphy_bitslip14_value0) - 1'd0: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip142 <= 8'd0; - case (a7ddrphy_bitslip14_value1) - 1'd0: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip150 <= 8'd0; - case (a7ddrphy_bitslip15_value0) - 1'd0: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; - end - endcase -end -always @(*) begin - a7ddrphy_bitslip152 <= 8'd0; - case (a7ddrphy_bitslip15_value1) - 1'd0: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; - end - 1'd1: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; - end - 2'd2: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; - end - 2'd3: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; - end - 3'd4: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; - end - 3'd5: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; - end - 3'd6: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; - end - 3'd7: begin - a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; - end - endcase + a7ddrphy_dqspattern_o0 <= 8'd0; + a7ddrphy_dqspattern_o0 <= 7'd85; + if (a7ddrphy_dqspattern0) begin + a7ddrphy_dqspattern_o0 <= 5'd21; + end + if (a7ddrphy_dqspattern1) begin + a7ddrphy_dqspattern_o0 <= 7'd84; + end + if (a7ddrphy_wlevel_en_storage) begin + a7ddrphy_dqspattern_o0 <= 1'd0; + if (a7ddrphy_wlevel_strobe_re) begin + a7ddrphy_dqspattern_o0 <= 1'd1; + end + end +end +always @(*) begin + a7ddrphy_bitslip00 <= 8'd0; + case (a7ddrphy_bitslip0_value0) + 1'd0: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip10 <= 8'd0; + case (a7ddrphy_bitslip1_value0) + 1'd0: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip01 <= 8'd0; + case (a7ddrphy_bitslip0_value1) + 1'd0: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip11 <= 8'd0; + case (a7ddrphy_bitslip1_value1) + 1'd0: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip02 <= 8'd0; + case (a7ddrphy_bitslip0_value2) + 1'd0: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip04 <= 8'd0; + case (a7ddrphy_bitslip0_value3) + 1'd0: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip12 <= 8'd0; + case (a7ddrphy_bitslip1_value2) + 1'd0: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip14 <= 8'd0; + case (a7ddrphy_bitslip1_value3) + 1'd0: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip20 <= 8'd0; + case (a7ddrphy_bitslip2_value0) + 1'd0: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip22 <= 8'd0; + case (a7ddrphy_bitslip2_value1) + 1'd0: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip30 <= 8'd0; + case (a7ddrphy_bitslip3_value0) + 1'd0: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip32 <= 8'd0; + case (a7ddrphy_bitslip3_value1) + 1'd0: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip40 <= 8'd0; + case (a7ddrphy_bitslip4_value0) + 1'd0: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip42 <= 8'd0; + case (a7ddrphy_bitslip4_value1) + 1'd0: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip50 <= 8'd0; + case (a7ddrphy_bitslip5_value0) + 1'd0: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip52 <= 8'd0; + case (a7ddrphy_bitslip5_value1) + 1'd0: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip60 <= 8'd0; + case (a7ddrphy_bitslip6_value0) + 1'd0: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip62 <= 8'd0; + case (a7ddrphy_bitslip6_value1) + 1'd0: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip70 <= 8'd0; + case (a7ddrphy_bitslip7_value0) + 1'd0: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip72 <= 8'd0; + case (a7ddrphy_bitslip7_value1) + 1'd0: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip80 <= 8'd0; + case (a7ddrphy_bitslip8_value0) + 1'd0: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip82 <= 8'd0; + case (a7ddrphy_bitslip8_value1) + 1'd0: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip90 <= 8'd0; + case (a7ddrphy_bitslip9_value0) + 1'd0: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip92 <= 8'd0; + case (a7ddrphy_bitslip9_value1) + 1'd0: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip100 <= 8'd0; + case (a7ddrphy_bitslip10_value0) + 1'd0: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip102 <= 8'd0; + case (a7ddrphy_bitslip10_value1) + 1'd0: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip110 <= 8'd0; + case (a7ddrphy_bitslip11_value0) + 1'd0: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip112 <= 8'd0; + case (a7ddrphy_bitslip11_value1) + 1'd0: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip120 <= 8'd0; + case (a7ddrphy_bitslip12_value0) + 1'd0: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip122 <= 8'd0; + case (a7ddrphy_bitslip12_value1) + 1'd0: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip130 <= 8'd0; + case (a7ddrphy_bitslip13_value0) + 1'd0: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip132 <= 8'd0; + case (a7ddrphy_bitslip13_value1) + 1'd0: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip140 <= 8'd0; + case (a7ddrphy_bitslip14_value0) + 1'd0: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip142 <= 8'd0; + case (a7ddrphy_bitslip14_value1) + 1'd0: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip150 <= 8'd0; + case (a7ddrphy_bitslip15_value0) + 1'd0: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8]; + end + endcase +end +always @(*) begin + a7ddrphy_bitslip152 <= 8'd0; + case (a7ddrphy_bitslip15_value1) + 1'd0: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1]; + end + 1'd1: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2]; + end + 2'd2: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3]; + end + 2'd3: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4]; + end + 3'd4: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5]; + end + 3'd5: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6]; + end + 3'd6: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7]; + end + 3'd7: begin + a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8]; + end + endcase end assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address; assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; @@ -3390,892 +3514,892 @@ assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; always @(*) begin - litedramcore_csr_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end + litedramcore_csr_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end end always @(*) begin - litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end -end -always @(*) begin - litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - end else begin - litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end else begin - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p1_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; - end - end else begin - end -end -always @(*) begin - litedramcore_slave_p3_rddata_valid <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - end else begin - litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; - end - end else begin - end -end -always @(*) begin - litedramcore_master_p0_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; - end else begin - litedramcore_master_p0_address <= litedramcore_slave_p0_address; - end - end else begin - litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; - end -end -always @(*) begin - litedramcore_master_p0_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; - end else begin - litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; - end - end else begin - litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; - end -end -always @(*) begin - litedramcore_master_p0_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; - end else begin - litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; - end - end else begin - litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; - end -end -always @(*) begin - litedramcore_master_p0_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; - end else begin - litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; - end - end else begin - litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; - end -end -always @(*) begin - litedramcore_master_p0_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; - end else begin - litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; - end - end else begin - litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; - end -end -always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; - end else begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; - end - end else begin - litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; - end -end -always @(*) begin - litedramcore_master_p0_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; - end else begin - litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; - end - end else begin - litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; - end -end -always @(*) begin - litedramcore_master_p0_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; - end else begin - litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; - end - end else begin - litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; - end -end -always @(*) begin - litedramcore_master_p0_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; - end else begin - litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; - end - end else begin - litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; - end -end -always @(*) begin - litedramcore_master_p0_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; - end else begin - litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; - end - end else begin - litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; - end -end -always @(*) begin - litedramcore_master_p0_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; - end else begin - litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; - end - end else begin - litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; - end - end else begin - litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p0_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; - end - end else begin - litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p0_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; - end - end else begin - litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; - end -end -always @(*) begin - litedramcore_master_p1_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; - end else begin - litedramcore_master_p1_address <= litedramcore_slave_p1_address; - end - end else begin - litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; - end -end -always @(*) begin - litedramcore_master_p1_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; - end else begin - litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; - end - end else begin - litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; - end -end -always @(*) begin - litedramcore_master_p1_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; - end else begin - litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; - end - end else begin - litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; - end -end -always @(*) begin - litedramcore_master_p1_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; - end else begin - litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; - end - end else begin - litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; - end -end -always @(*) begin - litedramcore_master_p1_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; - end else begin - litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; - end - end else begin - litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; - end -end -always @(*) begin - litedramcore_master_p1_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; - end else begin - litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; - end - end else begin - litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; - end -end -always @(*) begin - litedramcore_master_p1_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; - end else begin - litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; - end - end else begin - litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; - end -end -always @(*) begin - litedramcore_master_p1_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; - end else begin - litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; - end - end else begin - litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; - end -end -always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; - end else begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; - end - end else begin - litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; - end -end -always @(*) begin - litedramcore_master_p1_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; - end else begin - litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; - end - end else begin - litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; - end -end -always @(*) begin - litedramcore_master_p1_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; - end else begin - litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; - end - end else begin - litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; - end -end -always @(*) begin - litedramcore_master_p2_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; - end else begin - litedramcore_master_p2_address <= litedramcore_slave_p2_address; - end - end else begin - litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; - end -end -always @(*) begin - litedramcore_master_p2_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; - end else begin - litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; - end - end else begin - litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; - end -end -always @(*) begin - litedramcore_master_p2_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; - end else begin - litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; - end - end else begin - litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; - end -end -always @(*) begin - litedramcore_master_p2_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; - end else begin - litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; - end - end else begin - litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; - end -end -always @(*) begin - litedramcore_master_p2_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; - end else begin - litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; - end - end else begin - litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; - end -end -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end - end else begin - litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; - end -end -always @(*) begin - litedramcore_master_p2_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; - end else begin - litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; - end - end else begin - litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; - end -end -always @(*) begin - litedramcore_master_p2_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; - end else begin - litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; - end - end else begin - litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; - end -end -always @(*) begin - litedramcore_master_p2_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; - end else begin - litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; - end - end else begin - litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; - end -end -always @(*) begin - litedramcore_master_p2_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; - end else begin - litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; - end - end else begin - litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; - end -end -always @(*) begin - litedramcore_master_p2_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; - end else begin - litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; - end - end else begin - litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; - end - end else begin - litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p2_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; - end - end else begin - litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p2_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; - end - end else begin - litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; - end -end -always @(*) begin - litedramcore_master_p3_address <= 14'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; - end else begin - litedramcore_master_p3_address <= litedramcore_slave_p3_address; - end - end else begin - litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; - end -end -always @(*) begin - litedramcore_master_p3_bank <= 3'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; - end else begin - litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; - end - end else begin - litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; - end -end -always @(*) begin - litedramcore_master_p3_cas_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; - end else begin - litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; - end - end else begin - litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; - end -end -always @(*) begin - litedramcore_master_p3_cs_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; - end else begin - litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; - end - end else begin - litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; - end -end -always @(*) begin - litedramcore_master_p3_ras_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; - end else begin - litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; - end - end else begin - litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; - end -end -always @(*) begin - litedramcore_master_p3_we_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; - end else begin - litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; - end - end else begin - litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; - end -end -always @(*) begin - litedramcore_master_p3_cke <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; - end else begin - litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; - end - end else begin - litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; - end -end -always @(*) begin - litedramcore_master_p3_odt <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; - end else begin - litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; - end - end else begin - litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; - end -end -always @(*) begin - litedramcore_master_p3_reset_n <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; - end else begin - litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; - end - end else begin - litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; - end -end -always @(*) begin - litedramcore_master_p3_act_n <= 1'd1; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; - end else begin - litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; - end - end else begin - litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; - end -end -always @(*) begin - litedramcore_master_p3_wrdata <= 32'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; - end else begin - litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; - end - end else begin - litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; - end - end else begin - litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; - end -end -always @(*) begin - litedramcore_master_p3_wrdata_mask <= 4'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; - end - end else begin - litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; - end -end -always @(*) begin - litedramcore_master_p3_rddata_en <= 1'd0; - if (litedramcore_sel) begin - if (litedramcore_ext_dfi_sel) begin - litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; - end - end else begin - litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; - end + litedramcore_csr_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_csr_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + end else begin + litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_ext_dfi_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end else begin + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata; + end + end else begin + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + end else begin + litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; + end + end else begin + end +end +always @(*) begin + litedramcore_master_p0_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address; + end else begin + litedramcore_master_p0_address <= litedramcore_slave_p0_address; + end + end else begin + litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank; + end else begin + litedramcore_master_p0_bank <= litedramcore_slave_p0_bank; + end + end else begin + litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n; + end + end else begin + litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n; + end + end else begin + litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n; + end + end else begin + litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n; + end +end +always @(*) begin + litedramcore_master_p0_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n; + end else begin + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + end + end else begin + litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n; + end +end +always @(*) begin + litedramcore_master_p0_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke; + end else begin + litedramcore_master_p0_cke <= litedramcore_slave_p0_cke; + end + end else begin + litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt; + end else begin + litedramcore_master_p0_odt <= litedramcore_slave_p0_odt; + end + end else begin + litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n; + end + end else begin + litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n; + end else begin + litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n; + end + end else begin + litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata; + end + end else begin + litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en; + end + end else begin + litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask; + end + end else begin + litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en; + end + end else begin + litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address; + end else begin + litedramcore_master_p1_address <= litedramcore_slave_p1_address; + end + end else begin + litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank; + end else begin + litedramcore_master_p1_bank <= litedramcore_slave_p1_bank; + end + end else begin + litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n; + end + end else begin + litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n; + end +end +always @(*) begin + litedramcore_master_p1_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n; + end + end else begin + litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n; + end + end else begin + litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n; + end +end +always @(*) begin + litedramcore_master_p1_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n; + end else begin + litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n; + end + end else begin + litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n; + end +end +always @(*) begin + litedramcore_master_p1_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke; + end else begin + litedramcore_master_p1_cke <= litedramcore_slave_p1_cke; + end + end else begin + litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt; + end else begin + litedramcore_master_p1_odt <= litedramcore_slave_p1_odt; + end + end else begin + litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + end + end else begin + litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n; + end else begin + litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n; + end + end else begin + litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata; + end + end else begin + litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address; + end else begin + litedramcore_master_p2_address <= litedramcore_slave_p2_address; + end + end else begin + litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank; + end else begin + litedramcore_master_p2_bank <= litedramcore_slave_p2_bank; + end + end else begin + litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n; + end + end else begin + litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n; + end + end else begin + litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n; + end + end else begin + litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n; + end +end +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end + end else begin + litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n; + end +end +always @(*) begin + litedramcore_master_p2_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke; + end else begin + litedramcore_master_p2_cke <= litedramcore_slave_p2_cke; + end + end else begin + litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt; + end else begin + litedramcore_master_p2_odt <= litedramcore_slave_p2_odt; + end + end else begin + litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n; + end + end else begin + litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n; + end else begin + litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n; + end + end else begin + litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata; + end + end else begin + litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en; + end + end else begin + litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask; + end + end else begin + litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en; + end + end else begin + litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address <= 14'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address; + end else begin + litedramcore_master_p3_address <= litedramcore_slave_p3_address; + end + end else begin + litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank <= 3'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank; + end else begin + litedramcore_master_p3_bank <= litedramcore_slave_p3_bank; + end + end else begin + litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n; + end + end else begin + litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n; + end + end else begin + litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n; + end +end +always @(*) begin + litedramcore_master_p3_ras_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n; + end + end else begin + litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n; + end +end +always @(*) begin + litedramcore_master_p3_we_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n; + end else begin + litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n; + end + end else begin + litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n; + end +end +always @(*) begin + litedramcore_master_p3_cke <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke; + end else begin + litedramcore_master_p3_cke <= litedramcore_slave_p3_cke; + end + end else begin + litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt; + end else begin + litedramcore_master_p3_odt <= litedramcore_slave_p3_odt; + end + end else begin + litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n; + end + end else begin + litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n <= 1'd1; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n; + end else begin + litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n; + end + end else begin + litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata <= 32'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata; + end + end else begin + litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en; + end + end else begin + litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask <= 4'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask; + end + end else begin + litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en <= 1'd0; + if (litedramcore_sel) begin + if (litedramcore_ext_dfi_sel) begin + litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en; + end + end else begin + litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en; + end end assign litedramcore_csr_dfi_p0_cke = litedramcore_cke; assign litedramcore_csr_dfi_p1_cke = litedramcore_cke; @@ -4290,36 +4414,36 @@ assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n; assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n; always @(*) begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); - end else begin - litedramcore_csr_dfi_p0_we_n <= 1'd1; - end + litedramcore_csr_dfi_p0_we_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we); + end else begin + litedramcore_csr_dfi_p0_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); - end else begin - litedramcore_csr_dfi_p0_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas); + end else begin + litedramcore_csr_dfi_p0_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p0_cs_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p0_cs_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); - end else begin - litedramcore_csr_dfi_p0_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras); + end else begin + litedramcore_csr_dfi_p0_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage; assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage; @@ -4328,36 +4452,36 @@ assign litedramcore_csr_dfi_p0_rddata_en = (litedramcore_phaseinjector0_command_ assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); - end else begin - litedramcore_csr_dfi_p1_we_n <= 1'd1; - end + litedramcore_csr_dfi_p1_we_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we); + end else begin + litedramcore_csr_dfi_p1_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); - end else begin - litedramcore_csr_dfi_p1_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas); + end else begin + litedramcore_csr_dfi_p1_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p1_cs_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p1_cs_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); - end else begin - litedramcore_csr_dfi_p1_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras); + end else begin + litedramcore_csr_dfi_p1_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage; assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage; @@ -4366,36 +4490,36 @@ assign litedramcore_csr_dfi_p1_rddata_en = (litedramcore_phaseinjector1_command_ assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); - end else begin - litedramcore_csr_dfi_p2_we_n <= 1'd1; - end + litedramcore_csr_dfi_p2_we_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we); + end else begin + litedramcore_csr_dfi_p2_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); - end else begin - litedramcore_csr_dfi_p2_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas); + end else begin + litedramcore_csr_dfi_p2_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p2_cs_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p2_cs_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); - end else begin - litedramcore_csr_dfi_p2_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras); + end else begin + litedramcore_csr_dfi_p2_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage; assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage; @@ -4404,36 +4528,36 @@ assign litedramcore_csr_dfi_p2_rddata_en = (litedramcore_phaseinjector2_command_ assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0; always @(*) begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); - end else begin - litedramcore_csr_dfi_p3_we_n <= 1'd1; - end + litedramcore_csr_dfi_p3_we_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we); + end else begin + litedramcore_csr_dfi_p3_we_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); - end else begin - litedramcore_csr_dfi_p3_cas_n <= 1'd1; - end + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas); + end else begin + litedramcore_csr_dfi_p3_cas_n <= 1'd1; + end end always @(*) begin - litedramcore_csr_dfi_p3_cs_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; - end else begin - litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; - end + litedramcore_csr_dfi_p3_cs_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}}; + end else begin + litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}}; + end end always @(*) begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); - end else begin - litedramcore_csr_dfi_p3_ras_n <= 1'd1; - end + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras); + end else begin + litedramcore_csr_dfi_p3_ras_n <= 1'd1; + end end assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage; assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage; @@ -4511,4590 +4635,4686 @@ assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; always @(*) begin - litedramcore_refresher_next_state <= 2'd0; - litedramcore_refresher_next_state <= litedramcore_refresher_state; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_refresher_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_refresher_next_state <= 2'd3; - end else begin - litedramcore_refresher_next_state <= 1'd0; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_refresher_next_state <= 1'd0; - end - end - default: begin - if (1'd1) begin - if (litedramcore_wants_refresh) begin - litedramcore_refresher_next_state <= 1'd1; - end - end - end - endcase -end -always @(*) begin - litedramcore_zqcs_executer_start <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - litedramcore_zqcs_executer_start <= 1'd1; - end else begin - end - end - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_last <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - end - 2'd2: begin - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_last <= 1'd1; - end - end - end - 2'd3: begin - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_last <= 1'd1; - end - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_sequencer_start0 <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - if (litedramcore_cmd_ready) begin - litedramcore_sequencer_start0 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_cmd_valid <= 1'd0; - case (litedramcore_refresher_state) - 1'd1: begin - litedramcore_cmd_valid <= 1'd1; - end - 2'd2: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_sequencer_done0) begin - if (litedramcore_wants_zqcs) begin - end else begin - litedramcore_cmd_valid <= 1'd0; - end - end - end - 2'd3: begin - litedramcore_cmd_valid <= 1'd1; - if (litedramcore_zqcs_executer_done) begin - litedramcore_cmd_valid <= 1'd0; - end - end - default: begin - end - endcase -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; -assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; -assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; -assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); -assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); -assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); + litedramcore_refresher_next_state <= 2'd0; + litedramcore_refresher_next_state <= litedramcore_refresher_state; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_refresher_next_state <= 2'd3; + end else begin + litedramcore_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + litedramcore_refresher_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start <= 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last <= 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last <= 1'd1; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_valid <= 1'd0; + case (litedramcore_refresher_state) + 1'd1: begin + litedramcore_cmd_valid <= 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid <= 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid <= 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid <= 1'd0; + end + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready; +assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid; +assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready; +assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first; +assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last; +assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we; +assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr; +assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]); assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin - litedramcore_bankmachine0_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine0_row_col_n_addr_sel) begin - litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine0_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); always @(*) begin - litedramcore_bankmachine0_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine0_next_state <= 4'd0; - litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - if (litedramcore_bankmachine0_cmd_ready) begin - litedramcore_bankmachine0_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine0_refresh_req)) begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine0_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine0_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine0_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - litedramcore_bankmachine0_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - litedramcore_bankmachine0_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine0_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine0_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine0_twtpcon_ready) begin - litedramcore_bankmachine0_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_valid <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; -assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; -assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; -assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); -assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); -assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine0_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin + if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout; +assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable; +assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid; +assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first; +assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last; +assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we; +assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr; +assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable; +assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first; +assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last; +assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we; +assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr; +assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready; +always @(*) begin + litedramcore_bankmachine0_wrport_adr <= 4'd0; + if (litedramcore_bankmachine0_replace) begin + litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1); + end else begin + litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce; + end +end +assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din; +assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace)); +assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re); +assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume; +assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r; +assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16); +assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0); +assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready); +assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid; +assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready; +assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first; +assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we; +assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr; +assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid; +assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready; +assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first; +assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last; +assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we; +assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine0_next_state <= 4'd0; + litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + litedramcore_bankmachine0_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine0_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine0_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + litedramcore_bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + litedramcore_bankmachine0_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine0_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_source_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_source_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready; +assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid; +assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready; +assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first; +assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last; +assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we; +assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr; +assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]); assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin - litedramcore_bankmachine1_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine1_row_col_n_addr_sel) begin - litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine1_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); always @(*) begin - litedramcore_bankmachine1_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine1_next_state <= 4'd0; - litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - if (litedramcore_bankmachine1_cmd_ready) begin - litedramcore_bankmachine1_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine1_refresh_req)) begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - litedramcore_bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - litedramcore_bankmachine1_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine1_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_close <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine1_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; -assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; -assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; -assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); -assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); -assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine1_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin + if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout; +assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable; +assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid; +assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first; +assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last; +assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we; +assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr; +assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable; +assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first; +assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last; +assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we; +assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr; +assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready; +always @(*) begin + litedramcore_bankmachine1_wrport_adr <= 4'd0; + if (litedramcore_bankmachine1_replace) begin + litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1); + end else begin + litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce; + end +end +assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din; +assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace)); +assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re); +assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume; +assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r; +assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16); +assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0); +assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready); +assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid; +assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready; +assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first; +assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we; +assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr; +assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid; +assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready; +assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first; +assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last; +assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we; +assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine1_next_state <= 4'd0; + litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + litedramcore_bankmachine1_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine1_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine1_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine1_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + litedramcore_bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + litedramcore_bankmachine1_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine1_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_source_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_source_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close <= 1'd0; + case (litedramcore_bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready; +assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid; +assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready; +assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first; +assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last; +assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we; +assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr; +assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]); assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin - litedramcore_bankmachine2_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine2_row_col_n_addr_sel) begin - litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine2_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); always @(*) begin - litedramcore_bankmachine2_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine2_next_state <= 4'd0; - litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - if (litedramcore_bankmachine2_cmd_ready) begin - litedramcore_bankmachine2_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine2_refresh_req)) begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine2_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine2_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine2_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - litedramcore_bankmachine2_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin - litedramcore_bankmachine2_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine2_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine2_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; -assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; -assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; -assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); -assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); -assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine2_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin + if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout; +assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable; +assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid; +assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first; +assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last; +assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we; +assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr; +assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable; +assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first; +assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last; +assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we; +assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr; +assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready; +always @(*) begin + litedramcore_bankmachine2_wrport_adr <= 4'd0; + if (litedramcore_bankmachine2_replace) begin + litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1); + end else begin + litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce; + end +end +assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din; +assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace)); +assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re); +assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume; +assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r; +assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16); +assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0); +assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready); +assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid; +assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready; +assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first; +assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we; +assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr; +assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid; +assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready; +assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first; +assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last; +assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we; +assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine2_next_state <= 4'd0; + litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + litedramcore_bankmachine2_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine2_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine2_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine2_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + litedramcore_bankmachine2_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + litedramcore_bankmachine2_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine2_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_source_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_source_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready; +assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid; +assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready; +assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first; +assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last; +assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we; +assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr; +assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]); assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin - litedramcore_bankmachine3_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine3_row_col_n_addr_sel) begin - litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine3_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); always @(*) begin - litedramcore_bankmachine3_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine3_next_state <= 4'd0; - litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - if (litedramcore_bankmachine3_cmd_ready) begin - litedramcore_bankmachine3_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine3_refresh_req)) begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine3_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine3_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine3_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - litedramcore_bankmachine3_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - litedramcore_bankmachine3_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine3_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; -assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; -assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; -assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); -assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); -assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine3_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin + if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout; +assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable; +assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid; +assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first; +assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last; +assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we; +assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr; +assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable; +assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first; +assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last; +assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we; +assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr; +assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready; +always @(*) begin + litedramcore_bankmachine3_wrport_adr <= 4'd0; + if (litedramcore_bankmachine3_replace) begin + litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1); + end else begin + litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce; + end +end +assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din; +assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace)); +assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re); +assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume; +assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r; +assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16); +assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0); +assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready); +assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid; +assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready; +assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first; +assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we; +assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr; +assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid; +assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready; +assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first; +assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last; +assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we; +assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine3_next_state <= 4'd0; + litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + litedramcore_bankmachine3_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine3_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine3_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine3_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + litedramcore_bankmachine3_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + litedramcore_bankmachine3_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine3_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_source_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_source_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready; +assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid; +assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready; +assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first; +assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last; +assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we; +assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr; +assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]); assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; always @(*) begin - litedramcore_bankmachine4_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine4_row_col_n_addr_sel) begin - litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine4_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); always @(*) begin - litedramcore_bankmachine4_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine4_next_state <= 4'd0; - litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - if (litedramcore_bankmachine4_cmd_ready) begin - litedramcore_bankmachine4_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine4_refresh_req)) begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine4_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine4_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine4_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - litedramcore_bankmachine4_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin - litedramcore_bankmachine4_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine4_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine4_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine4_twtpcon_ready) begin - litedramcore_bankmachine4_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; -assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; -assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; -assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); -assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); -assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine4_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin + if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout; +assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable; +assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid; +assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first; +assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last; +assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we; +assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr; +assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable; +assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first; +assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last; +assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we; +assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr; +assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready; +always @(*) begin + litedramcore_bankmachine4_wrport_adr <= 4'd0; + if (litedramcore_bankmachine4_replace) begin + litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1); + end else begin + litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce; + end +end +assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din; +assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace)); +assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re); +assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume; +assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r; +assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16); +assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0); +assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready); +assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid; +assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready; +assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first; +assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we; +assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr; +assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid; +assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready; +assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first; +assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last; +assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we; +assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine4_next_state <= 4'd0; + litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + litedramcore_bankmachine4_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine4_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine4_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine4_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + litedramcore_bankmachine4_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + litedramcore_bankmachine4_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine4_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_source_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_source_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready; +assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid; +assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready; +assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first; +assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last; +assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we; +assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr; +assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]); assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; always @(*) begin - litedramcore_bankmachine5_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine5_row_col_n_addr_sel) begin - litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine5_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); always @(*) begin - litedramcore_bankmachine5_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine5_next_state <= 4'd0; - litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - if (litedramcore_bankmachine5_cmd_ready) begin - litedramcore_bankmachine5_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine5_refresh_req)) begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - litedramcore_bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - litedramcore_bankmachine5_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine5_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_close <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine5_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; -assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; -assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; -assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); -assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); -assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine5_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin + if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout; +assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable; +assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid; +assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first; +assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last; +assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we; +assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr; +assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable; +assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first; +assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last; +assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we; +assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr; +assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready; +always @(*) begin + litedramcore_bankmachine5_wrport_adr <= 4'd0; + if (litedramcore_bankmachine5_replace) begin + litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1); + end else begin + litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce; + end +end +assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din; +assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace)); +assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re); +assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume; +assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r; +assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16); +assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0); +assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready); +assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid; +assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready; +assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first; +assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we; +assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr; +assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid; +assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready; +assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first; +assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last; +assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we; +assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine5_next_state <= 4'd0; + litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + litedramcore_bankmachine5_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine5_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine5_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine5_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + litedramcore_bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + litedramcore_bankmachine5_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine5_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_source_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_source_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close <= 1'd0; + case (litedramcore_bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready; +assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid; +assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready; +assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first; +assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last; +assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we; +assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr; +assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]); assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; always @(*) begin - litedramcore_bankmachine6_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine6_row_col_n_addr_sel) begin - litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine6_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); always @(*) begin - litedramcore_bankmachine6_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine6_next_state <= 4'd0; - litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - if (litedramcore_bankmachine6_cmd_ready) begin - litedramcore_bankmachine6_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine6_refresh_req)) begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine6_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine6_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine6_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - litedramcore_bankmachine6_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin - litedramcore_bankmachine6_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine6_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine6_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; -assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; -assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; -assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; -assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); -assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); -assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); + litedramcore_bankmachine6_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin + if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout; +assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable; +assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid; +assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first; +assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last; +assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we; +assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr; +assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable; +assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first; +assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last; +assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we; +assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr; +assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready; +always @(*) begin + litedramcore_bankmachine6_wrport_adr <= 4'd0; + if (litedramcore_bankmachine6_replace) begin + litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1); + end else begin + litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce; + end +end +assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din; +assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace)); +assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re); +assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume; +assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r; +assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16); +assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0); +assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready); +assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid; +assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready; +assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first; +assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we; +assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr; +assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid; +assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready; +assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first; +assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last; +assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we; +assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine6_next_state <= 4'd0; + litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + litedramcore_bankmachine6_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine6_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine6_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine6_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + litedramcore_bankmachine6_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + litedramcore_bankmachine6_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine6_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_source_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_source_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready; +assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid; +assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready; +assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first; +assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last; +assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we; +assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr; +assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]); assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; always @(*) begin - litedramcore_bankmachine7_cmd_payload_a <= 14'd0; - if (litedramcore_bankmachine7_row_col_n_addr_sel) begin - litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end else begin - litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); - end + litedramcore_bankmachine7_cmd_payload_a <= 14'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}}); + end end assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); always @(*) begin - litedramcore_bankmachine7_auto_precharge <= 1'd0; - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin - if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin - litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); - end - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; -always @(*) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0; - if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); - end else begin - litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce; - end -end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); -assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); -assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); -always @(*) begin - litedramcore_bankmachine7_next_state <= 4'd0; - litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - end - 2'd2: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_next_state <= 3'd5; - end - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - if (litedramcore_bankmachine7_cmd_ready) begin - litedramcore_bankmachine7_next_state <= 3'd7; - end - end - end - 3'd4: begin - if ((~litedramcore_bankmachine7_refresh_req)) begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - end - 3'd5: begin - litedramcore_bankmachine7_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - 3'd7: begin - litedramcore_bankmachine7_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_bankmachine7_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - litedramcore_bankmachine7_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - litedramcore_bankmachine7_next_state <= 2'd2; - end - end else begin - litedramcore_bankmachine7_next_state <= 1'd1; - end - end else begin - litedramcore_bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - end - 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase -end -always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; - case (litedramcore_bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase + litedramcore_bankmachine7_auto_precharge <= 1'd0; + if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin + if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin + litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout; +assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable; +assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid; +assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first; +assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last; +assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we; +assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr; +assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable; +assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first; +assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last; +assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we; +assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr; +assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready; +always @(*) begin + litedramcore_bankmachine7_wrport_adr <= 4'd0; + if (litedramcore_bankmachine7_replace) begin + litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1); + end else begin + litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce; + end +end +assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din; +assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace)); +assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re); +assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume; +assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r; +assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16); +assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0); +assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready); +assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid; +assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready; +assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first; +assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we; +assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr; +assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid; +assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready; +assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first; +assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last; +assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we; +assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr; +always @(*) begin + litedramcore_bankmachine7_next_state <= 4'd0; + litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_next_state <= 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + litedramcore_bankmachine7_next_state <= 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + litedramcore_bankmachine7_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + 3'd7: begin + litedramcore_bankmachine7_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_bankmachine7_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + litedramcore_bankmachine7_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + litedramcore_bankmachine7_next_state <= 2'd2; + end + end else begin + litedramcore_bankmachine7_next_state <= 1'd1; + end + end else begin + litedramcore_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + case (litedramcore_bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_source_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_source_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase end assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1); assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1); @@ -9127,15 +9347,15 @@ assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedr assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); always @(*) begin - litedramcore_choose_cmd_valids <= 8'd0; - litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); - litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids <= 8'd0; + litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); end assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; @@ -9145,106 +9365,106 @@ assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin - litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; - end + litedramcore_choose_cmd_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; - end + litedramcore_choose_cmd_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1; + end end always @(*) begin - litedramcore_choose_cmd_cmd_payload_we <= 1'd0; - if (litedramcore_choose_cmd_cmd_valid) begin - litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; - end + litedramcore_choose_cmd_cmd_payload_we <= 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2; + end end always @(*) begin - litedramcore_bankmachine0_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin - litedramcore_bankmachine0_cmd_ready <= 1'd1; - end + litedramcore_bankmachine0_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine1_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin - litedramcore_bankmachine1_cmd_ready <= 1'd1; - end + litedramcore_bankmachine1_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine2_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin - litedramcore_bankmachine2_cmd_ready <= 1'd1; - end + litedramcore_bankmachine2_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine3_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin - litedramcore_bankmachine3_cmd_ready <= 1'd1; - end + litedramcore_bankmachine3_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine4_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin - litedramcore_bankmachine4_cmd_ready <= 1'd1; - end + litedramcore_bankmachine4_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine5_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin - litedramcore_bankmachine5_cmd_ready <= 1'd1; - end + litedramcore_bankmachine5_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine6_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin - litedramcore_bankmachine6_cmd_ready <= 1'd1; - end + litedramcore_bankmachine6_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready <= 1'd1; + end end always @(*) begin - litedramcore_bankmachine7_cmd_ready <= 1'd0; - if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end - if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin - litedramcore_bankmachine7_cmd_ready <= 1'd1; - end + litedramcore_bankmachine7_cmd_ready <= 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready <= 1'd1; + end end assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); always @(*) begin - litedramcore_choose_req_valids <= 8'd0; - litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); - litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids <= 8'd0; + litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); end assign litedramcore_choose_req_request = litedramcore_choose_req_valids; assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; @@ -9254,22 +9474,22 @@ assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin - litedramcore_choose_req_cmd_payload_cas <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; - end + litedramcore_choose_req_cmd_payload_cas <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_ras <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; - end + litedramcore_choose_req_cmd_payload_ras <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4; + end end always @(*) begin - litedramcore_choose_req_cmd_payload_we <= 1'd0; - if (litedramcore_choose_req_cmd_valid) begin - litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; - end + litedramcore_choose_req_cmd_payload_we <= 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we <= t_array_muxed5; + end end assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); assign litedramcore_dfi_p0_reset_n = 1'd1; @@ -9286,473 +9506,473 @@ assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); always @(*) begin - litedramcore_multiplexer_next_state <= 4'd0; - litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (litedramcore_read_available) begin - if (((~litedramcore_write_available) | litedramcore_max_time1)) begin - litedramcore_multiplexer_next_state <= 2'd3; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - 2'd2: begin - if (litedramcore_cmd_last) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 2'd3: begin - if (litedramcore_twtrcon_ready) begin - litedramcore_multiplexer_next_state <= 1'd0; - end - end - 3'd4: begin - litedramcore_multiplexer_next_state <= 3'd5; - end - 3'd5: begin - litedramcore_multiplexer_next_state <= 3'd6; - end - 3'd6: begin - litedramcore_multiplexer_next_state <= 3'd7; - end - 3'd7: begin - litedramcore_multiplexer_next_state <= 4'd8; - end - 4'd8: begin - litedramcore_multiplexer_next_state <= 4'd9; - end - 4'd9: begin - litedramcore_multiplexer_next_state <= 4'd10; - end - 4'd10: begin - litedramcore_multiplexer_next_state <= 1'd1; - end - default: begin - if (litedramcore_write_available) begin - if (((~litedramcore_read_available) | litedramcore_max_time0)) begin - litedramcore_multiplexer_next_state <= 3'd4; - end - end - if (litedramcore_go_to_refresh) begin - litedramcore_multiplexer_next_state <= 2'd2; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel0 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd0)) begin - litedramcore_steerer_sel0 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd0)) begin - litedramcore_steerer_sel0 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_cmd_ready <= 1'd1; - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel1 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 1'd1)) begin - litedramcore_steerer_sel1 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 1'd1)) begin - litedramcore_steerer_sel1 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel2 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd2)) begin - litedramcore_steerer_sel2 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd2)) begin - litedramcore_steerer_sel2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_wrphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_wrcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_steerer_sel3 <= 1'd0; - if ((a7ddrphy_rdphase_storage == 2'd3)) begin - litedramcore_steerer_sel3 <= 2'd2; - end - if ((litedramcore_rdcmdphase == 2'd3)) begin - litedramcore_steerer_sel3 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_en0 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_en0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - litedramcore_choose_req_want_reads <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end - end - endcase -end -always @(*) begin - litedramcore_en1 <= 1'd0; - case (litedramcore_multiplexer_state) - 1'd1: begin - litedramcore_en1 <= 1'd1; - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - 4'd9: begin - end - 4'd10: begin - end - default: begin - end - endcase + litedramcore_multiplexer_next_state <= 4'd0; + litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + litedramcore_multiplexer_next_state <= 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + litedramcore_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + litedramcore_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + litedramcore_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + litedramcore_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + litedramcore_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + litedramcore_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + litedramcore_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + litedramcore_multiplexer_next_state <= 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + litedramcore_multiplexer_next_state <= 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + litedramcore_multiplexer_next_state <= 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel0 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd0)) begin + litedramcore_steerer_sel0 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd0)) begin + litedramcore_steerer_sel0 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel1 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 1'd1)) begin + litedramcore_steerer_sel1 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 1'd1)) begin + litedramcore_steerer_sel1 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel2 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd2)) begin + litedramcore_steerer_sel2 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd2)) begin + litedramcore_steerer_sel2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 <= 2'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_wrphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_wrcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_steerer_sel3 <= 1'd0; + if ((a7ddrphy_rdphase_storage == 2'd3)) begin + litedramcore_steerer_sel3 <= 2'd2; + end + if ((litedramcore_rdcmdphase == 2'd3)) begin + litedramcore_steerer_sel3 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_en0 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_en0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + litedramcore_choose_req_want_reads <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 <= 1'd0; + case (litedramcore_multiplexer_state) + 1'd1: begin + litedramcore_en1 <= 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + default: begin + end + endcase end assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); @@ -9798,26 +10018,26 @@ assign user_port_cmd_ready = ((((((((1'd0 | (((litedramcore_roundrobin0_grant == assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1; assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8; always @(*) begin - litedramcore_interface_wdata <= 128'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; - end - default: begin - litedramcore_interface_wdata <= 1'd0; - end - endcase -end -always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; - case ({litedramcore_new_master_wdata_ready1}) - 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; - end - default: begin - litedramcore_interface_wdata_we <= 1'd0; - end - endcase + litedramcore_interface_wdata <= 128'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata <= user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata <= 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we <= 16'd0; + case ({litedramcore_new_master_wdata_ready1}) + 1'd1: begin + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we <= 1'd0; + end + endcase end assign user_port_rdata_payload_data = litedramcore_interface_rdata; assign litedramcore_roundrobin0_grant = 1'd0; @@ -9829,129 +10049,129 @@ assign litedramcore_roundrobin5_grant = 1'd0; assign litedramcore_roundrobin6_grant = 1'd0; assign litedramcore_roundrobin7_grant = 1'd0; always @(*) begin - litedramcore_next_state <= 2'd0; - litedramcore_next_state <= litedramcore_state; - case (litedramcore_state) - 1'd1: begin - litedramcore_next_state <= 2'd2; - end - 2'd2: begin - litedramcore_next_state <= 1'd0; - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value2 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); - end - end - endcase -end -always @(*) begin - litedramcore_we_next_value_ce2 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we_next_value_ce2 <= 1'd1; - end - end - endcase -end -always @(*) begin - litedramcore_wishbone_ack <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_ack <= 1'd1; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_wishbone_dat_r <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - litedramcore_wishbone_dat_r <= litedramcore_dat_r; - end - default: begin - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value0 <= 32'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; - end - endcase -end -always @(*) begin - litedramcore_dat_w_next_value_ce0 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - end - 2'd2: begin - end - default: begin - litedramcore_dat_w_next_value_ce0 <= 1'd1; - end - endcase -end -always @(*) begin - litedramcore_adr_next_value1 <= 14'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value1 <= 1'd0; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; - end - end - endcase -end -always @(*) begin - litedramcore_adr_next_value_ce1 <= 1'd0; - case (litedramcore_state) - 1'd1: begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - 2'd2: begin - end - default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr_next_value_ce1 <= 1'd1; - end - end - endcase + litedramcore_next_state <= 2'd0; + litedramcore_next_state <= litedramcore_state; + case (litedramcore_state) + 1'd1: begin + litedramcore_next_state <= 2'd2; + end + 2'd2: begin + litedramcore_next_state <= 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value2 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_we_next_value_ce2 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we_next_value_ce2 <= 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_ack <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_wishbone_dat_r <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_wishbone_dat_r <= litedramcore_dat_r; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value0 <= 32'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w; + end + endcase +end +always @(*) begin + litedramcore_dat_w_next_value_ce0 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + end + 2'd2: begin + end + default: begin + litedramcore_dat_w_next_value_ce0 <= 1'd1; + end + endcase +end +always @(*) begin + litedramcore_adr_next_value1 <= 14'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value1 <= 1'd0; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value1 <= litedramcore_wishbone_adr; + end + end + endcase +end +always @(*) begin + litedramcore_adr_next_value_ce1 <= 1'd0; + case (litedramcore_state) + 1'd1: begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + 2'd2: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr_next_value_ce1 <= 1'd1; + end + end + endcase end assign litedramcore_wishbone_adr = wb_bus_adr; assign litedramcore_wishbone_dat_w = wb_bus_dat_w; @@ -9967,201 +10187,201 @@ assign wb_bus_err = litedramcore_wishbone_err; assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_done0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_done0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_we <= (~interface0_bank_bus_we); + end end always @(*) begin - csrbank0_init_done0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin - csrbank0_init_done0_re <= interface0_bank_bus_we; - end + csrbank0_init_done0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_init_done0_re <= interface0_bank_bus_we; + end end assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; always @(*) begin - csrbank0_init_error0_re <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_re <= interface0_bank_bus_we; - end + csrbank0_init_error0_re <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_re <= interface0_bank_bus_we; + end end always @(*) begin - csrbank0_init_error0_we <= 1'd0; - if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin - csrbank0_init_error0_we <= (~interface0_bank_bus_we); - end + csrbank0_init_error0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_init_error0_we <= (~interface0_bank_bus_we); + end end assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_rst0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_re <= interface1_bank_bus_we; - end + csrbank1_rst0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_rst0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin - csrbank1_rst0_we <= (~interface1_bank_bus_we); - end + csrbank1_rst0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_rst0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_dly_sel0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); - end + csrbank1_dly_sel0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_dly_sel0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin - csrbank1_dly_sel0_re <= interface1_bank_bus_we; - end + csrbank1_dly_sel0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dly_sel0_re <= interface1_bank_bus_we; + end end assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; always @(*) begin - csrbank1_half_sys8x_taps0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); - end + csrbank1_half_sys8x_taps0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_half_sys8x_taps0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin - csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; - end + csrbank1_half_sys8x_taps0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we; + end end assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; always @(*) begin - csrbank1_wlevel_en0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_re <= interface1_bank_bus_we; - end + csrbank1_wlevel_en0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wlevel_en0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin - csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); - end + csrbank1_wlevel_en0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wlevel_strobe_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; - end + a7ddrphy_wlevel_strobe_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_wlevel_strobe_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin - a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wlevel_strobe_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin - a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_inc_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_inc_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we; + end end always @(*) begin - a7ddrphy_rdly_dq_inc_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin - a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_inc_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we); + end end assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin - a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin + a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_rdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_rdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_rdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin - a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_rdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin + a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin - a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin + a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we; + end end assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; always @(*) begin - a7ddrphy_wdly_dq_bitslip_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); - end + a7ddrphy_wdly_dq_bitslip_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we); + end end always @(*) begin - a7ddrphy_wdly_dq_bitslip_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin - a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; - end + a7ddrphy_wdly_dq_bitslip_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin + a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we; + end end assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_rdphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_rdphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_we <= (~interface1_bank_bus_we); + end end always @(*) begin - csrbank1_rdphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin - csrbank1_rdphase0_re <= interface1_bank_bus_we; - end + csrbank1_rdphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin + csrbank1_rdphase0_re <= interface1_bank_bus_we; + end end assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0]; always @(*) begin - csrbank1_wrphase0_re <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_re <= interface1_bank_bus_we; - end + csrbank1_wrphase0_re <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_re <= interface1_bank_bus_we; + end end always @(*) begin - csrbank1_wrphase0_we <= 1'd0; - if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin - csrbank1_wrphase0_we <= (~interface1_bank_bus_we); - end + csrbank1_wrphase0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin + csrbank1_wrphase0_we <= (~interface1_bank_bus_we); + end end assign csrbank1_rst0_w = a7ddrphy_rst_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; @@ -10172,328 +10392,328 @@ assign csrbank1_wrphase0_w = a7ddrphy_wrphase_storage[1:0]; assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; always @(*) begin - csrbank2_dfii_control0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_control0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_control0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin - csrbank2_dfii_control0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_control0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_dfii_control0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi0_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin - csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector0_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector0_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector0_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin - litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector0_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi0_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin - csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi0_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin - csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi0_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin - csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi0_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi0_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi0_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin - csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi0_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi1_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin - csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector1_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector1_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector1_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin - litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector1_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi1_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin - csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi1_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin - csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi1_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin - csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin + csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi1_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi1_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi1_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin - csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi1_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin + csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi2_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin - csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin + csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we; + end end assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector2_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector2_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we); + end end always @(*) begin - litedramcore_phaseinjector2_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin - litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector2_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin + litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi2_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin - csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin + csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi2_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin - csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin + csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi2_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin - csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin + csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi2_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi2_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi2_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin - csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi2_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin + csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; always @(*) begin - csrbank2_dfii_pi3_command0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_command0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_command0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin - csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin + csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we); + end end assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; always @(*) begin - litedramcore_phaseinjector3_command_issue_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; - end + litedramcore_phaseinjector3_command_issue_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we; + end end always @(*) begin - litedramcore_phaseinjector3_command_issue_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin - litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); - end + litedramcore_phaseinjector3_command_issue_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin + litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; always @(*) begin - csrbank2_dfii_pi3_address0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_address0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_address0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin - csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_address0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin + csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we; + end end assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; always @(*) begin - csrbank2_dfii_pi3_baddress0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_baddress0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_baddress0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin - csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_baddress0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin + csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_wrdata0_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_wrdata0_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we; + end end always @(*) begin - csrbank2_dfii_pi3_wrdata0_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin - csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_wrdata0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin + csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we); + end end assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; always @(*) begin - csrbank2_dfii_pi3_rddata_we <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); - end + csrbank2_dfii_pi3_rddata_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we); + end end always @(*) begin - csrbank2_dfii_pi3_rddata_re <= 1'd0; - if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin - csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; - end + csrbank2_dfii_pi3_rddata_re <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin + csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we; + end end assign litedramcore_sel = litedramcore_storage[0]; assign litedramcore_cke = litedramcore_storage[1]; @@ -10563,1194 +10783,1194 @@ assign interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); always @(*) begin - rhs_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; - end - 1'd1: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; - end - 2'd2: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; - end - 2'd3: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; - end - 3'd4: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; - end - 3'd5: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; - end - 3'd6: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; - end - default: begin - rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed1 <= 14'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed2 <= 3'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed3 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed4 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed5 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed0 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed1 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed2 <= 1'd0; - case (litedramcore_choose_cmd_grant) - 1'd0: begin - t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed6 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; - end - 1'd1: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; - end - 2'd2: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; - end - 2'd3: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; - end - 3'd4: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; - end - 3'd5: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; - end - 3'd6: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; - end - default: begin - rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; - end - endcase -end -always @(*) begin - rhs_array_muxed7 <= 14'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; - end - 1'd1: begin - rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; - end - 2'd2: begin - rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; - end - 2'd3: begin - rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; - end - 3'd4: begin - rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; - end - 3'd5: begin - rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; - end - 3'd6: begin - rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; - end - default: begin - rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; - end - endcase -end -always @(*) begin - rhs_array_muxed8 <= 3'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; - end - 1'd1: begin - rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; - end - 2'd2: begin - rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; - end - 2'd3: begin - rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; - end - 3'd4: begin - rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; - end - 3'd5: begin - rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; - end - 3'd6: begin - rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; - end - default: begin - rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; - end - endcase -end -always @(*) begin - rhs_array_muxed9 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; - end - 1'd1: begin - rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; - end - 2'd2: begin - rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; - end - 2'd3: begin - rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; - end - 3'd4: begin - rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; - end - 3'd5: begin - rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; - end - 3'd6: begin - rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; - end - default: begin - rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; - end - endcase -end -always @(*) begin - rhs_array_muxed10 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; - end - 1'd1: begin - rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; - end - 2'd2: begin - rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; - end - 2'd3: begin - rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; - end - 3'd4: begin - rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; - end - 3'd5: begin - rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; - end - 3'd6: begin - rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; - end - default: begin - rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; - end - endcase -end -always @(*) begin - rhs_array_muxed11 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; - end - 1'd1: begin - rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; - end - 2'd2: begin - rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; - end - 2'd3: begin - rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; - end - 3'd4: begin - rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; - end - 3'd5: begin - rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; - end - 3'd6: begin - rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; - end - default: begin - rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; - end - endcase -end -always @(*) begin - t_array_muxed3 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; - end - 1'd1: begin - t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; - end - 2'd2: begin - t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; - end - 2'd3: begin - t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; - end - 3'd4: begin - t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; - end - 3'd5: begin - t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; - end - 3'd6: begin - t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; - end - default: begin - t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; - end - endcase -end -always @(*) begin - t_array_muxed4 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; - end - 1'd1: begin - t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; - end - 2'd2: begin - t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; - end - 2'd3: begin - t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; - end - 3'd4: begin - t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; - end - 3'd5: begin - t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; - end - 3'd6: begin - t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; - end - default: begin - t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; - end - endcase -end -always @(*) begin - t_array_muxed5 <= 1'd0; - case (litedramcore_choose_req_grant) - 1'd0: begin - t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; - end - 1'd1: begin - t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; - end - 2'd2: begin - t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; - end - 2'd3: begin - t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; - end - 3'd4: begin - t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; - end - 3'd5: begin - t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; - end - 3'd6: begin - t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; - end - default: begin - t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed12 <= 21'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed13 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed13 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed14 <= 1'd0; - case (litedramcore_roundrobin0_grant) - default: begin - rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed15 <= 21'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed16 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed16 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed17 <= 1'd0; - case (litedramcore_roundrobin1_grant) - default: begin - rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed18 <= 21'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed19 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed19 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed20 <= 1'd0; - case (litedramcore_roundrobin2_grant) - default: begin - rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed21 <= 21'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed22 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed22 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed23 <= 1'd0; - case (litedramcore_roundrobin3_grant) - default: begin - rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase + rhs_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 <= 14'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 <= 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 <= 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 <= litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 <= 14'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 <= 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 <= 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 <= 21'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed13 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 <= 1'd0; + case (litedramcore_roundrobin0_grant) + default: begin + rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 <= 21'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed16 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 <= 1'd0; + case (litedramcore_roundrobin1_grant) + default: begin + rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 <= 21'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed19 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 <= 1'd0; + case (litedramcore_roundrobin2_grant) + default: begin + rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 <= 21'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed22 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 <= 1'd0; + case (litedramcore_roundrobin3_grant) + default: begin + rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase end always @(*) begin - rhs_array_muxed24 <= 21'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed25 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed25 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed26 <= 1'd0; - case (litedramcore_roundrobin4_grant) - default: begin - rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed27 <= 21'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed28 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed28 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed29 <= 1'd0; - case (litedramcore_roundrobin5_grant) - default: begin - rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed30 <= 21'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed31 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed31 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed32 <= 1'd0; - case (litedramcore_roundrobin6_grant) - default: begin - rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - rhs_array_muxed33 <= 21'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; - end - endcase -end -always @(*) begin - rhs_array_muxed34 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed34 <= user_port_cmd_payload_we; - end - endcase -end -always @(*) begin - rhs_array_muxed35 <= 1'd0; - case (litedramcore_roundrobin7_grant) - default: begin - rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); - end - endcase -end -always @(*) begin - array_muxed0 <= 3'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed0 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed1 <= 14'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed1 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed1 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed1 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed2 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed2 <= 1'd0; - end - 1'd1: begin - array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed3 <= 1'd0; - end - 1'd1: begin - array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed4 <= 1'd0; - end - 1'd1: begin - array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed5 <= 1'd0; - end - 1'd1: begin - array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed6 <= 1'd0; - case (litedramcore_steerer_sel0) - 1'd0: begin - array_muxed6 <= 1'd0; - end - 1'd1: begin - array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed7 <= 3'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed7 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed8 <= 14'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed8 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed8 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed8 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed9 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed9 <= 1'd0; - end - 1'd1: begin - array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed10 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed10 <= 1'd0; - end - 1'd1: begin - array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed11 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed11 <= 1'd0; - end - 1'd1: begin - array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed12 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed12 <= 1'd0; - end - 1'd1: begin - array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed13 <= 1'd0; - case (litedramcore_steerer_sel1) - 1'd0: begin - array_muxed13 <= 1'd0; - end - 1'd1: begin - array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed14 <= 3'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed14 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed15 <= 14'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed15 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed15 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed15 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed16 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed16 <= 1'd0; - end - 1'd1: begin - array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed17 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed17 <= 1'd0; - end - 1'd1: begin - array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed18 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed18 <= 1'd0; - end - 1'd1: begin - array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed19 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed19 <= 1'd0; - end - 1'd1: begin - array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed20 <= 1'd0; - case (litedramcore_steerer_sel2) - 1'd0: begin - array_muxed20 <= 1'd0; - end - 1'd1: begin - array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase -end -always @(*) begin - array_muxed21 <= 3'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed21 <= litedramcore_nop_ba[2:0]; - end - 1'd1: begin - array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; - end - 2'd2: begin - array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; - end - default: begin - array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; - end - endcase -end -always @(*) begin - array_muxed22 <= 14'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed22 <= litedramcore_nop_a; - end - 1'd1: begin - array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; - end - 2'd2: begin - array_muxed22 <= litedramcore_choose_req_cmd_payload_a; - end - default: begin - array_muxed22 <= litedramcore_cmd_payload_a; - end - endcase -end -always @(*) begin - array_muxed23 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed23 <= 1'd0; - end - 1'd1: begin - array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); - end - 2'd2: begin - array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); - end - default: begin - array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); - end - endcase -end -always @(*) begin - array_muxed24 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed24 <= 1'd0; - end - 1'd1: begin - array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); - end - 2'd2: begin - array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); - end - default: begin - array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); - end - endcase -end -always @(*) begin - array_muxed25 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed25 <= 1'd0; - end - 1'd1: begin - array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); - end - 2'd2: begin - array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); - end - default: begin - array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); - end - endcase -end -always @(*) begin - array_muxed26 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed26 <= 1'd0; - end - 1'd1: begin - array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); - end - 2'd2: begin - array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); - end - default: begin - array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); - end - endcase -end -always @(*) begin - array_muxed27 <= 1'd0; - case (litedramcore_steerer_sel3) - 1'd0: begin - array_muxed27 <= 1'd0; - end - 1'd1: begin - array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); - end - 2'd2: begin - array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); - end - default: begin - array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); - end - endcase + rhs_array_muxed24 <= 21'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed25 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 <= 1'd0; + case (litedramcore_roundrobin4_grant) + default: begin + rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 <= 21'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed28 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 <= 1'd0; + case (litedramcore_roundrobin5_grant) + default: begin + rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 <= 21'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed31 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 <= 1'd0; + case (litedramcore_roundrobin6_grant) + default: begin + rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 <= 21'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed34 <= user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 <= 1'd0; + case (litedramcore_roundrobin7_grant) + default: begin + rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 <= 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 <= 14'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 <= 1'd0; + end + 1'd1: begin + array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 <= 1'd0; + end + 1'd1: begin + array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 <= 1'd0; + end + 1'd1: begin + array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 <= 1'd0; + end + 1'd1: begin + array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 <= 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 <= 1'd0; + end + 1'd1: begin + array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 <= 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 <= 14'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 <= 1'd0; + end + 1'd1: begin + array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 <= 1'd0; + end + 1'd1: begin + array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 <= 1'd0; + end + 1'd1: begin + array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 <= 1'd0; + end + 1'd1: begin + array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 <= 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 <= 1'd0; + end + 1'd1: begin + array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 <= 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 <= 14'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 <= 1'd0; + end + 1'd1: begin + array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 <= 1'd0; + end + 1'd1: begin + array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 <= 1'd0; + end + 1'd1: begin + array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 <= 1'd0; + end + 1'd1: begin + array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 <= 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 <= 1'd0; + end + 1'd1: begin + array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 <= 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 <= litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 <= litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 <= 14'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 <= litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 <= litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 <= litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 <= 1'd0; + end + 1'd1: begin + array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 <= 1'd0; + end + 1'd1: begin + array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 <= 1'd0; + end + 1'd1: begin + array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 <= 1'd0; + end + 1'd1: begin + array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 <= 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 <= 1'd0; + end + 1'd1: begin + array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase end assign xilinxasyncresetsynchronizerimpl0 = (~locked); assign xilinxasyncresetsynchronizerimpl1 = (~locked); @@ -11763,2132 +11983,2132 @@ assign xilinxasyncresetsynchronizerimpl3 = (~locked); //------------------------------------------------------------------------------ always @(posedge iodelay_clk) begin - if ((reset_counter != 1'd0)) begin - reset_counter <= (reset_counter - 1'd1); - end else begin - ic_reset <= 1'd0; - end - if (iodelay_rst) begin - reset_counter <= 4'd15; - ic_reset <= 1'd1; - end + if ((reset_counter != 1'd0)) begin + reset_counter <= (reset_counter - 1'd1); + end else begin + ic_reset <= 1'd0; + end + if (iodelay_rst) begin + reset_counter <= 4'd15; + ic_reset <= 1'd1; + end end always @(posedge sys_clk) begin - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; - a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value0 <= 3'd7; - end - a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value0 <= 3'd7; - end - a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value1 <= 3'd7; - end - a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value1 <= 3'd7; - end - a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value2 <= 3'd7; - end - a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip0_value3 <= 3'd7; - end - a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value2 <= 3'd7; - end - a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip1_value3 <= 3'd7; - end - a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value0 <= 3'd7; - end - a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip2_value1 <= 3'd7; - end - a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value0 <= 3'd7; - end - a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip3_value1 <= 3'd7; - end - a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value0 <= 3'd7; - end - a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip4_value1 <= 3'd7; - end - a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value0 <= 3'd7; - end - a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip5_value1 <= 3'd7; - end - a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value0 <= 3'd7; - end - a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip6_value1 <= 3'd7; - end - a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value0 <= 3'd7; - end - a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip7_value1 <= 3'd7; - end - a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value0 <= 3'd7; - end - a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip8_value1 <= 3'd7; - end - a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value0 <= 3'd7; - end - a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip9_value1 <= 3'd7; - end - a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value0 <= 3'd7; - end - a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip10_value1 <= 3'd7; - end - a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value0 <= 3'd7; - end - a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip11_value1 <= 3'd7; - end - a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value0 <= 3'd7; - end - a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip12_value1 <= 3'd7; - end - a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value0 <= 3'd7; - end - a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip13_value1 <= 3'd7; - end - a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value0 <= 3'd7; - end - a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip14_value1 <= 3'd7; - end - a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value0 <= 3'd7; - end - a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; - if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin - a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); - end - if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin - a7ddrphy_bitslip15_value1 <= 3'd7; - end - a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; - a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); - a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; - a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; - a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; - a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; - a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; - a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; - a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; - a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); - a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; - a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; - if (litedramcore_csr_dfi_p0_rddata_valid) begin - litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; - end - if (litedramcore_csr_dfi_p1_rddata_valid) begin - litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; - end - if (litedramcore_csr_dfi_p2_rddata_valid) begin - litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; - end - if (litedramcore_csr_dfi_p3_rddata_valid) begin - litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; - end - if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin - litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); - end else begin - litedramcore_timer_count1 <= 10'd781; - end - litedramcore_postponer_req_o <= 1'd0; - if (litedramcore_postponer_req_i) begin - litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); - if ((litedramcore_postponer_count == 1'd0)) begin - litedramcore_postponer_count <= 1'd0; - litedramcore_postponer_req_o <= 1'd1; - end - end - if (litedramcore_sequencer_start0) begin - litedramcore_sequencer_count <= 1'd0; - end else begin - if (litedramcore_sequencer_done1) begin - if ((litedramcore_sequencer_count != 1'd0)) begin - litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); - end - end - end - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_sequencer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd1; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd0; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_sequencer_done1 <= 1'd1; - end - if ((litedramcore_sequencer_counter == 6'd35)) begin - litedramcore_sequencer_counter <= 1'd0; - end else begin - if ((litedramcore_sequencer_counter != 1'd0)) begin - litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); - end else begin - if (litedramcore_sequencer_start1) begin - litedramcore_sequencer_counter <= 1'd1; - end - end - end - if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin - litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); - end else begin - litedramcore_zqcs_timer_count1 <= 27'd99999999; - end - litedramcore_zqcs_executer_done <= 1'd0; - if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin - litedramcore_cmd_payload_a <= 11'd1024; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd1; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 2'd3)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_cmd_payload_a <= 1'd0; - litedramcore_cmd_payload_ba <= 1'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_zqcs_executer_done <= 1'd1; - end - if ((litedramcore_zqcs_executer_counter == 5'd19)) begin - litedramcore_zqcs_executer_counter <= 1'd0; - end else begin - if ((litedramcore_zqcs_executer_counter != 1'd0)) begin - litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); - end else begin - if (litedramcore_zqcs_executer_start) begin - litedramcore_zqcs_executer_counter <= 1'd1; - end - end - end - litedramcore_refresher_state <= litedramcore_refresher_next_state; - if (litedramcore_bankmachine0_row_close) begin - litedramcore_bankmachine0_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine0_row_open) begin - litedramcore_bankmachine0_row_opened <= 1'd1; - litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin - litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; - litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; - litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine0_twtpcon_valid) begin - litedramcore_bankmachine0_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_twtpcon_ready)) begin - litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine0_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trccon_valid) begin - litedramcore_bankmachine0_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trccon_ready)) begin - litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); - if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin - litedramcore_bankmachine0_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine0_trascon_valid) begin - litedramcore_bankmachine0_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine0_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); - if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin - litedramcore_bankmachine0_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; - if (litedramcore_bankmachine1_row_close) begin - litedramcore_bankmachine1_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine1_row_open) begin - litedramcore_bankmachine1_row_opened <= 1'd1; - litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin - litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; - litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; - litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine1_twtpcon_valid) begin - litedramcore_bankmachine1_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_twtpcon_ready)) begin - litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine1_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trccon_valid) begin - litedramcore_bankmachine1_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trccon_ready)) begin - litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); - if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin - litedramcore_bankmachine1_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine1_trascon_valid) begin - litedramcore_bankmachine1_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine1_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); - if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin - litedramcore_bankmachine1_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; - if (litedramcore_bankmachine2_row_close) begin - litedramcore_bankmachine2_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine2_row_open) begin - litedramcore_bankmachine2_row_opened <= 1'd1; - litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin - litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; - litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; - litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine2_twtpcon_valid) begin - litedramcore_bankmachine2_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_twtpcon_ready)) begin - litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine2_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trccon_valid) begin - litedramcore_bankmachine2_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trccon_ready)) begin - litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); - if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin - litedramcore_bankmachine2_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine2_trascon_valid) begin - litedramcore_bankmachine2_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine2_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); - if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin - litedramcore_bankmachine2_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; - if (litedramcore_bankmachine3_row_close) begin - litedramcore_bankmachine3_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine3_row_open) begin - litedramcore_bankmachine3_row_opened <= 1'd1; - litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin - litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; - litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; - litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine3_twtpcon_valid) begin - litedramcore_bankmachine3_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_twtpcon_ready)) begin - litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine3_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trccon_valid) begin - litedramcore_bankmachine3_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trccon_ready)) begin - litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); - if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin - litedramcore_bankmachine3_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine3_trascon_valid) begin - litedramcore_bankmachine3_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine3_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); - if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin - litedramcore_bankmachine3_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; - if (litedramcore_bankmachine4_row_close) begin - litedramcore_bankmachine4_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine4_row_open) begin - litedramcore_bankmachine4_row_opened <= 1'd1; - litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin - litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; - litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; - litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine4_twtpcon_valid) begin - litedramcore_bankmachine4_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_twtpcon_ready)) begin - litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine4_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trccon_valid) begin - litedramcore_bankmachine4_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trccon_ready)) begin - litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); - if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin - litedramcore_bankmachine4_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine4_trascon_valid) begin - litedramcore_bankmachine4_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine4_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); - if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin - litedramcore_bankmachine4_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; - if (litedramcore_bankmachine5_row_close) begin - litedramcore_bankmachine5_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine5_row_open) begin - litedramcore_bankmachine5_row_opened <= 1'd1; - litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin - litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; - litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; - litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine5_twtpcon_valid) begin - litedramcore_bankmachine5_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_twtpcon_ready)) begin - litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine5_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trccon_valid) begin - litedramcore_bankmachine5_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trccon_ready)) begin - litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); - if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin - litedramcore_bankmachine5_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine5_trascon_valid) begin - litedramcore_bankmachine5_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine5_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); - if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin - litedramcore_bankmachine5_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; - if (litedramcore_bankmachine6_row_close) begin - litedramcore_bankmachine6_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine6_row_open) begin - litedramcore_bankmachine6_row_opened <= 1'd1; - litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin - litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; - litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; - litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine6_twtpcon_valid) begin - litedramcore_bankmachine6_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_twtpcon_ready)) begin - litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine6_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trccon_valid) begin - litedramcore_bankmachine6_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trccon_ready)) begin - litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); - if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin - litedramcore_bankmachine6_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine6_trascon_valid) begin - litedramcore_bankmachine6_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine6_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); - if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin - litedramcore_bankmachine6_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; - if (litedramcore_bankmachine7_row_close) begin - litedramcore_bankmachine7_row_opened <= 1'd0; - end else begin - if (litedramcore_bankmachine7_row_open) begin - litedramcore_bankmachine7_row_opened <= 1'd1; - litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; - end - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); - end - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); - end - if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin - if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); - end - end else begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); - end - end - if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin - litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; - litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; - litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; - end - if (litedramcore_bankmachine7_twtpcon_valid) begin - litedramcore_bankmachine7_twtpcon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_twtpcon_ready)) begin - litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); - if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin - litedramcore_bankmachine7_twtpcon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trccon_valid) begin - litedramcore_bankmachine7_trccon_count <= 3'd5; - if (1'd0) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trccon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trccon_ready)) begin - litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); - if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin - litedramcore_bankmachine7_trccon_ready <= 1'd1; - end - end - end - if (litedramcore_bankmachine7_trascon_valid) begin - litedramcore_bankmachine7_trascon_count <= 3'd4; - if (1'd0) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end else begin - litedramcore_bankmachine7_trascon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); - if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin - litedramcore_bankmachine7_trascon_ready <= 1'd1; - end - end - end - litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; - if ((~litedramcore_en0)) begin - litedramcore_time0 <= 5'd31; - end else begin - if ((~litedramcore_max_time0)) begin - litedramcore_time0 <= (litedramcore_time0 - 1'd1); - end - end - if ((~litedramcore_en1)) begin - litedramcore_time1 <= 4'd15; - end else begin - if ((~litedramcore_max_time1)) begin - litedramcore_time1 <= (litedramcore_time1 - 1'd1); - end - end - if (litedramcore_choose_cmd_ce) begin - case (litedramcore_choose_cmd_grant) - 1'd0: begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end else begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_cmd_request[7]) begin - litedramcore_choose_cmd_grant <= 3'd7; - end else begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_cmd_request[0]) begin - litedramcore_choose_cmd_grant <= 1'd0; - end else begin - if (litedramcore_choose_cmd_request[1]) begin - litedramcore_choose_cmd_grant <= 1'd1; - end else begin - if (litedramcore_choose_cmd_request[2]) begin - litedramcore_choose_cmd_grant <= 2'd2; - end else begin - if (litedramcore_choose_cmd_request[3]) begin - litedramcore_choose_cmd_grant <= 2'd3; - end else begin - if (litedramcore_choose_cmd_request[4]) begin - litedramcore_choose_cmd_grant <= 3'd4; - end else begin - if (litedramcore_choose_cmd_request[5]) begin - litedramcore_choose_cmd_grant <= 3'd5; - end else begin - if (litedramcore_choose_cmd_request[6]) begin - litedramcore_choose_cmd_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - if (litedramcore_choose_req_ce) begin - case (litedramcore_choose_req_grant) - 1'd0: begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end - end - end - end - end - end - end - end - 1'd1: begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end - end - end - end - end - end - end - end - 2'd2: begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end - end - end - end - end - end - end - end - 2'd3: begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end - end - end - end - end - end - end - end - 3'd4: begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end - end - end - end - end - end - end - end - 3'd5: begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end else begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end - end - end - end - end - end - end - end - 3'd6: begin - if (litedramcore_choose_req_request[7]) begin - litedramcore_choose_req_grant <= 3'd7; - end else begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end - end - end - end - end - end - end - end - 3'd7: begin - if (litedramcore_choose_req_request[0]) begin - litedramcore_choose_req_grant <= 1'd0; - end else begin - if (litedramcore_choose_req_request[1]) begin - litedramcore_choose_req_grant <= 1'd1; - end else begin - if (litedramcore_choose_req_request[2]) begin - litedramcore_choose_req_grant <= 2'd2; - end else begin - if (litedramcore_choose_req_request[3]) begin - litedramcore_choose_req_grant <= 2'd3; - end else begin - if (litedramcore_choose_req_request[4]) begin - litedramcore_choose_req_grant <= 3'd4; - end else begin - if (litedramcore_choose_req_request[5]) begin - litedramcore_choose_req_grant <= 3'd5; - end else begin - if (litedramcore_choose_req_request[6]) begin - litedramcore_choose_req_grant <= 3'd6; - end - end - end - end - end - end - end - end - endcase - end - litedramcore_dfi_p0_cs_n <= 1'd0; - litedramcore_dfi_p0_bank <= array_muxed0; - litedramcore_dfi_p0_address <= array_muxed1; - litedramcore_dfi_p0_cas_n <= (~array_muxed2); - litedramcore_dfi_p0_ras_n <= (~array_muxed3); - litedramcore_dfi_p0_we_n <= (~array_muxed4); - litedramcore_dfi_p0_rddata_en <= array_muxed5; - litedramcore_dfi_p0_wrdata_en <= array_muxed6; - litedramcore_dfi_p1_cs_n <= 1'd0; - litedramcore_dfi_p1_bank <= array_muxed7; - litedramcore_dfi_p1_address <= array_muxed8; - litedramcore_dfi_p1_cas_n <= (~array_muxed9); - litedramcore_dfi_p1_ras_n <= (~array_muxed10); - litedramcore_dfi_p1_we_n <= (~array_muxed11); - litedramcore_dfi_p1_rddata_en <= array_muxed12; - litedramcore_dfi_p1_wrdata_en <= array_muxed13; - litedramcore_dfi_p2_cs_n <= 1'd0; - litedramcore_dfi_p2_bank <= array_muxed14; - litedramcore_dfi_p2_address <= array_muxed15; - litedramcore_dfi_p2_cas_n <= (~array_muxed16); - litedramcore_dfi_p2_ras_n <= (~array_muxed17); - litedramcore_dfi_p2_we_n <= (~array_muxed18); - litedramcore_dfi_p2_rddata_en <= array_muxed19; - litedramcore_dfi_p2_wrdata_en <= array_muxed20; - litedramcore_dfi_p3_cs_n <= 1'd0; - litedramcore_dfi_p3_bank <= array_muxed21; - litedramcore_dfi_p3_address <= array_muxed22; - litedramcore_dfi_p3_cas_n <= (~array_muxed23); - litedramcore_dfi_p3_ras_n <= (~array_muxed24); - litedramcore_dfi_p3_we_n <= (~array_muxed25); - litedramcore_dfi_p3_rddata_en <= array_muxed26; - litedramcore_dfi_p3_wrdata_en <= array_muxed27; - if (litedramcore_trrdcon_valid) begin - litedramcore_trrdcon_count <= 1'd1; - if (1'd0) begin - litedramcore_trrdcon_ready <= 1'd1; - end else begin - litedramcore_trrdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_trrdcon_ready)) begin - litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); - if ((litedramcore_trrdcon_count == 1'd1)) begin - litedramcore_trrdcon_ready <= 1'd1; - end - end - end - litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; - if ((litedramcore_tfawcon_count < 3'd4)) begin - if ((litedramcore_tfawcon_count == 2'd3)) begin - litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); - end else begin - litedramcore_tfawcon_ready <= 1'd1; - end - end - if (litedramcore_tccdcon_valid) begin - litedramcore_tccdcon_count <= 1'd0; - if (1'd1) begin - litedramcore_tccdcon_ready <= 1'd1; - end else begin - litedramcore_tccdcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_tccdcon_ready)) begin - litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); - if ((litedramcore_tccdcon_count == 1'd1)) begin - litedramcore_tccdcon_ready <= 1'd1; - end - end - end - if (litedramcore_twtrcon_valid) begin - litedramcore_twtrcon_count <= 3'd4; - if (1'd0) begin - litedramcore_twtrcon_ready <= 1'd1; - end else begin - litedramcore_twtrcon_ready <= 1'd0; - end - end else begin - if ((~litedramcore_twtrcon_ready)) begin - litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); - if ((litedramcore_twtrcon_count == 1'd1)) begin - litedramcore_twtrcon_ready <= 1'd1; - end - end - end - litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; - litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); - litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; - litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); - litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; - litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; - litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; - litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; - litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; - litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; - litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; - litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; - litedramcore_state <= litedramcore_next_state; - if (litedramcore_dat_w_next_value_ce0) begin - litedramcore_dat_w <= litedramcore_dat_w_next_value0; - end - if (litedramcore_adr_next_value_ce1) begin - litedramcore_adr <= litedramcore_adr_next_value1; - end - if (litedramcore_we_next_value_ce2) begin - litedramcore_we <= litedramcore_we_next_value2; - end - interface0_bank_bus_dat_r <= 1'd0; - if (csrbank0_sel) begin - case (interface0_bank_bus_adr[8:0]) - 1'd0: begin - interface0_bank_bus_dat_r <= csrbank0_init_done0_w; - end - 1'd1: begin - interface0_bank_bus_dat_r <= csrbank0_init_error0_w; - end - endcase - end - if (csrbank0_init_done0_re) begin - init_done_storage <= csrbank0_init_done0_r; - end - init_done_re <= csrbank0_init_done0_re; - if (csrbank0_init_error0_re) begin - init_error_storage <= csrbank0_init_error0_r; - end - init_error_re <= csrbank0_init_error0_re; - interface1_bank_bus_dat_r <= 1'd0; - if (csrbank1_sel) begin - case (interface1_bank_bus_adr[8:0]) - 1'd0: begin - interface1_bank_bus_dat_r <= csrbank1_rst0_w; - end - 1'd1: begin - interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; - end - 2'd2: begin - interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; - end - 2'd3: begin - interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; - end - 3'd4: begin - interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; - end - 3'd5: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; - end - 3'd6: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; - end - 3'd7: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; - end - 4'd8: begin - interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; - end - 4'd9: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; - end - 4'd10: begin - interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; - end - 4'd11: begin - interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; - end - 4'd12: begin - interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; - end - endcase - end - if (csrbank1_rst0_re) begin - a7ddrphy_rst_storage <= csrbank1_rst0_r; - end - a7ddrphy_rst_re <= csrbank1_rst0_re; - if (csrbank1_dly_sel0_re) begin - a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; - end - a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; - if (csrbank1_half_sys8x_taps0_re) begin - a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; - end - a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; - if (csrbank1_wlevel_en0_re) begin - a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; - end - a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; - if (csrbank1_rdphase0_re) begin - a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; - end - a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; - if (csrbank1_wrphase0_re) begin - a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; - end - a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; - interface2_bank_bus_dat_r <= 1'd0; - if (csrbank2_sel) begin - case (interface2_bank_bus_adr[8:0]) - 1'd0: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; - end - 1'd1: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; - end - 2'd2: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; - end - 2'd3: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; - end - 3'd4: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; - end - 3'd5: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; - end - 3'd6: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; - end - 3'd7: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; - end - 4'd8: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; - end - 4'd9: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; - end - 4'd10: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; - end - 4'd11: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; - end - 4'd12: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; - end - 4'd13: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; - end - 4'd14: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; - end - 4'd15: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; - end - 5'd16: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; - end - 5'd17: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; - end - 5'd18: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; - end - 5'd19: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; - end - 5'd20: begin - interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; - end - 5'd21: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; - end - 5'd22: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; - end - 5'd23: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; - end - 5'd24: begin - interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; - end - endcase - end - if (csrbank2_dfii_control0_re) begin - litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; - end - litedramcore_re <= csrbank2_dfii_control0_re; - if (csrbank2_dfii_pi0_command0_re) begin - litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; - end - litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; - if (csrbank2_dfii_pi0_address0_re) begin - litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; - end - litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; - if (csrbank2_dfii_pi0_baddress0_re) begin - litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; - end - litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; - if (csrbank2_dfii_pi0_wrdata0_re) begin - litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; - end - litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; - litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; - if (csrbank2_dfii_pi1_command0_re) begin - litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; - end - litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; - if (csrbank2_dfii_pi1_address0_re) begin - litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; - end - litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; - if (csrbank2_dfii_pi1_baddress0_re) begin - litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; - end - litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; - if (csrbank2_dfii_pi1_wrdata0_re) begin - litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; - end - litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; - litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; - if (csrbank2_dfii_pi2_command0_re) begin - litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; - end - litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; - if (csrbank2_dfii_pi2_address0_re) begin - litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; - end - litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; - if (csrbank2_dfii_pi2_baddress0_re) begin - litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; - end - litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; - if (csrbank2_dfii_pi2_wrdata0_re) begin - litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; - end - litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; - litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; - if (csrbank2_dfii_pi3_command0_re) begin - litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; - end - litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; - if (csrbank2_dfii_pi3_address0_re) begin - litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; - end - litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; - if (csrbank2_dfii_pi3_baddress0_re) begin - litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; - end - litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; - if (csrbank2_dfii_pi3_wrdata0_re) begin - litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; - end - litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; - litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; - if (sys_rst) begin - a7ddrphy_rst_storage <= 1'd0; - a7ddrphy_rst_re <= 1'd0; - a7ddrphy_dly_sel_storage <= 2'd0; - a7ddrphy_dly_sel_re <= 1'd0; - a7ddrphy_half_sys8x_taps_storage <= 5'd8; - a7ddrphy_half_sys8x_taps_re <= 1'd0; - a7ddrphy_wlevel_en_storage <= 1'd0; - a7ddrphy_wlevel_en_re <= 1'd0; - a7ddrphy_rdphase_storage <= 2'd2; - a7ddrphy_rdphase_re <= 1'd0; - a7ddrphy_wrphase_storage <= 2'd3; - a7ddrphy_wrphase_re <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_dqspattern_o1 <= 8'd0; - a7ddrphy_bitslip0_value0 <= 3'd7; - a7ddrphy_bitslip1_value0 <= 3'd7; - a7ddrphy_bitslip0_value1 <= 3'd7; - a7ddrphy_bitslip1_value1 <= 3'd7; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; - a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; - a7ddrphy_bitslip0_value2 <= 3'd7; - a7ddrphy_bitslip0_value3 <= 3'd7; - a7ddrphy_bitslip1_value2 <= 3'd7; - a7ddrphy_bitslip1_value3 <= 3'd7; - a7ddrphy_bitslip2_value0 <= 3'd7; - a7ddrphy_bitslip2_value1 <= 3'd7; - a7ddrphy_bitslip3_value0 <= 3'd7; - a7ddrphy_bitslip3_value1 <= 3'd7; - a7ddrphy_bitslip4_value0 <= 3'd7; - a7ddrphy_bitslip4_value1 <= 3'd7; - a7ddrphy_bitslip5_value0 <= 3'd7; - a7ddrphy_bitslip5_value1 <= 3'd7; - a7ddrphy_bitslip6_value0 <= 3'd7; - a7ddrphy_bitslip6_value1 <= 3'd7; - a7ddrphy_bitslip7_value0 <= 3'd7; - a7ddrphy_bitslip7_value1 <= 3'd7; - a7ddrphy_bitslip8_value0 <= 3'd7; - a7ddrphy_bitslip8_value1 <= 3'd7; - a7ddrphy_bitslip9_value0 <= 3'd7; - a7ddrphy_bitslip9_value1 <= 3'd7; - a7ddrphy_bitslip10_value0 <= 3'd7; - a7ddrphy_bitslip10_value1 <= 3'd7; - a7ddrphy_bitslip11_value0 <= 3'd7; - a7ddrphy_bitslip11_value1 <= 3'd7; - a7ddrphy_bitslip12_value0 <= 3'd7; - a7ddrphy_bitslip12_value1 <= 3'd7; - a7ddrphy_bitslip13_value0 <= 3'd7; - a7ddrphy_bitslip13_value1 <= 3'd7; - a7ddrphy_bitslip14_value0 <= 3'd7; - a7ddrphy_bitslip14_value1 <= 3'd7; - a7ddrphy_bitslip15_value0 <= 3'd7; - a7ddrphy_bitslip15_value1 <= 3'd7; - a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; - a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; - a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; - litedramcore_storage <= 4'd1; - litedramcore_re <= 1'd0; - litedramcore_phaseinjector0_command_storage <= 6'd0; - litedramcore_phaseinjector0_command_re <= 1'd0; - litedramcore_phaseinjector0_address_re <= 1'd0; - litedramcore_phaseinjector0_baddress_re <= 1'd0; - litedramcore_phaseinjector0_wrdata_re <= 1'd0; - litedramcore_phaseinjector0_rddata_status <= 32'd0; - litedramcore_phaseinjector0_rddata_re <= 1'd0; - litedramcore_phaseinjector1_command_storage <= 6'd0; - litedramcore_phaseinjector1_command_re <= 1'd0; - litedramcore_phaseinjector1_address_re <= 1'd0; - litedramcore_phaseinjector1_baddress_re <= 1'd0; - litedramcore_phaseinjector1_wrdata_re <= 1'd0; - litedramcore_phaseinjector1_rddata_status <= 32'd0; - litedramcore_phaseinjector1_rddata_re <= 1'd0; - litedramcore_phaseinjector2_command_storage <= 6'd0; - litedramcore_phaseinjector2_command_re <= 1'd0; - litedramcore_phaseinjector2_address_re <= 1'd0; - litedramcore_phaseinjector2_baddress_re <= 1'd0; - litedramcore_phaseinjector2_wrdata_re <= 1'd0; - litedramcore_phaseinjector2_rddata_status <= 32'd0; - litedramcore_phaseinjector2_rddata_re <= 1'd0; - litedramcore_phaseinjector3_command_storage <= 6'd0; - litedramcore_phaseinjector3_command_re <= 1'd0; - litedramcore_phaseinjector3_address_re <= 1'd0; - litedramcore_phaseinjector3_baddress_re <= 1'd0; - litedramcore_phaseinjector3_wrdata_re <= 1'd0; - litedramcore_phaseinjector3_rddata_status <= 32'd0; - litedramcore_phaseinjector3_rddata_re <= 1'd0; - litedramcore_dfi_p0_address <= 14'd0; - litedramcore_dfi_p0_bank <= 3'd0; - litedramcore_dfi_p0_cas_n <= 1'd1; - litedramcore_dfi_p0_cs_n <= 1'd1; - litedramcore_dfi_p0_ras_n <= 1'd1; - litedramcore_dfi_p0_we_n <= 1'd1; - litedramcore_dfi_p0_wrdata_en <= 1'd0; - litedramcore_dfi_p0_rddata_en <= 1'd0; - litedramcore_dfi_p1_address <= 14'd0; - litedramcore_dfi_p1_bank <= 3'd0; - litedramcore_dfi_p1_cas_n <= 1'd1; - litedramcore_dfi_p1_cs_n <= 1'd1; - litedramcore_dfi_p1_ras_n <= 1'd1; - litedramcore_dfi_p1_we_n <= 1'd1; - litedramcore_dfi_p1_wrdata_en <= 1'd0; - litedramcore_dfi_p1_rddata_en <= 1'd0; - litedramcore_dfi_p2_address <= 14'd0; - litedramcore_dfi_p2_bank <= 3'd0; - litedramcore_dfi_p2_cas_n <= 1'd1; - litedramcore_dfi_p2_cs_n <= 1'd1; - litedramcore_dfi_p2_ras_n <= 1'd1; - litedramcore_dfi_p2_we_n <= 1'd1; - litedramcore_dfi_p2_wrdata_en <= 1'd0; - litedramcore_dfi_p2_rddata_en <= 1'd0; - litedramcore_dfi_p3_address <= 14'd0; - litedramcore_dfi_p3_bank <= 3'd0; - litedramcore_dfi_p3_cas_n <= 1'd1; - litedramcore_dfi_p3_cs_n <= 1'd1; - litedramcore_dfi_p3_ras_n <= 1'd1; - litedramcore_dfi_p3_we_n <= 1'd1; - litedramcore_dfi_p3_wrdata_en <= 1'd0; - litedramcore_dfi_p3_rddata_en <= 1'd0; - litedramcore_cmd_payload_a <= 14'd0; - litedramcore_cmd_payload_ba <= 3'd0; - litedramcore_cmd_payload_cas <= 1'd0; - litedramcore_cmd_payload_ras <= 1'd0; - litedramcore_cmd_payload_we <= 1'd0; - litedramcore_timer_count1 <= 10'd781; - litedramcore_postponer_req_o <= 1'd0; - litedramcore_postponer_count <= 1'd0; - litedramcore_sequencer_done1 <= 1'd0; - litedramcore_sequencer_counter <= 6'd0; - litedramcore_sequencer_count <= 1'd0; - litedramcore_zqcs_timer_count1 <= 27'd99999999; - litedramcore_zqcs_executer_done <= 1'd0; - litedramcore_zqcs_executer_counter <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine0_row <= 14'd0; - litedramcore_bankmachine0_row_opened <= 1'd0; - litedramcore_bankmachine0_twtpcon_ready <= 1'd0; - litedramcore_bankmachine0_twtpcon_count <= 3'd0; - litedramcore_bankmachine0_trccon_ready <= 1'd0; - litedramcore_bankmachine0_trccon_count <= 3'd0; - litedramcore_bankmachine0_trascon_ready <= 1'd0; - litedramcore_bankmachine0_trascon_count <= 3'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine1_row <= 14'd0; - litedramcore_bankmachine1_row_opened <= 1'd0; - litedramcore_bankmachine1_twtpcon_ready <= 1'd0; - litedramcore_bankmachine1_twtpcon_count <= 3'd0; - litedramcore_bankmachine1_trccon_ready <= 1'd0; - litedramcore_bankmachine1_trccon_count <= 3'd0; - litedramcore_bankmachine1_trascon_ready <= 1'd0; - litedramcore_bankmachine1_trascon_count <= 3'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine2_row <= 14'd0; - litedramcore_bankmachine2_row_opened <= 1'd0; - litedramcore_bankmachine2_twtpcon_ready <= 1'd0; - litedramcore_bankmachine2_twtpcon_count <= 3'd0; - litedramcore_bankmachine2_trccon_ready <= 1'd0; - litedramcore_bankmachine2_trccon_count <= 3'd0; - litedramcore_bankmachine2_trascon_ready <= 1'd0; - litedramcore_bankmachine2_trascon_count <= 3'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine3_row <= 14'd0; - litedramcore_bankmachine3_row_opened <= 1'd0; - litedramcore_bankmachine3_twtpcon_ready <= 1'd0; - litedramcore_bankmachine3_twtpcon_count <= 3'd0; - litedramcore_bankmachine3_trccon_ready <= 1'd0; - litedramcore_bankmachine3_trccon_count <= 3'd0; - litedramcore_bankmachine3_trascon_ready <= 1'd0; - litedramcore_bankmachine3_trascon_count <= 3'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine4_row <= 14'd0; - litedramcore_bankmachine4_row_opened <= 1'd0; - litedramcore_bankmachine4_twtpcon_ready <= 1'd0; - litedramcore_bankmachine4_twtpcon_count <= 3'd0; - litedramcore_bankmachine4_trccon_ready <= 1'd0; - litedramcore_bankmachine4_trccon_count <= 3'd0; - litedramcore_bankmachine4_trascon_ready <= 1'd0; - litedramcore_bankmachine4_trascon_count <= 3'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine5_row <= 14'd0; - litedramcore_bankmachine5_row_opened <= 1'd0; - litedramcore_bankmachine5_twtpcon_ready <= 1'd0; - litedramcore_bankmachine5_twtpcon_count <= 3'd0; - litedramcore_bankmachine5_trccon_ready <= 1'd0; - litedramcore_bankmachine5_trccon_count <= 3'd0; - litedramcore_bankmachine5_trascon_ready <= 1'd0; - litedramcore_bankmachine5_trascon_count <= 3'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine6_row <= 14'd0; - litedramcore_bankmachine6_row_opened <= 1'd0; - litedramcore_bankmachine6_twtpcon_ready <= 1'd0; - litedramcore_bankmachine6_twtpcon_count <= 3'd0; - litedramcore_bankmachine6_trccon_ready <= 1'd0; - litedramcore_bankmachine6_trccon_count <= 3'd0; - litedramcore_bankmachine6_trascon_ready <= 1'd0; - litedramcore_bankmachine6_trascon_count <= 3'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; - litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; - litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; - litedramcore_bankmachine7_row <= 14'd0; - litedramcore_bankmachine7_row_opened <= 1'd0; - litedramcore_bankmachine7_twtpcon_ready <= 1'd0; - litedramcore_bankmachine7_twtpcon_count <= 3'd0; - litedramcore_bankmachine7_trccon_ready <= 1'd0; - litedramcore_bankmachine7_trccon_count <= 3'd0; - litedramcore_bankmachine7_trascon_ready <= 1'd0; - litedramcore_bankmachine7_trascon_count <= 3'd0; - litedramcore_choose_cmd_grant <= 3'd0; - litedramcore_choose_req_grant <= 3'd0; - litedramcore_trrdcon_ready <= 1'd0; - litedramcore_trrdcon_count <= 1'd0; - litedramcore_tfawcon_ready <= 1'd1; - litedramcore_tfawcon_window <= 5'd0; - litedramcore_tccdcon_ready <= 1'd0; - litedramcore_tccdcon_count <= 1'd0; - litedramcore_twtrcon_ready <= 1'd0; - litedramcore_twtrcon_count <= 3'd0; - litedramcore_time0 <= 5'd0; - litedramcore_time1 <= 4'd0; - init_done_storage <= 1'd0; - init_done_re <= 1'd0; - init_error_storage <= 1'd0; - init_error_re <= 1'd0; - litedramcore_we <= 1'd0; - litedramcore_refresher_state <= 2'd0; - litedramcore_bankmachine0_state <= 4'd0; - litedramcore_bankmachine1_state <= 4'd0; - litedramcore_bankmachine2_state <= 4'd0; - litedramcore_bankmachine3_state <= 4'd0; - litedramcore_bankmachine4_state <= 4'd0; - litedramcore_bankmachine5_state <= 4'd0; - litedramcore_bankmachine6_state <= 4'd0; - litedramcore_bankmachine7_state <= 4'd0; - litedramcore_multiplexer_state <= 4'd0; - litedramcore_new_master_wdata_ready0 <= 1'd0; - litedramcore_new_master_wdata_ready1 <= 1'd0; - litedramcore_new_master_rdata_valid0 <= 1'd0; - litedramcore_new_master_rdata_valid1 <= 1'd0; - litedramcore_new_master_rdata_valid2 <= 1'd0; - litedramcore_new_master_rdata_valid3 <= 1'd0; - litedramcore_new_master_rdata_valid4 <= 1'd0; - litedramcore_new_master_rdata_valid5 <= 1'd0; - litedramcore_new_master_rdata_valid6 <= 1'd0; - litedramcore_new_master_rdata_valid7 <= 1'd0; - litedramcore_new_master_rdata_valid8 <= 1'd0; - litedramcore_state <= 2'd0; - end + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0; + a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value0 <= 3'd7; + end + a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value0 <= 3'd7; + end + a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value1 <= 3'd7; + end + a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value1 <= 3'd7; + end + a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]}; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value2 <= 3'd7; + end + a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip0_value3 <= 3'd7; + end + a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value2 <= 3'd7; + end + a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip1_value3 <= 3'd7; + end + a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value0 <= 3'd7; + end + a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip2_value1 <= 3'd7; + end + a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value0 <= 3'd7; + end + a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip3_value1 <= 3'd7; + end + a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value0 <= 3'd7; + end + a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip4_value1 <= 3'd7; + end + a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value0 <= 3'd7; + end + a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip5_value1 <= 3'd7; + end + a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value0 <= 3'd7; + end + a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip6_value1 <= 3'd7; + end + a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value0 <= 3'd7; + end + a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip7_value1 <= 3'd7; + end + a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value0 <= 3'd7; + end + a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip8_value1 <= 3'd7; + end + a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value0 <= 3'd7; + end + a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip9_value1 <= 3'd7; + end + a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value0 <= 3'd7; + end + a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip10_value1 <= 3'd7; + end + a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value0 <= 3'd7; + end + a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip11_value1 <= 3'd7; + end + a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value0 <= 3'd7; + end + a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip12_value1 <= 3'd7; + end + a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value0 <= 3'd7; + end + a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip13_value1 <= 3'd7; + end + a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value0 <= 3'd7; + end + a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip14_value1 <= 3'd7; + end + a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value0 <= 3'd7; + end + a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]}; + if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin + a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1); + end + if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin + a7ddrphy_bitslip15_value1 <= 3'd7; + end + a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]}; + a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en); + a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0; + a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1; + a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2; + a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3; + a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4; + a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5; + a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6; + a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en); + a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0; + a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1; + if (litedramcore_csr_dfi_p0_rddata_valid) begin + litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata; + end + if (litedramcore_csr_dfi_p1_rddata_valid) begin + litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata; + end + if (litedramcore_csr_dfi_p2_rddata_valid) begin + litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata; + end + if (litedramcore_csr_dfi_p3_rddata_valid) begin + litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + litedramcore_refresher_state <= litedramcore_refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1); + end + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1); + end + if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin + if ((~litedramcore_bankmachine0_do_read)) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_do_read) begin + litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin + litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid; + litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first; + litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1); + end + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1); + end + if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin + if ((~litedramcore_bankmachine1_do_read)) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_do_read) begin + litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin + litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid; + litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first; + litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1); + end + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1); + end + if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin + if ((~litedramcore_bankmachine2_do_read)) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_do_read) begin + litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin + litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid; + litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first; + litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1); + end + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1); + end + if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin + if ((~litedramcore_bankmachine3_do_read)) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_do_read) begin + litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin + litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid; + litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first; + litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1); + end + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1); + end + if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin + if ((~litedramcore_bankmachine4_do_read)) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_do_read) begin + litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin + litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid; + litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first; + litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1); + end + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1); + end + if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin + if ((~litedramcore_bankmachine5_do_read)) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_do_read) begin + litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin + litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid; + litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first; + litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1); + end + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1); + end + if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin + if ((~litedramcore_bankmachine6_do_read)) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_do_read) begin + litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin + litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid; + litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first; + litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1); + end + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1); + end + if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin + if ((~litedramcore_bankmachine7_do_read)) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_do_read) begin + litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin + litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid; + litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first; + litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state; + litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0; + litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0; + litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1; + litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2; + litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3; + litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4; + litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5; + litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6; + litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7; + litedramcore_state <= litedramcore_next_state; + if (litedramcore_dat_w_next_value_ce0) begin + litedramcore_dat_w <= litedramcore_dat_w_next_value0; + end + if (litedramcore_adr_next_value_ce1) begin + litedramcore_adr <= litedramcore_adr_next_value1; + end + if (litedramcore_we_next_value_ce2) begin + litedramcore_we <= litedramcore_we_next_value2; + end + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_rst0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_rdphase0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_wrphase0_w; + end + endcase + end + if (csrbank1_rst0_re) begin + a7ddrphy_rst_storage <= csrbank1_rst0_r; + end + a7ddrphy_rst_re <= csrbank1_rst0_re; + if (csrbank1_dly_sel0_re) begin + a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r; + end + a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; + if (csrbank1_half_sys8x_taps0_re) begin + a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r; + end + a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re; + if (csrbank1_wlevel_en0_re) begin + a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r; + end + a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re; + if (csrbank1_rdphase0_re) begin + a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r; + end + a7ddrphy_rdphase_re <= csrbank1_rdphase0_re; + if (csrbank1_wrphase0_re) begin + a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r; + end + a7ddrphy_wrphase_re <= csrbank1_wrphase0_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w; + end + 4'd13: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w; + end + 4'd14: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w; + end + 5'd16: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w; + end + 5'd19: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w; + end + 5'd20: begin + interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w; + end + 5'd22: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank2_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank2_dfii_control0_r; + end + litedramcore_re <= csrbank2_dfii_control0_re; + if (csrbank2_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re; + if (csrbank2_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re; + if (csrbank2_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re; + if (csrbank2_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re; + litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re; + if (csrbank2_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re; + if (csrbank2_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re; + if (csrbank2_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re; + if (csrbank2_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re; + litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re; + if (csrbank2_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re; + if (csrbank2_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re; + if (csrbank2_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re; + if (csrbank2_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re; + litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re; + if (csrbank2_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re; + if (csrbank2_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re; + if (csrbank2_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re; + if (csrbank2_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re; + litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re; + if (sys_rst) begin + a7ddrphy_rst_storage <= 1'd0; + a7ddrphy_rst_re <= 1'd0; + a7ddrphy_dly_sel_storage <= 2'd0; + a7ddrphy_dly_sel_re <= 1'd0; + a7ddrphy_half_sys8x_taps_storage <= 5'd8; + a7ddrphy_half_sys8x_taps_re <= 1'd0; + a7ddrphy_wlevel_en_storage <= 1'd0; + a7ddrphy_wlevel_en_re <= 1'd0; + a7ddrphy_rdphase_storage <= 2'd2; + a7ddrphy_rdphase_re <= 1'd0; + a7ddrphy_wrphase_storage <= 2'd3; + a7ddrphy_wrphase_re <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_dqspattern_o1 <= 8'd0; + a7ddrphy_bitslip0_value0 <= 3'd7; + a7ddrphy_bitslip1_value0 <= 3'd7; + a7ddrphy_bitslip0_value1 <= 3'd7; + a7ddrphy_bitslip1_value1 <= 3'd7; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0; + a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0; + a7ddrphy_bitslip0_value2 <= 3'd7; + a7ddrphy_bitslip0_value3 <= 3'd7; + a7ddrphy_bitslip1_value2 <= 3'd7; + a7ddrphy_bitslip1_value3 <= 3'd7; + a7ddrphy_bitslip2_value0 <= 3'd7; + a7ddrphy_bitslip2_value1 <= 3'd7; + a7ddrphy_bitslip3_value0 <= 3'd7; + a7ddrphy_bitslip3_value1 <= 3'd7; + a7ddrphy_bitslip4_value0 <= 3'd7; + a7ddrphy_bitslip4_value1 <= 3'd7; + a7ddrphy_bitslip5_value0 <= 3'd7; + a7ddrphy_bitslip5_value1 <= 3'd7; + a7ddrphy_bitslip6_value0 <= 3'd7; + a7ddrphy_bitslip6_value1 <= 3'd7; + a7ddrphy_bitslip7_value0 <= 3'd7; + a7ddrphy_bitslip7_value1 <= 3'd7; + a7ddrphy_bitslip8_value0 <= 3'd7; + a7ddrphy_bitslip8_value1 <= 3'd7; + a7ddrphy_bitslip9_value0 <= 3'd7; + a7ddrphy_bitslip9_value1 <= 3'd7; + a7ddrphy_bitslip10_value0 <= 3'd7; + a7ddrphy_bitslip10_value1 <= 3'd7; + a7ddrphy_bitslip11_value0 <= 3'd7; + a7ddrphy_bitslip11_value1 <= 3'd7; + a7ddrphy_bitslip12_value0 <= 3'd7; + a7ddrphy_bitslip12_value1 <= 3'd7; + a7ddrphy_bitslip13_value0 <= 3'd7; + a7ddrphy_bitslip13_value1 <= 3'd7; + a7ddrphy_bitslip14_value0 <= 3'd7; + a7ddrphy_bitslip14_value1 <= 3'd7; + a7ddrphy_bitslip15_value0 <= 3'd7; + a7ddrphy_bitslip15_value1 <= 3'd7; + a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0; + a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0; + a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_rddata_status <= 32'd0; + litedramcore_phaseinjector0_rddata_re <= 1'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_rddata_status <= 32'd0; + litedramcore_phaseinjector1_rddata_re <= 1'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_rddata_status <= 32'd0; + litedramcore_phaseinjector2_rddata_re <= 1'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_rddata_status <= 32'd0; + litedramcore_phaseinjector3_rddata_re <= 1'd0; + litedramcore_dfi_p0_address <= 14'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 14'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 14'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 14'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_cmd_payload_a <= 14'd0; + litedramcore_cmd_payload_ba <= 3'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_level <= 5'd0; + litedramcore_bankmachine0_produce <= 4'd0; + litedramcore_bankmachine0_consume <= 4'd0; + litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine0_row <= 14'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_level <= 5'd0; + litedramcore_bankmachine1_produce <= 4'd0; + litedramcore_bankmachine1_consume <= 4'd0; + litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine1_row <= 14'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_level <= 5'd0; + litedramcore_bankmachine2_produce <= 4'd0; + litedramcore_bankmachine2_consume <= 4'd0; + litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine2_row <= 14'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_level <= 5'd0; + litedramcore_bankmachine3_produce <= 4'd0; + litedramcore_bankmachine3_consume <= 4'd0; + litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine3_row <= 14'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_level <= 5'd0; + litedramcore_bankmachine4_produce <= 4'd0; + litedramcore_bankmachine4_consume <= 4'd0; + litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine4_row <= 14'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_level <= 5'd0; + litedramcore_bankmachine5_produce <= 4'd0; + litedramcore_bankmachine5_consume <= 4'd0; + litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine5_row <= 14'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_level <= 5'd0; + litedramcore_bankmachine6_produce <= 4'd0; + litedramcore_bankmachine6_consume <= 4'd0; + litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine6_row <= 14'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_level <= 5'd0; + litedramcore_bankmachine7_produce <= 4'd0; + litedramcore_bankmachine7_consume <= 4'd0; + litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0; + litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0; + litedramcore_bankmachine7_row <= 14'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + litedramcore_we <= 1'd0; + litedramcore_refresher_state <= 2'd0; + litedramcore_bankmachine0_state <= 4'd0; + litedramcore_bankmachine1_state <= 4'd0; + litedramcore_bankmachine2_state <= 4'd0; + litedramcore_bankmachine3_state <= 4'd0; + litedramcore_bankmachine4_state <= 4'd0; + litedramcore_bankmachine5_state <= 4'd0; + litedramcore_bankmachine6_state <= 4'd0; + litedramcore_bankmachine7_state <= 4'd0; + litedramcore_multiplexer_state <= 4'd0; + litedramcore_new_master_wdata_ready0 <= 1'd0; + litedramcore_new_master_wdata_ready1 <= 1'd0; + litedramcore_new_master_rdata_valid0 <= 1'd0; + litedramcore_new_master_rdata_valid1 <= 1'd0; + litedramcore_new_master_rdata_valid2 <= 1'd0; + litedramcore_new_master_rdata_valid3 <= 1'd0; + litedramcore_new_master_rdata_valid4 <= 1'd0; + litedramcore_new_master_rdata_valid5 <= 1'd0; + litedramcore_new_master_rdata_valid6 <= 1'd0; + litedramcore_new_master_rdata_valid7 <= 1'd0; + litedramcore_new_master_rdata_valid8 <= 1'd0; + litedramcore_state <= 2'd0; + end end @@ -15811,14 +16031,14 @@ IOBUF IOBUF_15( reg [23:0] storage[0:15]; reg [23:0] storage_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) - storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; - storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine0_wrport_we) + storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w; + storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0; -assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0; +assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr]; //------------------------------------------------------------------------------ @@ -15829,14 +16049,14 @@ assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[lit reg [23:0] storage_1[0:15]; reg [23:0] storage_1_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) - storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; - storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine1_wrport_we) + storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w; + storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0; -assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0; +assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr]; //------------------------------------------------------------------------------ @@ -15847,14 +16067,14 @@ assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[l reg [23:0] storage_2[0:15]; reg [23:0] storage_2_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) - storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; - storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine2_wrport_we) + storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w; + storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0; -assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0; +assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr]; //------------------------------------------------------------------------------ @@ -15865,14 +16085,14 @@ assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[l reg [23:0] storage_3[0:15]; reg [23:0] storage_3_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) - storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; - storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine3_wrport_we) + storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w; + storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0; -assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0; +assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr]; //------------------------------------------------------------------------------ @@ -15883,14 +16103,14 @@ assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[l reg [23:0] storage_4[0:15]; reg [23:0] storage_4_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) - storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; - storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine4_wrport_we) + storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w; + storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0; -assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0; +assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr]; //------------------------------------------------------------------------------ @@ -15901,14 +16121,14 @@ assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[l reg [23:0] storage_5[0:15]; reg [23:0] storage_5_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) - storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; - storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine5_wrport_we) + storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w; + storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0; -assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0; +assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr]; //------------------------------------------------------------------------------ @@ -15919,14 +16139,14 @@ assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[l reg [23:0] storage_6[0:15]; reg [23:0] storage_6_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) - storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; - storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine6_wrport_we) + storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w; + storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0; -assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0; +assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr]; //------------------------------------------------------------------------------ @@ -15937,14 +16157,14 @@ assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[l reg [23:0] storage_7[0:15]; reg [23:0] storage_7_dat0; always @(posedge sys_clk) begin - if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) - storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; - storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; + if (litedramcore_bankmachine7_wrport_we) + storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w; + storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr]; end always @(posedge sys_clk) begin end -assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0; -assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; +assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0; +assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr]; FDCE FDCE( @@ -16038,7 +16258,8 @@ PLLE2_ADV #( .LOCKED(locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE ( .C(iodelay_clk), @@ -16048,7 +16269,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_1 ( .C(iodelay_clk), @@ -16058,7 +16280,8 @@ PLLE2_ADV #( .Q(iodelay_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_2 ( .C(sys_clk), @@ -16068,7 +16291,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_3 ( .C(sys_clk), @@ -16078,7 +16302,8 @@ PLLE2_ADV #( .Q(sys_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_4 ( .C(sys4x_clk), @@ -16088,7 +16313,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_5 ( .C(sys4x_clk), @@ -16098,7 +16324,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl2_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( +(* ars_ff1 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_6 ( .C(sys4x_dqs_clk), @@ -16108,7 +16335,8 @@ PLLE2_ADV #( .Q(xilinxasyncresetsynchronizerimpl3_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( +(* ars_ff2 = "true", async_reg = "true" *) +FDPE #( .INIT(1'd1) ) FDPE_7 ( .C(sys4x_dqs_clk), @@ -16121,5 +16349,5 @@ PLLE2_ADV #( endmodule // ----------------------------------------------------------------------------- -// Auto-Generated by LiteX on 2022-08-04 21:07:01. +// Auto-Generated by LiteX on 2022-10-28 19:01:25. //------------------------------------------------------------------------------ From 1f5a2e8aaa67326ef7e673288b7c55f13bff34ba Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 29 Sep 2022 12:20:40 +0800 Subject: [PATCH 5/6] soc: Expose sw_soc_reset for syscon reset The soc itself will be reset when a syscon soc reset is triggered. Separately, top- board files can use the sw_soc_rst signal if they need to reset other peripherals Signed-off-by: Matt Johnston --- soc.vhdl | 47 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 33 insertions(+), 14 deletions(-) diff --git a/soc.vhdl b/soc.vhdl index 3282ca9..4c756ca 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -51,6 +51,16 @@ use work.wishbone_types.all; -- 3 : SD card -- 4 : GPIO +-- Resets: +-- The soc can be reset externally by its parent top- entity (via rst port), +-- or can be reset by software via syscon. In the software reset case +-- the reset signal will also be exposed via sw_soc_reset port - toplevels +-- can use that to reset other peripherals if required. +-- +-- When using DRAM the alt_reset signal will be high after soc reset, to +-- run sdram init routines. After startup software will switch alt_reset to +-- low, so a core reset will use the non-alt reset address. + entity soc is generic ( MEMORY_SIZE : natural; @@ -127,12 +137,18 @@ entity soc is -- GPIO signals gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0); gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0); - gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0') + gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0'); + + -- SOC reset trigger from syscon + sw_soc_reset : out std_ulogic ); end entity soc; architecture behaviour of soc is + -- internal reset + signal soc_reset : std_ulogic; + -- Wishbone master signals: signal wishbone_dcore_in : wishbone_slave_out; signal wishbone_dcore_out : wishbone_master_out; @@ -310,18 +326,21 @@ architecture behaviour of soc is begin + -- either external reset, or from syscon + soc_reset <= rst or sw_soc_reset; + resets: process(system_clk) begin if rising_edge(system_clk) then - rst_core <= rst or do_core_reset; - rst_uart <= rst; - rst_spi <= rst; - rst_xics <= rst; - rst_gpio <= rst; - rst_bram <= rst; - rst_dtm <= rst; - rst_wbar <= rst; - rst_wbdb <= rst; + rst_core <= soc_reset or do_core_reset; + rst_uart <= soc_reset; + rst_spi <= soc_reset; + rst_xics <= soc_reset; + rst_gpio <= soc_reset; + rst_bram <= soc_reset; + rst_dtm <= soc_reset; + rst_wbar <= soc_reset; + rst_wbdb <= soc_reset; alt_reset_d <= alt_reset; end if; end process; @@ -478,7 +497,7 @@ begin if rising_edge(system_clk) then do_cyc := '0'; end_cyc := '0'; - if (rst) then + if (soc_reset) then state := IDLE; wb_io_out.ack <= '0'; wb_io_out.stall <= '0'; @@ -761,12 +780,12 @@ begin ) port map( clk => system_clk, - rst => rst, + rst => soc_reset, wishbone_in => wb_syscon_in, wishbone_out => wb_syscon_out, dram_at_0 => dram_at_0, core_reset => do_core_reset, - soc_reset => open, -- XXX TODO + soc_reset => sw_soc_reset, alt_reset => alt_reset ); @@ -1063,7 +1082,7 @@ begin wb_x_state: process(system_clk) begin if rising_edge(system_clk) then - if not rst then + if not soc_reset then -- Wishbone arbiter assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure; assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure; From 56f1c41e9c88af8bcbf7a496b0267ff05fd39155 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Thu, 27 Oct 2022 11:50:12 +0800 Subject: [PATCH 6/6] arty: Add software reset from syscon Signed-off-by: Matt Johnston --- fpga/top-arty.vhdl | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index b6b8913..e1ebf60 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -104,6 +104,8 @@ architecture behaviour of toplevel is -- Reset signals: signal soc_rst : std_ulogic; signal pll_rst : std_ulogic; + signal sw_rst : std_ulogic; + signal periph_rst : std_ulogic; -- Internal clock signals: signal system_clk : std_ulogic; @@ -216,6 +218,7 @@ begin -- System signals system_clk => system_clk, rst => soc_rst, + sw_soc_reset => sw_rst, -- UART signals uart0_txd => uart_main_tx, @@ -299,6 +302,7 @@ begin nodram: if not USE_LITEDRAM generate signal ddram_clk_dummy : std_ulogic; + signal gen_rst : std_ulogic; begin reset_controller: entity work.soc_reset generic map( @@ -310,9 +314,11 @@ begin pll_locked_in => system_clk_locked and eth_clk_locked, ext_rst_in => ext_rst_n, pll_rst_out => pll_rst, - rst_out => soc_rst + rst_out => gen_rst ); + soc_rst <= gen_rst; + clkgen: entity work.clock_generator generic map( CLK_INPUT_HZ => 100000000, @@ -345,8 +351,7 @@ begin has_dram: if USE_LITEDRAM generate signal dram_init_done : std_ulogic; signal dram_init_error : std_ulogic; - signal dram_sys_rst : std_ulogic; - signal rst_gen_rst : std_ulogic; + signal gen_rst : std_ulogic; begin -- Eventually dig out the frequency from the generator @@ -365,7 +370,7 @@ begin pll_locked_in => eth_clk_locked, ext_rst_in => ext_rst_n, pll_rst_out => pll_rst, - rst_out => rst_gen_rst + rst_out => open ); -- Generate SoC reset @@ -374,7 +379,7 @@ begin if ext_rst_n = '0' then soc_rst <= '1'; elsif rising_edge(system_clk) then - soc_rst <= dram_sys_rst or not eth_clk_locked or not system_clk_locked; + soc_rst <= gen_rst or not eth_clk_locked or not system_clk_locked; end if; end process; @@ -395,7 +400,7 @@ begin clk_in => ext_clk, rst => pll_rst, system_clk => system_clk, - system_reset => dram_sys_rst, + system_reset => gen_rst, pll_locked => system_clk_locked, wb_in => wb_dram_in, @@ -431,6 +436,8 @@ begin end generate; + periph_rst <= soc_rst or sw_rst; + has_liteeth : if USE_LITEETH generate component liteeth_core port ( @@ -520,7 +527,7 @@ begin liteeth : liteeth_core port map( sys_clock => system_clk, - sys_reset => soc_rst, + sys_reset => periph_rst, mii_eth_clocks_tx => eth_clocks_tx, mii_eth_clocks_rx => eth_clocks_rx, mii_eth_rst_n => eth_rst_n, @@ -608,7 +615,7 @@ begin litesdcard : litesdcard_core port map ( clk => system_clk, - rst => soc_rst, + rst => periph_rst, wb_ctrl_adr => wb_sdcard_adr, wb_ctrl_dat_w => wb_ext_io_in.dat, wb_ctrl_dat_r => wb_sdcard_out.dat,