diff --git a/fpga/antmicro_artix_dc_scm.xdc b/fpga/antmicro_artix_dc_scm.xdc new file mode 100644 index 0000000..7b17439 --- /dev/null +++ b/fpga/antmicro_artix_dc_scm.xdc @@ -0,0 +1,33 @@ +################################################################################ +# clkin, reset, uart pins... +################################################################################ + +set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }]; + +set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]; +set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]; + +set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { d11_led }]; +set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { d12_led }]; +set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { d13_led }]; + + +################################################################################ +# Design constraints and bitsteam attributes +################################################################################ + +#Internal VREF +set_property INTERNAL_VREF 0.675 [get_iobanks 34] + +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] + +################################################################################ +# Clock constraints +################################################################################ + +create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; diff --git a/fpga/top-antmicro-artix-dc-scm.vhdl b/fpga/top-antmicro-artix-dc-scm.vhdl new file mode 100644 index 0000000..8f6d56c --- /dev/null +++ b/fpga/top-antmicro-artix-dc-scm.vhdl @@ -0,0 +1,245 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +library work; +use work.wishbone_types.all; + +entity toplevel is + generic ( + MEMORY_SIZE : integer := 16384; + RAM_INIT_FILE : string := "firmware.hex"; + RESET_LOW : boolean := true; + CLK_FREQUENCY : positive := 100000000; + HAS_FPU : boolean := true; + HAS_BTC : boolean := true; + USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; + DISABLE_FLATTEN_CORE : boolean := false; + SCLK_STARTUPE2 : boolean := false; + SPI_FLASH_OFFSET : integer := 4194304; + SPI_FLASH_DEF_CKDV : natural := 1; + SPI_FLASH_DEF_QUAD : boolean := true; + LOG_LENGTH : natural := 512; + USE_LITEETH : boolean := false; + UART_IS_16550 : boolean := false; + HAS_UART1 : boolean := true; + USE_LITESDCARD : boolean := false; + HAS_GPIO : boolean := true; + NGPIO : natural := 32 + ); + port( + ext_clk : in std_ulogic; + + d11_led : out std_ulogic; + d12_led : out std_ulogic; + d13_led : out std_ulogic; + + -- UART0 signals: + uart_main_tx : out std_ulogic; + uart_main_rx : in std_ulogic + + ); +end entity toplevel; + +architecture behaviour of toplevel is + signal ext_rst_n : std_ulogic; + + -- Reset signals: + signal soc_rst : std_ulogic; + signal pll_rst : std_ulogic; + + -- Internal clock signals: + signal system_clk : std_ulogic; + signal system_clk_locked : std_ulogic; + signal eth_clk_locked : std_ulogic; + + -- External IOs from the SoC + signal wb_ext_io_in : wb_io_master_out; + signal wb_ext_io_out : wb_io_slave_out; + + -- DRAM main data wishbone connection + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + + -- DRAM control wishbone connection + signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteEth connection + signal ext_irq_eth : std_ulogic; + signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; + + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + + -- Control/status + signal core_alt_reset : std_ulogic; + + -- Status LED + signal led0_b_pwm : std_ulogic; + signal led0_r_pwm : std_ulogic; + signal led0_g_pwm : std_ulogic; + + -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise + signal pwm_counter : std_ulogic_vector(8 downto 0); + + -- SPI flash + signal spi_sck : std_ulogic; + signal spi_cs_n : std_ulogic; + signal spi_sdat_o : std_ulogic_vector(3 downto 0); + signal spi_sdat_oe : std_ulogic_vector(3 downto 0); + signal spi_sdat_i : std_ulogic_vector(3 downto 0); + + -- GPIO + signal gpio_in : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_out : std_ulogic_vector(NGPIO - 1 downto 0); + signal gpio_dir : std_ulogic_vector(NGPIO - 1 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; +begin + -- Main SoC + soc0: entity work.soc + generic map( + MEMORY_SIZE => BRAM_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE, + SIM => false, + CLK_FREQ => CLK_FREQUENCY, + HAS_FPU => HAS_FPU, + HAS_BTC => HAS_BTC, + HAS_DRAM => USE_LITEDRAM, + DRAM_SIZE => 512 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, + DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE, + HAS_SPI_FLASH => false, + SPI_FLASH_DLINES => 4, + SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, + SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV, + SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD, + LOG_LENGTH => LOG_LENGTH, + HAS_LITEETH => USE_LITEETH, + UART0_IS_16550 => UART_IS_16550, + HAS_UART1 => HAS_UART1, + HAS_SD_CARD => USE_LITESDCARD, + HAS_GPIO => HAS_GPIO, + NGPIO => NGPIO + ) + port map ( + -- System signals + system_clk => system_clk, + rst => soc_rst, + + -- UART signals + uart0_txd => uart_main_tx, + uart0_rxd => uart_main_rx, + + -- UART1 signals + --uart1_txd => uart_pmod_tx, + --uart1_rxd => uart_pmod_rx, + + -- SPI signals +-- spi_flash_sck => spi_sck, +-- spi_flash_cs_n => spi_cs_n, + spi_flash_sdat_o => spi_sdat_o, + spi_flash_sdat_oe => spi_sdat_oe, + spi_flash_sdat_i => spi_sdat_i, + + -- GPIO signals + gpio_in => gpio_in, + gpio_out => gpio_out, + gpio_dir => gpio_dir, + + -- External interrupts + ext_irq_eth => ext_irq_eth, + ext_irq_sdcard => ext_irq_sdcard, + + -- DRAM wishbone + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + + -- IO wishbone + wb_ext_io_in => wb_ext_io_in, + wb_ext_io_out => wb_ext_io_out, +-- wb_ext_is_dram_csr => , +-- wb_ext_is_dram_init => , +-- wb_ext_is_eth => , +-- wb_ext_is_sdcard => , + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out, + + alt_reset => core_alt_reset + ); + + reset_controller: entity work.soc_reset + generic map( + RESET_LOW => RESET_LOW + ) + port map( + ext_clk => ext_clk, + pll_clk => system_clk, + pll_locked_in => system_clk_locked, + ext_rst_in => ext_rst_n, + pll_rst_out => pll_rst, + rst_out => soc_rst + ); + + clkgen: entity work.clock_generator + generic map( + CLK_INPUT_HZ => 100000000, + CLK_OUTPUT_HZ => CLK_FREQUENCY + ) + port map( + ext_clk => ext_clk, + pll_rst_in => pll_rst, + pll_clk_out => system_clk, + pll_locked_out => system_clk_locked + ); + + wb_ext_io_out.dat <= (others => '0'); + wb_ext_io_out.ack <= '0'; + wb_ext_io_out.stall <= '0'; + + wb_sdcard_out.ack <= '0'; + wb_sdcard_out.stall <= '0'; + + ext_irq_eth <= '0'; + ext_irq_sdcard <= '0'; + + ext_rst_n <= '1'; + + d11_led <= '0'; + d12_led <= soc_rst; + d13_led <= system_clk; + +end architecture behaviour; diff --git a/microwatt.core b/microwatt.core index 5e603f1..799ee21 100644 --- a/microwatt.core +++ b/microwatt.core @@ -109,6 +109,12 @@ filesets: - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} - fpga/top-arty.vhdl : {file_type : vhdlSource-2008} + antmicro-artix-dc-scm: + files: + - fpga/antmicro_artix_dc_scm.xdc: {file_type : xdc} + - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008} + - fpga/top-antmicro-artix-dc-scm.vhdl : {file_type : vhdlSource-2008} + wukong-v2: files: - fpga/wukong-v2.xdc : {file_type : xdc} @@ -347,6 +353,25 @@ targets: vivado: {part : xc7a100ticsg324-1L} toplevel : toplevel + antmicro-artix-dc-scm: + default_tool: vivado + filesets: [core, antmicro-artix-dc-scm, soc, fpga, debug_xilinx, uart16550, xilinx_specific] + parameters : + - memory_size + - ram_init_file + - clk_input + - clk_frequency + - disable_flatten_core + - log_length=2048 + - uart_is_16550 + - has_uart1 + - has_fpu + - has_btc + generate: [git_hash] + tools: + vivado: {part : xc7a100tfgg484-1} + toplevel : toplevel + wukong-v2-a100t-nodram: default_tool: vivado filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]