From ccd52bf6f2e43a6f041f77ecbf6d40f997d87e91 Mon Sep 17 00:00:00 2001 From: Alastair D'Silva Date: Thu, 3 Oct 2019 10:16:53 +1000 Subject: [PATCH] Tighten UART address The current scheme has UART0 repeating throughout the UART address range. This patch tightens the address checking so that it only occurs once. Signed-off-by: Alastair D'Silva --- soc.vhdl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/soc.vhdl b/soc.vhdl index 39d72a9..94ab393 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -106,7 +106,7 @@ begin -- Wishbone slaves address decoder & mux slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out) -- Selected slave - type slave_type is (SLAVE_UART, + type slave_type is (SLAVE_UART_0, SLAVE_MEMORY, SLAVE_NONE); variable slave : slave_type; @@ -116,8 +116,8 @@ begin if wb_master_out.adr(63 downto 24) = x"0000000000" then slave := SLAVE_MEMORY; elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then - if wb_master_out.adr(15 downto 12) = x"2" then - slave := SLAVE_UART; + if wb_master_out.adr(23 downto 12) = x"002" then + slave := SLAVE_UART_0; end if; end if; @@ -130,7 +130,7 @@ begin when SLAVE_MEMORY => wb_bram_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_bram_out; - when SLAVE_UART => + when SLAVE_UART_0 => wb_uart0_in.cyc <= wb_master_out.cyc; wb_master_in <= wb_uart0_out; when others =>