diff --git a/fpga/antmicro_artix_dc_scm.xdc b/fpga/antmicro_artix_dc_scm.xdc
new file mode 100644
index 0000000..969a7d2
--- /dev/null
+++ b/fpga/antmicro_artix_dc_scm.xdc
@@ -0,0 +1,412 @@
+################################################################################
+# clkin, reset, uart pins...
+################################################################################
+
+set_property -dict { PACKAGE_PIN C18  IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
+
+set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
+set_property -dict { PACKAGE_PIN P19  IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
+
+set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { d11_led }];
+set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { d12_led }];
+set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { d13_led }];
+
+################################################################################
+# SPI Flash
+################################################################################
+# P22 DQ0
+# R22 DQ1
+# P21 DQ2
+# R21 DQ3
+# T19 CS_B
+
+set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
+#set_property -dict { PACKAGE_PIN L12 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_clk }];
+set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
+set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
+set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
+set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
+
+# Put registers into IOBs to improve timing
+set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/*sck_1*}]
+set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_delay_1.dat_i_l*}]
+
+################################################################################
+# DRAM (generated by LiteX)
+################################################################################
+
+# ddram:0.a
+set_property LOC M2 [get_ports {ddram_a[0]}]
+set_property SLEW FAST [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
+
+# ddram:0.a
+set_property LOC M5 [get_ports {ddram_a[1]}]
+set_property SLEW FAST [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
+
+# ddram:0.a
+set_property LOC M3 [get_ports {ddram_a[2]}]
+set_property SLEW FAST [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
+
+# ddram:0.a
+set_property LOC M1 [get_ports {ddram_a[3]}]
+set_property SLEW FAST [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
+
+# ddram:0.a
+set_property LOC L6 [get_ports {ddram_a[4]}]
+set_property SLEW FAST [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
+
+# ddram:0.a
+set_property LOC P1 [get_ports {ddram_a[5]}]
+set_property SLEW FAST [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
+
+# ddram:0.a
+set_property LOC N3 [get_ports {ddram_a[6]}]
+set_property SLEW FAST [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
+
+# ddram:0.a
+set_property LOC N2 [get_ports {ddram_a[7]}]
+set_property SLEW FAST [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
+
+# ddram:0.a
+set_property LOC M6 [get_ports {ddram_a[8]}]
+set_property SLEW FAST [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
+
+# ddram:0.a
+set_property LOC R1 [get_ports {ddram_a[9]}]
+set_property SLEW FAST [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
+
+# ddram:0.a
+set_property LOC L5 [get_ports {ddram_a[10]}]
+set_property SLEW FAST [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
+
+# ddram:0.a
+set_property LOC N5 [get_ports {ddram_a[11]}]
+set_property SLEW FAST [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
+
+# ddram:0.a
+set_property LOC N4 [get_ports {ddram_a[12]}]
+set_property SLEW FAST [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
+
+# ddram:0.a
+set_property LOC P2 [get_ports {ddram_a[13]}]
+set_property SLEW FAST [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
+
+# ddram:0.a
+set_property LOC P6 [get_ports {ddram_a[14]}]
+set_property SLEW FAST [get_ports {ddram_a[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[14]}]
+
+# ddram:0.ba
+set_property LOC L3 [get_ports {ddram_ba[0]}]
+set_property SLEW FAST [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
+
+# ddram:0.ba
+set_property LOC K6 [get_ports {ddram_ba[1]}]
+set_property SLEW FAST [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
+
+# ddram:0.ba
+set_property LOC L4 [get_ports {ddram_ba[2]}]
+set_property SLEW FAST [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
+
+# ddram:0.ras_n
+set_property LOC J4 [get_ports {ddram_ras_n}]
+set_property SLEW FAST [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
+
+# ddram:0.cas_n
+set_property LOC K3 [get_ports {ddram_cas_n}]
+set_property SLEW FAST [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
+
+# ddram:0.we_n
+set_property LOC L1 [get_ports {ddram_we_n}]
+set_property SLEW FAST [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
+
+# ddram:0.dm
+set_property LOC G3 [get_ports {ddram_dm[0]}]
+set_property SLEW FAST [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
+
+# ddram:0.dm
+set_property LOC F1 [get_ports {ddram_dm[1]}]
+set_property SLEW FAST [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
+
+# ddram:0.dq
+set_property LOC G2 [get_ports {ddram_dq[0]}]
+set_property SLEW FAST [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
+
+# ddram:0.dq
+set_property LOC H4 [get_ports {ddram_dq[1]}]
+set_property SLEW FAST [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
+
+# ddram:0.dq
+set_property LOC H5 [get_ports {ddram_dq[2]}]
+set_property SLEW FAST [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
+
+# ddram:0.dq
+set_property LOC J1 [get_ports {ddram_dq[3]}]
+set_property SLEW FAST [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
+
+# ddram:0.dq
+set_property LOC K1 [get_ports {ddram_dq[4]}]
+set_property SLEW FAST [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
+
+# ddram:0.dq
+set_property LOC H3 [get_ports {ddram_dq[5]}]
+set_property SLEW FAST [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
+
+# ddram:0.dq
+set_property LOC H2 [get_ports {ddram_dq[6]}]
+set_property SLEW FAST [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
+
+# ddram:0.dq
+set_property LOC J5 [get_ports {ddram_dq[7]}]
+set_property SLEW FAST [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
+
+# ddram:0.dq
+set_property LOC E3 [get_ports {ddram_dq[8]}]
+set_property SLEW FAST [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
+
+# ddram:0.dq
+set_property LOC B2 [get_ports {ddram_dq[9]}]
+set_property SLEW FAST [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
+
+# ddram:0.dq
+set_property LOC F3 [get_ports {ddram_dq[10]}]
+set_property SLEW FAST [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
+
+# ddram:0.dq
+set_property LOC D2 [get_ports {ddram_dq[11]}]
+set_property SLEW FAST [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
+
+# ddram:0.dq
+set_property LOC C2 [get_ports {ddram_dq[12]}]
+set_property SLEW FAST [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
+
+# ddram:0.dq
+set_property LOC A1 [get_ports {ddram_dq[13]}]
+set_property SLEW FAST [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
+
+# ddram:0.dq
+set_property LOC E2 [get_ports {ddram_dq[14]}]
+set_property SLEW FAST [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
+
+# ddram:0.dq
+set_property LOC B1 [get_ports {ddram_dq[15]}]
+set_property SLEW FAST [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
+
+# ddram:0.dqs_p
+set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
+
+# ddram:0.dqs_p
+set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
+
+# ddram:0.dqs_n
+set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
+
+# ddram:0.dqs_n
+set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
+
+# ddram:0.clk_p
+set_property LOC P5 [get_ports {ddram_clk_p}]
+set_property SLEW FAST [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
+
+# ddram:0.clk_n
+set_property LOC P4 [get_ports {ddram_clk_n}]
+set_property SLEW FAST [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
+
+# ddram:0.cke
+set_property LOC J6 [get_ports {ddram_cke}]
+set_property SLEW FAST [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
+
+# ddram:0.odt
+set_property LOC K4 [get_ports {ddram_odt}]
+set_property SLEW FAST [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
+
+# ddram:0.reset_n
+set_property LOC G1 [get_ports {ddram_reset_n}]
+set_property SLEW FAST [get_ports {ddram_reset_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
+
+################################################################################
+# Ethernet (generated by LiteX)
+################################################################################
+
+# eth_clocks:0.tx
+set_property LOC J19 [get_ports {eth_clocks_tx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]
+
+# eth_clocks:0.rx
+set_property LOC K19 [get_ports {eth_clocks_rx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]
+
+# eth:0.rst_n
+set_property LOC N18 [get_ports {eth_rst_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
+
+# eth:0.int_n
+set_property LOC N20 [get_ports {eth_int_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_int_n}]
+
+# eth:0.mdio
+set_property LOC M21 [get_ports {eth_mdio}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]
+
+# eth:0.mdc
+set_property LOC N22 [get_ports {eth_mdc}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]
+
+# eth:0.rx_ctl
+set_property LOC M22 [get_ports {eth_rx_ctl}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_ctl}]
+
+# eth:0.rx_data
+set_property LOC L20 [get_ports {eth_rx_data[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
+
+# eth:0.rx_data
+set_property LOC L21 [get_ports {eth_rx_data[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
+
+# eth:0.rx_data
+set_property LOC K21 [get_ports {eth_rx_data[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
+
+# eth:0.rx_data
+set_property LOC K22 [get_ports {eth_rx_data[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
+
+# eth:0.tx_ctl
+set_property LOC J22 [get_ports {eth_tx_ctl}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_ctl}]
+
+# eth:0.tx_data
+set_property LOC G20 [get_ports {eth_tx_data[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
+
+# eth:0.tx_data
+set_property LOC H20 [get_ports {eth_tx_data[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
+
+# eth:0.tx_data
+set_property LOC H22 [get_ports {eth_tx_data[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
+
+# eth:0.tx_data
+set_property LOC J21 [get_ports {eth_tx_data[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
+
+
+
+################################################################################
+# Design constraints and bitsteam attributes
+################################################################################
+
+#Internal VREF
+set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+set_property INTERNAL_VREF 0.675 [get_iobanks 35]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_ethphy_eth_rx_clk_ibuf]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {has_liteeth.liteeth/main_maccore_ethphy_eth_rx_clk_ibuf}]
+
+################################################################################
+# Clock constraints
+################################################################################
+
+create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];
+
+create_clock -name eth_clocks_rx -period 8.0 [get_ports { eth_clocks_rx }]
+
+create_clock -name eth_clocks_tx -period 8.0 [get_ports { eth_clocks_tx }]
+
+
+set_clock_groups -asynchronous -group [get_clocks sys_clk_pin -include_generated_clocks] -group [get_clocks eth_clocks_rx -include_generated_clocks]
+
+set_clock_groups -asynchronous -group [get_clocks sys_clk_pin -include_generated_clocks] -group [get_clocks eth_clocks_tx -include_generated_clocks]
+
+
+
+################################################################################
+# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
+################################################################################
+
+
+set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
+
+set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
+
+set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]
diff --git a/fpga/top-antmicro-artix-dc-scm.vhdl b/fpga/top-antmicro-artix-dc-scm.vhdl
new file mode 100644
index 0000000..b8fd75f
--- /dev/null
+++ b/fpga/top-antmicro-artix-dc-scm.vhdl
@@ -0,0 +1,504 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+    generic (
+        MEMORY_SIZE        : integer  := 16384;
+        RAM_INIT_FILE      : string   := "firmware.hex";
+        RESET_LOW          : boolean  := true;
+        CLK_FREQUENCY      : positive := 100000000;
+        HAS_FPU            : boolean  := true;
+        HAS_BTC            : boolean  := true;
+        USE_LITEDRAM       : boolean  := false;
+        NO_BRAM            : boolean  := false;
+        DISABLE_FLATTEN_CORE : boolean := false;
+        SCLK_STARTUPE2     : boolean := false;
+        SPI_FLASH_OFFSET   : integer := 3145728;
+        SPI_FLASH_DEF_CKDV : natural := 1;
+        SPI_FLASH_DEF_QUAD : boolean := true;
+        LOG_LENGTH         : natural := 512;
+        USE_LITEETH        : boolean  := true;
+        UART_IS_16550      : boolean  := false;
+        HAS_UART1          : boolean  := true;
+        USE_LITESDCARD     : boolean := false;
+        HAS_GPIO           : boolean := true;
+        NGPIO              : natural := 32
+        );
+    port(
+        ext_clk   : in  std_ulogic;
+
+        -- UART0 signals:
+        uart_main_tx : out std_ulogic;
+        uart_main_rx : in  std_ulogic;
+
+        -- LEDs
+        d11_led : out std_ulogic;
+        d12_led : out std_ulogic;
+        d13_led : out std_ulogic;
+
+
+        -- SPI
+        spi_flash_cs_n   : out std_ulogic;
+        spi_flash_mosi   : inout std_ulogic;
+        spi_flash_miso   : inout std_ulogic;
+        spi_flash_wp_n   : inout std_ulogic;
+        spi_flash_hold_n : inout std_ulogic;
+
+        -- Ethernet
+        eth_clocks_tx    : out std_ulogic;
+        eth_clocks_rx    : in std_ulogic;
+        eth_rst_n        : out std_ulogic;
+        eth_int_n        : in std_ulogic;
+        eth_mdio         : inout std_ulogic;
+        eth_mdc          : out std_ulogic;
+        eth_rx_ctl       : in std_ulogic;
+        eth_rx_data      : in std_ulogic_vector(3 downto 0);
+        eth_tx_ctl       : out std_ulogic;
+        eth_tx_data      : out std_ulogic_vector(3 downto 0);
+
+        -- DRAM wires
+        ddram_a       : out std_ulogic_vector(14 downto 0);
+        ddram_ba      : out std_ulogic_vector(2 downto 0);
+        ddram_ras_n   : out std_ulogic;
+        ddram_cas_n   : out std_ulogic;
+        ddram_we_n    : out std_ulogic;
+        ddram_dm      : out std_ulogic_vector(1 downto 0);
+        ddram_dq      : inout std_ulogic_vector(15 downto 0);
+        ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+        ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
+        ddram_clk_p   : out std_ulogic;
+        ddram_clk_n   : out std_ulogic;
+        ddram_cke     : out std_ulogic;
+        ddram_odt     : out std_ulogic;
+        ddram_reset_n : out std_ulogic
+        );
+end entity toplevel;
+
+architecture behaviour of toplevel is
+    signal ext_rst_n : std_ulogic;
+
+    -- Reset signals:
+    signal soc_rst : std_ulogic;
+    signal pll_rst : std_ulogic;
+
+    -- Internal clock signals:
+    signal system_clk        : std_ulogic;
+    signal system_clk_locked : std_ulogic;
+
+    -- External IOs from the SoC
+    signal wb_ext_io_in        : wb_io_master_out;
+    signal wb_ext_io_out       : wb_io_slave_out;
+    signal wb_ext_is_dram_csr  : std_ulogic;
+    signal wb_ext_is_dram_init : std_ulogic;
+    signal wb_ext_is_eth       : std_ulogic;
+
+
+    -- DRAM main data wishbone connection
+    signal wb_dram_in          : wishbone_master_out;
+    signal wb_dram_out         : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_out    : wb_io_slave_out := wb_io_slave_out_init;
+
+    -- LiteEth connection
+    signal ext_irq_eth         : std_ulogic;
+    signal wb_eth_out          : wb_io_slave_out := wb_io_slave_out_init;
+
+    -- LiteSDCard connection
+    signal ext_irq_sdcard      : std_ulogic := '0';
+    signal wb_sdcard_out       : wb_io_slave_out := wb_io_slave_out_init;
+    signal wb_sddma_out        : wb_io_master_out := wb_io_master_out_init;
+    signal wb_sddma_in         : wb_io_slave_out;
+    signal wb_sddma_nr         : wb_io_master_out;
+    signal wb_sddma_ir         : wb_io_slave_out;
+    -- for conversion from non-pipelined wishbone to pipelined
+    signal wb_sddma_stb_sent   : std_ulogic;
+
+    -- Control/status
+    signal core_alt_reset : std_ulogic;
+
+    -- Status LED
+    signal led0_b_pwm : std_ulogic;
+    signal led0_r_pwm : std_ulogic;
+    signal led0_g_pwm : std_ulogic;
+
+    -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
+    signal pwm_counter  : std_ulogic_vector(8 downto 0);
+
+    -- SPI flash
+    signal spi_sck     : std_ulogic;
+    signal spi_cs_n    : std_ulogic;
+    signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
+
+    -- GPIO
+    signal gpio_in     : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal gpio_out    : std_ulogic_vector(NGPIO - 1 downto 0);
+    signal gpio_dir    : std_ulogic_vector(NGPIO - 1 downto 0);
+
+    -- ddram clock signals as vectors
+    signal ddram_clk_p_vec : std_logic_vector(0 downto 0);
+    signal ddram_clk_n_vec : std_logic_vector(0 downto 0);
+
+    -- Fixup various memory sizes based on generics
+    function get_bram_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return 0;
+        else
+            return MEMORY_SIZE;
+        end if;
+    end function;
+
+    function get_payload_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return MEMORY_SIZE;
+        else
+            return 0;
+        end if;
+    end function;
+    
+    constant BRAM_SIZE    : natural := get_bram_size;
+    constant PAYLOAD_SIZE : natural := get_payload_size;
+begin
+
+    -- Main SoC
+    soc0: entity work.soc
+        generic map(
+            MEMORY_SIZE        => BRAM_SIZE,
+            RAM_INIT_FILE      => RAM_INIT_FILE,
+            SIM                => false,
+            CLK_FREQ           => CLK_FREQUENCY,
+            HAS_FPU            => HAS_FPU,
+            HAS_BTC            => HAS_BTC,
+            HAS_DRAM           => USE_LITEDRAM,
+            DRAM_SIZE          => 512 * 1024 * 1024,
+            DRAM_INIT_SIZE     => PAYLOAD_SIZE,
+            DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+            HAS_SPI_FLASH      => true,
+            SPI_FLASH_DLINES   => 4,
+            SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
+            SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
+            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            LOG_LENGTH         => LOG_LENGTH,
+            HAS_LITEETH        => USE_LITEETH,
+            UART0_IS_16550     => UART_IS_16550,
+            HAS_UART1          => HAS_UART1,
+            HAS_SD_CARD        => USE_LITESDCARD,
+            HAS_GPIO           => HAS_GPIO,
+            NGPIO              => NGPIO
+            )
+        port map (
+            -- System signals
+            system_clk        => system_clk,
+            rst               => soc_rst,
+
+            -- UART signals
+            uart0_txd         => uart_main_tx,
+            uart0_rxd         => uart_main_rx,
+
+	    -- UART1 signals
+	    --uart1_txd         => uart_pmod_tx,
+	    --uart1_rxd         => uart_pmod_rx,
+
+            -- SPI signals
+            spi_flash_sck     => spi_sck,
+            spi_flash_cs_n    => spi_cs_n,
+            spi_flash_sdat_o  => spi_sdat_o,
+            spi_flash_sdat_oe => spi_sdat_oe,
+            spi_flash_sdat_i  => spi_sdat_i,
+
+            -- GPIO signals
+            gpio_in           => gpio_in,
+            gpio_out          => gpio_out,
+            gpio_dir          => gpio_dir,
+
+            -- External interrupts
+            ext_irq_eth       => ext_irq_eth,
+            ext_irq_sdcard    => ext_irq_sdcard,
+
+            -- DRAM wishbone
+            wb_dram_in           => wb_dram_in,
+            wb_dram_out          => wb_dram_out,
+
+            -- IO wishbone
+            wb_ext_io_in         => wb_ext_io_in,
+            wb_ext_io_out        => wb_ext_io_out,
+            wb_ext_is_dram_csr   => wb_ext_is_dram_csr,
+            wb_ext_is_dram_init  => wb_ext_is_dram_init,
+            wb_ext_is_eth        => wb_ext_is_eth,
+--            wb_ext_is_sdcard     => ,
+
+            -- DMA wishbone
+            wishbone_dma_in      => wb_sddma_in,
+            wishbone_dma_out     => wb_sddma_out,
+
+            alt_reset            => core_alt_reset
+            );
+
+
+    -- SPI Flash
+    --
+    -- Note: Unlike many other boards, the SPI flash on the Arty has
+    -- an actual pin to generate the clock and doesn't require to use
+    -- the STARTUPE2 primitive.
+    --
+    spi_flash_cs_n   <= spi_cs_n;
+    spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+    spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+    spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+    spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+    spi_sdat_i(0)    <= spi_flash_mosi;
+    spi_sdat_i(1)    <= spi_flash_miso;
+    spi_sdat_i(2)    <= spi_flash_wp_n;
+    spi_sdat_i(3)    <= spi_flash_hold_n;
+
+    STARTUPE2_INST: STARTUPE2
+        port map (
+            CLK => '0',
+            GSR => '0',
+            GTS => '0',
+            KEYCLEARB => '0',
+            PACK => '0',
+            USRCCLKO => spi_sck,
+            USRCCLKTS => '0',
+            USRDONEO => '1',
+            USRDONETS => '0'
+            );
+
+    nodram: if not USE_LITEDRAM generate
+        signal ddram_clk_dummy : std_ulogic;
+    begin
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => system_clk_locked,
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => soc_rst
+                );
+
+        clkgen: entity work.clock_generator
+            generic map(
+                CLK_INPUT_HZ => 100000000,
+                CLK_OUTPUT_HZ => CLK_FREQUENCY
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_rst_in => pll_rst,
+                pll_clk_out => system_clk,
+                pll_locked_out => system_clk_locked
+                );
+
+	core_alt_reset <= '0';
+
+        d11_led <= '0';
+        d12_led <= soc_rst;
+        d13_led <= system_clk;
+
+        -- Vivado barfs on those differential signals if left
+        -- unconnected. So instanciate a diff. buffer and feed
+        -- it a constant '0'.
+        dummy_dram_clk: OBUFDS
+            port map (
+                O => ddram_clk_p,
+                OB => ddram_clk_n,
+                I => ddram_clk_dummy
+                );
+        ddram_clk_dummy <= '0';
+
+    end generate;
+
+    has_dram: if USE_LITEDRAM generate
+        signal dram_init_done  : std_ulogic;
+        signal dram_init_error : std_ulogic;
+        signal dram_sys_rst    : std_ulogic;
+        signal rst_gen_rst     : std_ulogic;
+    begin
+
+        -- Eventually dig out the frequency from the generator
+        -- but for now, assert it's 100Mhz
+        assert CLK_FREQUENCY = 100000000;
+
+        reset_controller: entity work.soc_reset
+            generic map(
+                RESET_LOW => RESET_LOW,
+                PLL_RESET_BITS => 18,
+                SOC_RESET_BITS => 1
+                )
+            port map(
+                ext_clk => ext_clk,
+                pll_clk => system_clk,
+                pll_locked_in => '1',
+                ext_rst_in => ext_rst_n,
+                pll_rst_out => pll_rst,
+                rst_out => open
+                );
+
+        -- Generate SoC reset
+        soc_rst_gen: process(system_clk)
+        begin
+            if ext_rst_n = '0' then
+                soc_rst <= '1';
+            elsif rising_edge(system_clk) then
+                soc_rst <= dram_sys_rst or not system_clk_locked;
+            end if;
+        end process;
+
+	ddram_clk_p_vec <= (others => ddram_clk_p);
+	ddram_clk_n_vec <= (others => ddram_clk_n);
+
+        dram: entity work.litedram_wrapper
+            generic map(
+                DRAM_ABITS => 25,
+                DRAM_ALINES => 15,
+                DRAM_DLINES => 16,
+                DRAM_CKLINES => 1,
+                DRAM_PORT_WIDTH => 128,
+                PAYLOAD_FILE => RAM_INIT_FILE,
+                PAYLOAD_SIZE => PAYLOAD_SIZE
+                )
+            port map(
+                clk_in          => ext_clk,
+                rst             => pll_rst,
+                system_clk      => system_clk,
+                system_reset    => dram_sys_rst,
+                core_alt_reset  => core_alt_reset,
+		pll_locked	=> system_clk_locked,
+
+                wb_in           => wb_dram_in,
+                wb_out          => wb_dram_out,
+                wb_ctrl_in      => wb_ext_io_in,
+                wb_ctrl_out     => wb_dram_ctrl_out,
+                wb_ctrl_is_csr  => wb_ext_is_dram_csr,
+                wb_ctrl_is_init => wb_ext_is_dram_init,
+
+                init_done       => dram_init_done,
+                init_error      => dram_init_error,
+
+                ddram_a         => ddram_a,
+                ddram_ba        => ddram_ba,
+                ddram_ras_n     => ddram_ras_n,
+                ddram_cas_n     => ddram_cas_n,
+                ddram_we_n      => ddram_we_n,
+                ddram_cs_n      => open,
+                ddram_dm        => ddram_dm,
+                ddram_dq        => ddram_dq,
+                ddram_dqs_p     => ddram_dqs_p,
+                ddram_dqs_n     => ddram_dqs_n,
+                ddram_clk_p     => ddram_clk_p_vec,
+                ddram_clk_n     => ddram_clk_n_vec,
+                ddram_cke       => ddram_cke,
+                ddram_odt       => ddram_odt,
+                ddram_reset_n   => ddram_reset_n
+                );
+
+        d11_led <= not dram_init_done;
+        d12_led <= soc_rst;
+        d13_led <= dram_init_error;
+
+    end generate;
+
+    has_liteeth : if USE_LITEETH generate
+
+        component liteeth_core port (
+            sys_clock           : in std_ulogic;
+            sys_reset           : in std_ulogic;
+            rgmii_eth_clocks_tx : out std_ulogic;
+            rgmii_eth_clocks_rx : in std_ulogic;
+            rgmii_eth_rst_n     : out std_ulogic;
+            rgmii_eth_int_n     : in std_ulogic;
+            rgmii_eth_mdio      : inout std_ulogic;
+            rgmii_eth_mdc       : out std_ulogic;
+            rgmii_eth_rx_ctl    : in std_ulogic;
+            rgmii_eth_rx_data   : in std_ulogic_vector(3 downto 0);
+            rgmii_eth_tx_ctl    : out std_ulogic;
+            rgmii_eth_tx_data   : out std_ulogic_vector(3 downto 0);
+            wishbone_adr        : in std_ulogic_vector(29 downto 0);
+            wishbone_dat_w      : in std_ulogic_vector(31 downto 0);
+            wishbone_dat_r      : out std_ulogic_vector(31 downto 0);
+            wishbone_sel        : in std_ulogic_vector(3 downto 0);
+            wishbone_cyc        : in std_ulogic;
+            wishbone_stb        : in std_ulogic;
+            wishbone_ack        : out std_ulogic;
+            wishbone_we         : in std_ulogic;
+            wishbone_cti        : in std_ulogic_vector(2 downto 0);
+            wishbone_bte        : in std_ulogic_vector(1 downto 0);
+            wishbone_err        : out std_ulogic;
+            interrupt           : out std_ulogic
+            );
+        end component;
+
+        signal wb_eth_cyc     : std_ulogic;
+        signal wb_eth_adr     : std_ulogic_vector(29 downto 0);
+
+    begin
+        liteeth :  liteeth_core
+            port map(
+                sys_clock           => system_clk,
+                sys_reset           => soc_rst,
+                rgmii_eth_clocks_tx => eth_clocks_tx,
+                rgmii_eth_clocks_rx => eth_clocks_rx,
+                rgmii_eth_rst_n     => eth_rst_n,
+                rgmii_eth_int_n     => eth_int_n,
+                rgmii_eth_mdio      => eth_mdio,
+                rgmii_eth_mdc       => eth_mdc,
+                rgmii_eth_rx_ctl    => eth_rx_ctl,
+                rgmii_eth_rx_data   => eth_rx_data,
+                rgmii_eth_tx_ctl    => eth_tx_ctl,
+                rgmii_eth_tx_data   => eth_tx_data,
+                wishbone_adr        => wb_eth_adr,
+                wishbone_dat_w      => wb_ext_io_in.dat,
+                wishbone_dat_r      => wb_eth_out.dat,
+                wishbone_sel        => wb_ext_io_in.sel,
+                wishbone_cyc        => wb_eth_cyc,
+                wishbone_stb        => wb_ext_io_in.stb,
+                wishbone_ack        => wb_eth_out.ack,
+                wishbone_we         => wb_ext_io_in.we,
+                wishbone_cti        => "000",
+                wishbone_bte        => "00",
+                wishbone_err        => open,
+                interrupt           => ext_irq_eth
+                );
+
+        -- Gate cyc with "chip select" from soc
+        wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth;
+
+        -- Remove top address bits as liteeth decoder doesn't know about them
+        wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0);
+
+        -- LiteETH isn't pipelined
+        wb_eth_out.stall <= not wb_eth_out.ack;
+
+    end generate;
+
+    no_liteeth : if not USE_LITEETH generate
+        ext_irq_eth    <= '0';
+    end generate;
+
+
+    -- Mux WB response on the IO bus
+    wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else
+                     wb_dram_ctrl_out;
+
+    wb_sdcard_out.ack <= '0';
+    wb_sdcard_out.stall <= '0';
+
+    ext_irq_sdcard <= '0';
+
+    ext_rst_n <= '1';
+
+end architecture behaviour;
diff --git a/microwatt.core b/microwatt.core
index 5e603f1..b14a61e 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -109,6 +109,12 @@ filesets:
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
       - fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
 
+  antmicro-artix-dc-scm:
+    files:
+      - fpga/antmicro_artix_dc_scm.xdc: {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-antmicro-artix-dc-scm.vhdl : {file_type : vhdlSource-2008}
+
   wukong-v2:
     files:
       - fpga/wukong-v2.xdc : {file_type : xdc}
@@ -347,6 +353,28 @@ targets:
       vivado: {part : xc7a100ticsg324-1L}
     toplevel : toplevel
 
+  antmicro-artix-dc-scm:
+    default_tool: vivado
+    filesets: [core, antmicro-artix-dc-scm, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - use_liteeth=true
+      - clk_input
+      - clk_frequency
+      - disable_flatten_core
+      - no_bram
+      - log_length=2048
+      - uart_is_16550
+      - has_uart1
+      - has_fpu
+      - has_btc
+    generate: [litedram_nexys_video, liteeth_nexys_video, git_hash]
+    tools:
+      vivado: {part : xc7a100tfgg484-1}
+    toplevel : toplevel
+
   wukong-v2-a100t-nodram:
     default_tool: vivado
     filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
diff --git a/openocd/antmicro-artix-dc-scm.cfg b/openocd/antmicro-artix-dc-scm.cfg
new file mode 100644
index 0000000..885e5c2
--- /dev/null
+++ b/openocd/antmicro-artix-dc-scm.cfg
@@ -0,0 +1,6 @@
+interface ftdi
+ftdi_vid_pid 0x0403 0x6011
+ftdi_channel 0
+ftdi_layout_init 0x00e8 0x60eb
+reset_config none
+adapter_khz 25000