diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index c3be9d9..6e524f0 100644
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -10,6 +10,7 @@ use work.wishbone_types.all;
 
 entity toplevel is
     generic (
+        CPUS               : natural  := 1;
         MEMORY_SIZE        : integer  := 16384;
         RAM_INIT_FILE      : string   := "firmware.hex";
         RESET_LOW          : boolean  := true;
@@ -241,6 +242,7 @@ begin
             MEMORY_SIZE        => BRAM_SIZE,
             RAM_INIT_FILE      => RAM_INIT_FILE,
             SIM                => false,
+            NCPUS              => CPUS,
             CLK_FREQ           => CLK_FREQUENCY,
             HAS_FPU            => HAS_FPU,
             HAS_BTC            => HAS_BTC,
diff --git a/microwatt.core b/microwatt.core
index f56bee0..ed2aa01 100644
--- a/microwatt.core
+++ b/microwatt.core
@@ -335,6 +335,7 @@ targets:
     default_tool: vivado
     filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
     parameters:
+      - cpus
       - memory_size
       - ram_init_file
       - use_litedram=true
@@ -496,6 +497,12 @@ generate:
     parameters: {vendor : xilinx, frequency : 100e6}
 
 parameters:
+  cpus:
+    datatype    : int
+    description : Number of CPU cores to include in the SoC.
+    paramtype   : generic
+    default     : 1
+
   memory_size:
     datatype    : int
     description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload