diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl
index 6e524f0..e86cecd 100644
--- a/fpga/top-arty.vhdl
+++ b/fpga/top-arty.vhdl
@@ -145,6 +145,7 @@ architecture behaviour of toplevel is
 
     -- Status
     signal run_out : std_ulogic;
+    signal run_outs : std_ulogic_vector(CPUS-1 downto 0);
 
     -- Reset signals:
     signal soc_rst : std_ulogic;
@@ -269,6 +270,7 @@ begin
             rst               => soc_rst,
             sw_soc_reset      => sw_rst,
             run_out           => run_out,
+            run_outs          => run_outs,
 
             -- UART signals
             uart0_txd         => uart_main_tx,
@@ -746,9 +748,9 @@ begin
     end process;
 
     led4 <= system_clk_locked;
-    led5 <= eth_clk_locked;
-    led6 <= not soc_rst;
-    led7 <= run_out;
+    led5 <= not soc_rst;
+    led6 <= run_outs(1) when CPUS > 1 else '0';
+    led7 <= run_outs(0);
 
     -- GPIO
     gpio_in(10) <= btn0;
diff --git a/soc.vhdl b/soc.vhdl
index bf58826..7ae2cf2 100644
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -101,6 +101,7 @@ entity soc is
 	system_clk   : in  std_ulogic;
 
         run_out      : out std_ulogic;
+        run_outs     : out std_ulogic_vector(NCPUS-1 downto 0);
 
 	-- "Large" (64-bit) DRAM wishbone
 	wb_dram_in       : out wishbone_master_out;
@@ -393,6 +394,7 @@ begin
     end generate;
 
     run_out <= or (core_run_out);
+    run_outs <= core_run_out and not do_core_reset;
 
     -- Wishbone bus master arbiter & mux
     wb_masters_out(2*NCPUS)     <= wishbone_widen_data(wishbone_dma_out);