From 9c3d14dd5aa4ef82604759909fa6fab25550227d Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Wed, 26 Jul 2023 15:49:12 +1000 Subject: [PATCH] dcache: Make reading of DTLB independent of d_in.valid This improves timing. Signed-off-by: Paul Mackerras --- dcache.vhdl | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/dcache.vhdl b/dcache.vhdl index 11f563f..c9541e5 100644 --- a/dcache.vhdl +++ b/dcache.vhdl @@ -633,14 +633,20 @@ begin addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ); valid := d_in.valid; end if; - -- If we have any op and the previous op isn't finished, + -- If the previous op isn't finished, -- then keep the same output for next cycle. - if r0_stall = '0' and valid = '1' then - assert not is_X(addrbits); - index := to_integer(unsigned(addrbits)); - tlb_valid_way <= dtlb_valids(index); - tlb_tag_way <= dtlb_tags(index); - tlb_pte_way <= dtlb_ptes(index); + if r0_stall = '0' then + assert not (valid = '1' and is_X(addrbits)); + if is_X(addrbits) then + tlb_valid_way <= (others => 'X'); + tlb_tag_way <= (others => 'X'); + tlb_pte_way <= (others => 'X'); + else + index := to_integer(unsigned(addrbits)); + tlb_valid_way <= dtlb_valids(index); + tlb_tag_way <= dtlb_tags(index); + tlb_pte_way <= dtlb_ptes(index); + end if; end if; if rst = '1' then tlb_read_valid <= '0';