diff --git a/Makefile b/Makefile index bf1e761..23c79b2 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,6 @@ GHDL ?= ghdl -GHDLFLAGS=--std=08 --work=unisim -CFLAGS=-O2 -Wall +GHDLFLAGS=--std=08 --work=unisim -frelaxed +CFLAGS=-O3 -Wall GHDLSYNTH ?= ghdl.so YOSYS ?= yosys @@ -50,7 +50,7 @@ core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \ loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl core_debug.vhdl \ core.vhdl -soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl \ +soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \ wishbone_debug_master.vhdl xics.vhdl syscon.vhdl soc.vhdl soc_sim_files = sim_console.vhdl sim_uart.vhdl sim_bram_helpers.vhdl \ @@ -66,6 +66,7 @@ soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files)) core_tbs = multiply_tb divider_tb rotator_tb countzero_tb soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb +soc_dram_tbs = dram_tb core_dram_tb $(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl $(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@ @@ -76,6 +77,34 @@ $(core_tbs): %: $(core_files) glibc_random.vhdl glibc_random_helpers.vhdl %.vhdl soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl $(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@ +# LiteDRAM sim +VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null) +ifeq (, $(VERILATOR_ROOT)) +$(soc_dram_tbs): + $(error "Verilator is required to make this target !") +else + +VERILATOR_CFLAGS=-O3 +VERILATOR_FLAGS=-O3 +verilated_dram: litedram/generated/sim/litedram_core.v + verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $< --trace + make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT) + +SIM_DRAM_CFLAGS = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd +SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVL_PRINTF=printf -faligned-new +sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram + $(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@ + +soc_dram_files = $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl +soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl +soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o +dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o -Wl,obj_dir/verilated_vcd_c.o -Wl,-lstdc++ +soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files) + +$(soc_dram_tbs): %: $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) %.vhdl + $(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(core_files) $(soc_dram_files) $(soc_dram_sim_files) $@.vhdl -e $@ +endif + # Hello world MEMORY_SIZE=8192 RAM_INIT_FILE=hello_world/hello_world.hex @@ -167,6 +196,7 @@ _clean: rm -f *.o work-*cf unisim-*cf $(all) rm -f fpga/*.o fpga/work-*cf rm -f sim-unisim/*.o sim-unisim/unisim-*cf + rm -f litedram/extras/*.o rm -f TAGS rm -f scripts/mw_debug/*.o rm -f scripts/mw_debug/mw_debug diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl new file mode 100644 index 0000000..8f91746 --- /dev/null +++ b/core_dram_tb.vhdl @@ -0,0 +1,135 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.common.all; +use work.wishbone_types.all; + +entity core_dram_tb is + generic ( + MEMORY_SIZE : natural := (384*1024); + MAIN_RAM_FILE : string := "main_ram.bin"; + DRAM_INIT_FILE : string := ""; + DRAM_INIT_SIZE : natural := 16#c000# + ); +end core_dram_tb; + +architecture behave of core_dram_tb is + signal clk, rst: std_logic; + signal system_clk, soc_rst : std_ulogic; + + -- testbench signals + constant clk_period : time := 10 ns; + + -- Sim DRAM + signal wb_dram_in : wishbone_master_out; + signal wb_dram_out : wishbone_slave_out; + signal wb_dram_ctrl_in : wb_io_master_out; + signal wb_dram_ctrl_out : wb_io_slave_out; + signal wb_dram_is_csr : std_ulogic; + signal wb_dram_is_init : std_ulogic; + signal core_alt_reset : std_ulogic; + + -- ROM size + function get_rom_size return natural is + begin + if MEMORY_SIZE = 0 then + return DRAM_INIT_SIZE; + else + return 0; + end if; + end function; + + constant ROM_SIZE : natural := get_rom_size; +begin + + soc0: entity work.soc + generic map( + SIM => true, + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => MAIN_RAM_FILE, + RESET_LOW => false, + HAS_DRAM => true, + DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => ROM_SIZE, + CLK_FREQ => 100000000 + ) + port map( + rst => soc_rst, + system_clk => system_clk, + uart0_rxd => '0', + uart0_txd => open, + wb_dram_in => wb_dram_in, + wb_dram_out => wb_dram_out, + wb_dram_ctrl_in => wb_dram_ctrl_in, + wb_dram_ctrl_out => wb_dram_ctrl_out, + wb_dram_is_csr => wb_dram_is_csr, + wb_dram_is_init => wb_dram_is_init, + alt_reset => core_alt_reset + ); + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 1, + PAYLOAD_FILE => DRAM_INIT_FILE, + PAYLOAD_SIZE => ROM_SIZE + ) + port map( + clk_in => clk, + rst => rst, + system_clk => system_clk, + system_reset => soc_rst, + core_alt_reset => core_alt_reset, + pll_locked => open, + + wb_in => wb_dram_in, + wb_out => wb_dram_out, + wb_ctrl_in => wb_dram_ctrl_in, + wb_ctrl_out => wb_dram_ctrl_out, + wb_ctrl_is_csr => wb_dram_is_csr, + wb_ctrl_is_init => wb_dram_is_init, + + serial_tx => open, + serial_rx => '1', + + init_done => open, + init_error => open, + + ddram_a => open, + ddram_ba => open, + ddram_ras_n => open, + ddram_cas_n => open, + ddram_we_n => open, + ddram_cs_n => open, + ddram_dm => open, + ddram_dq => open, + ddram_dqs_p => open, + ddram_dqs_n => open, + ddram_clk_p => open, + ddram_clk_n => open, + ddram_cke => open, + ddram_odt => open, + ddram_reset_n => open + ); + + clk_process: process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + rst_process: process + begin + rst <= '1'; + wait for 10*clk_period; + rst <= '0'; + wait; + end process; + + jtag: entity work.sim_jtag; + +end; diff --git a/dram_tb.vhdl b/dram_tb.vhdl new file mode 100644 index 0000000..af0578e --- /dev/null +++ b/dram_tb.vhdl @@ -0,0 +1,301 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.common.all; +use work.wishbone_types.all; + +entity dram_tb is + generic ( + DRAM_INIT_FILE : string := ""; + DRAM_INIT_SIZE : natural := 0 + ); +end dram_tb; + +architecture behave of dram_tb is + signal clk, rst: std_logic; + signal clk_in, soc_rst : std_ulogic; + + -- testbench signals + constant clk_period : time := 10 ns; + + -- Sim DRAM + signal wb_in : wishbone_master_out; + signal wb_out : wishbone_slave_out; + signal wb_ctrl_in : wb_io_master_out; + + subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0); + subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0); + subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0); + + -- Counter for acks + signal acks : integer := 0; + signal reset_acks : std_ulogic; + + -- Read data fifo + signal rd_ready : std_ulogic := '0'; + signal rd_valid : std_ulogic; + signal rd_data : data_t; +begin + + dram: entity work.litedram_wrapper + generic map( + DRAM_ABITS => 24, + DRAM_ALINES => 1, + PAYLOAD_FILE => DRAM_INIT_FILE, + PAYLOAD_SIZE => DRAM_INIT_SIZE + ) + port map( + clk_in => clk_in, + rst => rst, + system_clk => clk, + system_reset => soc_rst, + core_alt_reset => open, + pll_locked => open, + + wb_in => wb_in, + wb_out => wb_out, + wb_ctrl_in => wb_ctrl_in, + wb_ctrl_out => open, + wb_ctrl_is_csr => '0', + wb_ctrl_is_init => '0', + + serial_tx => open, + serial_rx => '1', + + init_done => open, + init_error => open, + + ddram_a => open, + ddram_ba => open, + ddram_ras_n => open, + ddram_cas_n => open, + ddram_we_n => open, + ddram_cs_n => open, + ddram_dm => open, + ddram_dq => open, + ddram_dqs_p => open, + ddram_dqs_n => open, + ddram_clk_p => open, + ddram_clk_n => open, + ddram_cke => open, + ddram_odt => open, + ddram_reset_n => open + ); + + clk_process: process + begin + clk_in <= '0'; + wait for clk_period/2; + clk_in <= '1'; + wait for clk_period/2; + end process; + + rst_process: process + begin + rst <= '1'; + wait for 10*clk_period; + rst <= '0'; + wait; + end process; + + wb_ctrl_in.cyc <= '0'; + wb_ctrl_in.stb <= '0'; + + -- Read data receive queue + data_queue: entity work.sync_fifo + generic map ( + DEPTH => 16, + WIDTH => rd_data'length + ) + port map ( + clk => clk, + reset => soc_rst or reset_acks, + rd_ready => rd_ready, + rd_valid => rd_valid, + rd_data => rd_data, + wr_ready => open, + wr_valid => wb_out.ack, + wr_data => wb_out.dat + ); + + recv_acks: process(clk) + begin + if rising_edge(clk) then + if rst = '1' or reset_acks = '1' then + acks <= 0; + elsif wb_out.ack = '1' then + acks <= acks + 1; +-- report "WB ACK ! DATA=" & to_hstring(wb_out.dat); + end if; + end if; + end process; + + sim: process + procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is + begin + wb_in.adr <= addr; + wb_in.sel <= sel; + wb_in.dat <= data; + wb_in.we <= '1'; + wb_in.stb <= '1'; + wb_in.cyc <= '1'; + loop + wait until rising_edge(clk); + if wb_out.stall = '0' then + wb_in.stb <= '0'; + exit; + end if; + end loop; + end procedure; + + procedure wb_read(addr: addr_t) is + begin + wb_in.adr <= addr; + wb_in.sel <= x"ff"; + wb_in.we <= '0'; + wb_in.stb <= '1'; + wb_in.cyc <= '1'; + loop + wait until rising_edge(clk); + if wb_out.stall = '0' then + wb_in.stb <= '0'; + exit; + end if; + end loop; + end procedure; + + procedure wait_acks(count: integer) is + begin + wait until acks = count; + wait until rising_edge(clk); + end procedure; + + procedure clr_acks is + begin + reset_acks <= '1'; + wait until rising_edge(clk); + reset_acks <= '0'; + end procedure; + + procedure read_data(data: out data_t) is + begin + assert rd_valid = '1' report "No data to read" severity failure; + rd_ready <= '1'; + wait until rising_edge(clk); + rd_ready <= '0'; + data := rd_data; + end procedure; + + function add_off(a: addr_t; off: integer) return addr_t is + begin + return addr_t(unsigned(a) + off); + end function; + + function make_pattern(num : integer) return data_t is + variable r : data_t; + variable t,b : integer; + begin + for i in 0 to (data_t'length/8)-1 loop + t := (i+1)*8-1; + b := i*8; + r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8)); + end loop; + return r; + end function; + + procedure check_data(p: data_t) is + variable d : data_t; + begin + read_data(d); + assert d = p report "bad data, want " & to_hstring(p) & + " got " & to_hstring(d) severity failure; + end procedure; + + variable a : addr_t := (others => '0'); + variable d : data_t := (others => '0'); + variable d1 : data_t := (others => '0'); + begin + reset_acks <= '0'; + rst <= '1'; + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + wait until rising_edge(clk_in); + rst <= '0'; + wait until rising_edge(clk_in); + wait until soc_rst = '0'; + wait until rising_edge(clk); + + report "Simple write miss..."; + clr_acks; + wb_write(a, x"0123456789abcdef", x"ff"); + wait_acks(1); + + report "Simple read miss..."; + clr_acks; + wb_read(a); + wait_acks(1); + read_data(d); + assert d = x"0123456789abcdef" report "bad data" severity failure; + + report "Simple read hit..."; + clr_acks; + wb_read(a); + wait_acks(1); + read_data(d); + assert d = x"0123456789abcdef" report "bad data" severity failure; + + report "Back to back 4 stores 4 reads on hit..."; + clr_acks; + for i in 0 to 3 loop + wb_write(add_off(a, i*8), make_pattern(i), x"ff"); + end loop; + for i in 0 to 3 loop + wb_read(add_off(a, i*8)); + end loop; + wait_acks(8); + for i in 0 to 7 loop + if i < 4 then + read_data(d); + else + check_data(make_pattern(i-4)); + end if; + end loop; + + report "Back to back 4 stores 4 reads on miss..."; + a(10) := '1'; + clr_acks; + for i in 0 to 3 loop + wb_write(add_off(a, i*8), make_pattern(i), x"ff"); + end loop; + for i in 0 to 3 loop + wb_read(add_off(a, i*8)); + end loop; + wait_acks(8); + for i in 0 to 7 loop + if i < 4 then + read_data(d); + else + check_data(make_pattern(i-4)); + end if; + end loop; + + report "Back to back interleaved 4 stores 4 reads on hit..."; + a(10) := '1'; + clr_acks; + for i in 0 to 3 loop + wb_write(add_off(a, i*8), make_pattern(i), x"ff"); + wb_read(add_off(a, i*8)); + end loop; + wait_acks(8); + for i in 0 to 3 loop + read_data(d); + check_data(make_pattern(i)); + end loop; + + std.env.finish; + end process; +end architecture; diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index e3782ed..c8c2ed8 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -10,11 +10,12 @@ use work.wishbone_types.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 16384; + MEMORY_SIZE : integer := 16384; RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_FREQUENCY : positive := 100000000; USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false ); port( @@ -85,6 +86,28 @@ architecture behaviour of toplevel is -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise signal pwm_counter : std_ulogic_vector(8 downto 0); + + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; begin uart_pmod_rts_n <= '0'; @@ -92,13 +115,14 @@ begin -- Main SoC soc0: entity work.soc generic map( - MEMORY_SIZE => MEMORY_SIZE, + MEMORY_SIZE => BRAM_SIZE, RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 256 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( @@ -159,7 +183,7 @@ begin ); ddram_clk_dummy <= '0'; - end generate; + end generate; has_dram: if USE_LITEDRAM generate signal dram_init_done : std_ulogic; @@ -189,7 +213,9 @@ begin dram: entity work.litedram_wrapper generic map( DRAM_ABITS => 24, - DRAM_ALINES => 14 + DRAM_ALINES => 14, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE ) port map( clk_in => ext_clk, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 9acbee1..42e6c11 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -10,11 +10,12 @@ use work.wishbone_types.all; entity toplevel is generic ( - MEMORY_SIZE : positive := 16384; + MEMORY_SIZE : integer := 16384; RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; CLK_FREQUENCY : positive := 100000000; USE_LITEDRAM : boolean := false; + NO_BRAM : boolean := false; DISABLE_FLATTEN_CORE : boolean := false ); port( @@ -70,18 +71,40 @@ architecture behaviour of toplevel is -- Control/status signal core_alt_reset : std_ulogic; + -- Fixup various memory sizes based on generics + function get_bram_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return 0; + else + return MEMORY_SIZE; + end if; + end function; + + function get_payload_size return natural is + begin + if USE_LITEDRAM and NO_BRAM then + return MEMORY_SIZE; + else + return 0; + end if; + end function; + + constant BRAM_SIZE : natural := get_bram_size; + constant PAYLOAD_SIZE : natural := get_payload_size; begin -- Main SoC soc0: entity work.soc generic map( - MEMORY_SIZE => MEMORY_SIZE, + MEMORY_SIZE => BRAM_SIZE, RAM_INIT_FILE => RAM_INIT_FILE, RESET_LOW => RESET_LOW, SIM => false, CLK_FREQ => CLK_FREQUENCY, HAS_DRAM => USE_LITEDRAM, DRAM_SIZE => 512 * 1024 * 1024, + DRAM_INIT_SIZE => PAYLOAD_SIZE, DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE ) port map ( @@ -171,7 +194,9 @@ begin dram: entity work.litedram_wrapper generic map( DRAM_ABITS => 25, - DRAM_ALINES => 15 + DRAM_ALINES => 15, + PAYLOAD_FILE => RAM_INIT_FILE, + PAYLOAD_SIZE => PAYLOAD_SIZE ) port map( clk_in => ext_clk, diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index 443a8ae..866ccb4 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -23,6 +23,7 @@ #define SYS_REG_INFO 0x08 #define SYS_REG_INFO_HAS_UART (1ull << 0) #define SYS_REG_INFO_HAS_DRAM (1ull << 1) +#define SYS_REG_INFO_HAS_BRAM (1ull << 2) #define SYS_REG_BRAMINFO 0x10 #define SYS_REG_DRAMINFO 0x18 #define SYS_REG_CLKINFO 0x20 @@ -30,6 +31,7 @@ #define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0) #define SYS_REG_CTRL_CORE_RESET (1ull << 1) #define SYS_REG_CTRL_SOC_RESET (1ull << 2) +#define SYS_REG_DRAMINITINFO 0x30 /* * Register definitions for the potato UART diff --git a/litedram/extras/VexRiscv.v b/litedram/extras/VexRiscv.v deleted file mode 100644 index 0fda9d8..0000000 --- a/litedram/extras/VexRiscv.v +++ /dev/null @@ -1,3967 +0,0 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:53 -// Component : VexRiscv - - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -module StreamFifoLowLatency ( - input io_push_valid, - output io_push_ready, - input io_push_payload_error, - input [31:0] io_push_payload_inst, - output reg io_pop_valid, - input io_pop_ready, - output reg io_pop_payload_error, - output reg [31:0] io_pop_payload_inst, - input io_flush, - output [0:0] io_occupancy, - input clk, - input reset); - wire _zz_5_; - wire [0:0] _zz_6_; - reg _zz_1_; - reg pushPtr_willIncrement; - reg pushPtr_willClear; - wire pushPtr_willOverflowIfInc; - wire pushPtr_willOverflow; - reg popPtr_willIncrement; - reg popPtr_willClear; - wire popPtr_willOverflowIfInc; - wire popPtr_willOverflow; - wire ptrMatch; - reg risingOccupancy; - wire empty; - wire full; - wire pushing; - wire popping; - wire [32:0] _zz_2_; - wire [32:0] _zz_3_; - reg [32:0] _zz_4_; - assign _zz_5_ = (! empty); - assign _zz_6_ = _zz_2_[0 : 0]; - always @ (*) begin - _zz_1_ = 1'b0; - if(pushing)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - pushPtr_willIncrement = 1'b0; - if(pushing)begin - pushPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - pushPtr_willClear = 1'b0; - if(io_flush)begin - pushPtr_willClear = 1'b1; - end - end - - assign pushPtr_willOverflowIfInc = 1'b1; - assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin - popPtr_willIncrement = 1'b0; - if(popping)begin - popPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - popPtr_willClear = 1'b0; - if(io_flush)begin - popPtr_willClear = 1'b1; - end - end - - assign popPtr_willOverflowIfInc = 1'b1; - assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); - assign ptrMatch = 1'b1; - assign empty = (ptrMatch && (! risingOccupancy)); - assign full = (ptrMatch && risingOccupancy); - assign pushing = (io_push_valid && io_push_ready); - assign popping = (io_pop_valid && io_pop_ready); - assign io_push_ready = (! full); - always @ (*) begin - if(_zz_5_)begin - io_pop_valid = 1'b1; - end else begin - io_pop_valid = io_push_valid; - end - end - - assign _zz_2_ = _zz_3_; - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_error = _zz_6_[0]; - end else begin - io_pop_payload_error = io_push_payload_error; - end - end - - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_inst = _zz_2_[32 : 1]; - end else begin - io_pop_payload_inst = io_push_payload_inst; - end - end - - assign io_occupancy = (risingOccupancy && ptrMatch); - assign _zz_3_ = _zz_4_; - always @ (posedge clk) begin - if(reset) begin - risingOccupancy <= 1'b0; - end else begin - if((pushing != popping))begin - risingOccupancy <= pushing; - end - if(io_flush)begin - risingOccupancy <= 1'b0; - end - end - end - - always @ (posedge clk) begin - if(_zz_1_)begin - _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - reg [31:0] _zz_161_; - reg [31:0] _zz_162_; - reg [31:0] _zz_163_; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_164_; - wire _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire _zz_168_; - wire _zz_169_; - wire _zz_170_; - wire [1:0] _zz_171_; - wire _zz_172_; - wire _zz_173_; - wire _zz_174_; - wire _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire _zz_185_; - wire _zz_186_; - wire _zz_187_; - wire [1:0] _zz_188_; - wire _zz_189_; - wire [3:0] _zz_190_; - wire [2:0] _zz_191_; - wire [31:0] _zz_192_; - wire [2:0] _zz_193_; - wire [0:0] _zz_194_; - wire [2:0] _zz_195_; - wire [0:0] _zz_196_; - wire [2:0] _zz_197_; - wire [0:0] _zz_198_; - wire [2:0] _zz_199_; - wire [0:0] _zz_200_; - wire [2:0] _zz_201_; - wire [2:0] _zz_202_; - wire [0:0] _zz_203_; - wire [0:0] _zz_204_; - wire [0:0] _zz_205_; - wire [0:0] _zz_206_; - wire [0:0] _zz_207_; - wire [0:0] _zz_208_; - wire [0:0] _zz_209_; - wire [0:0] _zz_210_; - wire [0:0] _zz_211_; - wire [0:0] _zz_212_; - wire [0:0] _zz_213_; - wire [0:0] _zz_214_; - wire [2:0] _zz_215_; - wire [4:0] _zz_216_; - wire [11:0] _zz_217_; - wire [11:0] _zz_218_; - wire [31:0] _zz_219_; - wire [31:0] _zz_220_; - wire [31:0] _zz_221_; - wire [31:0] _zz_222_; - wire [31:0] _zz_223_; - wire [31:0] _zz_224_; - wire [31:0] _zz_225_; - wire [31:0] _zz_226_; - wire [32:0] _zz_227_; - wire [19:0] _zz_228_; - wire [11:0] _zz_229_; - wire [11:0] _zz_230_; - wire [1:0] _zz_231_; - wire [1:0] _zz_232_; - wire [1:0] _zz_233_; - wire [1:0] _zz_234_; - wire [0:0] _zz_235_; - wire [0:0] _zz_236_; - wire [0:0] _zz_237_; - wire [0:0] _zz_238_; - wire [0:0] _zz_239_; - wire [0:0] _zz_240_; - wire [6:0] _zz_241_; - wire _zz_242_; - wire _zz_243_; - wire [1:0] _zz_244_; - wire [31:0] _zz_245_; - wire [31:0] _zz_246_; - wire [31:0] _zz_247_; - wire _zz_248_; - wire [0:0] _zz_249_; - wire [0:0] _zz_250_; - wire _zz_251_; - wire [0:0] _zz_252_; - wire [18:0] _zz_253_; - wire [31:0] _zz_254_; - wire [31:0] _zz_255_; - wire [31:0] _zz_256_; - wire [31:0] _zz_257_; - wire [31:0] _zz_258_; - wire [31:0] _zz_259_; - wire _zz_260_; - wire [1:0] _zz_261_; - wire [1:0] _zz_262_; - wire _zz_263_; - wire [0:0] _zz_264_; - wire [14:0] _zz_265_; - wire [31:0] _zz_266_; - wire [31:0] _zz_267_; - wire [31:0] _zz_268_; - wire [31:0] _zz_269_; - wire [0:0] _zz_270_; - wire [0:0] _zz_271_; - wire [0:0] _zz_272_; - wire [0:0] _zz_273_; - wire _zz_274_; - wire [0:0] _zz_275_; - wire [11:0] _zz_276_; - wire [31:0] _zz_277_; - wire [31:0] _zz_278_; - wire [31:0] _zz_279_; - wire _zz_280_; - wire [0:0] _zz_281_; - wire [1:0] _zz_282_; - wire [0:0] _zz_283_; - wire [0:0] _zz_284_; - wire [1:0] _zz_285_; - wire [1:0] _zz_286_; - wire _zz_287_; - wire [0:0] _zz_288_; - wire [8:0] _zz_289_; - wire [31:0] _zz_290_; - wire [31:0] _zz_291_; - wire [31:0] _zz_292_; - wire [31:0] _zz_293_; - wire [31:0] _zz_294_; - wire [31:0] _zz_295_; - wire [31:0] _zz_296_; - wire [31:0] _zz_297_; - wire _zz_298_; - wire _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire [1:0] _zz_302_; - wire [1:0] _zz_303_; - wire _zz_304_; - wire [0:0] _zz_305_; - wire [5:0] _zz_306_; - wire [31:0] _zz_307_; - wire [31:0] _zz_308_; - wire [31:0] _zz_309_; - wire [31:0] _zz_310_; - wire _zz_311_; - wire _zz_312_; - wire [1:0] _zz_313_; - wire [1:0] _zz_314_; - wire _zz_315_; - wire [0:0] _zz_316_; - wire [2:0] _zz_317_; - wire [31:0] _zz_318_; - wire [31:0] _zz_319_; - wire [31:0] _zz_320_; - wire [31:0] _zz_321_; - wire _zz_322_; - wire [0:0] _zz_323_; - wire [0:0] _zz_324_; - wire [0:0] _zz_325_; - wire [1:0] _zz_326_; - wire [5:0] _zz_327_; - wire [5:0] _zz_328_; - wire _zz_329_; - wire _zz_330_; - wire [31:0] _zz_331_; - wire [31:0] _zz_332_; - wire [31:0] _zz_333_; - wire [31:0] _zz_334_; - wire [31:0] _zz_335_; - wire [31:0] _zz_336_; - wire [31:0] _zz_337_; - wire _zz_338_; - wire [0:0] _zz_339_; - wire [2:0] _zz_340_; - wire [31:0] _zz_341_; - wire [31:0] _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire [31:0] _zz_345_; - wire [31:0] _zz_346_; - wire [31:0] _zz_347_; - wire _zz_348_; - wire [0:0] _zz_349_; - wire [12:0] _zz_350_; - wire [31:0] _zz_351_; - wire [31:0] _zz_352_; - wire [31:0] _zz_353_; - wire _zz_354_; - wire [0:0] _zz_355_; - wire [6:0] _zz_356_; - wire [31:0] _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire _zz_360_; - wire [0:0] _zz_361_; - wire [0:0] _zz_362_; - wire [31:0] decode_RS1; - wire execute_BRANCH_DO; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_SRC2_FORCE_ZERO; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_3_; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] execute_BRANCH_CALC; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_STORE; - wire [31:0] memory_MEMORY_READ_DATA; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire decode_IS_CSR; - wire [31:0] decode_RS2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_11_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_16_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17_; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire decode_CSR_READ_OPCODE; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; - wire _zz_28_; - wire _zz_29_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_31_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; - wire _zz_33_; - wire decode_RS2_USE; - wire decode_RS1_USE; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_34_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_; - wire _zz_36_; - wire [31:0] _zz_37_; - wire [31:0] _zz_38_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40_; - wire [31:0] _zz_41_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_42_; - wire [31:0] _zz_43_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_44_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_; - wire [31:0] _zz_48_; - wire _zz_49_; - reg _zz_50_; - wire [31:0] _zz_51_; - wire [31:0] _zz_52_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_53_; - wire _zz_54_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_55_; - wire _zz_56_; - wire _zz_57_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_59_; - wire `AluCtrlEnum_defaultEncoding_type _zz_60_; - wire _zz_61_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_62_; - wire _zz_63_; - wire _zz_64_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_72_; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP_physicalAddress; - wire memory_MMU_RSP_isIoAccess; - wire memory_MMU_RSP_allowRead; - wire memory_MMU_RSP_allowWrite; - wire memory_MMU_RSP_allowExecute; - wire memory_MMU_RSP_exception; - wire memory_MMU_RSP_refilling; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; - wire [31:0] _zz_73_; - wire [31:0] _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP_physicalAddress; - wire execute_MMU_RSP_isIoAccess; - wire execute_MMU_RSP_allowRead; - wire execute_MMU_RSP_allowWrite; - wire execute_MMU_RSP_allowExecute; - wire execute_MMU_RSP_exception; - wire execute_MMU_RSP_refilling; - wire _zz_81_; - wire [31:0] execute_SRC_ADD; - wire [1:0] _zz_82_; - wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; - wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - wire _zz_83_; - wire decode_MEMORY_ENABLE; - reg [31:0] _zz_84_; - reg [31:0] _zz_85_; - wire [31:0] decode_PC; - wire [31:0] _zz_86_; - wire [31:0] _zz_87_; - wire [31:0] _zz_88_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_89_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - reg decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusSimplePlugin_fetcherHalt; - reg IBusSimplePlugin_fetcherflushIt; - reg IBusSimplePlugin_incomingInstruction; - wire IBusSimplePlugin_pcValids_0; - wire IBusSimplePlugin_pcValids_1; - wire IBusSimplePlugin_pcValids_2; - wire IBusSimplePlugin_pcValids_3; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - wire [31:0] iBus_cmd_payload_pc; - wire iBus_rsp_valid; - wire iBus_rsp_payload_error; - wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; - wire IBusSimplePlugin_redoBranch_valid; - wire [31:0] IBusSimplePlugin_redoBranch_payload; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusSimplePlugin_jump_pcLoad_valid; - wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [3:0] _zz_90_; - wire [3:0] _zz_91_; - wire _zz_92_; - wire _zz_93_; - wire _zz_94_; - wire IBusSimplePlugin_fetchPc_output_valid; - wire IBusSimplePlugin_fetchPc_output_ready; - wire [31:0] IBusSimplePlugin_fetchPc_output_payload; - reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusSimplePlugin_fetchPc_corrected; - reg IBusSimplePlugin_fetchPc_pcRegPropagate; - reg IBusSimplePlugin_fetchPc_booted; - reg IBusSimplePlugin_fetchPc_inc; - reg [31:0] IBusSimplePlugin_fetchPc_pc; - reg IBusSimplePlugin_iBusRsp_stages_0_input_valid; - reg IBusSimplePlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; - reg IBusSimplePlugin_iBusRsp_stages_0_halt; - wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; - wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; - wire _zz_95_; - wire _zz_96_; - wire _zz_97_; - wire _zz_98_; - reg _zz_99_; - reg IBusSimplePlugin_iBusRsp_readyForError; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; - wire IBusSimplePlugin_injector_decodeInput_valid; - wire IBusSimplePlugin_injector_decodeInput_ready; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; - wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_100_; - reg [31:0] _zz_101_; - reg _zz_102_; - reg [31:0] _zz_103_; - reg _zz_104_; - reg IBusSimplePlugin_injector_nextPcCalc_valids_0; - reg IBusSimplePlugin_injector_nextPcCalc_valids_1; - reg IBusSimplePlugin_injector_nextPcCalc_valids_2; - reg IBusSimplePlugin_injector_nextPcCalc_valids_3; - reg IBusSimplePlugin_injector_nextPcCalc_valids_4; - reg IBusSimplePlugin_injector_decodeRemoved; - reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; - wire IBusSimplePlugin_cmd_ready; - wire [31:0] IBusSimplePlugin_cmd_payload_pc; - reg [2:0] IBusSimplePlugin_pendingCmd; - wire [2:0] IBusSimplePlugin_pendingCmdNext; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; - wire iBus_rsp_takeWhen_valid; - wire iBus_rsp_takeWhen_payload_error; - wire [31:0] iBus_rsp_takeWhen_payload_inst; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; - reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - wire IBusSimplePlugin_rspJoin_join_valid; - wire IBusSimplePlugin_rspJoin_join_ready; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; - wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - reg IBusSimplePlugin_rspJoin_redoRequired; - wire _zz_105_; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_106_; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_107_; - reg [3:0] _zz_108_; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_109_; - reg [31:0] _zz_110_; - wire _zz_111_; - reg [31:0] _zz_112_; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [25:0] _zz_113_; - wire _zz_114_; - wire _zz_115_; - wire _zz_116_; - wire _zz_117_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_119_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_120_; - wire `AluCtrlEnum_defaultEncoding_type _zz_121_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_122_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_124_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_125_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_126_; - reg [31:0] _zz_127_; - wire _zz_128_; - reg [19:0] _zz_129_; - wire _zz_130_; - reg [19:0] _zz_131_; - reg [31:0] _zz_132_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_133_; - reg _zz_134_; - reg _zz_135_; - wire _zz_136_; - reg _zz_137_; - reg [4:0] _zz_138_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_139_; - reg _zz_140_; - reg _zz_141_; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_142_; - reg [10:0] _zz_143_; - wire _zz_144_; - reg [19:0] _zz_145_; - wire _zz_146_; - reg [18:0] _zz_147_; - reg [31:0] _zz_148_; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_149_; - wire _zz_150_; - wire _zz_151_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_152_; - wire _zz_153_; - wire [1:0] _zz_154_; - wire _zz_155_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_156_; - wire [31:0] _zz_157_; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg execute_to_memory_MMU_FAULT; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; - reg execute_to_memory_MMU_RSP_isIoAccess; - reg execute_to_memory_MMU_RSP_allowRead; - reg execute_to_memory_MMU_RSP_allowWrite; - reg execute_to_memory_MMU_RSP_allowExecute; - reg execute_to_memory_MMU_RSP_exception; - reg execute_to_memory_MMU_RSP_refilling; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg execute_to_memory_ALIGNEMENT_FAULT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BRANCH_DO; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire iBus_cmd_m2sPipe_valid; - wire iBus_cmd_m2sPipe_ready; - wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg _zz_158_; - reg [31:0] _zz_159_; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_160_; - `ifndef SYNTHESIS - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_1__string; - reg [23:0] _zz_2__string; - reg [23:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_11__string; - reg [95:0] _zz_12__string; - reg [95:0] _zz_13__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_14__string; - reg [31:0] _zz_15__string; - reg [31:0] _zz_16__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17__string; - reg [63:0] _zz_18__string; - reg [63:0] _zz_19__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_20__string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_23__string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_26__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_27__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_30__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_32__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_35__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_42__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_45__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_47__string; - reg [39:0] _zz_55__string; - reg [39:0] _zz_58__string; - reg [31:0] _zz_59__string; - reg [63:0] _zz_60__string; - reg [23:0] _zz_62__string; - reg [95:0] _zz_65__string; - reg [71:0] _zz_70__string; - reg [71:0] _zz_118__string; - reg [95:0] _zz_119__string; - reg [23:0] _zz_120__string; - reg [63:0] _zz_121__string; - reg [31:0] _zz_122__string; - reg [39:0] _zz_123__string; - reg [39:0] _zz_124__string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_167_ = (! execute_arbitration_isStuckByOthers); - assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); - assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_171_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling); - assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_177_ = (1'b1 || (! 1'b1)); - assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0)); - assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0)); - assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0)); - assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_188_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_189_ = execute_INSTRUCTION[13]; - assign _zz_190_ = (_zz_90_ - (4'b0001)); - assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; - assign _zz_192_ = {29'd0, _zz_191_}; - assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_); - assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign _zz_195_ = {2'd0, _zz_194_}; - assign _zz_196_ = iBus_rsp_valid; - assign _zz_197_ = {2'd0, _zz_196_}; - assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); - assign _zz_199_ = {2'd0, _zz_198_}; - assign _zz_200_ = iBus_rsp_valid; - assign _zz_201_ = {2'd0, _zz_200_}; - assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); - assign _zz_203_ = _zz_113_[2 : 2]; - assign _zz_204_ = _zz_113_[4 : 4]; - assign _zz_205_ = _zz_113_[5 : 5]; - assign _zz_206_ = _zz_113_[6 : 6]; - assign _zz_207_ = _zz_113_[9 : 9]; - assign _zz_208_ = _zz_113_[10 : 10]; - assign _zz_209_ = _zz_113_[13 : 13]; - assign _zz_210_ = _zz_113_[20 : 20]; - assign _zz_211_ = _zz_113_[21 : 21]; - assign _zz_212_ = _zz_113_[24 : 24]; - assign _zz_213_ = _zz_113_[25 : 25]; - assign _zz_214_ = execute_SRC_LESS; - assign _zz_215_ = (3'b100); - assign _zz_216_ = execute_INSTRUCTION[19 : 15]; - assign _zz_217_ = execute_INSTRUCTION[31 : 20]; - assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_)); - assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_)); - assign _zz_221_ = execute_SRC1; - assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_); - assign _zz_224_ = (32'b00000000000000000000000000000001); - assign _zz_225_ = (32'b00000000000000000000000000000000); - assign _zz_226_ = (_zz_227_ >>> 1); - assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_229_ = execute_INSTRUCTION[31 : 20]; - assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_231_ = (_zz_152_ & (~ _zz_232_)); - assign _zz_232_ = (_zz_152_ - (2'b01)); - assign _zz_233_ = (_zz_154_ & (~ _zz_234_)); - assign _zz_234_ = (_zz_154_ - (2'b01)); - assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_242_ = 1'b1; - assign _zz_243_ = 1'b1; - assign _zz_244_ = {_zz_94_,_zz_93_}; - assign _zz_245_ = (32'b00000000000000000000000000010000); - assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); - assign _zz_247_ = (32'b00000000000000000000000001010000); - assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_250_ = (1'b0); - assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00)); - assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0)); - assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}}; - assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_255_ = (32'b00000000000000000000000000100100); - assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100)); - assign _zz_257_ = (32'b00000000000000000001000000010000); - assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_259_ = (32'b00000000000000000001000000000000); - assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)}; - assign _zz_262_ = (2'b00); - assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0)); - assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00)); - assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}}; - assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); - assign _zz_267_ = (32'b00000000000000000000000000000100); - assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_269_ = (32'b00000000000000000000000001000000); - assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000)); - assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000)); - assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000)); - assign _zz_273_ = (1'b0); - assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000)); - assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00)); - assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}}; - assign _zz_277_ = (32'b00000000000000000110000000010100); - assign _zz_278_ = (32'b00000000000000000101000000010100); - assign _zz_279_ = (32'b00000000000000000110000000010100); - assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000)); - assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000)); - assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)}; - assign _zz_283_ = _zz_117_; - assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000)); - assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)}; - assign _zz_286_ = (2'b00); - assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00)); - assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00)); - assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}}; - assign _zz_290_ = (32'b00000000000000000000000000011000); - assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_292_ = (32'b00000000000000000010000000000000); - assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_294_ = (32'b00000000000000000001000000000000); - assign _zz_295_ = (32'b00000000000000000000000001110000); - assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_297_ = (32'b00000000000000000000000000000000); - assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); - assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000)); - assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000)); - assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_}; - assign _zz_303_ = (2'b00); - assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00)); - assign _zz_305_ = (_zz_312_ != (1'b0)); - assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}}; - assign _zz_307_ = (32'b00000000000000000001000001010000); - assign _zz_308_ = (32'b00000000000000000010000001010000); - assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_310_ = (32'b00000000000000000000000000000100); - assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)}; - assign _zz_314_ = (2'b00); - assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000)); - assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000)); - assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}}; - assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_319_ = (32'b00000000000000000000000000100000); - assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_321_ = (32'b00000000000000000000000000100000); - assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000)); - assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000)); - assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000)); - assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)}; - assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}}; - assign _zz_328_ = (6'b000000); - assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0)); - assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00)); - assign _zz_331_ = (32'b00000000000000000010000000010100); - assign _zz_332_ = (32'b01000000000000000100000000110100); - assign _zz_333_ = (32'b00000000000000000000000001010000); - assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_335_ = (32'b00000000000000000000000000000000); - assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); - assign _zz_337_ = (32'b00000000000000000000000001000000); - assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000)); - assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); - assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}}; - assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); - assign _zz_342_ = (32'b00000000000000000101000000010000); - assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); - assign _zz_345_ = (32'b00000000000000000001000001111111); - assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_347_ = (32'b00000000000000000010000001110011); - assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}}; - assign _zz_351_ = (32'b00000000000000000101000001011111); - assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_353_ = (32'b00000000000000000000000001100011); - assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}}; - assign _zz_357_ = (32'b10111110000000000111000001111111); - assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_359_ = (32'b00000000000000000000000000110011); - assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); - always @ (posedge clk) begin - if(_zz_50_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_242_) begin - _zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_243_) begin - _zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid(iBus_rsp_takeWhen_valid), - .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), - .io_push_payload_error(iBus_rsp_takeWhen_payload_error), - .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), - .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), - .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), - .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), - .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), - .io_flush(IBusSimplePlugin_fetcherflushIt), - .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), - .clk(clk), - .reset(reset) - ); - always @(*) begin - case(_zz_244_) - 2'b00 : begin - _zz_163_ = CsrPlugin_jumpInterface_payload; - end - 2'b01 : begin - _zz_163_ = DBusSimplePlugin_redoBranch_payload; - end - 2'b10 : begin - _zz_163_ = BranchPlugin_jumpInterface_payload; - end - default : begin - _zz_163_ = IBusSimplePlugin_redoBranch_payload; - end - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_1_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC "; - default : _zz_1__string = "???"; - endcase - end - always @(*) begin - case(_zz_2_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC "; - default : _zz_2__string = "???"; - endcase - end - always @(*) begin - case(_zz_3_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC "; - default : _zz_3__string = "???"; - endcase - end - always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; - endcase - end - always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; - endcase - end - always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; - endcase - end - always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_8_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; - default : _zz_8__string = "?????"; - endcase - end - always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; - endcase - end - always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_11_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 "; - default : _zz_11__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_12_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; - default : _zz_12__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_13_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; - default : _zz_13__string = "????????????"; - endcase - end - always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_14_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; - default : _zz_14__string = "????"; - endcase - end - always @(*) begin - case(_zz_15_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; - default : _zz_15__string = "????"; - endcase - end - always @(*) begin - case(_zz_16_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR"; - default : _zz_16__string = "????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_17_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; - default : _zz_17__string = "????????"; - endcase - end - always @(*) begin - case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; - endcase - end - always @(*) begin - case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_23_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1"; - default : _zz_23__string = "?????"; - endcase - end - always @(*) begin - case(_zz_24_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; - default : _zz_24__string = "?????"; - endcase - end - always @(*) begin - case(_zz_25_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; - default : _zz_25__string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_27_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL"; - default : _zz_27__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_30_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL"; - default : _zz_30__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_32_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; - default : _zz_32__string = "????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_35_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 "; - default : _zz_35__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_40_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; - default : _zz_40__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_42_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 "; - default : _zz_42__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_45_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE "; - default : _zz_45__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_47_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1"; - default : _zz_47__string = "?????"; - endcase - end - always @(*) begin - case(_zz_55_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL"; - default : _zz_55__string = "?????"; - endcase - end - always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; - endcase - end - always @(*) begin - case(_zz_59_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR"; - default : _zz_59__string = "????"; - endcase - end - always @(*) begin - case(_zz_60_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE "; - default : _zz_60__string = "????????"; - endcase - end - always @(*) begin - case(_zz_62_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC "; - default : _zz_62__string = "???"; - endcase - end - always @(*) begin - case(_zz_65_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 "; - default : _zz_65__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_70_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1 "; - default : _zz_70__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_118_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1 "; - default : _zz_118__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_119_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1 "; - default : _zz_119__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_120_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC "; - default : _zz_120__string = "???"; - endcase - end - always @(*) begin - case(_zz_121_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE "; - default : _zz_121__string = "????????"; - endcase - end - always @(*) begin - case(_zz_122_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR"; - default : _zz_122__string = "????"; - endcase - end - always @(*) begin - case(_zz_123_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1"; - default : _zz_123__string = "?????"; - endcase - end - always @(*) begin - case(_zz_124_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL"; - default : _zz_124__string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; - default : decode_to_execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end - `endif - - assign decode_RS1 = _zz_52_; - assign execute_BRANCH_DO = _zz_33_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_; - assign decode_SRC2_FORCE_ZERO = _zz_44_; - assign decode_SRC2_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_46_; - assign decode_CSR_WRITE_OPCODE = _zz_29_; - assign execute_BRANCH_CALC = _zz_31_; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_86_; - assign decode_SRC_LESS_UNSIGNED = _zz_63_; - assign decode_MEMORY_STORE = _zz_56_; - assign memory_MEMORY_READ_DATA = _zz_73_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_; - assign decode_IS_CSR = _zz_64_; - assign decode_RS2 = _zz_51_; - assign _zz_4_ = _zz_5_; - assign _zz_6_ = _zz_7_; - assign decode_ENV_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_82_; - assign decode_SRC1_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; - assign decode_BRANCH_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_ALU_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign decode_CSR_READ_OPCODE = _zz_28_; - assign decode_SHIFT_CTRL = _zz_20_; - assign _zz_21_ = _zz_22_; - assign decode_ALU_BITWISE_CTRL = _zz_23_; - assign _zz_24_ = _zz_25_; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_26_; - assign execute_ENV_CTRL = _zz_27_; - assign writeBack_ENV_CTRL = _zz_30_; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_32_; - assign decode_RS2_USE = _zz_67_; - assign decode_RS1_USE = _zz_61_; - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_34_ = execute_REGFILE_WRITE_DATA; - if(_zz_164_)begin - _zz_34_ = _zz_133_; - end - if(_zz_165_)begin - _zz_34_ = execute_CsrPlugin_readData; - end - end - - assign execute_SHIFT_CTRL = _zz_35_; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39_ = execute_PC; - assign execute_SRC2_CTRL = _zz_40_; - assign execute_SRC1_CTRL = _zz_42_; - assign decode_SRC_USE_SUB_LESS = _zz_68_; - assign decode_SRC_ADD_ZERO = _zz_57_; - assign execute_SRC_ADD_SUB = _zz_38_; - assign execute_SRC_LESS = _zz_36_; - assign execute_ALU_CTRL = _zz_45_; - assign execute_SRC2 = _zz_41_; - assign execute_SRC1 = _zz_43_; - assign execute_ALU_BITWISE_CTRL = _zz_47_; - assign _zz_48_ = writeBack_INSTRUCTION; - assign _zz_49_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_50_ = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_50_ = 1'b1; - end - end - - assign decode_INSTRUCTION_ANTICIPATED = _zz_89_; - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_69_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin - decode_REGFILE_WRITE_VALID = 1'b0; - end - end - - assign decode_LEGAL_INSTRUCTION = _zz_71_; - assign decode_INSTRUCTION_READY = 1'b1; - assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_72_ = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_72_ = writeBack_DBusSimplePlugin_rspFormated; - end - end - - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; - assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; - assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; - assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; - assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; - assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; - assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; - assign memory_PC = execute_to_memory_PC; - assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = _zz_81_; - assign execute_MMU_RSP_physicalAddress = _zz_74_; - assign execute_MMU_RSP_isIoAccess = _zz_75_; - assign execute_MMU_RSP_allowRead = _zz_76_; - assign execute_MMU_RSP_allowWrite = _zz_77_; - assign execute_MMU_RSP_allowExecute = _zz_78_; - assign execute_MMU_RSP_exception = _zz_79_; - assign execute_MMU_RSP_refilling = _zz_80_; - assign execute_SRC_ADD = _zz_37_; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = _zz_83_; - assign decode_MEMORY_ENABLE = _zz_66_; - always @ (*) begin - _zz_84_ = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_84_ = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_84_ = BranchPlugin_jumpInterface_payload; - end - end - - always @ (*) begin - _zz_85_ = decode_FORMAL_PC_NEXT; - if(IBusSimplePlugin_redoBranch_valid)begin - _zz_85_ = IBusSimplePlugin_redoBranch_payload; - end - end - - assign decode_PC = _zz_88_; - assign decode_INSTRUCTION = _zz_87_; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - end - - always @ (*) begin - decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin - decode_arbitration_haltByOther = 1'b1; - end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; - end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin - decode_arbitration_haltByOther = 1'b1; - end - end - - always @ (*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_166_)begin - decode_arbitration_removeIt = 1'b1; - end - if(decode_arbitration_isFlushed)begin - decode_arbitration_removeIt = 1'b1; - end - end - - always @ (*) begin - decode_arbitration_flushIt = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin - decode_arbitration_flushNext = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushNext = 1'b1; - end - if(_zz_166_)begin - decode_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin - execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_164_)begin - if(_zz_167_)begin - if(! execute_LightShifterPlugin_done) begin - execute_arbitration_haltItself = 1'b1; - end - end - end - if(_zz_165_)begin - if(execute_CsrPlugin_blockedBySideEffects)begin - execute_arbitration_haltItself = 1'b1; - end - end - end - - assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed)begin - execute_arbitration_removeIt = 1'b1; - end - end - - assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin - execute_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin - memory_arbitration_haltItself = 1'b1; - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin - memory_arbitration_removeIt = 1'b0; - if(_zz_168_)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_168_)begin - memory_arbitration_flushNext = 1'b1; - end - end - - assign writeBack_arbitration_haltItself = 1'b0; - assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin - writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin - writeBack_arbitration_flushNext = 1'b0; - if(_zz_169_)begin - writeBack_arbitration_flushNext = 1'b1; - end - if(_zz_170_)begin - writeBack_arbitration_flushNext = 1'b1; - end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin - IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - if(_zz_169_)begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - if(_zz_170_)begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - end - - always @ (*) begin - IBusSimplePlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusSimplePlugin_fetcherflushIt = 1'b1; - end - end - - always @ (*) begin - IBusSimplePlugin_incomingInstruction = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; - end - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; - end - end - - always @ (*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_169_)begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(_zz_170_)begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - end - - always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_169_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; - end - if(_zz_170_)begin - case(_zz_171_) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; - end - default : begin - end - endcase - end - end - - assign CsrPlugin_forceMachineWire = 1'b0; - assign CsrPlugin_allowInterrupts = 1'b1; - assign CsrPlugin_allowException = 1'b1; - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000)); - assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_91_ = (_zz_90_ & (~ _zz_190_)); - assign _zz_92_ = _zz_91_[3]; - assign _zz_93_ = (_zz_91_[1] || _zz_92_); - assign _zz_94_ = (_zz_91_[2] || _zz_92_); - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_; - always @ (*) begin - IBusSimplePlugin_fetchPc_corrected = 1'b0; - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_corrected = 1'b1; - end - end - - always @ (*) begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; - end - end - - always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_); - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; - end - IBusSimplePlugin_fetchPc_pc[0] = 1'b0; - IBusSimplePlugin_fetchPc_pc[1] = 1'b0; - end - - assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); - assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0; - end - end - - assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; - assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(_zz_172_)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end - - assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_); - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0; - end - end - - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_); - assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_); - assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_; - assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_98_ = _zz_99_; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_; - assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; - always @ (*) begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b1; - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; - end - if((! IBusSimplePlugin_pcValids_0))begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_; - assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst); - assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; - assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; - assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; - assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; - assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); - assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc; - assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; - assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; - assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_); - always @ (*) begin - IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); - if(_zz_172_)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - end - - assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)}; - assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); - assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; - assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; - always @ (*) begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; - end - end - - assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; - always @ (*) begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_173_)begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; - end - end - - always @ (*) begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b1; - end - end - - assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); - assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired)); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError); - assign IBusSimplePlugin_redoBranch_payload = decode_PC; - always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_173_)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100); - end - end - - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)}; - assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_106_ = 1'b0; - assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); - always @ (*) begin - execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - end - - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)); - assign dBus_cmd_payload_wr = execute_MEMORY_STORE; - assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - case(dBus_cmd_payload_size) - 2'b00 : begin - _zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_107_ = execute_RS2[31 : 0]; - end - endcase - end - - assign dBus_cmd_payload_data = _zz_107_; - assign _zz_82_ = dBus_cmd_payload_address[1 : 0]; - always @ (*) begin - case(dBus_cmd_payload_size) - 2'b00 : begin - _zz_108_ = (4'b0001); - end - 2'b01 : begin - _zz_108_ = (4'b0011); - end - default : begin - _zz_108_ = (4'b1111); - end - endcase - end - - assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); - assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception; - assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling; - assign _zz_73_ = dBus_rsp_data; - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_174_)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_MMU_RSP_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_175_)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end - end - - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); - if(_zz_174_)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_}; - end - if(! memory_MMU_RSP_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); - end - end - end - - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_175_)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin - writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; - end - 2'b10 : begin - writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; - end - 2'b11 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; - end - default : begin - end - endcase - end - - assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_110_[31] = _zz_109_; - _zz_110_[30] = _zz_109_; - _zz_110_[29] = _zz_109_; - _zz_110_[28] = _zz_109_; - _zz_110_[27] = _zz_109_; - _zz_110_[26] = _zz_109_; - _zz_110_[25] = _zz_109_; - _zz_110_[24] = _zz_109_; - _zz_110_[23] = _zz_109_; - _zz_110_[22] = _zz_109_; - _zz_110_[21] = _zz_109_; - _zz_110_[20] = _zz_109_; - _zz_110_[19] = _zz_109_; - _zz_110_[18] = _zz_109_; - _zz_110_[17] = _zz_109_; - _zz_110_[16] = _zz_109_; - _zz_110_[15] = _zz_109_; - _zz_110_[14] = _zz_109_; - _zz_110_[13] = _zz_109_; - _zz_110_[12] = _zz_109_; - _zz_110_[11] = _zz_109_; - _zz_110_[10] = _zz_109_; - _zz_110_[9] = _zz_109_; - _zz_110_[8] = _zz_109_; - _zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_112_[31] = _zz_111_; - _zz_112_[30] = _zz_111_; - _zz_112_[29] = _zz_111_; - _zz_112_[28] = _zz_111_; - _zz_112_[27] = _zz_111_; - _zz_112_[26] = _zz_111_; - _zz_112_[25] = _zz_111_; - _zz_112_[24] = _zz_111_; - _zz_112_[23] = _zz_111_; - _zz_112_[22] = _zz_111_; - _zz_112_[21] = _zz_111_; - _zz_112_[20] = _zz_111_; - _zz_112_[19] = _zz_111_; - _zz_112_[18] = _zz_111_; - _zz_112_[17] = _zz_111_; - _zz_112_[16] = _zz_111_; - _zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_188_) - 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_110_; - end - 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_112_; - end - default : begin - writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; - end - endcase - end - - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress; - assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusSimplePlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); - assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}}; - assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000)); - assign _zz_118_ = _zz_113_[1 : 0]; - assign _zz_70_ = _zz_118_; - assign _zz_69_ = _zz_203_[0]; - assign _zz_68_ = _zz_204_[0]; - assign _zz_67_ = _zz_205_[0]; - assign _zz_66_ = _zz_206_[0]; - assign _zz_119_ = _zz_113_[8 : 7]; - assign _zz_65_ = _zz_119_; - assign _zz_64_ = _zz_207_[0]; - assign _zz_63_ = _zz_208_[0]; - assign _zz_120_ = _zz_113_[12 : 11]; - assign _zz_62_ = _zz_120_; - assign _zz_61_ = _zz_209_[0]; - assign _zz_121_ = _zz_113_[15 : 14]; - assign _zz_60_ = _zz_121_; - assign _zz_122_ = _zz_113_[17 : 16]; - assign _zz_59_ = _zz_122_; - assign _zz_123_ = _zz_113_[19 : 18]; - assign _zz_58_ = _zz_123_; - assign _zz_57_ = _zz_210_[0]; - assign _zz_56_ = _zz_211_[0]; - assign _zz_124_ = _zz_113_[23 : 22]; - assign _zz_55_ = _zz_124_; - assign _zz_54_ = _zz_212_[0]; - assign _zz_53_ = _zz_213_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_161_; - assign decode_RegFilePlugin_rs2Data = _zz_162_; - assign _zz_52_ = decode_RegFilePlugin_rs1Data; - assign _zz_51_ = decode_RegFilePlugin_rs2Data; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring); - if(_zz_125_)begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_72_; - always @ (*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); - end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); - end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); - end - endcase - end - - always @ (*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_126_ = execute_IntAluPlugin_bitwise; - end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_126_ = {31'd0, _zz_214_}; - end - default : begin - _zz_126_ = execute_SRC_ADD_SUB; - end - endcase - end - - assign _zz_46_ = _zz_126_; - assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - always @ (*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_127_ = execute_RS1; - end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_127_ = {29'd0, _zz_215_}; - end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; - end - default : begin - _zz_127_ = {27'd0, _zz_216_}; - end - endcase - end - - assign _zz_43_ = _zz_127_; - assign _zz_128_ = _zz_217_[11]; - always @ (*) begin - _zz_129_[19] = _zz_128_; - _zz_129_[18] = _zz_128_; - _zz_129_[17] = _zz_128_; - _zz_129_[16] = _zz_128_; - _zz_129_[15] = _zz_128_; - _zz_129_[14] = _zz_128_; - _zz_129_[13] = _zz_128_; - _zz_129_[12] = _zz_128_; - _zz_129_[11] = _zz_128_; - _zz_129_[10] = _zz_128_; - _zz_129_[9] = _zz_128_; - _zz_129_[8] = _zz_128_; - _zz_129_[7] = _zz_128_; - _zz_129_[6] = _zz_128_; - _zz_129_[5] = _zz_128_; - _zz_129_[4] = _zz_128_; - _zz_129_[3] = _zz_128_; - _zz_129_[2] = _zz_128_; - _zz_129_[1] = _zz_128_; - _zz_129_[0] = _zz_128_; - end - - assign _zz_130_ = _zz_218_[11]; - always @ (*) begin - _zz_131_[19] = _zz_130_; - _zz_131_[18] = _zz_130_; - _zz_131_[17] = _zz_130_; - _zz_131_[16] = _zz_130_; - _zz_131_[15] = _zz_130_; - _zz_131_[14] = _zz_130_; - _zz_131_[13] = _zz_130_; - _zz_131_[12] = _zz_130_; - _zz_131_[11] = _zz_130_; - _zz_131_[10] = _zz_130_; - _zz_131_[9] = _zz_130_; - _zz_131_[8] = _zz_130_; - _zz_131_[7] = _zz_130_; - _zz_131_[6] = _zz_130_; - _zz_131_[5] = _zz_130_; - _zz_131_[4] = _zz_130_; - _zz_131_[3] = _zz_130_; - _zz_131_[2] = _zz_130_; - _zz_131_[1] = _zz_130_; - _zz_131_[0] = _zz_130_; - end - - always @ (*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_132_ = execute_RS2; - end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]}; - end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; - end - default : begin - _zz_132_ = _zz_39_; - end - endcase - end - - assign _zz_41_ = _zz_132_; - always @ (*) begin - execute_SrcPlugin_addSub = _zz_219_; - if(execute_SRC2_FORCE_ZERO)begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_38_ = execute_SrcPlugin_addSub; - assign _zz_37_ = execute_SrcPlugin_addSub; - assign _zz_36_ = execute_SrcPlugin_less; - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); - assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); - always @ (*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1); - end - default : begin - _zz_133_ = _zz_226_; - end - endcase - end - - always @ (*) begin - _zz_134_ = 1'b0; - if(_zz_137_)begin - if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; - end - end - if(_zz_176_)begin - if(_zz_177_)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; - end - end - end - if(_zz_178_)begin - if(_zz_179_)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; - end - end - end - if(_zz_180_)begin - if(_zz_181_)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; - end - end - end - if((! decode_RS1_USE))begin - _zz_134_ = 1'b0; - end - end - - always @ (*) begin - _zz_135_ = 1'b0; - if(_zz_137_)begin - if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; - end - end - if(_zz_176_)begin - if(_zz_177_)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; - end - end - end - if(_zz_178_)begin - if(_zz_179_)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; - end - end - end - if(_zz_180_)begin - if(_zz_181_)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; - end - end - end - if((! decode_RS2_USE))begin - _zz_135_ = 1'b0; - end - end - - assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring); - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_139_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_139_ == (3'b000))) begin - _zz_140_ = execute_BranchPlugin_eq; - end else if((_zz_139_ == (3'b001))) begin - _zz_140_ = (! execute_BranchPlugin_eq); - end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin - _zz_140_ = (! execute_SRC_LESS); - end else begin - _zz_140_ = execute_SRC_LESS; - end - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_141_ = 1'b0; - end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_141_ = 1'b1; - end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_141_ = 1'b1; - end - default : begin - _zz_141_ = _zz_140_; - end - endcase - end - - assign _zz_33_ = _zz_141_; - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_142_ = _zz_228_[19]; - always @ (*) begin - _zz_143_[10] = _zz_142_; - _zz_143_[9] = _zz_142_; - _zz_143_[8] = _zz_142_; - _zz_143_[7] = _zz_142_; - _zz_143_[6] = _zz_142_; - _zz_143_[5] = _zz_142_; - _zz_143_[4] = _zz_142_; - _zz_143_[3] = _zz_142_; - _zz_143_[2] = _zz_142_; - _zz_143_[1] = _zz_142_; - _zz_143_[0] = _zz_142_; - end - - assign _zz_144_ = _zz_229_[11]; - always @ (*) begin - _zz_145_[19] = _zz_144_; - _zz_145_[18] = _zz_144_; - _zz_145_[17] = _zz_144_; - _zz_145_[16] = _zz_144_; - _zz_145_[15] = _zz_144_; - _zz_145_[14] = _zz_144_; - _zz_145_[13] = _zz_144_; - _zz_145_[12] = _zz_144_; - _zz_145_[11] = _zz_144_; - _zz_145_[10] = _zz_144_; - _zz_145_[9] = _zz_144_; - _zz_145_[8] = _zz_144_; - _zz_145_[7] = _zz_144_; - _zz_145_[6] = _zz_144_; - _zz_145_[5] = _zz_144_; - _zz_145_[4] = _zz_144_; - _zz_145_[3] = _zz_144_; - _zz_145_[2] = _zz_144_; - _zz_145_[1] = _zz_144_; - _zz_145_[0] = _zz_144_; - end - - assign _zz_146_ = _zz_230_[11]; - always @ (*) begin - _zz_147_[18] = _zz_146_; - _zz_147_[17] = _zz_146_; - _zz_147_[16] = _zz_146_; - _zz_147_[15] = _zz_146_; - _zz_147_[14] = _zz_146_; - _zz_147_[13] = _zz_146_; - _zz_147_[12] = _zz_146_; - _zz_147_[11] = _zz_146_; - _zz_147_[10] = _zz_146_; - _zz_147_[9] = _zz_146_; - _zz_147_[8] = _zz_146_; - _zz_147_[7] = _zz_146_; - _zz_147_[6] = _zz_146_; - _zz_147_[5] = _zz_146_; - _zz_147_[4] = _zz_146_; - _zz_147_[3] = _zz_146_; - _zz_147_[2] = _zz_146_; - _zz_147_[1] = _zz_146_; - _zz_147_[0] = _zz_146_; - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]}; - end - default : begin - _zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - end - endcase - end - - assign execute_BranchPlugin_branch_src2 = _zz_148_; - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - always @ (*) begin - CsrPlugin_privilege = (2'b11); - if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); - end - end - - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_153_ = _zz_231_[0]; - assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_155_ = _zz_233_[0]; - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_166_)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; - end - if(decode_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; - end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; - end - if(execute_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; - end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_168_)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - if(CsrPlugin_hadException)begin - CsrPlugin_pipelineLiberator_done = 1'b0; - end - end - - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - end - end - - always @ (*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; - end - end - - always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); - always @ (*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @ (*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end - end - end - - always @ (*) begin - CsrPlugin_selfException_valid = 1'b0; - if(_zz_182_)begin - CsrPlugin_selfException_valid = 1'b1; - end - end - - always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_182_)begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); - end - default : begin - CsrPlugin_selfException_payload_code = (4'b1011); - end - endcase - end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_156_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_157_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase - end - - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_189_) - 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; - end - default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000)); - assign _zz_25_ = decode_ALU_BITWISE_CTRL; - assign _zz_23_ = _zz_58_; - assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_22_ = decode_SHIFT_CTRL; - assign _zz_20_ = _zz_70_; - assign _zz_35_ = decode_to_execute_SHIFT_CTRL; - assign _zz_19_ = decode_ALU_CTRL; - assign _zz_17_ = _zz_60_; - assign _zz_45_ = decode_to_execute_ALU_CTRL; - assign _zz_16_ = decode_BRANCH_CTRL; - assign _zz_14_ = _zz_59_; - assign _zz_32_ = decode_to_execute_BRANCH_CTRL; - assign _zz_13_ = decode_SRC1_CTRL; - assign _zz_11_ = _zz_65_; - assign _zz_42_ = decode_to_execute_SRC1_CTRL; - assign _zz_10_ = decode_ENV_CTRL; - assign _zz_7_ = execute_ENV_CTRL; - assign _zz_5_ = memory_ENV_CTRL; - assign _zz_8_ = _zz_55_; - assign _zz_27_ = decode_to_execute_ENV_CTRL; - assign _zz_26_ = execute_to_memory_ENV_CTRL; - assign _zz_30_ = memory_to_writeBack_ENV_CTRL; - assign _zz_3_ = decode_SRC2_CTRL; - assign _zz_1_ = _zz_62_; - assign _zz_40_ = decode_to_execute_SRC2_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = _zz_158_; - assign iBus_cmd_m2sPipe_payload_pc = _zz_159_; - assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); - assign iBusWishbone_CTI = (3'b000); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); - assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; - assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; - assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); - assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; - assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; - assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = (3'b000); - assign dBusWishbone_BTE = (2'b00); - always @ (*) begin - case(dBus_cmd_halfPipe_payload_size) - 2'b00 : begin - _zz_160_ = (4'b0001); - end - 2'b01 : begin - _zz_160_ = (4'b0011); - end - default : begin - _zz_160_ = (4'b1111); - end - endcase - end - - always @ (*) begin - dBusWishbone_SEL = _zz_241_[3:0]; - if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = (4'b1111); - end - end - - assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; - assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; - assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); - assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; - assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; - assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); - assign dBus_rsp_data = dBusWishbone_DAT_MISO; - assign dBus_rsp_error = 1'b0; - always @ (posedge clk) begin - if(reset) begin - IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; - IBusSimplePlugin_fetchPc_booted <= 1'b0; - IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_99_ <= 1'b0; - _zz_100_ <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - IBusSimplePlugin_pendingCmd <= (3'b000); - IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); - _zz_125_ <= 1'b1; - execute_LightShifterPlugin_isActive <= 1'b0; - _zz_137_ <= 1'b0; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - _zz_156_ <= (32'b00000000000000000000000000000000); - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_158_ <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; - end else begin - IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; - end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b1; - end - if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; - end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin - IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; - end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_99_ <= 1'b0; - end - if(_zz_97_)begin - _zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; - end - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; - end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_100_ <= 1'b0; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if((! execute_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if((! memory_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if((! writeBack_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(decode_arbitration_removeIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - end - IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_); - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_); - end - _zz_125_ <= 1'b0; - if(_zz_164_)begin - if(_zz_167_)begin - execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - end - end - if(execute_arbitration_removeIt)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - _zz_137_ <= _zz_136_; - if((! decode_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if((! execute_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if((! memory_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_183_)begin - if(_zz_184_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_185_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_186_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_169_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(_zz_170_)begin - case(_zz_171_) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000)); - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= 1'b0; - end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; - end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; - end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_235_[0]; - CsrPlugin_mstatus_MIE <= _zz_236_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_238_[0]; - CsrPlugin_mie_MTIE <= _zz_239_[0]; - CsrPlugin_mie_MSIE <= _zz_240_[0]; - end - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(iBus_cmd_ready)begin - _zz_158_ <= iBus_cmd_valid; - end - if(_zz_187_)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; - end - end - end - - always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; - end - if(IBusSimplePlugin_injector_decodeInput_ready)begin - IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - end - if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin - IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; - IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; - IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; - IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; - IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; - IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; - IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; - end - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); - end - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - end - if(_zz_164_)begin - if(_zz_167_)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); - end - end - if(_zz_136_)begin - _zz_138_ <= _zz_48_[11 : 7]; - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - end - if(_zz_166_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(_zz_168_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); - end - if(_zz_183_)begin - if(_zz_184_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_185_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_186_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - end - if(_zz_169_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase - end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_21_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; - execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; - execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; - execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; - execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; - execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; - execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_15_; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_12_; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9_; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6_; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_85_; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39_; - end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; - end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_2_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_237_[0]; - end - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(iBus_cmd_ready)begin - _zz_159_ <= iBus_cmd_payload_pc; - end - if(_zz_187_)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; - end - end - -endmodule - diff --git a/litedram/extras/fusesoc-add-files.py b/litedram/extras/fusesoc-add-files.py index b646bea..aad9476 100644 --- a/litedram/extras/fusesoc-add-files.py +++ b/litedram/extras/fusesoc-add-files.py @@ -6,7 +6,8 @@ import pathlib class LiteDRAMGenerator(Generator): def run(self): - board = self.config.get('board') + board = self.config.get('board') + payload = self.config.get('payload') # Collect a bunch of directory path script_dir = os.path.dirname(sys.argv[0]) @@ -16,28 +17,16 @@ class LiteDRAMGenerator(Generator): print("Adding LiteDRAM for board... ", board) - # Grab init-cpu.txt if it exists - cpu_file = os.path.join(gen_dir, "init-cpu.txt") - if os.path.exists(cpu_file): - cpu = pathlib.Path(cpu_file).read_text() - else: - cpu = None - # Add files to fusesoc files = [] f = os.path.join(gen_dir, "litedram_core.v") files.append({f : {'file_type' : 'verilogSource'}}) - f = os.path.join(gen_dir, "litedram-wrapper.vhdl") - files.append({f : {'file_type' : 'vhdlSource-2008'}}) f = os.path.join(gen_dir, "litedram-initmem.vhdl") files.append({f : {'file_type' : 'vhdlSource-2008'}}) f = os.path.join(gen_dir, "litedram_core.init") files.append({f : {'file_type' : 'user'}}) - - # Look for init CPU types and add corresponding files - if cpu == "vexriscv": - f = os.path.join(base_dir, "extras", "VexRiscv.v") - files.append({f : {'file_type' : 'verilogSource'}}) + f = os.path.join(extras_dir, "litedram-wrapper-l2.vhdl") + files.append({f : {'file_type' : 'vhdlSource-2008'}}) self.add_files(files) diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl new file mode 100644 index 0000000..eb818ee --- /dev/null +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -0,0 +1,1039 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; +use work.helpers.all; + +entity litedram_wrapper is + generic ( + DRAM_ABITS : positive; + DRAM_ALINES : positive; + + -- Pseudo-ROM payload + PAYLOAD_SIZE : natural; + PAYLOAD_FILE : string; + + -- L2 cache -- + + -- Line size in bytes + LINE_SIZE : positive := 128; + -- Number of lines in a set + NUM_LINES : positive := 64; + -- Number of ways + NUM_WAYS : positive := 4; + -- Max number of stores in the queue + STOREQ_DEPTH : positive := 8; + -- Don't send loads until all pending stores acked in litedram + NO_LS_OVERLAP : boolean := false; + + -- Debug + LITEDRAM_TRACE : boolean := false; + TRACE : boolean := false + ); + port( + -- LiteDRAM generates the system clock and reset + -- from the input clkin + clk_in : in std_ulogic; + rst : in std_ulogic; + system_clk : out std_ulogic; + system_reset : out std_ulogic; + core_alt_reset : out std_ulogic; + pll_locked : out std_ulogic; + + -- Wishbone ports: + wb_in : in wishbone_master_out; + wb_out : out wishbone_slave_out; + wb_ctrl_in : in wb_io_master_out; + wb_ctrl_out : out wb_io_slave_out; + wb_ctrl_is_csr : in std_ulogic; + wb_ctrl_is_init : in std_ulogic; + + -- Init core serial debug + serial_tx : out std_ulogic; + serial_rx : in std_ulogic; + + -- Misc + init_done : out std_ulogic; + init_error : out std_ulogic; + + -- DRAM wires + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic + ); +end entity litedram_wrapper; + +architecture behaviour of litedram_wrapper is + + component litedram_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); + end component; + + signal user_port0_cmd_valid : std_ulogic; + signal user_port0_cmd_ready : std_ulogic; + signal user_port0_cmd_we : std_ulogic; + signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal user_port0_wdata_valid : std_ulogic; + signal user_port0_wdata_ready : std_ulogic; + signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); + signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); + signal user_port0_rdata_valid : std_ulogic; + signal user_port0_rdata_ready : std_ulogic; + signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); + + signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); + signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); + signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); + signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); + signal wb_ctrl_cyc : std_ulogic := '0'; + signal wb_ctrl_stb : std_ulogic; + signal wb_ctrl_ack : std_ulogic; + signal wb_ctrl_we : std_ulogic; + + signal wb_init_in : wb_io_master_out; + signal wb_init_out : wb_io_slave_out; + + -- DRAM data port width + constant DRAM_DBITS : natural := 128; + constant DRAM_SBITS : natural := (DRAM_DBITS / 8); + + -- BRAM organisation: We never access more than wishbone_data_bits at + -- a time so to save resources we make the array only that wide, and + -- use consecutive indices for to make a cache "line" + -- + -- ROW_SIZE is the width in bytes of the BRAM (based on litedram, so 128-bits) + constant ROW_SIZE : natural := DRAM_DBITS / 8; + -- ROW_PER_LINE is the number of row (litedram transactions) in a line + constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE; + -- BRAM_ROWS is the number of rows in BRAM needed to represent the full + -- dcache + constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE; + + -- Bit fields counts in the address + + -- ROW_BITS is the number of bits to select a row + constant ROW_BITS : natural := log2(BRAM_ROWS); + -- ROW_LINEBITS is the number of bits to select a row within a line + constant ROW_LINEBITS : natural := log2(ROW_PER_LINE); + -- LINE_OFF_BITS is the number of bits for the offset in a cache line + constant LINE_OFF_BITS : natural := log2(LINE_SIZE); + -- ROW_OFF_BITS is the number of bits for the offset in a row + constant ROW_OFF_BITS : natural := log2(ROW_SIZE); + -- REAL_ADDR_BITS is the number of real address bits that we store + constant REAL_ADDR_BITS : positive := DRAM_ABITS + ROW_OFF_BITS; + -- INDEX_BITS is the number if bits to select a cache line + constant INDEX_BITS : natural := log2(NUM_LINES); + -- SET_SIZE_BITS is the log base 2 of the set size + constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS; + -- TAG_BITS is the number of bits of the tag part of the address + constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS; + -- WAY_BITS is the number of bits to select a way + constant WAY_BITS : natural := log2(NUM_WAYS); + + subtype row_t is integer range 0 to BRAM_ROWS-1; + subtype index_t is integer range 0 to NUM_LINES-1; + subtype way_t is integer range 0 to NUM_WAYS-1; + + -- The cache data BRAM organized as described above for each way + subtype cache_row_t is std_ulogic_vector(DRAM_DBITS-1 downto 0); + + -- The cache tags LUTRAM has a row per set. Vivado is a pain and will + -- not handle a clean (commented) definition of the cache tags as a 3d + -- memory. For now, work around it by putting all the tags + subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0); +-- type cache_tags_set_t is array(way_t) of cache_tag_t; +-- type cache_tags_array_t is array(index_t) of cache_tags_set_t; + constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS; + subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0); + type cache_tags_array_t is array(index_t) of cache_tags_set_t; + + -- The cache valid bits + subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0); + type cache_valids_t is array(index_t) of cache_way_valids_t; + + -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs + signal cache_tags : cache_tags_array_t; + signal cache_valids : cache_valids_t; + + attribute ram_style : string; + attribute ram_style of cache_tags : signal is "distributed"; + + -- + -- Store queue signals + -- + -- We store a single wishbone dword per entry (64-bit) but all + -- 16 sel bits for the DRAM. + -- XXX Investigate storing only AD3 and 8 sel bits if it's better + constant STOREQ_BITS : positive := wishbone_data_bits + DRAM_SBITS; + + signal storeq_rd_ready : std_ulogic; + signal storeq_rd_valid : std_ulogic; + signal storeq_rd_data : std_ulogic_vector(STOREQ_BITS-1 downto 0); + signal storeq_wr_ready : std_ulogic; + signal storeq_wr_valid : std_ulogic; + signal storeq_wr_data : std_ulogic_vector(STOREQ_BITS-1 downto 0); + + -- + -- Cache management signals + -- + + -- Cache state machine + type state_t is (IDLE, -- Normal load hit processing + REFILL_WAIT_ACK); -- Cache refill wait ack + signal state : state_t; + + -- Latched WB request. + signal wb_req : wishbone_master_out := wishbone_master_out_init; + + -- Read pipeline (to handle cache RAM latency) + signal read_ack_0 : std_ulogic; + signal read_ack_1 : std_ulogic; + signal read_ad3_0 : std_ulogic; + signal read_ad3_1 : std_ulogic; + signal read_way_0 : way_t; + signal read_way_1 : way_t; + + -- Async signals decoding latched request + type req_op_t is (OP_NONE, + OP_LOAD_HIT, + OP_LOAD_MISS, + OP_STORE_HIT, + OP_STORE_MISS); + + signal req_index : index_t; + signal req_row : row_t; + signal req_hit_way : way_t; + signal req_tag : cache_tag_t; + signal req_op : req_op_t; + signal req_laddr : std_ulogic_vector(REAL_ADDR_BITS-1 downto 0); + signal req_ad3 : std_ulogic; + signal req_we : std_ulogic_vector(DRAM_SBITS-1 downto 0); + signal req_wdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); + signal accept_store : std_ulogic; + + -- Line refill command signals and latches + signal refill_cmd_valid : std_ulogic; + signal refill_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); + signal refill_way : way_t; + signal refill_index : index_t; + signal refill_row : row_t; + + -- Cache RAM interface + type cache_ram_out_t is array(way_t) of cache_row_t; + signal cache_out : cache_ram_out_t; + + -- PLRU output interface + type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0); + signal plru_victim : plru_out_t; + + -- + -- Helper functions to decode incoming requests + -- + + -- Return the cache line index (tag index) for an address + function get_index(addr: wishbone_addr_type) return index_t is + begin + return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))); + end; + + -- Return the cache row index (data memory) for an address + function get_row(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto 0)) return row_t is + begin + return to_integer(unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))); + end; + + -- Returns whether this is the last row of a line. It takes a DRAM address + function is_last_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS)) + return boolean is + constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); + begin + return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones; + end; + + -- Returns whether this is the last row of a line + function is_last_row(row: row_t) return boolean is + variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0); + constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1'); + begin + row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS)); + return row_v(ROW_LINEBITS-1 downto 0) = ones; + end; + + -- Return the address of the next row in the current cache line. It takes a + -- DRAM address + function next_row_addr(addr: std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS)) + return std_ulogic_vector is + variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0); + variable result : std_ulogic_vector(REAL_ADDR_BITS-1 downto ROW_OFF_BITS); + begin + -- Is there no simpler way in VHDL to generate that 3 bits adder ? + row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS); + row_idx := std_ulogic_vector(unsigned(row_idx) + 1); + result := addr; + result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx; + return result; + end; + + -- Return the next row in the current cache line. We use a dedicated + -- function in order to limit the size of the generated adder to be + -- only the bits within a cache line (3 bits with default settings) + -- + function next_row(row: row_t) return row_t is + variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0); + variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0); + variable result : std_ulogic_vector(ROW_BITS-1 downto 0); + begin + row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS)); + row_idx := row_v(ROW_LINEBITS-1 downto 0); + row_v(ROW_LINEBITS-1 downto 0) := std_ulogic_vector(unsigned(row_idx) + 1); + return to_integer(unsigned(row_v)); + end; + + -- Get the tag value from the address + function get_tag(addr: wishbone_addr_type) return cache_tag_t is + begin + return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS); + end; + + -- Read a tag from a tag memory row + function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is + begin + return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS); + end; + + -- Write a tag to tag memory row + procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t; + tag: cache_tag_t) is + begin + tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag; + end; + +begin + + -- Sanity checks + assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE; + assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE; + assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE; + assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE; + assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS) + report "geometry bits don't add up" severity FAILURE; + assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS) + report "geometry bits don't add up" severity FAILURE; + assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS) + report "geometry bits don't add up" severity FAILURE; + assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS) + report "geometry bits don't add up" severity FAILURE; + assert (128 = DRAM_DBITS) + report "Can't yet handle a DRAM width that isn't 128-bits" severity FAILURE; + + -- alternate core reset address set when DRAM is not initialized. + core_alt_reset <= not init_done; + + -- Init code BRAM memory slave + init_ram_0: entity work.dram_init_mem + generic map( + EXTRA_PAYLOAD_FILE => PAYLOAD_FILE, + EXTRA_PAYLOAD_SIZE => PAYLOAD_SIZE + ) + port map( + clk => system_clk, + wb_in => wb_init_in, + wb_out => wb_init_out + ); + + -- + -- Control bus wishbone: This muxes the wishbone to the CSRs + -- and an internal small one to the init BRAM + -- + + -- Init DRAM wishbone IN signals + wb_init_in.adr <= wb_ctrl_in.adr; + wb_init_in.dat <= wb_ctrl_in.dat; + wb_init_in.sel <= wb_ctrl_in.sel; + wb_init_in.we <= wb_ctrl_in.we; + wb_init_in.stb <= wb_ctrl_in.stb; + wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init; + + -- DRAM CSR IN signals. Extra latch to help with timing + csr_latch: process(system_clk) + begin + if rising_edge(system_clk) then + if system_reset = '1' then + wb_ctrl_cyc <= '0'; + wb_ctrl_stb <= '0'; + else + -- XXX Maybe only update addr when cyc = '1' to save power ? + wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); + wb_ctrl_dat_w <= wb_ctrl_in.dat; + wb_ctrl_sel <= wb_ctrl_in.sel; + wb_ctrl_we <= wb_ctrl_in.we; + wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; + wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; + + -- Clear stb on ack otherwise the memory will latch + -- the write twice which breaks levelling. On the next + -- cycle we will latch an updated stb that takes the + -- ack into account. + if wb_ctrl_ack = '1' then + wb_ctrl_stb <= '0'; + end if; + end if; + end if; + end process; + + -- Ctrl bus wishbone OUT signals. XXX Consider adding latch on + -- CSR response to help timing + wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1' + else wb_init_out.ack; + wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1' + else wb_init_out.dat; + wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else + '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack; + + + -- Generate a cache RAM for each way + rams: for i in 0 to NUM_WAYS-1 generate + signal do_read : std_ulogic; + signal do_write : std_ulogic; + signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0); + signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0); + signal wr_data : std_ulogic_vector(DRAM_DBITS-1 downto 0); + signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0); + signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0); + signal dout : cache_row_t; + begin + way: entity work.cache_ram + generic map ( + ROW_BITS => ROW_BITS, + WIDTH => DRAM_DBITS, + ADD_BUF => true + ) + port map ( + clk => system_clk, + rd_en => do_read, + rd_addr => rd_addr, + rd_data => dout, + wr_sel => wr_sel_m, + wr_addr => wr_addr, + wr_data => wr_data + ); + process(all) + begin + -- + -- Read port + -- + do_read <= '1'; + cache_out(i) <= dout; + rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS)); + + -- + -- Write mux: cache refills from DRAM or writes from Wishbone + -- + if state = IDLE then + -- Write from wishbone + wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS)); + wr_data <= req_wdata; + wr_sel <= req_we; + else + -- Refill from DRAM + wr_data <= user_port0_rdata_data; + wr_sel <= (others => '1'); + wr_addr <= std_ulogic_vector(to_unsigned(refill_row, ROW_BITS)); + end if; + + -- + -- Write enable logic + -- + do_write <= '0'; + if req_op = OP_STORE_HIT and req_hit_way = i then + do_write <= '1'; + elsif user_port0_rdata_valid = '1' and refill_way = i then + do_write <= '1'; + end if; + + -- Mask write selects with do_write since BRAM doesn't always + -- have a global write-enable (Vivado generates TDP instead + -- of SDP when using one, thus doubling cache BRAM usage). + for i in 0 to ROW_SIZE-1 loop + wr_sel_m(i) <= wr_sel(i) and do_write; + end loop; + + if TRACE and rising_edge(system_clk) then + if do_write = '1' then + report "cache write way:" & integer'image(i) & + " addr:" & to_hstring(wr_addr) & + " sel:" & to_hstring(wr_sel_m) & + " data:" & to_hstring(wr_data); + end if; + end if; + end process; + end generate; + + -- Generate PLRUs + maybe_plrus: if NUM_WAYS > 1 generate + begin + plrus: for i in 0 to NUM_LINES-1 generate + -- PLRU interface + signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0); + signal plru_acc_en : std_ulogic; + signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0); + begin + plru : entity work.plru + generic map ( + BITS => WAY_BITS + ) + port map ( + clk => system_clk, + rst => system_reset, + acc => plru_acc, + acc_en => plru_acc_en, + lru => plru_out + ); + + process(req_index, req_op, req_hit_way, plru_out) + begin + -- PLRU interface + if (req_op = OP_LOAD_HIT or + req_op = OP_STORE_HIT) and req_index = i then + plru_acc_en <= '1'; + else + plru_acc_en <= '0'; + end if; + plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS)); + plru_victim(i) <= plru_out; + end process; + end generate; + end generate; + + -- + -- Wishbone interface: + -- + -- - Incoming wishbone request latch (to help with timing) + -- - Read response pipeline (to match BRAM output buffer delay) + -- - Stall generation + -- + -- XXX TODO: Properly handle cyc drops before all acks are sent... + -- + request_latch: process(system_clk) + begin + if rising_edge(system_clk) then + -- We can latch a new request if we are idle (for now). We also + -- latch the absence of request. This is a pipeline that takes + -- one per-cycle unless non-IDLE. + -- + if wb_out.stall = '0' then + -- Avoid constantly updating addr/data for unrelated requests + if wb_in.cyc = '1' then + wb_req <= wb_in; + else + wb_req.cyc <= wb_in.cyc; + wb_req.stb <= wb_in.stb; + end if; + + if TRACE then + if wb_in.cyc = '1' and wb_in.stb = '1' then + report "latch new wb req ! addr:" & to_hstring(wb_in.adr) & + " we:" & std_ulogic'image(wb_in.we) & + " sel:" & to_hstring(wb_in.sel); + end if; + end if; + end if; + end if; + end process; + + -- + -- + -- Read response pipeline + -- + -- XXX Might have to put store acks in there too (see comment in wb_response) + read_pipe: process(system_clk) + begin + if rising_edge(system_clk) then + read_ack_0 <= '1' when req_op = OP_LOAD_HIT else '0'; + read_ad3_0 <= req_ad3; + read_way_0 <= req_hit_way; + + read_ack_1 <= read_ack_0; + read_ad3_1 <= read_ad3_0; + read_way_1 <= read_way_0; + + if TRACE then + if req_op = OP_LOAD_HIT then + report "Load hit addr:" & to_hstring(wb_req.adr) & + " idx:" & integer'image(req_index) & + " tag:" & to_hstring(req_tag) & + " way:" & integer'image(req_hit_way); + elsif req_op = OP_LOAD_MISS then + report "Load miss addr:" & to_hstring(wb_req.adr); + end if; + if read_ack_0 = '1' then + report "read data:" & to_hstring(cache_out(read_way_0)); + end if; + end if; + end if; + end process; + + wb_reponse: process(all) + variable rdata : std_ulogic_vector(DRAM_DBITS-1 downto 0); + variable store_done : std_ulogic; + begin + -- Can we accept a store ? This is set when IDLE and the store + -- queue & command queue are not full. + -- + -- Note: This is only used to control the WB request latch, stall + -- and store "early complete". We don't want to use this to control + -- cmd_valid to DRAM as this would create a circular dependency inside + -- LiteDRAM as cmd_ready I think is driven from cmd_valid. + -- + -- The state machine that controls the command queue must thus + -- reproduce this logic at least partially. + -- + -- Note also that user_port0_cmd_ready from LiteDRAM is combinational + -- from user_port0_cmd_valid. IE. we won't know that LiteDRAM cannot + -- accept a command until we try to send one. + -- + if state = IDLE then + accept_store <= user_port0_cmd_ready and storeq_wr_ready; + + -- Corner case !!! The read acks pipeline takes two extra cycles + -- which means a store ack can collide with a previous load hit + -- ack. Thus we stall stores if we have a load ack pending. + if read_ack_0 = '1' or read_ack_1 = '1' then + accept_store <= '0'; + end if; + else + accept_store <= '0'; + end if; + + -- Generate stalls. For loads, we stall if we are going to take a load + -- miss or are in the middle of a refill. For stores, if we can't + -- accept it. + case state is + when IDLE => + case req_op is + when OP_LOAD_MISS => + wb_out.stall <= '1'; + when OP_STORE_MISS | OP_STORE_HIT => + wb_out.stall <= not accept_store; + when others => + wb_out.stall <= '0'; + end case; + when REFILL_WAIT_ACK => + wb_out.stall <= '1'; + end case; + + -- Data out mux + rdata := cache_out(read_way_1); + wb_out.dat <= rdata(127 downto 64) when read_ad3_1 = '1' else rdata(63 downto 0); + + -- Early-complete stores on wishbone. + if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then + store_done := accept_store; + else + store_done := '0'; + end if; + + -- Generate ACKs on read hits and store complete + -- + -- XXXX TODO: This can happen on store right behind loads ! + -- This probably need to be fixed by putting store acks in + -- the same pipeline as the read acks. TOOD: Create a testbench + -- to exercise those corner cases as the core can't yet. + -- + wb_out.ack <= read_ack_1 or store_done; + assert read_ack_0 = '0' or store_done = '0' report + "Read ack and store ack collision !" + severity failure; + end process; + + -- + -- Cache request decode + -- + request_decode: process(all) + variable valid : std_ulogic; + variable is_hit : std_ulogic; + variable hit_way : way_t; + begin + -- Extract line, row and tag from request + req_index <= get_index(wb_req.adr); + req_row <= get_row(wb_req.adr(REAL_ADDR_BITS-1 downto 0)); + req_tag <= get_tag(wb_req.adr); + + -- Calculate address of beginning of cache line, will be + -- used for cache miss processing if needed + req_laddr <= wb_req.adr(REAL_ADDR_BITS - 1 downto LINE_OFF_BITS) & + (LINE_OFF_BITS-1 downto 0 => '0'); + + + -- Do we have a valid request in the WB latch ? + if state = IDLE then + valid := wb_req.cyc and wb_req.stb; + else + valid := '0'; + end if; + + -- Store signals + req_ad3 <= wb_req.adr(3); + req_wdata <= wb_req.dat & wb_req.dat; + req_we <= wb_req.sel & "00000000" when req_ad3 = '1' else + "00000000" & wb_req.sel; + + -- Test if pending request is a hit on any way + hit_way := 0; + is_hit := '0'; + for i in way_t loop + if valid = '1' and cache_valids(req_index)(i) = '1' then + if read_tag(i, cache_tags(req_index)) = req_tag then + hit_way := i; + is_hit := '1'; + end if; + end if; + end loop; + + -- Generate the req op. We only allow OP_LOAD_* when in the + -- IDLE state as our PLRU and ACK generation rely on this, + -- stores are allowed in IDLE state. + -- + req_op <= OP_NONE; + if valid = '1' then + if wb_req.we = '1' then + if is_hit = '1' then + req_op <= OP_STORE_HIT; + else + req_op <= OP_STORE_MISS; + end if; + else + if is_hit = '1' then + req_op <= OP_LOAD_HIT; + else + req_op <= OP_LOAD_MISS; + end if; + end if; + end if; + req_hit_way <= hit_way; + end process; + + -- + -- Store queue + -- + -- For now, queue up to 16 stores + store_queue: entity work.sync_fifo + generic map ( + DEPTH => STOREQ_DEPTH, + WIDTH => STOREQ_BITS + ) + port map ( + clk => system_clk, + reset => system_reset, + rd_ready => storeq_rd_ready, + rd_valid => storeq_rd_valid, + rd_data => storeq_rd_data, + wr_ready => storeq_wr_ready, + wr_valid => storeq_wr_valid, + wr_data => storeq_wr_data + ); + + storeq_control : process(all) + variable stq_data : wishbone_data_type; + variable stq_sel : std_ulogic_vector(DRAM_SBITS-1 downto 0); + begin + storeq_wr_data <= wb_req.dat & req_we; + + -- Only accept store if we can send a command + if req_op = OP_STORE_HIT or req_op = OP_STORE_MISS then + storeq_wr_valid <= user_port0_cmd_ready; + else + storeq_wr_valid <= '0'; + end if; + + stq_data := storeq_rd_data(storeq_rd_data'left downto DRAM_SBITS); + stq_sel := storeq_rd_data(DRAM_SBITS-1 downto 0); + user_port0_wdata_data <= stq_data & stq_data; + user_port0_wdata_we <= stq_sel; + user_port0_wdata_valid <= storeq_rd_valid; + storeq_rd_ready <= user_port0_wdata_ready; + + if TRACE then + if rising_edge(system_clk) then + if req_op = OP_STORE_HIT then + report "Store hit to:" & + to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & + " data:" & to_hstring(req_wdata) & + " we:" & to_hstring(req_we) & + " V:" & std_ulogic'image(accept_store); + else + report "Store miss to:" & + to_hstring(wb_req.adr(DRAM_ABITS+3 downto 0)) & + " data:" & to_hstring(req_wdata) & + " we:" & to_hstring(req_we) & + " V:" & std_ulogic'image(accept_store); + end if; + if storeq_wr_valid = '1' and storeq_wr_ready = '1' then + report "storeq push " & to_hstring(storeq_wr_data); + end if; + if storeq_rd_valid = '1' and storeq_rd_ready = '1' then + report "storeq pop " & to_hstring(storeq_rd_data); + end if; + end if; + end if; + end process; + + -- LiteDRAM command mux + dram_commands: process(all) + begin + if state = IDLE and (req_op = OP_STORE_HIT or req_op = OP_STORE_MISS) then + -- For stores, forward signals directly. Only send command if + -- the FIFO can accept a store + user_port0_cmd_addr <= wb_req.adr(DRAM_ABITS+3 downto 4); + user_port0_cmd_we <= '1'; + user_port0_cmd_valid <= storeq_wr_ready; + else + -- For loads, we route via a latch controlled by the refill machine + user_port0_cmd_addr <= refill_cmd_addr; + user_port0_cmd_valid <= refill_cmd_valid; + user_port0_cmd_we <= '0'; + end if; + user_port0_rdata_ready <= '1'; -- Always 1 + end process; + + -- LiteDRAM refill machine + -- + -- This handles the cache line refills + -- + refill_machine : process(system_clk) + variable tagset : cache_tags_set_t; + variable cmds_done : boolean; + variable replace_way : way_t; + variable wait_qdrain : boolean; + begin + if rising_edge(system_clk) then + -- On reset, clear all valid bits to force misses + if system_reset = '1' then + for i in index_t loop + cache_valids(i) <= (others => '0'); + end loop; + state <= IDLE; + refill_cmd_valid <= '0'; + else + -- Main state machine + case state is + when IDLE => + assert refill_cmd_valid = '0' report "refill cmd valid in IDLE state !" + severity failure; + + -- If NO_LS_OVERLAP is set, disallow a load miss if the store + -- queue still has data in it. + wait_qdrain := false; + if NO_LS_OVERLAP then + wait_qdrain := storeq_rd_valid = '1'; + end if; + + -- We need to read a cache line + if req_op = OP_LOAD_MISS and not wait_qdrain then + -- Grab way to replace + replace_way := to_integer(unsigned(plru_victim(req_index))); + + -- Force misses on that way while refilling that line + cache_valids(req_index)(replace_way) <= '0'; + + -- Store new tag in selected way + for i in 0 to NUM_WAYS-1 loop + if i = replace_way then + tagset := cache_tags(req_index); + write_tag(i, tagset, req_tag); + cache_tags(req_index) <= tagset; + end if; + end loop; + + -- Keep track of our index and way for subsequent stores + refill_index <= req_index; + refill_way <= replace_way; + refill_row <= get_row(req_laddr); + + -- Prep for first DRAM read + -- + -- XXX TODO: We could start a cycle early here by using + -- combo logic to generate the first command in + -- "dram_commands". In fact, we could make refill_cmd_addr + -- only contain the "counter" bits and wire it with the + -- other bits from req_laddr. + refill_cmd_addr <= req_laddr(DRAM_ABITS+3 downto 4); + refill_cmd_valid <= '1'; + + if TRACE then + report "refill addr " & to_hstring(req_laddr); + end if; + + -- Track that we had one request sent + state <= REFILL_WAIT_ACK; + end if; + + when REFILL_WAIT_ACK => + -- Commands are all sent if user_port0_cmd_valid is 0 + cmds_done := refill_cmd_valid = '0'; + + -- If we are still sending requests, was one accepted ? + if user_port0_cmd_ready = '1' and not cmds_done then + -- That was the last word ? We are done sending. Clear + -- command valid and set cmds_done so we can handle an + -- eventual last ack on the same cycle. + -- + if TRACE then + report "got refill cmd ack !"; + end if; + if is_last_row_addr(refill_cmd_addr) then + refill_cmd_valid <= '0'; + cmds_done := true; + if TRACE then + report "all refill cmds done !"; + end if; + else + -- Calculate the next row address + refill_cmd_addr <= next_row_addr(refill_cmd_addr); + if TRACE then + report "refill addr " & + to_hstring(next_row_addr(refill_cmd_addr)); + end if; + end if; + end if; + + -- Incoming read data processing + if user_port0_rdata_valid = '1' then + if TRACE then + report "got refill data ack !"; + end if; + -- Check for completion + if cmds_done and is_last_row(refill_row) then + if TRACE then + report "all refill data done !"; + end if; + -- Cache line is now valid + cache_valids(refill_index)(refill_way) <= '1'; + -- We are done + state <= IDLE; + end if; + + -- Increment store row counter + refill_row <= next_row(refill_row); + end if; + end case; + end if; + end if; + end process; + + may_trace: if LITEDRAM_TRACE generate + component litedram_trace_stub + end component; + begin + litedram_trace: litedram_trace_stub; + end generate; + + litedram: litedram_core + port map( + clk => clk_in, + rst => rst, + pll_locked => pll_locked, + ddram_a => ddram_a, + ddram_ba => ddram_ba, + ddram_ras_n => ddram_ras_n, + ddram_cas_n => ddram_cas_n, + ddram_we_n => ddram_we_n, + ddram_cs_n => ddram_cs_n, + ddram_dm => ddram_dm, + ddram_dq => ddram_dq, + ddram_dqs_p => ddram_dqs_p, + ddram_dqs_n => ddram_dqs_n, + ddram_clk_p => ddram_clk_p, + ddram_clk_n => ddram_clk_n, + ddram_cke => ddram_cke, + ddram_odt => ddram_odt, + ddram_reset_n => ddram_reset_n, + init_done => init_done, + init_error => init_error, + user_clk => system_clk, + user_rst => system_reset, + wb_ctrl_adr => wb_ctrl_adr, + wb_ctrl_dat_w => wb_ctrl_dat_w, + wb_ctrl_dat_r => wb_ctrl_dat_r, + wb_ctrl_sel => wb_ctrl_sel, + wb_ctrl_cyc => wb_ctrl_cyc, + wb_ctrl_stb => wb_ctrl_stb, + wb_ctrl_ack => wb_ctrl_ack, + wb_ctrl_we => wb_ctrl_we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + user_port_native_0_cmd_valid => user_port0_cmd_valid, + user_port_native_0_cmd_ready => user_port0_cmd_ready, + user_port_native_0_cmd_we => user_port0_cmd_we, + user_port_native_0_cmd_addr => user_port0_cmd_addr, + user_port_native_0_wdata_valid => user_port0_wdata_valid, + user_port_native_0_wdata_ready => user_port0_wdata_ready, + user_port_native_0_wdata_we => user_port0_wdata_we, + user_port_native_0_wdata_data => user_port0_wdata_data, + user_port_native_0_rdata_valid => user_port0_rdata_valid, + user_port_native_0_rdata_ready => user_port0_rdata_ready, + user_port_native_0_rdata_data => user_port0_rdata_data + ); + +end architecture behaviour; diff --git a/litedram/extras/sim_dram_verilate.mk b/litedram/extras/sim_dram_verilate.mk new file mode 100644 index 0000000..0d760d4 --- /dev/null +++ b/litedram/extras/sim_dram_verilate.mk @@ -0,0 +1,10 @@ +OPT_FAST=-O3 -fstrict-aliasing +OPT_SLOW=-O3 -fstrict-aliasing + +top_all: top_all2 + +include Vlitedram_core.mk + +top_all2: default $(VK_GLOBAL_OBJS) + +.PHONY: top_all top_all2 diff --git a/litedram/extras/sim_litedram.vhdl b/litedram/extras/sim_litedram.vhdl new file mode 100644 index 0000000..0016240 --- /dev/null +++ b/litedram/extras/sim_litedram.vhdl @@ -0,0 +1,214 @@ +library ieee; +use ieee.std_logic_1164.all; + +package sim_litedram is + -- WB req format: + -- 73 .. 71 : cti(2..0) + -- 70 .. 69 : bte(1..0) + -- 68 .. 65 : sel(3..0) + -- 64 : we + -- 63 : stb + -- 62 : cyc + -- 61 .. 32 : addr(29..0) + -- 31 .. 0 : write_data(31..0) + -- + procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0)); + attribute foreign of litedram_set_wb : procedure is "VHPIDIRECT litedram_set_wb"; + + -- WB rsp format: + -- 35 : init_error; + -- 34 : init_done; + -- 33 : err + -- 32 : ack + -- 31 .. 0 : read_data(31..0) + -- + procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0)); + attribute foreign of litedram_get_wb : procedure is "VHPIDIRECT litedram_get_wb"; + + -- User req format: + -- 171 : cmd_valid + -- 170 : cmd_we + -- 169 : wdata_valid + -- 168 : rdata_ready + -- 167 .. 144 : cmd_addr(23..0) + -- 143 .. 128 : wdata_we(15..0) + -- 127 .. 0 : wdata_data(127..0) + -- + procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0)); + attribute foreign of litedram_set_user : procedure is "VHPIDIRECT litedram_set_user"; + + -- User rsp format: + -- 130 : cmd_ready + -- 129 : wdata_ready + -- 128 : rdata_valid + -- 127 .. 0 : rdata_data(127..0) + + procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0)); + attribute foreign of litedram_get_user : procedure is "VHPIDIRECT litedram_get_user"; + + procedure litedram_clock; + attribute foreign of litedram_clock : procedure is "VHPIDIRECT litedram_clock"; + + procedure litedram_init(trace: integer); + attribute foreign of litedram_init : procedure is "VHPIDIRECT litedram_init"; +end sim_litedram; + +package body sim_litedram is + procedure litedram_set_wb(req : in std_ulogic_vector(73 downto 0)) is + begin + assert false report "VHPI" severity failure; + end procedure; + procedure litedram_get_wb(rsp : out std_ulogic_vector(35 downto 0)) is + begin + assert false report "VHPI" severity failure; + end procedure; + procedure litedram_set_user(req: in std_ulogic_vector(171 downto 0)) is + begin + assert false report "VHPI" severity failure; + end procedure; + procedure litedram_get_user(req: in std_ulogic_vector(130 downto 0)) is + begin + assert false report "VHPI" severity failure; + end procedure; + procedure litedram_clock is + begin + assert false report "VHPI" severity failure; + end procedure; + procedure litedram_init(trace: integer) is + begin + assert false report "VHPI" severity failure; + end procedure; +end sim_litedram; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.sim_litedram.all; + +entity litedram_core is + port( + clk : in std_ulogic; + rst : in std_ulogic; + pll_locked : out std_ulogic; + ddram_a : out std_ulogic_vector(0 downto 0); + ddram_ba : out std_ulogic_vector(2 downto 0); + ddram_ras_n : out std_ulogic; + ddram_cas_n : out std_ulogic; + ddram_we_n : out std_ulogic; + ddram_cs_n : out std_ulogic; + ddram_dm : out std_ulogic_vector(1 downto 0); + ddram_dq : inout std_ulogic_vector(15 downto 0); + ddram_dqs_p : inout std_ulogic_vector(1 downto 0); + ddram_dqs_n : inout std_ulogic_vector(1 downto 0); + ddram_clk_p : out std_ulogic; + ddram_clk_n : out std_ulogic; + ddram_cke : out std_ulogic; + ddram_odt : out std_ulogic; + ddram_reset_n : out std_ulogic; + init_done : out std_ulogic; + init_error : out std_ulogic; + user_clk : out std_ulogic; + user_rst : out std_ulogic; + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + user_port_native_0_cmd_valid : in std_ulogic; + user_port_native_0_cmd_ready : out std_ulogic; + user_port_native_0_cmd_we : in std_ulogic; + user_port_native_0_cmd_addr : in std_ulogic_vector(23 downto 0); + user_port_native_0_wdata_valid : in std_ulogic; + user_port_native_0_wdata_ready : out std_ulogic; + user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); + user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); + user_port_native_0_rdata_valid : out std_ulogic; + user_port_native_0_rdata_ready : in std_ulogic; + user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) + ); +end entity litedram_core; + +architecture behaviour of litedram_core is + signal idone : std_ulogic := '0'; + signal ierr : std_ulogic := '0'; + signal old_wb_cyc : std_ulogic := '1'; +begin + user_rst <= rst; + user_clk <= clk; + pll_locked <= '1'; + init_done <= idone; + init_error <= ierr; + + poll: process(user_clk) + procedure send_signals is + begin + litedram_set_wb(wb_ctrl_cti & wb_ctrl_bte & + wb_ctrl_sel & wb_ctrl_we & + wb_ctrl_stb & wb_ctrl_cyc & + wb_ctrl_adr & wb_ctrl_dat_w); + litedram_set_user(user_port_native_0_cmd_valid & + user_port_native_0_cmd_we & + user_port_native_0_wdata_valid & + user_port_native_0_rdata_ready & + user_port_native_0_cmd_addr & + user_port_native_0_wdata_we & + user_port_native_0_wdata_data); + end procedure; + + procedure recv_signals is + variable wb_response : std_ulogic_vector(35 downto 0); + variable ur_response : std_ulogic_vector(130 downto 0); + begin + litedram_get_wb(wb_response); + wb_ctrl_dat_r <= wb_response(31 downto 0); + wb_ctrl_ack <= wb_response(32); + wb_ctrl_err <= wb_response(33); + idone <= wb_response(34); + ierr <= wb_response(35); + litedram_get_user(ur_response); + user_port_native_0_cmd_ready <= ur_response(130); + user_port_native_0_wdata_ready <= ur_response(129); + user_port_native_0_rdata_valid <= ur_response(128); + user_port_native_0_rdata_data <= ur_response(127 downto 0); + end procedure; + + begin + if rising_edge(user_clk) then + + send_signals; + recv_signals; + -- Then generate a clock cycle ( 0->1 then 1->0 ) + litedram_clock; + recv_signals; + end if; + + if falling_edge(user_clk) then + send_signals; + recv_signals; + end if; + end process; + +end architecture; + +library work; +use work.sim_litedram.all; + +entity litedram_trace_stub is +end entity; + +architecture behaviour of litedram_trace_stub is +begin + process + begin + litedram_init(1); + wait; + end process; +end architecture; diff --git a/litedram/extras/sim_litedram_c.cpp b/litedram/extras/sim_litedram_c.cpp new file mode 100644 index 0000000..265e9b2 --- /dev/null +++ b/litedram/extras/sim_litedram_c.cpp @@ -0,0 +1,198 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sim_vhpi_c.h" +#include "Vlitedram_core.h" +#include "verilated_vcd_c.h" + +static Vlitedram_core *v; +vluint64_t main_time = 0; + +#if VM_TRACE +VerilatedVcdC *tfp; +#endif + +static void cleanup(void) +{ +#if VM_TRACE + if (tfp) { + tfp->flush(); + tfp->close(); + delete tfp; + } +#endif +} + +static inline void check_init(bool traces) +{ + if (v) + return; + // XX Catch exceptions ? + v = new Vlitedram_core; + if (!v) { + fprintf(stderr, "Failure allocating litedram core\n"); + exit(1); + } +#if VM_TRACE + if (traces) { + // init trace dump + Verilated::traceEverOn(true); + tfp = new VerilatedVcdC; + v->trace(tfp, 99); + tfp->open("litedram.vcd"); + } +#endif + atexit(cleanup); +} + +unsigned char get_bit(unsigned char **p) +{ + unsigned char b = **p; + + *p = *p + 1; + + return b == vhpi1 ? 1 : 0; +} + +uint64_t get_bits(unsigned char **p, int len) +{ + uint64_t r = 0; + + while(len--) + r = (r << 1) | get_bit(p); + + return r; +} + +void set_bit(unsigned char **p, int bit) +{ + **p = bit ? vhpi1 : vhpi0; + *p = *p + 1; +} + +void set_bits(unsigned char **p, uint64_t val, int len) +{ + while(len--) + set_bit(p, (val >> len) & 1); +} + +double sc_time_stamp(void) +{ + return main_time; +} + +#define check_size(s, exp) \ + do { \ + int __s = (s); \ + int __e = (exp); \ + if (__s != __e) \ + fprintf(stderr, "WARNING: %s exp %d got %d\n", __func__, __e, __s); \ + } while(0) + +static void do_eval(void) +{ + v->eval(); +#if VM_TRACE + if (tfp) + tfp->dump((double) main_time); +#endif +} + +extern "C" void litedram_set_wb(unsigned char *req) +{ + unsigned char *orig = req; + + check_init(false); + + v->wb_ctrl_cti = get_bits(&req, 3); + v->wb_ctrl_bte = get_bits(&req, 2); + v->wb_ctrl_sel = get_bits(&req, 4); + v->wb_ctrl_we = get_bit(&req); + v->wb_ctrl_stb = get_bit(&req); + v->wb_ctrl_cyc = get_bit(&req); + v->wb_ctrl_adr = get_bits(&req, 30); + v->wb_ctrl_dat_w = get_bits(&req, 32); + + check_size(req - orig, 74); + + do_eval(); +} + +extern "C" void litedram_get_wb(unsigned char *req) +{ + unsigned char *orig = req; + + check_init(false); + + set_bit(&req, v->init_error); + set_bit(&req, v->init_done); + set_bit(&req, v->wb_ctrl_err); + set_bit(&req, v->wb_ctrl_ack); + set_bits(&req, v->wb_ctrl_dat_r, 32); + + check_size(req - orig, 36); +} + +extern "C" void litedram_set_user(unsigned char *req) +{ + unsigned char *orig = req; + + check_init(false); + + v->user_port_native_0_cmd_valid = get_bit(&req); + v->user_port_native_0_cmd_we = get_bit(&req); + v->user_port_native_0_wdata_valid = get_bit(&req); + v->user_port_native_0_rdata_ready = get_bit(&req); + v->user_port_native_0_cmd_addr = get_bits(&req, 24); + v->user_port_native_0_wdata_we = get_bits(&req, 16); + v->user_port_native_0_wdata_data[3] = get_bits(&req, 32); + v->user_port_native_0_wdata_data[2] = get_bits(&req, 32); + v->user_port_native_0_wdata_data[1] = get_bits(&req, 32); + v->user_port_native_0_wdata_data[0] = get_bits(&req, 32); + + check_size(req - orig, 172); + + do_eval(); +} + +extern "C" void litedram_get_user(unsigned char *req) +{ + unsigned char *orig = req; + + check_init(false); + + set_bit(&req, v->user_port_native_0_cmd_ready); + set_bit(&req, v->user_port_native_0_wdata_ready); + set_bit(&req, v->user_port_native_0_rdata_valid); + set_bits(&req, v->user_port_native_0_rdata_data[3], 32); + set_bits(&req, v->user_port_native_0_rdata_data[2], 32); + set_bits(&req, v->user_port_native_0_rdata_data[1], 32); + set_bits(&req, v->user_port_native_0_rdata_data[0], 32); + + check_size(req - orig, 131); +} + +extern "C" void litedram_clock(void) +{ + check_init(false); + + v->clk = 1; + do_eval(); + main_time++; + v->clk = 0; + do_eval(); + main_time++; +} + +extern "C" void litedram_init(int trace_on) +{ + check_init(!!trace_on); +} + + diff --git a/litedram/extras/wave.gtkw b/litedram/extras/wave.gtkw new file mode 100644 index 0000000..e0d0637 --- /dev/null +++ b/litedram/extras/wave.gtkw @@ -0,0 +1,122 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Sat May 30 08:37:38 2020 +[*] +[dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw" +[dumpfile_mtime] "Sat May 30 08:35:43 2020" +[dumpfile_size] 1424191 +[savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave.gtkw" +[timestart] 677520000 +[size] 2509 1371 +[pos] -1 -1 +*-24.000000 642355000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.core_dram_tb. +[treeopen] top.core_dram_tb.dram. +[sst_width] 301 +[signals_width] 366 +[sst_expanded] 1 +[sst_vpaned_height] 410 +@28 +top.core_dram_tb.dram.system_clk +@200 +-wb_in +@22 +#{top.core_dram_tb.dram.wb_in.adr[31:0]} top.core_dram_tb.dram.wb_in.adr[31] top.core_dram_tb.dram.wb_in.adr[30] top.core_dram_tb.dram.wb_in.adr[29] top.core_dram_tb.dram.wb_in.adr[28] top.core_dram_tb.dram.wb_in.adr[27] top.core_dram_tb.dram.wb_in.adr[26] top.core_dram_tb.dram.wb_in.adr[25] top.core_dram_tb.dram.wb_in.adr[24] top.core_dram_tb.dram.wb_in.adr[23] top.core_dram_tb.dram.wb_in.adr[22] top.core_dram_tb.dram.wb_in.adr[21] top.core_dram_tb.dram.wb_in.adr[20] top.core_dram_tb.dram.wb_in.adr[19] top.core_dram_tb.dram.wb_in.adr[18] top.core_dram_tb.dram.wb_in.adr[17] top.core_dram_tb.dram.wb_in.adr[16] top.core_dram_tb.dram.wb_in.adr[15] top.core_dram_tb.dram.wb_in.adr[14] top.core_dram_tb.dram.wb_in.adr[13] top.core_dram_tb.dram.wb_in.adr[12] top.core_dram_tb.dram.wb_in.adr[11] top.core_dram_tb.dram.wb_in.adr[10] top.core_dram_tb.dram.wb_in.adr[9] top.core_dram_tb.dram.wb_in.adr[8] top.core_dram_tb.dram.wb_in.adr[7] top.core_dram_tb.dram.wb_in.adr[6] top.core_dram_tb.dram.wb_in.adr[5] top.core_dram_tb.dram.wb_in.adr[4] top.core_dram_tb.dram.wb_in.adr[3] top.core_dram_tb.dram.wb_in.adr[2] top.core_dram_tb.dram.wb_in.adr[1] top.core_dram_tb.dram.wb_in.adr[0] +@28 +top.core_dram_tb.dram.wb_in.cyc +@22 +#{top.core_dram_tb.dram.wb_in.dat[63:0]} top.core_dram_tb.dram.wb_in.dat[63] top.core_dram_tb.dram.wb_in.dat[62] top.core_dram_tb.dram.wb_in.dat[61] top.core_dram_tb.dram.wb_in.dat[60] top.core_dram_tb.dram.wb_in.dat[59] top.core_dram_tb.dram.wb_in.dat[58] top.core_dram_tb.dram.wb_in.dat[57] top.core_dram_tb.dram.wb_in.dat[56] top.core_dram_tb.dram.wb_in.dat[55] top.core_dram_tb.dram.wb_in.dat[54] top.core_dram_tb.dram.wb_in.dat[53] top.core_dram_tb.dram.wb_in.dat[52] top.core_dram_tb.dram.wb_in.dat[51] top.core_dram_tb.dram.wb_in.dat[50] top.core_dram_tb.dram.wb_in.dat[49] top.core_dram_tb.dram.wb_in.dat[48] top.core_dram_tb.dram.wb_in.dat[47] top.core_dram_tb.dram.wb_in.dat[46] top.core_dram_tb.dram.wb_in.dat[45] top.core_dram_tb.dram.wb_in.dat[44] top.core_dram_tb.dram.wb_in.dat[43] top.core_dram_tb.dram.wb_in.dat[42] top.core_dram_tb.dram.wb_in.dat[41] top.core_dram_tb.dram.wb_in.dat[40] top.core_dram_tb.dram.wb_in.dat[39] top.core_dram_tb.dram.wb_in.dat[38] top.core_dram_tb.dram.wb_in.dat[37] top.core_dram_tb.dram.wb_in.dat[36] top.core_dram_tb.dram.wb_in.dat[35] top.core_dram_tb.dram.wb_in.dat[34] top.core_dram_tb.dram.wb_in.dat[33] top.core_dram_tb.dram.wb_in.dat[32] top.core_dram_tb.dram.wb_in.dat[31] top.core_dram_tb.dram.wb_in.dat[30] top.core_dram_tb.dram.wb_in.dat[29] top.core_dram_tb.dram.wb_in.dat[28] top.core_dram_tb.dram.wb_in.dat[27] top.core_dram_tb.dram.wb_in.dat[26] top.core_dram_tb.dram.wb_in.dat[25] top.core_dram_tb.dram.wb_in.dat[24] top.core_dram_tb.dram.wb_in.dat[23] top.core_dram_tb.dram.wb_in.dat[22] top.core_dram_tb.dram.wb_in.dat[21] top.core_dram_tb.dram.wb_in.dat[20] top.core_dram_tb.dram.wb_in.dat[19] top.core_dram_tb.dram.wb_in.dat[18] top.core_dram_tb.dram.wb_in.dat[17] top.core_dram_tb.dram.wb_in.dat[16] top.core_dram_tb.dram.wb_in.dat[15] top.core_dram_tb.dram.wb_in.dat[14] top.core_dram_tb.dram.wb_in.dat[13] top.core_dram_tb.dram.wb_in.dat[12] top.core_dram_tb.dram.wb_in.dat[11] top.core_dram_tb.dram.wb_in.dat[10] top.core_dram_tb.dram.wb_in.dat[9] top.core_dram_tb.dram.wb_in.dat[8] top.core_dram_tb.dram.wb_in.dat[7] top.core_dram_tb.dram.wb_in.dat[6] top.core_dram_tb.dram.wb_in.dat[5] top.core_dram_tb.dram.wb_in.dat[4] top.core_dram_tb.dram.wb_in.dat[3] top.core_dram_tb.dram.wb_in.dat[2] top.core_dram_tb.dram.wb_in.dat[1] top.core_dram_tb.dram.wb_in.dat[0] +#{top.core_dram_tb.dram.wb_in.sel[7:0]} top.core_dram_tb.dram.wb_in.sel[7] top.core_dram_tb.dram.wb_in.sel[6] top.core_dram_tb.dram.wb_in.sel[5] top.core_dram_tb.dram.wb_in.sel[4] top.core_dram_tb.dram.wb_in.sel[3] top.core_dram_tb.dram.wb_in.sel[2] top.core_dram_tb.dram.wb_in.sel[1] top.core_dram_tb.dram.wb_in.sel[0] +@28 +top.core_dram_tb.dram.wb_in.stb +top.core_dram_tb.dram.wb_in.we +@200 +- +-wb_out +@28 +top.core_dram_tb.dram.wb_out.ack +@22 +#{top.core_dram_tb.dram.wb_out.dat[63:0]} top.core_dram_tb.dram.wb_out.dat[63] top.core_dram_tb.dram.wb_out.dat[62] top.core_dram_tb.dram.wb_out.dat[61] top.core_dram_tb.dram.wb_out.dat[60] top.core_dram_tb.dram.wb_out.dat[59] top.core_dram_tb.dram.wb_out.dat[58] top.core_dram_tb.dram.wb_out.dat[57] top.core_dram_tb.dram.wb_out.dat[56] top.core_dram_tb.dram.wb_out.dat[55] top.core_dram_tb.dram.wb_out.dat[54] top.core_dram_tb.dram.wb_out.dat[53] top.core_dram_tb.dram.wb_out.dat[52] top.core_dram_tb.dram.wb_out.dat[51] top.core_dram_tb.dram.wb_out.dat[50] top.core_dram_tb.dram.wb_out.dat[49] top.core_dram_tb.dram.wb_out.dat[48] top.core_dram_tb.dram.wb_out.dat[47] top.core_dram_tb.dram.wb_out.dat[46] top.core_dram_tb.dram.wb_out.dat[45] top.core_dram_tb.dram.wb_out.dat[44] top.core_dram_tb.dram.wb_out.dat[43] top.core_dram_tb.dram.wb_out.dat[42] top.core_dram_tb.dram.wb_out.dat[41] top.core_dram_tb.dram.wb_out.dat[40] top.core_dram_tb.dram.wb_out.dat[39] top.core_dram_tb.dram.wb_out.dat[38] top.core_dram_tb.dram.wb_out.dat[37] top.core_dram_tb.dram.wb_out.dat[36] top.core_dram_tb.dram.wb_out.dat[35] top.core_dram_tb.dram.wb_out.dat[34] top.core_dram_tb.dram.wb_out.dat[33] top.core_dram_tb.dram.wb_out.dat[32] top.core_dram_tb.dram.wb_out.dat[31] top.core_dram_tb.dram.wb_out.dat[30] top.core_dram_tb.dram.wb_out.dat[29] top.core_dram_tb.dram.wb_out.dat[28] top.core_dram_tb.dram.wb_out.dat[27] top.core_dram_tb.dram.wb_out.dat[26] top.core_dram_tb.dram.wb_out.dat[25] top.core_dram_tb.dram.wb_out.dat[24] top.core_dram_tb.dram.wb_out.dat[23] top.core_dram_tb.dram.wb_out.dat[22] top.core_dram_tb.dram.wb_out.dat[21] top.core_dram_tb.dram.wb_out.dat[20] top.core_dram_tb.dram.wb_out.dat[19] top.core_dram_tb.dram.wb_out.dat[18] top.core_dram_tb.dram.wb_out.dat[17] top.core_dram_tb.dram.wb_out.dat[16] top.core_dram_tb.dram.wb_out.dat[15] top.core_dram_tb.dram.wb_out.dat[14] top.core_dram_tb.dram.wb_out.dat[13] top.core_dram_tb.dram.wb_out.dat[12] top.core_dram_tb.dram.wb_out.dat[11] top.core_dram_tb.dram.wb_out.dat[10] top.core_dram_tb.dram.wb_out.dat[9] top.core_dram_tb.dram.wb_out.dat[8] top.core_dram_tb.dram.wb_out.dat[7] top.core_dram_tb.dram.wb_out.dat[6] top.core_dram_tb.dram.wb_out.dat[5] top.core_dram_tb.dram.wb_out.dat[4] top.core_dram_tb.dram.wb_out.dat[3] top.core_dram_tb.dram.wb_out.dat[2] top.core_dram_tb.dram.wb_out.dat[1] top.core_dram_tb.dram.wb_out.dat[0] +@28 +top.core_dram_tb.dram.wb_out.stall +@200 +- +-wb_req +@22 +#{top.core_dram_tb.dram.wb_req.adr[31:0]} top.core_dram_tb.dram.wb_req.adr[31] top.core_dram_tb.dram.wb_req.adr[30] top.core_dram_tb.dram.wb_req.adr[29] top.core_dram_tb.dram.wb_req.adr[28] top.core_dram_tb.dram.wb_req.adr[27] top.core_dram_tb.dram.wb_req.adr[26] top.core_dram_tb.dram.wb_req.adr[25] top.core_dram_tb.dram.wb_req.adr[24] top.core_dram_tb.dram.wb_req.adr[23] top.core_dram_tb.dram.wb_req.adr[22] top.core_dram_tb.dram.wb_req.adr[21] top.core_dram_tb.dram.wb_req.adr[20] top.core_dram_tb.dram.wb_req.adr[19] top.core_dram_tb.dram.wb_req.adr[18] top.core_dram_tb.dram.wb_req.adr[17] top.core_dram_tb.dram.wb_req.adr[16] top.core_dram_tb.dram.wb_req.adr[15] top.core_dram_tb.dram.wb_req.adr[14] top.core_dram_tb.dram.wb_req.adr[13] top.core_dram_tb.dram.wb_req.adr[12] top.core_dram_tb.dram.wb_req.adr[11] top.core_dram_tb.dram.wb_req.adr[10] top.core_dram_tb.dram.wb_req.adr[9] top.core_dram_tb.dram.wb_req.adr[8] top.core_dram_tb.dram.wb_req.adr[7] top.core_dram_tb.dram.wb_req.adr[6] top.core_dram_tb.dram.wb_req.adr[5] top.core_dram_tb.dram.wb_req.adr[4] top.core_dram_tb.dram.wb_req.adr[3] top.core_dram_tb.dram.wb_req.adr[2] top.core_dram_tb.dram.wb_req.adr[1] top.core_dram_tb.dram.wb_req.adr[0] +@28 +top.core_dram_tb.dram.wb_req.cyc +@22 +#{top.core_dram_tb.dram.wb_req.dat[63:0]} top.core_dram_tb.dram.wb_req.dat[63] top.core_dram_tb.dram.wb_req.dat[62] top.core_dram_tb.dram.wb_req.dat[61] top.core_dram_tb.dram.wb_req.dat[60] top.core_dram_tb.dram.wb_req.dat[59] top.core_dram_tb.dram.wb_req.dat[58] top.core_dram_tb.dram.wb_req.dat[57] top.core_dram_tb.dram.wb_req.dat[56] top.core_dram_tb.dram.wb_req.dat[55] top.core_dram_tb.dram.wb_req.dat[54] top.core_dram_tb.dram.wb_req.dat[53] top.core_dram_tb.dram.wb_req.dat[52] top.core_dram_tb.dram.wb_req.dat[51] top.core_dram_tb.dram.wb_req.dat[50] top.core_dram_tb.dram.wb_req.dat[49] top.core_dram_tb.dram.wb_req.dat[48] top.core_dram_tb.dram.wb_req.dat[47] top.core_dram_tb.dram.wb_req.dat[46] top.core_dram_tb.dram.wb_req.dat[45] top.core_dram_tb.dram.wb_req.dat[44] top.core_dram_tb.dram.wb_req.dat[43] top.core_dram_tb.dram.wb_req.dat[42] top.core_dram_tb.dram.wb_req.dat[41] top.core_dram_tb.dram.wb_req.dat[40] top.core_dram_tb.dram.wb_req.dat[39] top.core_dram_tb.dram.wb_req.dat[38] top.core_dram_tb.dram.wb_req.dat[37] top.core_dram_tb.dram.wb_req.dat[36] top.core_dram_tb.dram.wb_req.dat[35] top.core_dram_tb.dram.wb_req.dat[34] top.core_dram_tb.dram.wb_req.dat[33] top.core_dram_tb.dram.wb_req.dat[32] top.core_dram_tb.dram.wb_req.dat[31] top.core_dram_tb.dram.wb_req.dat[30] top.core_dram_tb.dram.wb_req.dat[29] top.core_dram_tb.dram.wb_req.dat[28] top.core_dram_tb.dram.wb_req.dat[27] top.core_dram_tb.dram.wb_req.dat[26] top.core_dram_tb.dram.wb_req.dat[25] top.core_dram_tb.dram.wb_req.dat[24] top.core_dram_tb.dram.wb_req.dat[23] top.core_dram_tb.dram.wb_req.dat[22] top.core_dram_tb.dram.wb_req.dat[21] top.core_dram_tb.dram.wb_req.dat[20] top.core_dram_tb.dram.wb_req.dat[19] top.core_dram_tb.dram.wb_req.dat[18] top.core_dram_tb.dram.wb_req.dat[17] top.core_dram_tb.dram.wb_req.dat[16] top.core_dram_tb.dram.wb_req.dat[15] top.core_dram_tb.dram.wb_req.dat[14] top.core_dram_tb.dram.wb_req.dat[13] top.core_dram_tb.dram.wb_req.dat[12] top.core_dram_tb.dram.wb_req.dat[11] top.core_dram_tb.dram.wb_req.dat[10] top.core_dram_tb.dram.wb_req.dat[9] top.core_dram_tb.dram.wb_req.dat[8] top.core_dram_tb.dram.wb_req.dat[7] top.core_dram_tb.dram.wb_req.dat[6] top.core_dram_tb.dram.wb_req.dat[5] top.core_dram_tb.dram.wb_req.dat[4] top.core_dram_tb.dram.wb_req.dat[3] top.core_dram_tb.dram.wb_req.dat[2] top.core_dram_tb.dram.wb_req.dat[1] top.core_dram_tb.dram.wb_req.dat[0] +#{top.core_dram_tb.dram.wb_req.sel[7:0]} top.core_dram_tb.dram.wb_req.sel[7] top.core_dram_tb.dram.wb_req.sel[6] top.core_dram_tb.dram.wb_req.sel[5] top.core_dram_tb.dram.wb_req.sel[4] top.core_dram_tb.dram.wb_req.sel[3] top.core_dram_tb.dram.wb_req.sel[2] top.core_dram_tb.dram.wb_req.sel[1] top.core_dram_tb.dram.wb_req.sel[0] +@28 +top.core_dram_tb.dram.wb_req.stb +top.core_dram_tb.dram.wb_req.we +@200 +- +-user_port +@28 +top.core_dram_tb.dram.user_port0_rdata_ready +top.core_dram_tb.dram.user_port0_rdata_valid +top.core_dram_tb.dram.user_port0_wdata_ready +top.core_dram_tb.dram.user_port0_wdata_valid +top.core_dram_tb.dram.user_port0_cmd_we +top.core_dram_tb.dram.user_port0_cmd_ready +top.core_dram_tb.dram.user_port0_cmd_valid +@22 +#{top.core_dram_tb.dram.user_port0_rdata_data[127:0]} top.core_dram_tb.dram.user_port0_rdata_data[127] top.core_dram_tb.dram.user_port0_rdata_data[126] top.core_dram_tb.dram.user_port0_rdata_data[125] top.core_dram_tb.dram.user_port0_rdata_data[124] top.core_dram_tb.dram.user_port0_rdata_data[123] top.core_dram_tb.dram.user_port0_rdata_data[122] top.core_dram_tb.dram.user_port0_rdata_data[121] top.core_dram_tb.dram.user_port0_rdata_data[120] top.core_dram_tb.dram.user_port0_rdata_data[119] top.core_dram_tb.dram.user_port0_rdata_data[118] top.core_dram_tb.dram.user_port0_rdata_data[117] top.core_dram_tb.dram.user_port0_rdata_data[116] top.core_dram_tb.dram.user_port0_rdata_data[115] top.core_dram_tb.dram.user_port0_rdata_data[114] top.core_dram_tb.dram.user_port0_rdata_data[113] top.core_dram_tb.dram.user_port0_rdata_data[112] top.core_dram_tb.dram.user_port0_rdata_data[111] top.core_dram_tb.dram.user_port0_rdata_data[110] top.core_dram_tb.dram.user_port0_rdata_data[109] top.core_dram_tb.dram.user_port0_rdata_data[108] top.core_dram_tb.dram.user_port0_rdata_data[107] top.core_dram_tb.dram.user_port0_rdata_data[106] top.core_dram_tb.dram.user_port0_rdata_data[105] top.core_dram_tb.dram.user_port0_rdata_data[104] top.core_dram_tb.dram.user_port0_rdata_data[103] top.core_dram_tb.dram.user_port0_rdata_data[102] top.core_dram_tb.dram.user_port0_rdata_data[101] top.core_dram_tb.dram.user_port0_rdata_data[100] top.core_dram_tb.dram.user_port0_rdata_data[99] top.core_dram_tb.dram.user_port0_rdata_data[98] top.core_dram_tb.dram.user_port0_rdata_data[97] top.core_dram_tb.dram.user_port0_rdata_data[96] top.core_dram_tb.dram.user_port0_rdata_data[95] top.core_dram_tb.dram.user_port0_rdata_data[94] top.core_dram_tb.dram.user_port0_rdata_data[93] top.core_dram_tb.dram.user_port0_rdata_data[92] top.core_dram_tb.dram.user_port0_rdata_data[91] top.core_dram_tb.dram.user_port0_rdata_data[90] top.core_dram_tb.dram.user_port0_rdata_data[89] top.core_dram_tb.dram.user_port0_rdata_data[88] top.core_dram_tb.dram.user_port0_rdata_data[87] top.core_dram_tb.dram.user_port0_rdata_data[86] top.core_dram_tb.dram.user_port0_rdata_data[85] top.core_dram_tb.dram.user_port0_rdata_data[84] top.core_dram_tb.dram.user_port0_rdata_data[83] top.core_dram_tb.dram.user_port0_rdata_data[82] top.core_dram_tb.dram.user_port0_rdata_data[81] top.core_dram_tb.dram.user_port0_rdata_data[80] top.core_dram_tb.dram.user_port0_rdata_data[79] top.core_dram_tb.dram.user_port0_rdata_data[78] top.core_dram_tb.dram.user_port0_rdata_data[77] top.core_dram_tb.dram.user_port0_rdata_data[76] top.core_dram_tb.dram.user_port0_rdata_data[75] top.core_dram_tb.dram.user_port0_rdata_data[74] top.core_dram_tb.dram.user_port0_rdata_data[73] top.core_dram_tb.dram.user_port0_rdata_data[72] top.core_dram_tb.dram.user_port0_rdata_data[71] top.core_dram_tb.dram.user_port0_rdata_data[70] top.core_dram_tb.dram.user_port0_rdata_data[69] top.core_dram_tb.dram.user_port0_rdata_data[68] top.core_dram_tb.dram.user_port0_rdata_data[67] top.core_dram_tb.dram.user_port0_rdata_data[66] top.core_dram_tb.dram.user_port0_rdata_data[65] top.core_dram_tb.dram.user_port0_rdata_data[64] top.core_dram_tb.dram.user_port0_rdata_data[63] top.core_dram_tb.dram.user_port0_rdata_data[62] top.core_dram_tb.dram.user_port0_rdata_data[61] top.core_dram_tb.dram.user_port0_rdata_data[60] top.core_dram_tb.dram.user_port0_rdata_data[59] top.core_dram_tb.dram.user_port0_rdata_data[58] top.core_dram_tb.dram.user_port0_rdata_data[57] top.core_dram_tb.dram.user_port0_rdata_data[56] top.core_dram_tb.dram.user_port0_rdata_data[55] top.core_dram_tb.dram.user_port0_rdata_data[54] top.core_dram_tb.dram.user_port0_rdata_data[53] top.core_dram_tb.dram.user_port0_rdata_data[52] top.core_dram_tb.dram.user_port0_rdata_data[51] top.core_dram_tb.dram.user_port0_rdata_data[50] top.core_dram_tb.dram.user_port0_rdata_data[49] top.core_dram_tb.dram.user_port0_rdata_data[48] top.core_dram_tb.dram.user_port0_rdata_data[47] top.core_dram_tb.dram.user_port0_rdata_data[46] top.core_dram_tb.dram.user_port0_rdata_data[45] top.core_dram_tb.dram.user_port0_rdata_data[44] top.core_dram_tb.dram.user_port0_rdata_data[43] top.core_dram_tb.dram.user_port0_rdata_data[42] top.core_dram_tb.dram.user_port0_rdata_data[41] top.core_dram_tb.dram.user_port0_rdata_data[40] top.core_dram_tb.dram.user_port0_rdata_data[39] top.core_dram_tb.dram.user_port0_rdata_data[38] top.core_dram_tb.dram.user_port0_rdata_data[37] top.core_dram_tb.dram.user_port0_rdata_data[36] top.core_dram_tb.dram.user_port0_rdata_data[35] top.core_dram_tb.dram.user_port0_rdata_data[34] top.core_dram_tb.dram.user_port0_rdata_data[33] top.core_dram_tb.dram.user_port0_rdata_data[32] top.core_dram_tb.dram.user_port0_rdata_data[31] top.core_dram_tb.dram.user_port0_rdata_data[30] top.core_dram_tb.dram.user_port0_rdata_data[29] top.core_dram_tb.dram.user_port0_rdata_data[28] top.core_dram_tb.dram.user_port0_rdata_data[27] top.core_dram_tb.dram.user_port0_rdata_data[26] top.core_dram_tb.dram.user_port0_rdata_data[25] top.core_dram_tb.dram.user_port0_rdata_data[24] top.core_dram_tb.dram.user_port0_rdata_data[23] top.core_dram_tb.dram.user_port0_rdata_data[22] top.core_dram_tb.dram.user_port0_rdata_data[21] top.core_dram_tb.dram.user_port0_rdata_data[20] top.core_dram_tb.dram.user_port0_rdata_data[19] top.core_dram_tb.dram.user_port0_rdata_data[18] top.core_dram_tb.dram.user_port0_rdata_data[17] top.core_dram_tb.dram.user_port0_rdata_data[16] top.core_dram_tb.dram.user_port0_rdata_data[15] top.core_dram_tb.dram.user_port0_rdata_data[14] top.core_dram_tb.dram.user_port0_rdata_data[13] top.core_dram_tb.dram.user_port0_rdata_data[12] top.core_dram_tb.dram.user_port0_rdata_data[11] top.core_dram_tb.dram.user_port0_rdata_data[10] top.core_dram_tb.dram.user_port0_rdata_data[9] top.core_dram_tb.dram.user_port0_rdata_data[8] top.core_dram_tb.dram.user_port0_rdata_data[7] top.core_dram_tb.dram.user_port0_rdata_data[6] top.core_dram_tb.dram.user_port0_rdata_data[5] top.core_dram_tb.dram.user_port0_rdata_data[4] top.core_dram_tb.dram.user_port0_rdata_data[3] top.core_dram_tb.dram.user_port0_rdata_data[2] top.core_dram_tb.dram.user_port0_rdata_data[1] top.core_dram_tb.dram.user_port0_rdata_data[0] +#{top.core_dram_tb.dram.user_port0_wdata_data[127:0]} top.core_dram_tb.dram.user_port0_wdata_data[127] top.core_dram_tb.dram.user_port0_wdata_data[126] top.core_dram_tb.dram.user_port0_wdata_data[125] top.core_dram_tb.dram.user_port0_wdata_data[124] top.core_dram_tb.dram.user_port0_wdata_data[123] top.core_dram_tb.dram.user_port0_wdata_data[122] top.core_dram_tb.dram.user_port0_wdata_data[121] top.core_dram_tb.dram.user_port0_wdata_data[120] top.core_dram_tb.dram.user_port0_wdata_data[119] top.core_dram_tb.dram.user_port0_wdata_data[118] top.core_dram_tb.dram.user_port0_wdata_data[117] top.core_dram_tb.dram.user_port0_wdata_data[116] top.core_dram_tb.dram.user_port0_wdata_data[115] top.core_dram_tb.dram.user_port0_wdata_data[114] top.core_dram_tb.dram.user_port0_wdata_data[113] top.core_dram_tb.dram.user_port0_wdata_data[112] top.core_dram_tb.dram.user_port0_wdata_data[111] top.core_dram_tb.dram.user_port0_wdata_data[110] top.core_dram_tb.dram.user_port0_wdata_data[109] top.core_dram_tb.dram.user_port0_wdata_data[108] top.core_dram_tb.dram.user_port0_wdata_data[107] top.core_dram_tb.dram.user_port0_wdata_data[106] top.core_dram_tb.dram.user_port0_wdata_data[105] top.core_dram_tb.dram.user_port0_wdata_data[104] top.core_dram_tb.dram.user_port0_wdata_data[103] top.core_dram_tb.dram.user_port0_wdata_data[102] top.core_dram_tb.dram.user_port0_wdata_data[101] top.core_dram_tb.dram.user_port0_wdata_data[100] top.core_dram_tb.dram.user_port0_wdata_data[99] top.core_dram_tb.dram.user_port0_wdata_data[98] top.core_dram_tb.dram.user_port0_wdata_data[97] top.core_dram_tb.dram.user_port0_wdata_data[96] top.core_dram_tb.dram.user_port0_wdata_data[95] top.core_dram_tb.dram.user_port0_wdata_data[94] top.core_dram_tb.dram.user_port0_wdata_data[93] top.core_dram_tb.dram.user_port0_wdata_data[92] top.core_dram_tb.dram.user_port0_wdata_data[91] top.core_dram_tb.dram.user_port0_wdata_data[90] top.core_dram_tb.dram.user_port0_wdata_data[89] top.core_dram_tb.dram.user_port0_wdata_data[88] top.core_dram_tb.dram.user_port0_wdata_data[87] top.core_dram_tb.dram.user_port0_wdata_data[86] top.core_dram_tb.dram.user_port0_wdata_data[85] top.core_dram_tb.dram.user_port0_wdata_data[84] top.core_dram_tb.dram.user_port0_wdata_data[83] top.core_dram_tb.dram.user_port0_wdata_data[82] top.core_dram_tb.dram.user_port0_wdata_data[81] top.core_dram_tb.dram.user_port0_wdata_data[80] top.core_dram_tb.dram.user_port0_wdata_data[79] top.core_dram_tb.dram.user_port0_wdata_data[78] top.core_dram_tb.dram.user_port0_wdata_data[77] top.core_dram_tb.dram.user_port0_wdata_data[76] top.core_dram_tb.dram.user_port0_wdata_data[75] top.core_dram_tb.dram.user_port0_wdata_data[74] top.core_dram_tb.dram.user_port0_wdata_data[73] top.core_dram_tb.dram.user_port0_wdata_data[72] top.core_dram_tb.dram.user_port0_wdata_data[71] top.core_dram_tb.dram.user_port0_wdata_data[70] top.core_dram_tb.dram.user_port0_wdata_data[69] top.core_dram_tb.dram.user_port0_wdata_data[68] top.core_dram_tb.dram.user_port0_wdata_data[67] top.core_dram_tb.dram.user_port0_wdata_data[66] top.core_dram_tb.dram.user_port0_wdata_data[65] top.core_dram_tb.dram.user_port0_wdata_data[64] top.core_dram_tb.dram.user_port0_wdata_data[63] top.core_dram_tb.dram.user_port0_wdata_data[62] top.core_dram_tb.dram.user_port0_wdata_data[61] top.core_dram_tb.dram.user_port0_wdata_data[60] top.core_dram_tb.dram.user_port0_wdata_data[59] top.core_dram_tb.dram.user_port0_wdata_data[58] top.core_dram_tb.dram.user_port0_wdata_data[57] top.core_dram_tb.dram.user_port0_wdata_data[56] top.core_dram_tb.dram.user_port0_wdata_data[55] top.core_dram_tb.dram.user_port0_wdata_data[54] top.core_dram_tb.dram.user_port0_wdata_data[53] top.core_dram_tb.dram.user_port0_wdata_data[52] top.core_dram_tb.dram.user_port0_wdata_data[51] top.core_dram_tb.dram.user_port0_wdata_data[50] top.core_dram_tb.dram.user_port0_wdata_data[49] top.core_dram_tb.dram.user_port0_wdata_data[48] top.core_dram_tb.dram.user_port0_wdata_data[47] top.core_dram_tb.dram.user_port0_wdata_data[46] top.core_dram_tb.dram.user_port0_wdata_data[45] top.core_dram_tb.dram.user_port0_wdata_data[44] top.core_dram_tb.dram.user_port0_wdata_data[43] top.core_dram_tb.dram.user_port0_wdata_data[42] top.core_dram_tb.dram.user_port0_wdata_data[41] top.core_dram_tb.dram.user_port0_wdata_data[40] top.core_dram_tb.dram.user_port0_wdata_data[39] top.core_dram_tb.dram.user_port0_wdata_data[38] top.core_dram_tb.dram.user_port0_wdata_data[37] top.core_dram_tb.dram.user_port0_wdata_data[36] top.core_dram_tb.dram.user_port0_wdata_data[35] top.core_dram_tb.dram.user_port0_wdata_data[34] top.core_dram_tb.dram.user_port0_wdata_data[33] top.core_dram_tb.dram.user_port0_wdata_data[32] top.core_dram_tb.dram.user_port0_wdata_data[31] top.core_dram_tb.dram.user_port0_wdata_data[30] top.core_dram_tb.dram.user_port0_wdata_data[29] top.core_dram_tb.dram.user_port0_wdata_data[28] top.core_dram_tb.dram.user_port0_wdata_data[27] top.core_dram_tb.dram.user_port0_wdata_data[26] top.core_dram_tb.dram.user_port0_wdata_data[25] top.core_dram_tb.dram.user_port0_wdata_data[24] top.core_dram_tb.dram.user_port0_wdata_data[23] top.core_dram_tb.dram.user_port0_wdata_data[22] top.core_dram_tb.dram.user_port0_wdata_data[21] top.core_dram_tb.dram.user_port0_wdata_data[20] top.core_dram_tb.dram.user_port0_wdata_data[19] top.core_dram_tb.dram.user_port0_wdata_data[18] top.core_dram_tb.dram.user_port0_wdata_data[17] top.core_dram_tb.dram.user_port0_wdata_data[16] top.core_dram_tb.dram.user_port0_wdata_data[15] top.core_dram_tb.dram.user_port0_wdata_data[14] top.core_dram_tb.dram.user_port0_wdata_data[13] top.core_dram_tb.dram.user_port0_wdata_data[12] top.core_dram_tb.dram.user_port0_wdata_data[11] top.core_dram_tb.dram.user_port0_wdata_data[10] top.core_dram_tb.dram.user_port0_wdata_data[9] top.core_dram_tb.dram.user_port0_wdata_data[8] top.core_dram_tb.dram.user_port0_wdata_data[7] top.core_dram_tb.dram.user_port0_wdata_data[6] top.core_dram_tb.dram.user_port0_wdata_data[5] top.core_dram_tb.dram.user_port0_wdata_data[4] top.core_dram_tb.dram.user_port0_wdata_data[3] top.core_dram_tb.dram.user_port0_wdata_data[2] top.core_dram_tb.dram.user_port0_wdata_data[1] top.core_dram_tb.dram.user_port0_wdata_data[0] +#{top.core_dram_tb.dram.user_port0_wdata_we[15:0]} top.core_dram_tb.dram.user_port0_wdata_we[15] top.core_dram_tb.dram.user_port0_wdata_we[14] top.core_dram_tb.dram.user_port0_wdata_we[13] top.core_dram_tb.dram.user_port0_wdata_we[12] top.core_dram_tb.dram.user_port0_wdata_we[11] top.core_dram_tb.dram.user_port0_wdata_we[10] top.core_dram_tb.dram.user_port0_wdata_we[9] top.core_dram_tb.dram.user_port0_wdata_we[8] top.core_dram_tb.dram.user_port0_wdata_we[7] top.core_dram_tb.dram.user_port0_wdata_we[6] top.core_dram_tb.dram.user_port0_wdata_we[5] top.core_dram_tb.dram.user_port0_wdata_we[4] top.core_dram_tb.dram.user_port0_wdata_we[3] top.core_dram_tb.dram.user_port0_wdata_we[2] top.core_dram_tb.dram.user_port0_wdata_we[1] top.core_dram_tb.dram.user_port0_wdata_we[0] +#{top.core_dram_tb.dram.user_port0_cmd_addr[23:0]} top.core_dram_tb.dram.user_port0_cmd_addr[23] top.core_dram_tb.dram.user_port0_cmd_addr[22] top.core_dram_tb.dram.user_port0_cmd_addr[21] top.core_dram_tb.dram.user_port0_cmd_addr[20] top.core_dram_tb.dram.user_port0_cmd_addr[19] top.core_dram_tb.dram.user_port0_cmd_addr[18] top.core_dram_tb.dram.user_port0_cmd_addr[17] top.core_dram_tb.dram.user_port0_cmd_addr[16] top.core_dram_tb.dram.user_port0_cmd_addr[15] top.core_dram_tb.dram.user_port0_cmd_addr[14] top.core_dram_tb.dram.user_port0_cmd_addr[13] top.core_dram_tb.dram.user_port0_cmd_addr[12] top.core_dram_tb.dram.user_port0_cmd_addr[11] top.core_dram_tb.dram.user_port0_cmd_addr[10] top.core_dram_tb.dram.user_port0_cmd_addr[9] top.core_dram_tb.dram.user_port0_cmd_addr[8] top.core_dram_tb.dram.user_port0_cmd_addr[7] top.core_dram_tb.dram.user_port0_cmd_addr[6] top.core_dram_tb.dram.user_port0_cmd_addr[5] top.core_dram_tb.dram.user_port0_cmd_addr[4] top.core_dram_tb.dram.user_port0_cmd_addr[3] top.core_dram_tb.dram.user_port0_cmd_addr[2] top.core_dram_tb.dram.user_port0_cmd_addr[1] top.core_dram_tb.dram.user_port0_cmd_addr[0] +@200 +- +-storeq +@28 +top.core_dram_tb.dram.accept_store +top.core_dram_tb.dram.storeq_wr_valid +top.core_dram_tb.dram.storeq_wr_ready +@22 +#{top.core_dram_tb.dram.storeq_wr_data[79:0]} top.core_dram_tb.dram.storeq_wr_data[79] top.core_dram_tb.dram.storeq_wr_data[78] top.core_dram_tb.dram.storeq_wr_data[77] top.core_dram_tb.dram.storeq_wr_data[76] top.core_dram_tb.dram.storeq_wr_data[75] top.core_dram_tb.dram.storeq_wr_data[74] top.core_dram_tb.dram.storeq_wr_data[73] top.core_dram_tb.dram.storeq_wr_data[72] top.core_dram_tb.dram.storeq_wr_data[71] top.core_dram_tb.dram.storeq_wr_data[70] top.core_dram_tb.dram.storeq_wr_data[69] top.core_dram_tb.dram.storeq_wr_data[68] top.core_dram_tb.dram.storeq_wr_data[67] top.core_dram_tb.dram.storeq_wr_data[66] top.core_dram_tb.dram.storeq_wr_data[65] top.core_dram_tb.dram.storeq_wr_data[64] top.core_dram_tb.dram.storeq_wr_data[63] top.core_dram_tb.dram.storeq_wr_data[62] top.core_dram_tb.dram.storeq_wr_data[61] top.core_dram_tb.dram.storeq_wr_data[60] top.core_dram_tb.dram.storeq_wr_data[59] top.core_dram_tb.dram.storeq_wr_data[58] top.core_dram_tb.dram.storeq_wr_data[57] top.core_dram_tb.dram.storeq_wr_data[56] top.core_dram_tb.dram.storeq_wr_data[55] top.core_dram_tb.dram.storeq_wr_data[54] top.core_dram_tb.dram.storeq_wr_data[53] top.core_dram_tb.dram.storeq_wr_data[52] top.core_dram_tb.dram.storeq_wr_data[51] top.core_dram_tb.dram.storeq_wr_data[50] top.core_dram_tb.dram.storeq_wr_data[49] top.core_dram_tb.dram.storeq_wr_data[48] top.core_dram_tb.dram.storeq_wr_data[47] top.core_dram_tb.dram.storeq_wr_data[46] top.core_dram_tb.dram.storeq_wr_data[45] top.core_dram_tb.dram.storeq_wr_data[44] top.core_dram_tb.dram.storeq_wr_data[43] top.core_dram_tb.dram.storeq_wr_data[42] top.core_dram_tb.dram.storeq_wr_data[41] top.core_dram_tb.dram.storeq_wr_data[40] top.core_dram_tb.dram.storeq_wr_data[39] top.core_dram_tb.dram.storeq_wr_data[38] top.core_dram_tb.dram.storeq_wr_data[37] top.core_dram_tb.dram.storeq_wr_data[36] top.core_dram_tb.dram.storeq_wr_data[35] top.core_dram_tb.dram.storeq_wr_data[34] top.core_dram_tb.dram.storeq_wr_data[33] top.core_dram_tb.dram.storeq_wr_data[32] top.core_dram_tb.dram.storeq_wr_data[31] top.core_dram_tb.dram.storeq_wr_data[30] top.core_dram_tb.dram.storeq_wr_data[29] top.core_dram_tb.dram.storeq_wr_data[28] top.core_dram_tb.dram.storeq_wr_data[27] top.core_dram_tb.dram.storeq_wr_data[26] top.core_dram_tb.dram.storeq_wr_data[25] top.core_dram_tb.dram.storeq_wr_data[24] top.core_dram_tb.dram.storeq_wr_data[23] top.core_dram_tb.dram.storeq_wr_data[22] top.core_dram_tb.dram.storeq_wr_data[21] top.core_dram_tb.dram.storeq_wr_data[20] top.core_dram_tb.dram.storeq_wr_data[19] top.core_dram_tb.dram.storeq_wr_data[18] top.core_dram_tb.dram.storeq_wr_data[17] top.core_dram_tb.dram.storeq_wr_data[16] top.core_dram_tb.dram.storeq_wr_data[15] top.core_dram_tb.dram.storeq_wr_data[14] top.core_dram_tb.dram.storeq_wr_data[13] top.core_dram_tb.dram.storeq_wr_data[12] top.core_dram_tb.dram.storeq_wr_data[11] top.core_dram_tb.dram.storeq_wr_data[10] top.core_dram_tb.dram.storeq_wr_data[9] top.core_dram_tb.dram.storeq_wr_data[8] top.core_dram_tb.dram.storeq_wr_data[7] top.core_dram_tb.dram.storeq_wr_data[6] top.core_dram_tb.dram.storeq_wr_data[5] top.core_dram_tb.dram.storeq_wr_data[4] top.core_dram_tb.dram.storeq_wr_data[3] top.core_dram_tb.dram.storeq_wr_data[2] top.core_dram_tb.dram.storeq_wr_data[1] top.core_dram_tb.dram.storeq_wr_data[0] +@28 +top.core_dram_tb.dram.storeq_rd_valid +top.core_dram_tb.dram.storeq_rd_ready +@22 +#{top.core_dram_tb.dram.storeq_rd_data[79:0]} top.core_dram_tb.dram.storeq_rd_data[79] top.core_dram_tb.dram.storeq_rd_data[78] top.core_dram_tb.dram.storeq_rd_data[77] top.core_dram_tb.dram.storeq_rd_data[76] top.core_dram_tb.dram.storeq_rd_data[75] top.core_dram_tb.dram.storeq_rd_data[74] top.core_dram_tb.dram.storeq_rd_data[73] top.core_dram_tb.dram.storeq_rd_data[72] top.core_dram_tb.dram.storeq_rd_data[71] top.core_dram_tb.dram.storeq_rd_data[70] top.core_dram_tb.dram.storeq_rd_data[69] top.core_dram_tb.dram.storeq_rd_data[68] top.core_dram_tb.dram.storeq_rd_data[67] top.core_dram_tb.dram.storeq_rd_data[66] top.core_dram_tb.dram.storeq_rd_data[65] top.core_dram_tb.dram.storeq_rd_data[64] top.core_dram_tb.dram.storeq_rd_data[63] top.core_dram_tb.dram.storeq_rd_data[62] top.core_dram_tb.dram.storeq_rd_data[61] top.core_dram_tb.dram.storeq_rd_data[60] top.core_dram_tb.dram.storeq_rd_data[59] top.core_dram_tb.dram.storeq_rd_data[58] top.core_dram_tb.dram.storeq_rd_data[57] top.core_dram_tb.dram.storeq_rd_data[56] top.core_dram_tb.dram.storeq_rd_data[55] top.core_dram_tb.dram.storeq_rd_data[54] top.core_dram_tb.dram.storeq_rd_data[53] top.core_dram_tb.dram.storeq_rd_data[52] top.core_dram_tb.dram.storeq_rd_data[51] top.core_dram_tb.dram.storeq_rd_data[50] top.core_dram_tb.dram.storeq_rd_data[49] top.core_dram_tb.dram.storeq_rd_data[48] top.core_dram_tb.dram.storeq_rd_data[47] top.core_dram_tb.dram.storeq_rd_data[46] top.core_dram_tb.dram.storeq_rd_data[45] top.core_dram_tb.dram.storeq_rd_data[44] top.core_dram_tb.dram.storeq_rd_data[43] top.core_dram_tb.dram.storeq_rd_data[42] top.core_dram_tb.dram.storeq_rd_data[41] top.core_dram_tb.dram.storeq_rd_data[40] top.core_dram_tb.dram.storeq_rd_data[39] top.core_dram_tb.dram.storeq_rd_data[38] top.core_dram_tb.dram.storeq_rd_data[37] top.core_dram_tb.dram.storeq_rd_data[36] top.core_dram_tb.dram.storeq_rd_data[35] top.core_dram_tb.dram.storeq_rd_data[34] top.core_dram_tb.dram.storeq_rd_data[33] top.core_dram_tb.dram.storeq_rd_data[32] top.core_dram_tb.dram.storeq_rd_data[31] top.core_dram_tb.dram.storeq_rd_data[30] top.core_dram_tb.dram.storeq_rd_data[29] top.core_dram_tb.dram.storeq_rd_data[28] top.core_dram_tb.dram.storeq_rd_data[27] top.core_dram_tb.dram.storeq_rd_data[26] top.core_dram_tb.dram.storeq_rd_data[25] top.core_dram_tb.dram.storeq_rd_data[24] top.core_dram_tb.dram.storeq_rd_data[23] top.core_dram_tb.dram.storeq_rd_data[22] top.core_dram_tb.dram.storeq_rd_data[21] top.core_dram_tb.dram.storeq_rd_data[20] top.core_dram_tb.dram.storeq_rd_data[19] top.core_dram_tb.dram.storeq_rd_data[18] top.core_dram_tb.dram.storeq_rd_data[17] top.core_dram_tb.dram.storeq_rd_data[16] top.core_dram_tb.dram.storeq_rd_data[15] top.core_dram_tb.dram.storeq_rd_data[14] top.core_dram_tb.dram.storeq_rd_data[13] top.core_dram_tb.dram.storeq_rd_data[12] top.core_dram_tb.dram.storeq_rd_data[11] top.core_dram_tb.dram.storeq_rd_data[10] top.core_dram_tb.dram.storeq_rd_data[9] top.core_dram_tb.dram.storeq_rd_data[8] top.core_dram_tb.dram.storeq_rd_data[7] top.core_dram_tb.dram.storeq_rd_data[6] top.core_dram_tb.dram.storeq_rd_data[5] top.core_dram_tb.dram.storeq_rd_data[4] top.core_dram_tb.dram.storeq_rd_data[3] top.core_dram_tb.dram.storeq_rd_data[2] top.core_dram_tb.dram.storeq_rd_data[1] top.core_dram_tb.dram.storeq_rd_data[0] +@200 +- +-misc +@420 +top.core_dram_tb.dram.req_op +top.core_dram_tb.dram.state +@200 +- +@201 +-sync_fifo +@28 +top.core_dram_tb.dram.store_queue.empty +top.core_dram_tb.dram.store_queue.full +@420 +top.core_dram_tb.dram.store_queue.op_next +top.core_dram_tb.dram.store_queue.op_prev +@28 +top.core_dram_tb.dram.store_queue.pop +top.core_dram_tb.dram.store_queue.push +@22 +#{top.core_dram_tb.dram.store_queue.rd_data[79:0]} top.core_dram_tb.dram.store_queue.rd_data[79] top.core_dram_tb.dram.store_queue.rd_data[78] top.core_dram_tb.dram.store_queue.rd_data[77] top.core_dram_tb.dram.store_queue.rd_data[76] top.core_dram_tb.dram.store_queue.rd_data[75] top.core_dram_tb.dram.store_queue.rd_data[74] top.core_dram_tb.dram.store_queue.rd_data[73] top.core_dram_tb.dram.store_queue.rd_data[72] top.core_dram_tb.dram.store_queue.rd_data[71] top.core_dram_tb.dram.store_queue.rd_data[70] top.core_dram_tb.dram.store_queue.rd_data[69] top.core_dram_tb.dram.store_queue.rd_data[68] top.core_dram_tb.dram.store_queue.rd_data[67] top.core_dram_tb.dram.store_queue.rd_data[66] top.core_dram_tb.dram.store_queue.rd_data[65] top.core_dram_tb.dram.store_queue.rd_data[64] top.core_dram_tb.dram.store_queue.rd_data[63] top.core_dram_tb.dram.store_queue.rd_data[62] top.core_dram_tb.dram.store_queue.rd_data[61] top.core_dram_tb.dram.store_queue.rd_data[60] top.core_dram_tb.dram.store_queue.rd_data[59] top.core_dram_tb.dram.store_queue.rd_data[58] top.core_dram_tb.dram.store_queue.rd_data[57] top.core_dram_tb.dram.store_queue.rd_data[56] top.core_dram_tb.dram.store_queue.rd_data[55] top.core_dram_tb.dram.store_queue.rd_data[54] top.core_dram_tb.dram.store_queue.rd_data[53] top.core_dram_tb.dram.store_queue.rd_data[52] top.core_dram_tb.dram.store_queue.rd_data[51] top.core_dram_tb.dram.store_queue.rd_data[50] top.core_dram_tb.dram.store_queue.rd_data[49] top.core_dram_tb.dram.store_queue.rd_data[48] top.core_dram_tb.dram.store_queue.rd_data[47] top.core_dram_tb.dram.store_queue.rd_data[46] top.core_dram_tb.dram.store_queue.rd_data[45] top.core_dram_tb.dram.store_queue.rd_data[44] top.core_dram_tb.dram.store_queue.rd_data[43] top.core_dram_tb.dram.store_queue.rd_data[42] top.core_dram_tb.dram.store_queue.rd_data[41] top.core_dram_tb.dram.store_queue.rd_data[40] top.core_dram_tb.dram.store_queue.rd_data[39] top.core_dram_tb.dram.store_queue.rd_data[38] top.core_dram_tb.dram.store_queue.rd_data[37] top.core_dram_tb.dram.store_queue.rd_data[36] top.core_dram_tb.dram.store_queue.rd_data[35] top.core_dram_tb.dram.store_queue.rd_data[34] top.core_dram_tb.dram.store_queue.rd_data[33] top.core_dram_tb.dram.store_queue.rd_data[32] top.core_dram_tb.dram.store_queue.rd_data[31] top.core_dram_tb.dram.store_queue.rd_data[30] top.core_dram_tb.dram.store_queue.rd_data[29] top.core_dram_tb.dram.store_queue.rd_data[28] top.core_dram_tb.dram.store_queue.rd_data[27] top.core_dram_tb.dram.store_queue.rd_data[26] top.core_dram_tb.dram.store_queue.rd_data[25] top.core_dram_tb.dram.store_queue.rd_data[24] top.core_dram_tb.dram.store_queue.rd_data[23] top.core_dram_tb.dram.store_queue.rd_data[22] top.core_dram_tb.dram.store_queue.rd_data[21] top.core_dram_tb.dram.store_queue.rd_data[20] top.core_dram_tb.dram.store_queue.rd_data[19] top.core_dram_tb.dram.store_queue.rd_data[18] top.core_dram_tb.dram.store_queue.rd_data[17] top.core_dram_tb.dram.store_queue.rd_data[16] top.core_dram_tb.dram.store_queue.rd_data[15] top.core_dram_tb.dram.store_queue.rd_data[14] top.core_dram_tb.dram.store_queue.rd_data[13] top.core_dram_tb.dram.store_queue.rd_data[12] top.core_dram_tb.dram.store_queue.rd_data[11] top.core_dram_tb.dram.store_queue.rd_data[10] top.core_dram_tb.dram.store_queue.rd_data[9] top.core_dram_tb.dram.store_queue.rd_data[8] top.core_dram_tb.dram.store_queue.rd_data[7] top.core_dram_tb.dram.store_queue.rd_data[6] top.core_dram_tb.dram.store_queue.rd_data[5] top.core_dram_tb.dram.store_queue.rd_data[4] top.core_dram_tb.dram.store_queue.rd_data[3] top.core_dram_tb.dram.store_queue.rd_data[2] top.core_dram_tb.dram.store_queue.rd_data[1] top.core_dram_tb.dram.store_queue.rd_data[0] +@420 +top.core_dram_tb.dram.store_queue.rd_idx +top.core_dram_tb.dram.store_queue.rd_next +@28 +top.core_dram_tb.dram.store_queue.rd_ready +top.core_dram_tb.dram.store_queue.rd_valid +@22 +#{top.core_dram_tb.dram.store_queue.wr_data[79:0]} top.core_dram_tb.dram.store_queue.wr_data[79] top.core_dram_tb.dram.store_queue.wr_data[78] top.core_dram_tb.dram.store_queue.wr_data[77] top.core_dram_tb.dram.store_queue.wr_data[76] top.core_dram_tb.dram.store_queue.wr_data[75] top.core_dram_tb.dram.store_queue.wr_data[74] top.core_dram_tb.dram.store_queue.wr_data[73] top.core_dram_tb.dram.store_queue.wr_data[72] top.core_dram_tb.dram.store_queue.wr_data[71] top.core_dram_tb.dram.store_queue.wr_data[70] top.core_dram_tb.dram.store_queue.wr_data[69] top.core_dram_tb.dram.store_queue.wr_data[68] top.core_dram_tb.dram.store_queue.wr_data[67] top.core_dram_tb.dram.store_queue.wr_data[66] top.core_dram_tb.dram.store_queue.wr_data[65] top.core_dram_tb.dram.store_queue.wr_data[64] top.core_dram_tb.dram.store_queue.wr_data[63] top.core_dram_tb.dram.store_queue.wr_data[62] top.core_dram_tb.dram.store_queue.wr_data[61] top.core_dram_tb.dram.store_queue.wr_data[60] top.core_dram_tb.dram.store_queue.wr_data[59] top.core_dram_tb.dram.store_queue.wr_data[58] top.core_dram_tb.dram.store_queue.wr_data[57] top.core_dram_tb.dram.store_queue.wr_data[56] top.core_dram_tb.dram.store_queue.wr_data[55] top.core_dram_tb.dram.store_queue.wr_data[54] top.core_dram_tb.dram.store_queue.wr_data[53] top.core_dram_tb.dram.store_queue.wr_data[52] top.core_dram_tb.dram.store_queue.wr_data[51] top.core_dram_tb.dram.store_queue.wr_data[50] top.core_dram_tb.dram.store_queue.wr_data[49] top.core_dram_tb.dram.store_queue.wr_data[48] top.core_dram_tb.dram.store_queue.wr_data[47] top.core_dram_tb.dram.store_queue.wr_data[46] top.core_dram_tb.dram.store_queue.wr_data[45] top.core_dram_tb.dram.store_queue.wr_data[44] top.core_dram_tb.dram.store_queue.wr_data[43] top.core_dram_tb.dram.store_queue.wr_data[42] top.core_dram_tb.dram.store_queue.wr_data[41] top.core_dram_tb.dram.store_queue.wr_data[40] top.core_dram_tb.dram.store_queue.wr_data[39] top.core_dram_tb.dram.store_queue.wr_data[38] top.core_dram_tb.dram.store_queue.wr_data[37] top.core_dram_tb.dram.store_queue.wr_data[36] top.core_dram_tb.dram.store_queue.wr_data[35] top.core_dram_tb.dram.store_queue.wr_data[34] top.core_dram_tb.dram.store_queue.wr_data[33] top.core_dram_tb.dram.store_queue.wr_data[32] top.core_dram_tb.dram.store_queue.wr_data[31] top.core_dram_tb.dram.store_queue.wr_data[30] top.core_dram_tb.dram.store_queue.wr_data[29] top.core_dram_tb.dram.store_queue.wr_data[28] top.core_dram_tb.dram.store_queue.wr_data[27] top.core_dram_tb.dram.store_queue.wr_data[26] top.core_dram_tb.dram.store_queue.wr_data[25] top.core_dram_tb.dram.store_queue.wr_data[24] top.core_dram_tb.dram.store_queue.wr_data[23] top.core_dram_tb.dram.store_queue.wr_data[22] top.core_dram_tb.dram.store_queue.wr_data[21] top.core_dram_tb.dram.store_queue.wr_data[20] top.core_dram_tb.dram.store_queue.wr_data[19] top.core_dram_tb.dram.store_queue.wr_data[18] top.core_dram_tb.dram.store_queue.wr_data[17] top.core_dram_tb.dram.store_queue.wr_data[16] top.core_dram_tb.dram.store_queue.wr_data[15] top.core_dram_tb.dram.store_queue.wr_data[14] top.core_dram_tb.dram.store_queue.wr_data[13] top.core_dram_tb.dram.store_queue.wr_data[12] top.core_dram_tb.dram.store_queue.wr_data[11] top.core_dram_tb.dram.store_queue.wr_data[10] top.core_dram_tb.dram.store_queue.wr_data[9] top.core_dram_tb.dram.store_queue.wr_data[8] top.core_dram_tb.dram.store_queue.wr_data[7] top.core_dram_tb.dram.store_queue.wr_data[6] top.core_dram_tb.dram.store_queue.wr_data[5] top.core_dram_tb.dram.store_queue.wr_data[4] top.core_dram_tb.dram.store_queue.wr_data[3] top.core_dram_tb.dram.store_queue.wr_data[2] top.core_dram_tb.dram.store_queue.wr_data[1] top.core_dram_tb.dram.store_queue.wr_data[0] +@420 +top.core_dram_tb.dram.store_queue.wr_idx +top.core_dram_tb.dram.store_queue.wr_next +@28 +top.core_dram_tb.dram.store_queue.wr_ready +top.core_dram_tb.dram.store_queue.wr_valid +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/litedram/extras/wave.opt b/litedram/extras/wave.opt new file mode 100644 index 0000000..f147269 --- /dev/null +++ b/litedram/extras/wave.opt @@ -0,0 +1,84 @@ +$ version 1.1 + +# Signals in entities : +/core_dram_tb/dram/rst +/core_dram_tb/dram/system_clk +/core_dram_tb/dram/system_reset +/core_dram_tb/dram/wb_in +/core_dram_tb/dram/wb_out +/core_dram_tb/dram/user_port0_cmd_valid +/core_dram_tb/dram/user_port0_cmd_ready +/core_dram_tb/dram/user_port0_cmd_we +/core_dram_tb/dram/user_port0_cmd_addr +/core_dram_tb/dram/user_port0_wdata_valid +/core_dram_tb/dram/user_port0_wdata_ready +/core_dram_tb/dram/user_port0_wdata_we +/core_dram_tb/dram/user_port0_wdata_data +/core_dram_tb/dram/user_port0_rdata_valid +/core_dram_tb/dram/user_port0_rdata_ready +/core_dram_tb/dram/user_port0_rdata_data +/core_dram_tb/dram/cache_tags +/core_dram_tb/dram/cache_valids +/core_dram_tb/dram/storeq_rd_ready +/core_dram_tb/dram/storeq_rd_valid +/core_dram_tb/dram/storeq_rd_data +/core_dram_tb/dram/storeq_wr_ready +/core_dram_tb/dram/storeq_wr_valid +/core_dram_tb/dram/storeq_wr_data +/core_dram_tb/dram/accept_store +/core_dram_tb/dram/state +/core_dram_tb/dram/wb_req +/core_dram_tb/dram/store_queued +/core_dram_tb/dram/read_ack_0 +/core_dram_tb/dram/read_ack_1 +/core_dram_tb/dram/read_ad3_0 +/core_dram_tb/dram/read_ad3_1 +/core_dram_tb/dram/read_way_0 +/core_dram_tb/dram/read_way_1 +/core_dram_tb/dram/req_index +/core_dram_tb/dram/req_row +/core_dram_tb/dram/req_hit_way +/core_dram_tb/dram/req_tag +/core_dram_tb/dram/req_op +/core_dram_tb/dram/req_laddr +/core_dram_tb/dram/req_ad3 +/core_dram_tb/dram/req_we +/core_dram_tb/dram/req_wdata +/core_dram_tb/dram/store_way +/core_dram_tb/dram/store_index +/core_dram_tb/dram/store_row +/core_dram_tb/dram/cache_out +/core_dram_tb/dram/plru_victim +/core_dram_tb/dram/replace_way +/core_dram_tb/dram/rams/do_read +/core_dram_tb/dram/rams/do_write +/core_dram_tb/dram/rams/rd_addr +/core_dram_tb/dram/rams/wr_addr +/core_dram_tb/dram/rams/wr_data +/core_dram_tb/dram/rams/wr_sel +/core_dram_tb/dram/rams/wr_sel_m +/core_dram_tb/dram/rams/dout +/core_dram_tb/dram/rams/way/clk +/core_dram_tb/dram/rams/way/rd_en +/core_dram_tb/dram/rams/way/rd_addr +/core_dram_tb/dram/rams/way/rd_data +/core_dram_tb/dram/rams/way/wr_sel +/core_dram_tb/dram/rams/way/wr_addr +/core_dram_tb/dram/rams/way/wr_data +/core_dram_tb/dram/rams/way/rd_data0 +/core_dram_tb/dram/store_queue/wr_ready +/core_dram_tb/dram/store_queue/wr_valid +/core_dram_tb/dram/store_queue/wr_data +/core_dram_tb/dram/store_queue/rd_ready +/core_dram_tb/dram/store_queue/rd_valid +/core_dram_tb/dram/store_queue/rd_data +/core_dram_tb/dram/store_queue/rd_idx +/core_dram_tb/dram/store_queue/rd_next +/core_dram_tb/dram/store_queue/wr_idx +/core_dram_tb/dram/store_queue/wr_next +/core_dram_tb/dram/store_queue/op_prev +/core_dram_tb/dram/store_queue/op_next +/core_dram_tb/dram/store_queue/full +/core_dram_tb/dram/store_queue/empty +/core_dram_tb/dram/store_queue/push +/core_dram_tb/dram/store_queue/pop diff --git a/litedram/extras/wave_tb.gtkw b/litedram/extras/wave_tb.gtkw new file mode 100644 index 0000000..fcdf6a9 --- /dev/null +++ b/litedram/extras/wave_tb.gtkw @@ -0,0 +1,80 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Sun May 31 12:53:52 2020 +[*] +[dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw" +[dumpfile_mtime] "Sun May 31 12:50:15 2020" +[dumpfile_size] 1134118 +[savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave_tb.gtkw" +[timestart] 1312950000 +[size] 2509 1371 +[pos] -1 -1 +*-24.248457 1386890000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.dram_tb. +[sst_width] 301 +[signals_width] 433 +[sst_expanded] 1 +[sst_vpaned_height] 410 +@28 +top.dram_tb.reset_acks +@420 +top.dram_tb.acks +@28 +top.dram_tb.rst +top.dram_tb.clk +@22 +#{top.dram_tb.wb_in.dat[63:0]} top.dram_tb.wb_in.dat[63] top.dram_tb.wb_in.dat[62] top.dram_tb.wb_in.dat[61] top.dram_tb.wb_in.dat[60] top.dram_tb.wb_in.dat[59] top.dram_tb.wb_in.dat[58] top.dram_tb.wb_in.dat[57] top.dram_tb.wb_in.dat[56] top.dram_tb.wb_in.dat[55] top.dram_tb.wb_in.dat[54] top.dram_tb.wb_in.dat[53] top.dram_tb.wb_in.dat[52] top.dram_tb.wb_in.dat[51] top.dram_tb.wb_in.dat[50] top.dram_tb.wb_in.dat[49] top.dram_tb.wb_in.dat[48] top.dram_tb.wb_in.dat[47] top.dram_tb.wb_in.dat[46] top.dram_tb.wb_in.dat[45] top.dram_tb.wb_in.dat[44] top.dram_tb.wb_in.dat[43] top.dram_tb.wb_in.dat[42] top.dram_tb.wb_in.dat[41] top.dram_tb.wb_in.dat[40] top.dram_tb.wb_in.dat[39] top.dram_tb.wb_in.dat[38] top.dram_tb.wb_in.dat[37] top.dram_tb.wb_in.dat[36] top.dram_tb.wb_in.dat[35] top.dram_tb.wb_in.dat[34] top.dram_tb.wb_in.dat[33] top.dram_tb.wb_in.dat[32] top.dram_tb.wb_in.dat[31] top.dram_tb.wb_in.dat[30] top.dram_tb.wb_in.dat[29] top.dram_tb.wb_in.dat[28] top.dram_tb.wb_in.dat[27] top.dram_tb.wb_in.dat[26] top.dram_tb.wb_in.dat[25] top.dram_tb.wb_in.dat[24] top.dram_tb.wb_in.dat[23] top.dram_tb.wb_in.dat[22] top.dram_tb.wb_in.dat[21] top.dram_tb.wb_in.dat[20] top.dram_tb.wb_in.dat[19] top.dram_tb.wb_in.dat[18] top.dram_tb.wb_in.dat[17] top.dram_tb.wb_in.dat[16] top.dram_tb.wb_in.dat[15] top.dram_tb.wb_in.dat[14] top.dram_tb.wb_in.dat[13] top.dram_tb.wb_in.dat[12] top.dram_tb.wb_in.dat[11] top.dram_tb.wb_in.dat[10] top.dram_tb.wb_in.dat[9] top.dram_tb.wb_in.dat[8] top.dram_tb.wb_in.dat[7] top.dram_tb.wb_in.dat[6] top.dram_tb.wb_in.dat[5] top.dram_tb.wb_in.dat[4] top.dram_tb.wb_in.dat[3] top.dram_tb.wb_in.dat[2] top.dram_tb.wb_in.dat[1] top.dram_tb.wb_in.dat[0] +#{top.dram_tb.wb_in.adr[31:0]} top.dram_tb.wb_in.adr[31] top.dram_tb.wb_in.adr[30] top.dram_tb.wb_in.adr[29] top.dram_tb.wb_in.adr[28] top.dram_tb.wb_in.adr[27] top.dram_tb.wb_in.adr[26] top.dram_tb.wb_in.adr[25] top.dram_tb.wb_in.adr[24] top.dram_tb.wb_in.adr[23] top.dram_tb.wb_in.adr[22] top.dram_tb.wb_in.adr[21] top.dram_tb.wb_in.adr[20] top.dram_tb.wb_in.adr[19] top.dram_tb.wb_in.adr[18] top.dram_tb.wb_in.adr[17] top.dram_tb.wb_in.adr[16] top.dram_tb.wb_in.adr[15] top.dram_tb.wb_in.adr[14] top.dram_tb.wb_in.adr[13] top.dram_tb.wb_in.adr[12] top.dram_tb.wb_in.adr[11] top.dram_tb.wb_in.adr[10] top.dram_tb.wb_in.adr[9] top.dram_tb.wb_in.adr[8] top.dram_tb.wb_in.adr[7] top.dram_tb.wb_in.adr[6] top.dram_tb.wb_in.adr[5] top.dram_tb.wb_in.adr[4] top.dram_tb.wb_in.adr[3] top.dram_tb.wb_in.adr[2] top.dram_tb.wb_in.adr[1] top.dram_tb.wb_in.adr[0] +@23 +#{top.dram_tb.wb_in.sel[7:0]} top.dram_tb.wb_in.sel[7] top.dram_tb.wb_in.sel[6] top.dram_tb.wb_in.sel[5] top.dram_tb.wb_in.sel[4] top.dram_tb.wb_in.sel[3] top.dram_tb.wb_in.sel[2] top.dram_tb.wb_in.sel[1] top.dram_tb.wb_in.sel[0] +@28 +top.dram_tb.wb_in.cyc +top.dram_tb.wb_in.stb +top.dram_tb.wb_in.we +top.dram_tb.wb_out.ack +top.dram_tb.wb_out.stall +@22 +#{top.dram_tb.wb_out.dat[63:0]} top.dram_tb.wb_out.dat[63] top.dram_tb.wb_out.dat[62] top.dram_tb.wb_out.dat[61] top.dram_tb.wb_out.dat[60] top.dram_tb.wb_out.dat[59] top.dram_tb.wb_out.dat[58] top.dram_tb.wb_out.dat[57] top.dram_tb.wb_out.dat[56] top.dram_tb.wb_out.dat[55] top.dram_tb.wb_out.dat[54] top.dram_tb.wb_out.dat[53] top.dram_tb.wb_out.dat[52] top.dram_tb.wb_out.dat[51] top.dram_tb.wb_out.dat[50] top.dram_tb.wb_out.dat[49] top.dram_tb.wb_out.dat[48] top.dram_tb.wb_out.dat[47] top.dram_tb.wb_out.dat[46] top.dram_tb.wb_out.dat[45] top.dram_tb.wb_out.dat[44] top.dram_tb.wb_out.dat[43] top.dram_tb.wb_out.dat[42] top.dram_tb.wb_out.dat[41] top.dram_tb.wb_out.dat[40] top.dram_tb.wb_out.dat[39] top.dram_tb.wb_out.dat[38] top.dram_tb.wb_out.dat[37] top.dram_tb.wb_out.dat[36] top.dram_tb.wb_out.dat[35] top.dram_tb.wb_out.dat[34] top.dram_tb.wb_out.dat[33] top.dram_tb.wb_out.dat[32] top.dram_tb.wb_out.dat[31] top.dram_tb.wb_out.dat[30] top.dram_tb.wb_out.dat[29] top.dram_tb.wb_out.dat[28] top.dram_tb.wb_out.dat[27] top.dram_tb.wb_out.dat[26] top.dram_tb.wb_out.dat[25] top.dram_tb.wb_out.dat[24] top.dram_tb.wb_out.dat[23] top.dram_tb.wb_out.dat[22] top.dram_tb.wb_out.dat[21] top.dram_tb.wb_out.dat[20] top.dram_tb.wb_out.dat[19] top.dram_tb.wb_out.dat[18] top.dram_tb.wb_out.dat[17] top.dram_tb.wb_out.dat[16] top.dram_tb.wb_out.dat[15] top.dram_tb.wb_out.dat[14] top.dram_tb.wb_out.dat[13] top.dram_tb.wb_out.dat[12] top.dram_tb.wb_out.dat[11] top.dram_tb.wb_out.dat[10] top.dram_tb.wb_out.dat[9] top.dram_tb.wb_out.dat[8] top.dram_tb.wb_out.dat[7] top.dram_tb.wb_out.dat[6] top.dram_tb.wb_out.dat[5] top.dram_tb.wb_out.dat[4] top.dram_tb.wb_out.dat[3] top.dram_tb.wb_out.dat[2] top.dram_tb.wb_out.dat[1] top.dram_tb.wb_out.dat[0] +@28 +top.dram_tb.rd_valid +top.dram_tb.rd_ready +@22 +#{top.dram_tb.rd_data[63:0]} top.dram_tb.rd_data[63] top.dram_tb.rd_data[62] top.dram_tb.rd_data[61] top.dram_tb.rd_data[60] top.dram_tb.rd_data[59] top.dram_tb.rd_data[58] top.dram_tb.rd_data[57] top.dram_tb.rd_data[56] top.dram_tb.rd_data[55] top.dram_tb.rd_data[54] top.dram_tb.rd_data[53] top.dram_tb.rd_data[52] top.dram_tb.rd_data[51] top.dram_tb.rd_data[50] top.dram_tb.rd_data[49] top.dram_tb.rd_data[48] top.dram_tb.rd_data[47] top.dram_tb.rd_data[46] top.dram_tb.rd_data[45] top.dram_tb.rd_data[44] top.dram_tb.rd_data[43] top.dram_tb.rd_data[42] top.dram_tb.rd_data[41] top.dram_tb.rd_data[40] top.dram_tb.rd_data[39] top.dram_tb.rd_data[38] top.dram_tb.rd_data[37] top.dram_tb.rd_data[36] top.dram_tb.rd_data[35] top.dram_tb.rd_data[34] top.dram_tb.rd_data[33] top.dram_tb.rd_data[32] top.dram_tb.rd_data[31] top.dram_tb.rd_data[30] top.dram_tb.rd_data[29] top.dram_tb.rd_data[28] top.dram_tb.rd_data[27] top.dram_tb.rd_data[26] top.dram_tb.rd_data[25] top.dram_tb.rd_data[24] top.dram_tb.rd_data[23] top.dram_tb.rd_data[22] top.dram_tb.rd_data[21] top.dram_tb.rd_data[20] top.dram_tb.rd_data[19] top.dram_tb.rd_data[18] top.dram_tb.rd_data[17] top.dram_tb.rd_data[16] top.dram_tb.rd_data[15] top.dram_tb.rd_data[14] top.dram_tb.rd_data[13] top.dram_tb.rd_data[12] top.dram_tb.rd_data[11] top.dram_tb.rd_data[10] top.dram_tb.rd_data[9] top.dram_tb.rd_data[8] top.dram_tb.rd_data[7] top.dram_tb.rd_data[6] top.dram_tb.rd_data[5] top.dram_tb.rd_data[4] top.dram_tb.rd_data[3] top.dram_tb.rd_data[2] top.dram_tb.rd_data[1] top.dram_tb.rd_data[0] +@200 +- +- +-wrapper +@28 +top.dram_tb.dram.accept_store +@420 +top.dram_tb.dram.req_op +top.dram_tb.dram.state +@28 +top.dram_tb.dram.read_ack_1 +top.dram_tb.dram.read_ack_0 +top.dram_tb.dram.storeq_wr_valid +top.dram_tb.dram.storeq_wr_ready +top.dram_tb.dram.storeq_rd_valid +top.dram_tb.dram.storeq_rd_ready +top.dram_tb.dram.user_port0_rdata_ready +top.dram_tb.dram.user_port0_rdata_valid +top.dram_tb.dram.user_port0_wdata_ready +top.dram_tb.dram.user_port0_wdata_valid +top.dram_tb.dram.user_port0_cmd_we +top.dram_tb.dram.user_port0_cmd_ready +top.dram_tb.dram.user_port0_cmd_valid +top.dram_tb.dram.refill_cmd_valid +@420 +top.dram_tb.dram.req_index +top.dram_tb.dram.req_hit_way +@28 +top.dram_tb.dram.req_ad3 +@420 +top.dram_tb.dram.refill_row +top.dram_tb.dram.refill_index +top.dram_tb.dram.refill_way +@28 +top.dram_tb.dram.system_clk +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml index a4c982b..4472d56 100644 --- a/litedram/gen-src/arty.yml +++ b/litedram/gen-src/arty.yml @@ -3,8 +3,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"minimal", + "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"standard", "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type @@ -37,5 +37,6 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_base" : 0xc0100000, # For cpu=None only + "csr_alignment" : 32, + "csr_data_width" : 32, } diff --git a/litedram/gen-src/dram-init-mem.vhdl b/litedram/gen-src/dram-init-mem.vhdl index f83d732..13bd0ce 100644 --- a/litedram/gen-src/dram-init-mem.vhdl +++ b/litedram/gen-src/dram-init-mem.vhdl @@ -5,66 +5,117 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py index e44cd08..15cd846 100755 --- a/litedram/gen-src/generate.py +++ b/litedram/gen-src/generate.py @@ -22,7 +22,7 @@ def make_new_dir(base, added): return r gen_src_dir = os.path.dirname(os.path.realpath(__file__)) -base_dir = os.path.join(gen_src_dir, os.pardir) +base_dir = os.path.normpath(os.path.join(gen_src_dir, os.pardir)) build_top_dir = make_new_dir(base_dir, "build") gen_src_dir = os.path.join(base_dir, "gen-src") gen_dir = make_new_dir(base_dir, "generated") @@ -31,14 +31,14 @@ gen_dir = make_new_dir(base_dir, "generated") # # XXX Not working yet # -def build_init_code(build_dir): +def build_init_code(build_dir, is_sim): # More path fudging sw_dir = os.path.join(build_dir, "software"); sw_inc_dir = os.path.join(sw_dir, "include") gen_inc_dir = os.path.join(sw_inc_dir, "generated") src_dir = os.path.join(gen_src_dir, "sdram_init") - lxbios_src_dir = os.path.join(soc_directory, "software", "bios") + lxbios_src_dir = os.path.join(soc_directory, "software", "liblitedram") lxbios_inc_dir = os.path.join(soc_directory, "software", "include") print(" sw dir:", sw_dir) print("gen_inc_dir:", gen_inc_dir) @@ -62,6 +62,8 @@ def build_init_code(build_dir): add_var("GENINC_DIR", sw_inc_dir) add_var("LXSRC_DIR", lxbios_src_dir) add_var("LXINC_DIR", lxbios_inc_dir) + if is_sim: + add_var("EXTRA_CFLAGS", "-D__SIM__") write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars)) # Build init code @@ -72,10 +74,13 @@ def build_init_code(build_dir): return os.path.join(sw_dir, "obj", "sdram_init.hex") -def generate_one(t, mw_init): +def generate_one(t): print("Generating target:", t) + # Is it a simulation ? + is_sim = t is "sim" + # Muck with directory path build_dir = make_new_dir(build_top_dir, t) t_dir = make_new_dir(gen_dir, t) @@ -101,20 +106,17 @@ def generate_one(t, mw_init): if k == "sdram_phy": core_config[k] = getattr(litedram_phys, core_config[k]) - # Override values for mw_init - if mw_init: - core_config["cpu"] = None - core_config["csr_alignment"] = 64 - # Generate core - if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: + if is_sim: + platform = SimPlatform("", io=[]) + elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]: platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]: platform = XilinxPlatform("", io=[], toolchain="vivado") else: raise ValueError("Unsupported SDRAM PHY: {}".format(core_config["sdram_phy"])) - soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, csr_data_width=32) + soc = LiteDRAMCore(platform, core_config, is_sim = is_sim, integrated_rom_size=0x6000) # Build into build_dir builder = Builder(soc, output_dir=build_dir, compile_gateware=False) @@ -123,38 +125,27 @@ def generate_one(t, mw_init): # Grab generated gatewar dir gw_dir = os.path.join(build_dir, "gateware") - # Generate init-cpu.txt if any and generate init code if none - cpu = core_config["cpu"] - if mw_init: - src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl") - src_init_file = build_init_code(build_dir) - src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl") - else: - write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu) - src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl") - src_init_file = os.path.join(gw_dir, "mem.init") - src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl") + # Generate init code + src_init_file = build_init_code(build_dir, is_sim) + src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl") # Copy generated files to target dir, amend them if necessary + initfile_name = "litedram_core.init" core_file = os.path.join(gw_dir, "litedram_core.v") - dst_init_file = os.path.join(t_dir, "litedram_core.init") - dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl") + dst_init_file = os.path.join(t_dir, initfile_name) dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl") - replace_in_file(core_file, "mem.init", "litedram_core.init") - shutil.copy(core_file, t_dir) shutil.copyfile(src_init_file, dst_init_file) - shutil.copyfile(src_wrap_file, dst_wrap_file) shutil.copyfile(src_initram_file, dst_initram_file) + if is_sim: + initfile_path = os.path.join("litedram", "generated", "sim", initfile_name) + replace_in_file(dst_initram_file, initfile_name, initfile_path) + shutil.copy(core_file, t_dir) def main(): - targets = ['arty','nexys-video'] - - # XXX Set mw_init to False to use a local VexRiscV for memory inits + targets = ['arty','nexys-video', 'sim'] for t in targets: - generate_one(t, mw_init = True) - - # XXX TODO: Remove build dir unless told not to via cmdline option + generate_one(t) if __name__ == "__main__": main() diff --git a/litedram/gen-src/nexys-video.yml b/litedram/gen-src/nexys-video.yml index 23c1ce4..287f2f2 100644 --- a/litedram/gen-src/nexys-video.yml +++ b/litedram/gen-src/nexys-video.yml @@ -3,8 +3,8 @@ { # General ------------------------------------------------------------------ - "cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32) - "cpu_variant":"minimal", + "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"standard", "speedgrade": -1, # FPGA speedgrade "memtype": "DDR3", # DRAM type @@ -37,5 +37,6 @@ }, # CSR Port ----------------------------------------------------------------- - "csr_base" : 0xc0100000, # For cpu=None only + "csr_alignment" : 32, + "csr_data_width" : 32, } diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile index 420072e..71ca921 100644 --- a/litedram/gen-src/sdram_init/Makefile +++ b/litedram/gen-src/sdram_init/Makefile @@ -21,7 +21,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy #### Flags -CPPFLAGS = -nostdinc -D__USE_LIBC +CPPFLAGS = -nostdinc -D__USE_LIBC $(EXTRA_CFLAGS) CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include) CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h index ded9b10..6d4068c 100644 --- a/litedram/gen-src/sdram_init/include/system.h +++ b/litedram/gen-src/sdram_init/include/system.h @@ -8,6 +8,13 @@ #define CSR_BASE DRAM_CTRL_BASE #define CONFIG_CPU_NOP "nop" +#ifdef __SIM__ +#define MEMTEST_BUS_SIZE 512//16 +#define MEMTEST_DATA_SIZE 1024//16 +#define MEMTEST_ADDR_SIZE 128//16 +#define CONFIG_SIM_DISABLE_DELAYS +#endif + extern void flush_cpu_dcache(void); extern void flush_cpu_icache(void); static inline void flush_l2_cache(void) { } diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c index fd43970..68eda15 100644 --- a/litedram/gen-src/sdram_init/main.c +++ b/litedram/gen-src/sdram_init/main.c @@ -54,12 +54,18 @@ void main(void) printf("UART "); if (ftr & SYS_REG_INFO_HAS_DRAM) printf("DRAM "); + if (ftr & SYS_REG_INFO_HAS_BRAM) + printf("BRAM "); printf("\n"); - val = readq(SYSCON_BASE + SYS_REG_BRAMINFO); - printf(" BRAM: %lld KB\n", val / 1024); + if (ftr & SYS_REG_INFO_HAS_BRAM) { + val = readq(SYSCON_BASE + SYS_REG_BRAMINFO); + printf(" BRAM: %lld KB\n", val / 1024); + } if (ftr & SYS_REG_INFO_HAS_DRAM) { val = readq(SYSCON_BASE + SYS_REG_DRAMINFO); printf(" DRAM: %lld MB\n", val / (1024 * 1024)); + val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO); + printf(" DRAM INIT: %lld KB\n", val / 1024); } val = readq(SYSCON_BASE + SYS_REG_CLKINFO); printf(" CLK: %lld MHz\n", val / 1000000); @@ -70,5 +76,15 @@ void main(void) MIGEN_GIT_SHA1, LITEX_GIT_SHA1); sdrinit(); } - printf("Booting from BRAM...\n"); + if (ftr & SYS_REG_INFO_HAS_BRAM) + printf("Booting from BRAM...\n"); + else { + void *s = (void *)(DRAM_INIT_BASE + 0x4000); + void *d = (void *)DRAM_BASE; + int sz = (0x10000 - 0x4000); + printf("Copying payload to DRAM...\n"); + memcpy(d, s, sz); + printf("Booting from DRAM...\n"); + flush_cpu_icache(); + } } diff --git a/litedram/gen-src/sim.yml b/litedram/gen-src/sim.yml new file mode 100644 index 0000000..0160000 --- /dev/null +++ b/litedram/gen-src/sim.yml @@ -0,0 +1,43 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + +{ + # General ------------------------------------------------------------------ + "cpu": "None", # Type of CPU used for init/calib (vexriscv, lm32) + "cpu_variant":"standard", + "speedgrade": -1, # FPGA speedgrade + "memtype": "DDR3", # DRAM type + "sim" : "True", + + # PHY ---------------------------------------------------------------------- + "cmd_delay": 0, # Command additional delay (in taps) + "cmd_latency": 0, # Command additional latency + "sdram_module": "MT41K128M16", # SDRAM modules of the board or SO-DIMM + "sdram_module_nb": 2, # Number of byte groups + "sdram_rank_nb": 1, # Number of ranks + "sdram_phy": "A7DDRPHY", # Type of FPGA PHY + + # Electrical --------------------------------------------------------------- + "rtt_nom": "60ohm", # Nominal termination + "rtt_wr": "60ohm", # Write termination + "ron": "34ohm", # Output driver impedance + + # Frequency ---------------------------------------------------------------- + "input_clk_freq": 100e6, # Input clock frequency + "sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk) + "iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency + + # Core --------------------------------------------------------------------- + "cmd_buffer_depth": 16, # Depth of the command buffer + + # User Ports --------------------------------------------------------------- + "user_ports": { + "native_0": { + "type": "native", + }, + }, + + # CSR Port ----------------------------------------------------------------- + "csr_alignment" : 32, + "csr_data_width" : 32, +} diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl deleted file mode 100644 index f12e3df..0000000 --- a/litedram/gen-src/wrapper-mw-init.vhdl +++ /dev/null @@ -1,284 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; - -library work; -use work.wishbone_types.all; - -entity litedram_wrapper is - generic ( - DRAM_ABITS : positive; - DRAM_ALINES : positive - ); - port( - -- LiteDRAM generates the system clock and reset - -- from the input clkin - clk_in : in std_ulogic; - rst : in std_ulogic; - system_clk : out std_ulogic; - system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; - pll_locked : out std_ulogic; - - -- Wishbone ports: - wb_in : in wishbone_master_out; - wb_out : out wishbone_slave_out; - wb_ctrl_in : in wb_io_master_out; - wb_ctrl_out : out wb_io_slave_out; - wb_ctrl_is_csr : in std_ulogic; - wb_ctrl_is_init : in std_ulogic; - - -- Init core serial debug - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - - -- Misc - init_done : out std_ulogic; - init_error : out std_ulogic; - - -- DRAM wires - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic - ); -end entity litedram_wrapper; - -architecture behaviour of litedram_wrapper is - - component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - wb_ctrl_adr : in std_ulogic_vector(29 downto 0); - wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); - wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); - wb_ctrl_sel : in std_ulogic_vector(3 downto 0); - wb_ctrl_cyc : in std_ulogic; - wb_ctrl_stb : in std_ulogic; - wb_ctrl_ack : out std_ulogic; - wb_ctrl_we : in std_ulogic; - wb_ctrl_cti : in std_ulogic_vector(2 downto 0); - wb_ctrl_bte : in std_ulogic_vector(1 downto 0); - wb_ctrl_err : out std_ulogic; - user_port_native_0_cmd_valid : in std_ulogic; - user_port_native_0_cmd_ready : out std_ulogic; - user_port_native_0_cmd_we : in std_ulogic; - user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port_native_0_wdata_valid : in std_ulogic; - user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port_native_0_rdata_valid : out std_ulogic; - user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) - ); - end component; - - signal user_port0_cmd_valid : std_ulogic; - signal user_port0_cmd_ready : std_ulogic; - signal user_port0_cmd_we : std_ulogic; - signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); - signal user_port0_wdata_valid : std_ulogic; - signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); - signal user_port0_rdata_valid : std_ulogic; - signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); - - signal ad3 : std_ulogic; - - signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); - signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); - signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); - signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); - signal wb_ctrl_cyc : std_ulogic; - signal wb_ctrl_stb : std_ulogic; - signal wb_ctrl_ack : std_ulogic; - signal wb_ctrl_we : std_ulogic; - - signal wb_init_in : wb_io_master_out; - signal wb_init_out : wb_io_slave_out; - - type state_t is (CMD, MWRITE, MREAD); - signal state : state_t; - -begin - - -- alternate core reset address set when DRAM is not initialized. - core_alt_reset <= not init_done; - - -- Init code BRAM memory slave - init_ram_0: entity work.dram_init_mem - port map( - clk => system_clk, - wb_in => wb_init_in, - wb_out => wb_init_out - ); - - -- - -- Control bus wishbone: This muxes the wishbone to the CSRs - -- and an internal small one to the init BRAM - -- - - -- Init DRAM wishbone IN signals - wb_init_in.adr <= wb_ctrl_in.adr; - wb_init_in.dat <= wb_ctrl_in.dat; - wb_init_in.sel <= wb_ctrl_in.sel; - wb_init_in.we <= wb_ctrl_in.we; - wb_init_in.stb <= wb_ctrl_in.stb; - wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init; - - -- DRAM CSR IN signals - wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); - wb_ctrl_dat_w <= wb_ctrl_in.dat; - wb_ctrl_sel <= wb_ctrl_in.sel; - wb_ctrl_we <= wb_ctrl_in.we; - wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; - wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; - - -- Ctrl bus wishbone OUT signals - wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1' - else wb_init_out.ack; - wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1' - else wb_init_out.dat; - wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else - '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack; - - -- - -- Data bus wishbone to LiteDRAM native port - -- - -- Address bit 3 selects the top or bottom half of the data - -- bus (64-bit wishbone vs. 128-bit DRAM interface) - -- - -- XXX TODO: Figure out how to pipeline this - -- - ad3 <= wb_in.adr(3); - - -- Wishbone port IN signals - user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0'; - user_port0_cmd_we <= wb_in.we when state = CMD else '0'; - user_port0_wdata_valid <= '1' when state = MWRITE else '0'; - user_port0_rdata_ready <= '1' when state = MREAD else '0'; - user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); - user_port0_wdata_data <= wb_in.dat & wb_in.dat; - user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else - "00000000" & wb_in.sel; - - -- Wishbone OUT signals - wb_out.ack <= user_port0_wdata_ready when state = MWRITE else - user_port0_rdata_valid when state = MREAD else '0'; - - wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else - user_port0_rdata_data(63 downto 0); - - -- We don't do pipelining yet. - wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - - -- DRAM user port State machine - sm: process(system_clk) - begin - - if rising_edge(system_clk) then - if system_reset = '1' then - state <= CMD; - else - case state is - when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then - state <= MWRITE when wb_in.we = '1' else MREAD; - end if; - when MWRITE => - if user_port0_wdata_ready = '1' then - state <= CMD; - end if; - when MREAD => - if user_port0_rdata_valid = '1' then - state <= CMD; - end if; - end case; - end if; - end if; - end process; - - litedram: litedram_core - port map( - clk => clk_in, - rst => rst, - pll_locked => pll_locked, - ddram_a => ddram_a, - ddram_ba => ddram_ba, - ddram_ras_n => ddram_ras_n, - ddram_cas_n => ddram_cas_n, - ddram_we_n => ddram_we_n, - ddram_cs_n => ddram_cs_n, - ddram_dm => ddram_dm, - ddram_dq => ddram_dq, - ddram_dqs_p => ddram_dqs_p, - ddram_dqs_n => ddram_dqs_n, - ddram_clk_p => ddram_clk_p, - ddram_clk_n => ddram_clk_n, - ddram_cke => ddram_cke, - ddram_odt => ddram_odt, - ddram_reset_n => ddram_reset_n, - init_done => init_done, - init_error => init_error, - user_clk => system_clk, - user_rst => system_reset, - wb_ctrl_adr => wb_ctrl_adr, - wb_ctrl_dat_w => wb_ctrl_dat_w, - wb_ctrl_dat_r => wb_ctrl_dat_r, - wb_ctrl_sel => wb_ctrl_sel, - wb_ctrl_cyc => wb_ctrl_cyc, - wb_ctrl_stb => wb_ctrl_stb, - wb_ctrl_ack => wb_ctrl_ack, - wb_ctrl_we => wb_ctrl_we, - wb_ctrl_cti => "000", - wb_ctrl_bte => "00", - wb_ctrl_err => open, - user_port_native_0_cmd_valid => user_port0_cmd_valid, - user_port_native_0_cmd_ready => user_port0_cmd_ready, - user_port_native_0_cmd_we => user_port0_cmd_we, - user_port_native_0_cmd_addr => user_port0_cmd_addr, - user_port_native_0_wdata_valid => user_port0_wdata_valid, - user_port_native_0_wdata_ready => user_port0_wdata_ready, - user_port_native_0_wdata_we => user_port0_wdata_we, - user_port_native_0_wdata_data => user_port0_wdata_data, - user_port_native_0_rdata_valid => user_port0_rdata_valid, - user_port_native_0_rdata_ready => user_port0_rdata_ready, - user_port_native_0_rdata_data => user_port0_rdata_data - ); - -end architecture behaviour; diff --git a/litedram/gen-src/wrapper-self-init.vhdl b/litedram/gen-src/wrapper-self-init.vhdl deleted file mode 100644 index d57c99b..0000000 --- a/litedram/gen-src/wrapper-self-init.vhdl +++ /dev/null @@ -1,225 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; - -library work; -use work.wishbone_types.all; - -entity litedram_wrapper is - generic ( - DRAM_ABITS : positive; - DRAM_ALINES : positive - ); - port( - -- LiteDRAM generates the system clock and reset - -- from the input clkin - clk_in : in std_ulogic; - rst : in std_ulogic; - system_clk : out std_ulogic; - system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; - pll_locked : out std_ulogic; - - -- Wishbone ports: - wb_in : in wishbone_master_out; - wb_out : out wishbone_slave_out; - wb_ctrl_in : in wb_io_master_out; - wb_ctrl_out : out wb_io_slave_out; - wb_ctrl_is_csr : in std_ulogic; - wb_ctrl_is_init : in std_ulogic; - - -- Init core serial debug - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - - -- Misc - init_done : out std_ulogic; - init_error : out std_ulogic; - - -- DRAM wires - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic -end entity litedram_wrapper; - -architecture behaviour of litedram_wrapper is - - component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - user_port_native_0_cmd_valid : in std_ulogic; - user_port_native_0_cmd_ready : out std_ulogic; - user_port_native_0_cmd_we : in std_ulogic; - user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port_native_0_wdata_valid : in std_ulogic; - user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port_native_0_rdata_valid : out std_ulogic; - user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) - ); - end component; - - signal user_port0_cmd_valid : std_ulogic; - signal user_port0_cmd_ready : std_ulogic; - signal user_port0_cmd_we : std_ulogic; - signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); - signal user_port0_wdata_valid : std_ulogic; - signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); - signal user_port0_rdata_valid : std_ulogic; - signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); - - signal ad3 : std_ulogic; - - signal dram_user_reset : std_ulogic; - - type state_t is (CMD, MWRITE, MREAD); - signal state : state_t; - -begin - - -- Reset, lift it when init done, no alt core reset - system_reset <= dram_user_reset or not init_done; - core_alt_reset <= '0'; - - -- Control bus is unused - wb_ctrl_out.ack <= (wb_is_ctrl = '1' or wb_is_init = '1') and wb_ctrl_in.cyc; - else wb_init_out.ack; - wb_ctrl_out.dat <= (others => '0'); - wb_ctrl_out.stall <= '0'; - - -- - -- Data bus wishbone to LiteDRAM native port - -- - -- Address bit 3 selects the top or bottom half of the data - -- bus (64-bit wishbone vs. 128-bit DRAM interface) - -- - -- XXX TODO: Figure out how to pipeline this - -- - ad3 <= wb_in.adr(3); - - -- Wishbone port IN signals - user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0'; - user_port0_cmd_we <= wb_in.we when state = CMD else '0'; - user_port0_wdata_valid <= '1' when state = MWRITE else '0'; - user_port0_rdata_ready <= '1' when state = MREAD else '0'; - user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); - user_port0_wdata_data <= wb_in.dat & wb_in.dat; - user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else - "00000000" & wb_in.sel; - - -- Wishbone OUT signals - wb_out.ack <= user_port0_wdata_ready when state = MWRITE else - user_port0_rdata_valid when state = MREAD else '0'; - - wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else - user_port0_rdata_data(63 downto 0); - - -- We don't do pipelining yet. - wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - - -- DRAM user port State machine - sm: process(system_clk) - begin - - if rising_edge(system_clk) then - if dram_user_reset = '1' then - state <= CMD; - else - case state is - when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then - state <= MWRITE when wb_in.we = '1' else MREAD; - end if; - when MWRITE => - if user_port0_wdata_ready = '1' then - state <= CMD; - end if; - when MREAD => - if user_port0_rdata_valid = '1' then - state <= CMD; - end if; - end case; - end if; - end if; - end process; - - litedram: litedram_core - port map( - clk => clk_in, - rst => rst, - serial_tx => serial_tx, - serial_rx => serial_rx, - pll_locked => pll_locked, - ddram_a => ddram_a, - ddram_ba => ddram_ba, - ddram_ras_n => ddram_ras_n, - ddram_cas_n => ddram_cas_n, - ddram_we_n => ddram_we_n, - ddram_cs_n => ddram_cs_n, - ddram_dm => ddram_dm, - ddram_dq => ddram_dq, - ddram_dqs_p => ddram_dqs_p, - ddram_dqs_n => ddram_dqs_n, - ddram_clk_p => ddram_clk_p, - ddram_clk_n => ddram_clk_n, - ddram_cke => ddram_cke, - ddram_odt => ddram_odt, - ddram_reset_n => ddram_reset_n, - init_done => init_done, - init_error => init_error, - user_clk => system_clk, - user_rst => dram_user_reset, - user_port_native_0_cmd_valid => user_port0_cmd_valid, - user_port_native_0_cmd_ready => user_port0_cmd_ready, - user_port_native_0_cmd_we => user_port0_cmd_we, - user_port_native_0_cmd_addr => user_port0_cmd_addr, - user_port_native_0_wdata_valid => user_port0_wdata_valid, - user_port_native_0_wdata_ready => user_port0_wdata_ready, - user_port_native_0_wdata_we => user_port0_wdata_we, - user_port_native_0_wdata_data => user_port0_wdata_data, - user_port_native_0_rdata_valid => user_port0_rdata_valid, - user_port_native_0_rdata_ready => user_port0_rdata_ready, - user_port_native_0_rdata_data => user_port0_rdata_data - ); - -end architecture behaviour; diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl index f83d732..13bd0ce 100644 --- a/litedram/generated/arty/litedram-initmem.vhdl +++ b/litedram/generated/arty/litedram-initmem.vhdl @@ -5,66 +5,117 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl deleted file mode 100644 index f12e3df..0000000 --- a/litedram/generated/arty/litedram-wrapper.vhdl +++ /dev/null @@ -1,284 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; - -library work; -use work.wishbone_types.all; - -entity litedram_wrapper is - generic ( - DRAM_ABITS : positive; - DRAM_ALINES : positive - ); - port( - -- LiteDRAM generates the system clock and reset - -- from the input clkin - clk_in : in std_ulogic; - rst : in std_ulogic; - system_clk : out std_ulogic; - system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; - pll_locked : out std_ulogic; - - -- Wishbone ports: - wb_in : in wishbone_master_out; - wb_out : out wishbone_slave_out; - wb_ctrl_in : in wb_io_master_out; - wb_ctrl_out : out wb_io_slave_out; - wb_ctrl_is_csr : in std_ulogic; - wb_ctrl_is_init : in std_ulogic; - - -- Init core serial debug - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - - -- Misc - init_done : out std_ulogic; - init_error : out std_ulogic; - - -- DRAM wires - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic - ); -end entity litedram_wrapper; - -architecture behaviour of litedram_wrapper is - - component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - wb_ctrl_adr : in std_ulogic_vector(29 downto 0); - wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); - wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); - wb_ctrl_sel : in std_ulogic_vector(3 downto 0); - wb_ctrl_cyc : in std_ulogic; - wb_ctrl_stb : in std_ulogic; - wb_ctrl_ack : out std_ulogic; - wb_ctrl_we : in std_ulogic; - wb_ctrl_cti : in std_ulogic_vector(2 downto 0); - wb_ctrl_bte : in std_ulogic_vector(1 downto 0); - wb_ctrl_err : out std_ulogic; - user_port_native_0_cmd_valid : in std_ulogic; - user_port_native_0_cmd_ready : out std_ulogic; - user_port_native_0_cmd_we : in std_ulogic; - user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port_native_0_wdata_valid : in std_ulogic; - user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port_native_0_rdata_valid : out std_ulogic; - user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) - ); - end component; - - signal user_port0_cmd_valid : std_ulogic; - signal user_port0_cmd_ready : std_ulogic; - signal user_port0_cmd_we : std_ulogic; - signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); - signal user_port0_wdata_valid : std_ulogic; - signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); - signal user_port0_rdata_valid : std_ulogic; - signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); - - signal ad3 : std_ulogic; - - signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); - signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); - signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); - signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); - signal wb_ctrl_cyc : std_ulogic; - signal wb_ctrl_stb : std_ulogic; - signal wb_ctrl_ack : std_ulogic; - signal wb_ctrl_we : std_ulogic; - - signal wb_init_in : wb_io_master_out; - signal wb_init_out : wb_io_slave_out; - - type state_t is (CMD, MWRITE, MREAD); - signal state : state_t; - -begin - - -- alternate core reset address set when DRAM is not initialized. - core_alt_reset <= not init_done; - - -- Init code BRAM memory slave - init_ram_0: entity work.dram_init_mem - port map( - clk => system_clk, - wb_in => wb_init_in, - wb_out => wb_init_out - ); - - -- - -- Control bus wishbone: This muxes the wishbone to the CSRs - -- and an internal small one to the init BRAM - -- - - -- Init DRAM wishbone IN signals - wb_init_in.adr <= wb_ctrl_in.adr; - wb_init_in.dat <= wb_ctrl_in.dat; - wb_init_in.sel <= wb_ctrl_in.sel; - wb_init_in.we <= wb_ctrl_in.we; - wb_init_in.stb <= wb_ctrl_in.stb; - wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init; - - -- DRAM CSR IN signals - wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); - wb_ctrl_dat_w <= wb_ctrl_in.dat; - wb_ctrl_sel <= wb_ctrl_in.sel; - wb_ctrl_we <= wb_ctrl_in.we; - wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; - wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; - - -- Ctrl bus wishbone OUT signals - wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1' - else wb_init_out.ack; - wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1' - else wb_init_out.dat; - wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else - '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack; - - -- - -- Data bus wishbone to LiteDRAM native port - -- - -- Address bit 3 selects the top or bottom half of the data - -- bus (64-bit wishbone vs. 128-bit DRAM interface) - -- - -- XXX TODO: Figure out how to pipeline this - -- - ad3 <= wb_in.adr(3); - - -- Wishbone port IN signals - user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0'; - user_port0_cmd_we <= wb_in.we when state = CMD else '0'; - user_port0_wdata_valid <= '1' when state = MWRITE else '0'; - user_port0_rdata_ready <= '1' when state = MREAD else '0'; - user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); - user_port0_wdata_data <= wb_in.dat & wb_in.dat; - user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else - "00000000" & wb_in.sel; - - -- Wishbone OUT signals - wb_out.ack <= user_port0_wdata_ready when state = MWRITE else - user_port0_rdata_valid when state = MREAD else '0'; - - wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else - user_port0_rdata_data(63 downto 0); - - -- We don't do pipelining yet. - wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - - -- DRAM user port State machine - sm: process(system_clk) - begin - - if rising_edge(system_clk) then - if system_reset = '1' then - state <= CMD; - else - case state is - when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then - state <= MWRITE when wb_in.we = '1' else MREAD; - end if; - when MWRITE => - if user_port0_wdata_ready = '1' then - state <= CMD; - end if; - when MREAD => - if user_port0_rdata_valid = '1' then - state <= CMD; - end if; - end case; - end if; - end if; - end process; - - litedram: litedram_core - port map( - clk => clk_in, - rst => rst, - pll_locked => pll_locked, - ddram_a => ddram_a, - ddram_ba => ddram_ba, - ddram_ras_n => ddram_ras_n, - ddram_cas_n => ddram_cas_n, - ddram_we_n => ddram_we_n, - ddram_cs_n => ddram_cs_n, - ddram_dm => ddram_dm, - ddram_dq => ddram_dq, - ddram_dqs_p => ddram_dqs_p, - ddram_dqs_n => ddram_dqs_n, - ddram_clk_p => ddram_clk_p, - ddram_clk_n => ddram_clk_n, - ddram_cke => ddram_cke, - ddram_odt => ddram_odt, - ddram_reset_n => ddram_reset_n, - init_done => init_done, - init_error => init_error, - user_clk => system_clk, - user_rst => system_reset, - wb_ctrl_adr => wb_ctrl_adr, - wb_ctrl_dat_w => wb_ctrl_dat_w, - wb_ctrl_dat_r => wb_ctrl_dat_r, - wb_ctrl_sel => wb_ctrl_sel, - wb_ctrl_cyc => wb_ctrl_cyc, - wb_ctrl_stb => wb_ctrl_stb, - wb_ctrl_ack => wb_ctrl_ack, - wb_ctrl_we => wb_ctrl_we, - wb_ctrl_cti => "000", - wb_ctrl_bte => "00", - wb_ctrl_err => open, - user_port_native_0_cmd_valid => user_port0_cmd_valid, - user_port_native_0_cmd_ready => user_port0_cmd_ready, - user_port_native_0_cmd_we => user_port0_cmd_we, - user_port_native_0_cmd_addr => user_port0_cmd_addr, - user_port_native_0_wdata_valid => user_port0_wdata_valid, - user_port_native_0_wdata_ready => user_port0_wdata_ready, - user_port_native_0_wdata_we => user_port0_wdata_we, - user_port_native_0_wdata_data => user_port0_wdata_data, - user_port_native_0_rdata_valid => user_port0_rdata_valid, - user_port_native_0_rdata_ready => user_port0_rdata_ready, - user_port_native_0_rdata_data => user_port0_rdata_data - ); - -end architecture behaviour; diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init index 22485ac..d20e710 100644 --- a/litedram/generated/arty/litedram_core.init +++ b/litedram/generated/arty/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421f000782107c6 3d80000060213f00 798c07c6618c0000 -618c108c658cf000 +618c10a4658cf000 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +3842a1003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,66 +519,88 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800161df94101c8 +48001735f94101c8 7c7e1b7860000000 -480011a17fe3fb78 +4800124d7fe3fb78 3821017060000000 -48001bdc7fc3f378 +48001cf47fc3f378 0100000000000000 4e80002000000280 0000000000000000 +7c0007ac00000000 +4e8000204c00012c +0000000000000000 3c4c000100000000 -7c0802a638429e74 -7d908026fbe1fff8 -f801001091810008 -480010adf821ff91 +7c0802a63842a05c +7d800026fbe1fff8 +91810008f8010010 +48001141f821ff91 3c62ffff60000000 -4bffff4d38637d60 +4bffff3538637c78 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637d80 -3c62ffff4bffff29 -38637da07bff0020 -7c0004ac4bffff19 +63ff000838637c98 +3c62ffff4bffff11 +38637cb87bff0020 +7c0004ac4bffff01 73e900017fe0feea 3c62ffff41820010 -4bfffefd38637db8 -4e00000073e90002 +4bfffee538637cd0 +4d80000073e90002 3c62ffff41820010 -4bfffee538637dc0 -3bff7fa83fe2ffff -4bfffed57fe3fb78 -608400103c80c000 -7c0004ac78840020 -3c62ffff7c8026ea -38637dc87884b282 -419200284bfffeb1 -608400183c80c000 +4bfffecd38637cd8 +4e00000073e90004 +3c62ffff41820010 +4bfffeb538637ce0 +3bff7f203fe2ffff +4bfffea57fe3fb78 +3c80c00041920028 +7884002060840010 +7c8026ea7c0004ac +7884b2823c62ffff +4bfffe7d38637ce8 +3c80c000418e004c +7884002060840018 +7c8026ea7c0004ac +788465023c62ffff +4bfffe5538637d08 +608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637de878846502 -3d20c0004bfffe89 +38637d287884b282 +3d20c0004bfffe31 7929002061290020 7d204eea7c0004ac 3c62ffff3c80000f -38637e0860844240 -4bfffe5d7c892392 -4bfffe557fe3fb78 -3ca2ffff41920028 +38637d4860844240 +4bfffe057c892392 +4bfffdfd7fe3fb78 +3ca2ffff418e0028 3c62ffff3c82ffff -38847e3838a57e28 -4bfffe3538637e40 -6000000048000dd5 -38637e703c62ffff -382100704bfffe21 -7d90812081810008 -0000000048001a54 +38847d7838a57d68 +4bfffddd38637d80 +6000000048000e29 +3c62ffff41920020 +4bfffdc538637db0 +8181000838210070 +48001b107d818120 +38637dc83c62ffff +3c80f0004bfffda9 +6084400038a0ffff +7884002054a50422 +480011e53c604000 +3c62ffff60000000 +4bfffd7d38637de8 +e801001038210070 +ebe1fff881810008 +7d8181207c0803a6 +000000004bfffde4 0000018003000000 -612908083d20c010 +612908043d20c010 7c0004ac79290020 3d40c0107c604f2a -614a081039200001 +614a080839200001 7c0004ac794a0020 4e8000207d20572a 0000000000000000 @@ -588,29 +610,29 @@ f801001091810008 4e8000204200fffc 0000000000000000 3d20c01000000000 -6129002839400001 +6129001439400001 792900207d431830 7c604f2a7c0004ac -610800303d00c010 +610800183d00c010 7c0004ac79080020 394000007d40472a 7d404f2a7c0004ac 000000004e800020 0000000000000000 394000013d20c010 -7d43183061290028 +7d43183061290014 7c0004ac79290020 3d00c0107c604f2a -7908002061080038 +790800206108001c 7d40472a7c0004ac 7c0004ac39400000 4e8000207d404f2a 0000000000000000 3d40c01000000000 -614a086839200025 +614a083439200025 7c0004ac794a0020 3d40c0107d20572a -614a087039200001 +614a083839200001 7c0004ac794a0020 4e8000207d20572a 0000000000000000 @@ -631,11 +653,11 @@ f801001091810008 9864000099240001 000000004e800020 0000000000000000 -38429b383c4c0001 -480017ed7c0802a6 +38429c883c4c0001 +480018557c0802a6 7c7e1b78f821ff21 -38637f403c62ffff -600000004bfffc21 +38637eb83c62ffff +600000004bfffb71 390100603ca08020 3940000460a50003 7d1d43783920002a @@ -648,45 +670,45 @@ f801001091810008 394affff4200ffe0 794a002139080004 3d20c0104082ffc4 -612908183be00000 +6129080c3be00000 7c0004ac79290020 3d20c0107fe04f2a -7929002061290820 +7929002061290810 7fe04f2a7c0004ac 4bfffd8d38600009 4bfffdc13860000f 7fa4eb783c60c010 -7863002060630828 +7863002060630814 3c60c0104bfffead -6063085838810064 +6063082c38810064 4bfffe9978630020 388100683c60c010 -7863002060630888 +7863002060630844 3c60c0104bfffe85 -606308b83881006c +6063085c3881006c 4bfffe7178630020 -612908a83d20c010 +612908543d20c010 7c0004ac79290020 3d20c0107fe04f2a -79290020612908b0 +7929002061290858 7fe04f2a7c0004ac 392000173d40c010 -794a0020614a0898 +794a0020614a084c 7d20572a7c0004ac 392000013d40c010 -794a0020614a08a0 +794a0020614a0850 7d20572a7c0004ac -612908783d20c010 +6129083c3d20c010 7c0004ac79290020 3d20c0107fe04f2a -7929002061290880 +7929002061290840 7fe04f2a7c0004ac 22de00017fc3f378 213e00034bfffd0d 793500203ee2ffff 7d2907b47ed607b4 3b0100703be00000 -7f3db2143af77f68 +7f3db2143af77ee0 7f5d4a147ebdaa14 3860000f4bfffd75 4bfffca93b800000 @@ -727,57 +749,57 @@ f801001091810008 4bffffcc3b400000 7fbfe2142f9f0020 409e006c7fbd0e70 -38637f503c62ffff -600000004bfff939 +38637ec83c62ffff +600000004bfff889 3be000007fc3f378 7f9fe8004bfffb8d 3d40c010419c0070 -614a081839200000 +614a080c39200000 7c0004ac794a0020 3d40c0107d20572a -794a0020614a0820 +794a0020614a0810 7d20572a7c0004ac 4bfffaed3860000b 4bfffb213860000f -480014e4382100e0 +4800154c382100e0 3c62ffff7cbfe050 7ca501947ca50e70 -38637f587fa4eb78 -4bfff8bd7ca507b4 +38637ed07fa4eb78 +4bfff80d7ca507b4 4bffff8460000000 3bff00017fc3f378 7fff07b44bfffb59 000000004bffff7c 00000b8001000000 -384297883c4c0001 +384298d83c4c0001 3d40c0107c0802a6 3920000e614a0800 f8010010794a0020 7c0004acf821ffa1 -600000007d20572a -4bfff85d38628018 +3c62ffff7d20572a +4bfff7ad38637f90 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384297303c4c0001 +384298803c4c0001 3d40c0107c0802a6 39200001614a0800 f8010010794a0020 7c0004acf821ffa1 3c62ffff7d20572a -4bfff80538637f88 +4bfff75538637f00 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384296d83c4c0001 +384298283c4c0001 390000807c0802a6 3d40aaaa7d0903a6 614aaaaa3d204000 -f821ff8148001399 +f821ff8148001401 3929000491490000 -4bfff8214200fff8 +4bfff7714200fff8 3940008060000000 7d4903a63d00aaaa 3be000003d204000 @@ -789,7 +811,7 @@ f821ff8148001399 3d2040007d0903a6 91490000614a5555 4200fff839290004 -600000004bfff7c5 +600000004bfff715 3d00555539400080 3d2040007d4903a6 8149000061085555 @@ -798,8 +820,8 @@ f821ff8148001399 4200ffe839290004 419e001c2fbf0000 38a001003c62ffff -38637e887fe4fb78 -600000004bfff701 +38637e007fe4fb78 +600000004bfff651 3ce080203d000008 60e700037d0903a6 392000013d404000 @@ -807,7 +829,7 @@ f821ff8148001399 7d2900d0792907e0 7d293838394a0004 912afffc7d294278 -4bfff7314200ffe4 +4bfff6814200ffe4 3d00000860000000 7d0903a63ce08020 3d40400060e70003 @@ -821,13 +843,13 @@ f821ff8148001399 2fbd00004200ffd4 3c62ffff419e001c 7fa4eb783ca00008 -4bfff64d38637eb0 +4bfff59d38637e28 3920200060000000 7d2903a639400000 794800203d2a1000 394a000139290002 9109000079291764 -4bfff6914200ffe8 +4bfff5e14200ffe8 3920200060000000 7d2903a639400000 3d2a10003bc00000 @@ -838,314 +860,327 @@ f821ff8148001399 2fbe00004200ffdc 3c62ffff419e001c 7fc4f37838a02000 -4bfff5c538637ed8 +4bfff51538637e50 7fffea1460000000 7ffff21438600000 -409e00a82f9f0000 -38637f003c62ffff -600000004bfff5a1 -3d4000087c9602a6 +409e00a42f9f0000 +38637e783c62ffff +600000004bfff4f1 +3d4000047c9602a6 7d4903a678840020 -3d49100039200000 -794a176479280020 -910a000039290001 -7ff602a64200ffec -3fe064007c9f2050 -4bfff5d17fff2396 -7bff002060000000 -3d0000087d3602a6 -7d0903a679290020 -810a00003d404000 -4200fff8394a0004 -7d2548507cb602a6 -7ca54b963ca06400 -7fe4fb783c62ffff -78a5006038637f10 -600000004bfff511 -3821008038600001 -0000000048001128 -0000038001000000 -384293e83c4c0001 -480010817c0802a6 -3fe0c010f821fec1 -63ff00283bc00001 -4bfffc457bff0020 -4bfff72938600000 -7fc0ff2a7c0004ac -639c00403f80c010 -7c0004ac7b9c0020 -3ba000007fc0e72a +3d49080039200000 +f92a0000794a1f24 +4200fff039290001 +7c9f20507ff602a6 +7fff23963fe06400 +600000004bfff525 +7d3602a67bff0020 +792900203d000004 +3d4040007d0903a6 +394a0008e90a0000 +7cb602a64200fff8 +3ca064007d254850 +3c62ffff7ca54b96 +38637e887fe4fb78 +4bfff46578a50060 +3860000160000000 +4800119438210080 +0100000000000000 +3c4c000100000380 +7c0802a63842953c +f821fec1480010ed +3bc000013fe0c010 +7bff002063ff0014 +386000004bfffc49 +7c0004ac4bfff72d +3f80c0107fc0ff2a +7b9c0020639c0020 +7fc0e72a7c0004ac +7c0004ac3ba00000 +386000017fa0ff2a +392000024bfff6fd +7d20ff2a7c0004ac +7fc0e72a7c0004ac 7fa0ff2a7c0004ac -4bfff6f938600001 -7c0004ac39200002 -7c0004ac7d20ff2a -7c0004ac7fc0e72a -3c62ffff7fa0ff2a -38637fc83b810070 -4bfff4653e02ffff -3d22ffff60000000 -3de2fffffb810080 -3dc2ffff39297fd8 -3ae100633e42ffff -3ac10061f9210098 -3a107f683be00000 -39ce7ff039ef7fe8 -392100643a527fa8 -3e80c0103b200001 -f92100883ea0c010 -7f39f83039210068 -62b5082062940818 -3bc000007b330020 -3b000000f9210090 -7a9400203ba00000 -480000547ab50020 -2f9d000f7fbeeb78 -3d20c010419e029c -7929002061290028 -7e604f2a7c0004ac -394000013d00c010 -7908002061080048 -7d40472a7c0004ac -7c0004ac39400000 -3bbd00017d404f2a -7fbd07b47f78db78 -3900000439410060 -7d5a53783920002a -38c0000038e00004 -3ca080207ce903a6 -60a500037927f842 -7d2900d0792907e0 -7d29283878a50020 -78e900207d273a78 -38c600017cea31ae -3908ffff4200ffd4 -79080021394a0004 -3b6000004082ffb8 -7f60a72a7c0004ac -7f60af2a7c0004ac -4bfff51d38600009 -4bfff5513860000f -7f44d3783c60c010 -7863002060630828 -e88100884bfff63d -606308583c60c010 -4bfff62978630020 -3c60c010e8810090 -7863002060630888 -3c60c0104bfff615 -606308b83881006c -4bfff60178630020 -612908a83d20c010 +3b8100703c62ffff +3e02ffff38637f40 +600000004bfff3b9 +fb8100803d22ffff +39297f503de2ffff +3e42ffff3dc2ffff +f92100983ae10063 +3be000003ac10061 +39ef7f603a107ee0 +3a527f2039ce7f68 +3b20000139210064 +3ea0c0103e80c010 +39210068f9210088 +6294080c7f39f830 +7b33002062b50810 +f92100903bc00000 +3ba000003b000000 +7ab500207a940020 +7fbeeb7848000054 +419e029c2f9d000f +612900143d20c010 7c0004ac79290020 -3d20c0107f604f2a -79290020612908b0 +3d00c0107e604f2a +6108002439400001 +7c0004ac79080020 +394000007d40472a +7d404f2a7c0004ac +7f78db783bbd0001 +394100607fbd07b4 +3920002a39000004 +38e000047d5a5378 +7ce903a638c00000 +7927f8423ca08020 +792907e060a50003 +78a500207d2900d0 +7d273a787d292838 +7cea31ae78e90020 +4200ffd438c60001 +394a00043908ffff +4082ffb879080021 +7c0004ac3b600000 +7c0004ac7f60a72a +386000097f60af2a +3860000f4bfff521 +3c60c0104bfff555 +606308147f44d378 +4bfff64178630020 +3c60c010e8810088 +786300206063082c +e88100904bfff62d +606308443c60c010 +4bfff61978630020 +3881006c3c60c010 +786300206063085c +3d20c0104bfff605 +7929002061290854 7f604f2a7c0004ac -392000173d40c010 -794a0020614a0898 -7d20572a7c0004ac -392000013d40c010 -794a0020614a08a0 -7d20572a7c0004ac -612908783d20c010 +612908583d20c010 7c0004ac79290020 -3d20c0107f604f2a -7929002061290880 +3d40c0107f604f2a +614a084c39200017 +7c0004ac794a0020 +3d40c0107d20572a +614a085039200001 +7c0004ac794a0020 +3d20c0107d20572a +792900206129083c 7f604f2a7c0004ac -7fa5eb78e8610098 -3b4000207fe4fb78 -4bfff22d3b600000 -7fe3fb7860000000 -4bfff5194bfff485 -3a2000013860000f -394000004bfff44d -e881008079480fa4 -7c70402af94100a0 -e94100a04bfff581 -7d1650ae88fc0001 -409e00a07f883800 -88fc00037d1750ae -409e00907f883800 -2baa0010394a0004 -7e248b78409effc0 -4bfff1bd7de37b78 -3b5affff60000000 -4bfff45d7fe3fb78 -7f7b8a147b5a0021 -4082ff807f7b07b4 -4bfff1957dc37378 -3920000060000000 -7d20a72a7c0004ac -7d20af2a7c0004ac -4bfff3753860000b -4bfff3a93860000f -4bfff52d7fe3fb78 -4bfff15d7e439378 -7f98d80060000000 -7f1bc378419cfd70 -3a2000004bfffd6c -3c62ffff4bffff70 -7fe4fb787fc5f378 -4bfff12d38637ff8 -3d20c01060000000 -7929002061290028 -7f204f2a7c0004ac -394000013d00c010 -7908002061080040 -7d40472a7c0004ac -7c0004ac39400000 -7bde00207d404f2a -38de00013d00c010 -7cc903a661080048 -7908002039400001 -4200003438e00000 -3af7ffff7fe3fb78 -7e4393784bfff489 -4bfff0b53b9cffff -2f9f000160000000 -419e00283ad6ffff -4bfffc783be00001 -7e604f2a7c0004ac -7d40472a7c0004ac -7ce04f2a7c0004ac -382101404bffffb4 -48000c6038600001 -0100000000000000 -3c4c000100001280 -7c0802a638428f5c -38637fb03c62ffff -f821ff7148000c1d -3be000003f60c010 -7b7b0020637b1000 -600000004bfff039 -7fe0df2a7c0004ac -635a10083f40c010 -7c0004ac7b5a0020 -3fa0c0107fe0d72a -7bbd002063bd0818 -7fe0ef2a7c0004ac -63de08203fc0c010 -7c0004ac7bde0020 -3f80c0107fe0f72a -639c08003920000c -7c0004ac7b9c0020 -386000007d20e72a -4bfff2096063c350 -7fe0ef2a7c0004ac +612908403d20c010 +7c0004ac79290020 +e86100987f604f2a +7fe4fb787fa5eb78 +3b6000003b400020 +600000004bfff181 +4bfff4897fe3fb78 +3860000f4bfff51d +4bfff4513a200001 +79480fa439400000 +f94100a0e8810080 +4bfff5857c70402a +88fc0001e94100a0 +7f8838007d1650ae +7d1750ae409e00a0 +7f88380088fc0003 +394a0004409e0090 +409effc02baa0010 +7de37b787e248b78 +600000004bfff111 +7fe3fb783b5affff +7b5a00214bfff461 +7f7b07b47f7b8a14 +7dc373784082ff80 +600000004bfff0e9 +7c0004ac39200000 +7c0004ac7d20a72a +3860000b7d20af2a +3860000f4bfff379 +7fe3fb784bfff3ad +7e4393784bfff531 +600000004bfff0b1 +419cfd707f98d800 +4bfffd6c7f1bc378 +4bffff703a200000 +7fc5f3783c62ffff +38637f707fe4fb78 +600000004bfff081 +612900143d20c010 +7c0004ac79290020 +3d00c0107f204f2a +6108002039400001 +7c0004ac79080020 +394000007d40472a +7d404f2a7c0004ac +3d00c0107bde0020 +6108002438de0001 +394000017cc903a6 +38e0000079080020 +7fe3fb7842000034 +4bfff48d3af7ffff +3b9cffff7e439378 +600000004bfff009 +3ad6ffff2f9f0001 +3be00001419e0028 +7c0004ac4bfffc78 +7c0004ac7e604f2a +7c0004ac7d40472a +4bffffb47ce04f2a +3860000138210140 +0000000048000ccc +0000128001000000 +384290b03c4c0001 +3c62ffff7c0802a6 +48000c8938637f28 +3f60c010f821ff71 +637b10003be00000 +4bffef8d7b7b0020 +7c0004ac60000000 +3f40c0107fe0df2a +7b5a0020635a1004 +7fe0d72a7c0004ac +63bd080c3fa0c010 +7c0004ac7bbd0020 +3fc0c0107fe0ef2a +7bde002063de0810 7fe0f72a7c0004ac -7c0004ac3920000e -386027107d20e72a -392002004bfff1e5 -7d20ef2a7c0004ac -7c0004ac39200002 -3860000f7d20f72a -7c0004ac4bfff189 -392000037fe0ef2a +3920000c3f80c010 +7b9c0020639c0800 +7d20e72a7c0004ac +6063c35038600000 +7c0004ac4bfff20d +7c0004ac7fe0ef2a +3920000e7fe0f72a +7d20e72a7c0004ac +4bfff1e938602710 +7c0004ac39200200 +392000027d20ef2a 7d20f72a7c0004ac -4bfff16d3860000f -7c0004ac39200006 -3b8000017d20ef2a -7f80f72a7c0004ac -4bfff14d3860000f -7c0004ac39200920 -7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff131 -392004004bfff165 +4bfff18d3860000f +7fe0ef2a7c0004ac +7c0004ac39200003 +3860000f7d20f72a +392000064bfff171 +7d20ef2a7c0004ac +7c0004ac3b800001 +3860000f7f80f72a +392009204bfff151 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff10d38600003 -4bfff141386000c8 -4bfff6cd4bfffa19 -2c2300004bfff721 -7c0004ac4082001c -7c0004ac7f80df2a -382100907f80d72a -7c0004ac48000af4 -386000017f80df2a -000000004bffffec -0000068001000000 -38428db03c4c0001 -600000003d20c000 -7929002061292000 -3d20c000f9228090 -7929002061290020 +4bfff1353860000f +4bfff169386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff111 +4bfffa194bfff145 +4bfff7254bfff6d1 +4082001c2c230000 +7f80df2a7c0004ac +7f80d72a7c0004ac +48000b6038210090 +7f80df2a7c0004ac +4bffffec38600001 +0100000000000000 +3c4c000100000680 +3d20c00038428f04 +6129200060000000 +f922800879290020 +612900203d20c000 +7c0004ac79290020 +3d40001c7d204eea +7d295392614a2000 +394a0018e9428008 +7c0004ac3929ffff +4e8000207d2057ea +0000000000000000 +3c4c000100000000 +6000000038428ea4 +39290010e9228008 7d204eea7c0004ac -614a20003d40001c -e94280907d295392 -3929ffff394a0018 +4082ffe871290008 +e94280085469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428d503c4c0001 -e922809060000000 -7c0004ac39290010 -712900087d204eea -5469063e4082ffe8 -7c0004ace9428090 -4e8000207d2057ea -0000000000000000 -3c4c000100000000 -7c0802a638428d0c -fbe1fff8fbc1fff0 -f80100103bc3ffff -8ffe0001f821ffd1 -409e00102fbf0000 -3860000038210030 -2b9f000a48000a20 -3860000d409e000c -7fe3fb784bffff81 -4bffffd04bffff79 -0100000000000000 -2c24000000000280 -3881fff040820008 -f86400002b850024 -4d9d002038600000 -78c683e43cc00001 -e924000060c62600 -2b8a002089490000 -7cc75436419d002c -4082001470e80001 -409e00542fa50000 -4800005c38a0000a -f924000039290001 -2fa500004bffffcc -2b8a0030409e0038 -409e003c38a0000a -2f8a007889490001 -89490001409e0030 -2f8a007838a00010 -39290002409e0020 -48000014f9240000 -409e000c2f850010 -419effd82b8a0030 -4800003038600000 -54ca063e38c9ffd0 -419d00342b8a0009 -7f8928007cc90734 -38e700014c9c0020 -f8e400007c6519d2 -e8e400007c691a14 -2fa9000089270000 -4e800020409effc8 -554a063e3949ff9f -419d00102b8a0019 -7d2907343929ffa9 -3949ffbf4bffffbc +38428e603c4c0001 +fbc1fff07c0802a6 +3bc3fffffbe1fff8 +f821ffd1f8010010 +2fbf00008ffe0001 +38210030409e0010 +48000a8c38600000 +409e000c2b9f000a +4bffff813860000d +4bffff797fe3fb78 +000000004bffffd0 +0000028001000000 +408200082c240000 +2b8500243881fff0 +38600000f8640000 +3cc000014d9d0020 +60c6260078c683e4 +89490000e9240000 +419d002c2b8a0020 +70e800017cc75436 +2fa5000040820014 +38a0000a409e0054 +392900014800005c +4bffffccf9240000 +409e00382fa50000 +38a0000a2b8a0030 +89490001409e003c +409e00302f8a0078 +38a0001089490001 +409e00202f8a0078 +f924000039290002 +2f85001048000014 +2b8a0030409e000c +38600000419effd8 +38c9ffd048000030 +2b8a000954ca063e +7cc90734419d0034 +4c9c00207f892800 +7c6519d238e70001 +7c691a14f8e40000 +89270000e8e40000 +409effc82fa90000 +3949ff9f4e800020 2b8a0019554a063e -3929ffc94d9d0020 -000000004bffffe4 -0000000000000000 -7d4348ae39200000 -409e000c2f8a0000 -4e8000207d234b78 -4bffffe839290001 +3929ffa9419d0010 +4bffffbc7d290734 +554a063e3949ffbf +4d9d00202b8a0019 +4bffffe43929ffc9 +0000000000000000 +3920000000000000 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 +0000000000000000 +3900000078aae8c2 +7d2903a6392a0001 +78a9e8c242000030 +1d29fff8792a1f24 +7c8452147d035214 +392000007ca92a14 +7d4903a639450001 +4e80002042000018 +7d23412a7d24402a +4bffffc439080008 +7d4849ae7d4448ae +4bffffdc39290001 0000000000000000 3923ff9f00000000 4d9d00202b890019 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428b283c4c0001 +38428c103c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1179,12 +1214,12 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428a1c +7c0802a638428b04 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 7fa3eb783bc00000 -600000004bfffe79 +600000004bfffe0d 409d00147fa3f040 7d3b5050e95f0000 419c00107fa9e040 @@ -1195,14 +1230,14 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a63842899c +7c0802a638428a84 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 7cde337838a0000a 7cfc3b78eb5d0000 7d3f4b787d194378 -600000004bfffcb5 +600000004bfffc49 7c6307b439400000 409e006c2fbe0000 409e00082faa0000 @@ -1226,16 +1261,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384288a03c4c0001 +384289883c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff60000000 +3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a42804039228088 +3a527fb839228000 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1363,9 +1398,9 @@ e88100604bfffb35 38a0000a7d21e214 f9410088f9010090 7f43d37838800000 -4bfff7a99ae90020 +4bfff73d9ae90020 f861008060000000 -4bfff8cd7f63db78 +4bfff8617f63db78 e921008060000000 409d00407fa91840 e94100887c634850 @@ -1431,6 +1466,7 @@ e8010010ebc1fff0 0000000000000000 0000002054524155 000000204d415244 +000000204d415242 2020202020202020 203a4d4152422020 0a424b20646c6c25 @@ -1439,13 +1475,17 @@ e8010010ebc1fff0 203a4d4152442020 0a424d20646c6c25 0000000000000000 +4152442020202020 +203a54494e49204d +0a424b20646c6c25 +0000000000000000 2020202020202020 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6138393331393333 +3163616539333236 0000000000000000 -0033306536316430 +0039326232623162 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1455,6 +1495,13 @@ e8010010ebc1fff0 20676e69746f6f42 415242206d6f7266 0000000a2e2e2e4d +20676e6979706f43 +2064616f6c796170 +2e4d415244206f74 +00000000000a2e2e +20676e69746f6f42 +415244206d6f7266 +0000000a2e2e2e4d 20747365746d654d 6c69616620737562 252f6425203a6465 @@ -1483,10 +1530,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 +00000000c0100818 00000000c0100830 +00000000c0100848 00000000c0100860 -00000000c0100890 -00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v index 48dc091..dc4a031 100644 --- a/litedram/generated/arty/litedram_core.v +++ b/litedram/generated/arty/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:27 +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:51 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -540,7 +540,7 @@ reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; reg litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] litedramcore_master_p3_rddata; wire litedramcore_master_p3_rddata_valid; -reg [3:0] litedramcore_storage = 4'd0; +reg [3:0] litedramcore_storage = 4'd1; reg litedramcore_re = 1'd0; reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; reg litedramcore_phaseinjector0_command_re = 1'd0; @@ -1607,7 +1607,7 @@ wire csrbank0_init_error0_re; wire csrbank0_init_error0_r; wire csrbank0_init_error0_we; wire csrbank0_init_error0_w; -reg csrbank0_sel = 1'd0; +wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; wire [31:0] interface1_bank_bus_dat_w; @@ -1624,7 +1624,7 @@ wire csrbank1_dly_sel0_re; wire [1:0] csrbank1_dly_sel0_r; wire csrbank1_dly_sel0_we; wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_sel = 1'd0; +wire csrbank1_sel; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; wire [31:0] interface2_bank_bus_dat_w; @@ -1713,7 +1713,7 @@ wire csrbank2_dfii_pi3_rddata_re; wire [31:0] csrbank2_dfii_pi3_rddata_r; wire csrbank2_dfii_pi3_rddata_we; wire [31:0] csrbank2_dfii_pi3_rddata_w; -reg csrbank2_sel = 1'd0; +wire csrbank2_sel; wire [13:0] adr; wire we; wire [31:0] dat_w; @@ -1899,7 +1899,7 @@ always @(*) begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we <= litedramcore_wishbone_we; + litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase @@ -3235,6 +3235,35 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on +always @(*) begin + litedramcore_master_p2_we_n <= 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; + end +// synthesis translate_off + dummy_d_26 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_27; +// synthesis translate_on +always @(*) begin + litedramcore_slave_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end else begin + end +// synthesis translate_off + dummy_d_27 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_28; +// synthesis translate_on always @(*) begin litedramcore_master_p2_cke <= 1'd0; if (litedramcore_storage[0]) begin @@ -3243,12 +3272,12 @@ always @(*) begin litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off - dummy_d_26 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_27; +reg dummy_d_29; // synthesis translate_on always @(*) begin litedramcore_master_p2_odt <= 1'd0; @@ -3258,12 +3287,12 @@ always @(*) begin litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off - dummy_d_27 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_28; +reg dummy_d_30; // synthesis translate_on always @(*) begin litedramcore_master_p2_reset_n <= 1'd0; @@ -3273,12 +3302,12 @@ always @(*) begin litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off - dummy_d_28 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_29; +reg dummy_d_31; // synthesis translate_on always @(*) begin litedramcore_master_p2_act_n <= 1'd1; @@ -3288,12 +3317,12 @@ always @(*) begin litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off - dummy_d_29 = dummy_s; + dummy_d_31 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_30; +reg dummy_d_32; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata <= 32'd0; @@ -3303,12 +3332,12 @@ always @(*) begin litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_32 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_33; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata <= 32'd0; @@ -3317,12 +3346,12 @@ always @(*) begin litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_33 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_34; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_en <= 1'd0; @@ -3332,12 +3361,12 @@ always @(*) begin litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_34 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_35; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata_valid <= 1'd0; @@ -3346,12 +3375,12 @@ always @(*) begin litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_35 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_36; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_mask <= 4'd0; @@ -3361,12 +3390,12 @@ always @(*) begin litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_36 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_35; +reg dummy_d_37; // synthesis translate_on always @(*) begin litedramcore_master_p2_rddata_en <= 1'd0; @@ -3376,12 +3405,12 @@ always @(*) begin litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_37 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_38; // synthesis translate_on always @(*) begin litedramcore_master_p3_address <= 14'd0; @@ -3391,12 +3420,12 @@ always @(*) begin litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_38 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_39; // synthesis translate_on always @(*) begin litedramcore_master_p3_bank <= 3'd0; @@ -3406,12 +3435,12 @@ always @(*) begin litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_39 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_40; // synthesis translate_on always @(*) begin litedramcore_master_p3_cas_n <= 1'd1; @@ -3421,12 +3450,12 @@ always @(*) begin litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off - dummy_d_38 = dummy_s; + dummy_d_40 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_39; +reg dummy_d_41; // synthesis translate_on always @(*) begin litedramcore_master_p3_cs_n <= 1'd1; @@ -3436,12 +3465,12 @@ always @(*) begin litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_41 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_42; // synthesis translate_on always @(*) begin litedramcore_master_p3_ras_n <= 1'd1; @@ -3451,12 +3480,12 @@ always @(*) begin litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_42 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_43; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata <= 32'd0; @@ -3465,12 +3494,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_43 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_44; // synthesis translate_on always @(*) begin litedramcore_master_p3_we_n <= 1'd1; @@ -3480,12 +3509,12 @@ always @(*) begin litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_44 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_45; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata_valid <= 1'd0; @@ -3494,12 +3523,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_45 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_46; // synthesis translate_on always @(*) begin litedramcore_master_p3_cke <= 1'd0; @@ -3509,12 +3538,12 @@ always @(*) begin litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_46 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_45; +reg dummy_d_47; // synthesis translate_on always @(*) begin litedramcore_master_p3_odt <= 1'd0; @@ -3524,12 +3553,12 @@ always @(*) begin litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off - dummy_d_45 = dummy_s; + dummy_d_47 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_46; +reg dummy_d_48; // synthesis translate_on always @(*) begin litedramcore_master_p3_reset_n <= 1'd0; @@ -3539,12 +3568,12 @@ always @(*) begin litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off - dummy_d_46 = dummy_s; + dummy_d_48 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_47; +reg dummy_d_49; // synthesis translate_on always @(*) begin litedramcore_master_p3_act_n <= 1'd1; @@ -3554,12 +3583,12 @@ always @(*) begin litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off - dummy_d_47 = dummy_s; + dummy_d_49 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_48; +reg dummy_d_50; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata <= 32'd0; @@ -3569,12 +3598,12 @@ always @(*) begin litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off - dummy_d_48 = dummy_s; + dummy_d_50 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_49; +reg dummy_d_51; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata <= 32'd0; @@ -3583,12 +3612,12 @@ always @(*) begin litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off - dummy_d_49 = dummy_s; + dummy_d_51 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_50; +reg dummy_d_52; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_en <= 1'd0; @@ -3598,12 +3627,12 @@ always @(*) begin litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off - dummy_d_50 = dummy_s; + dummy_d_52 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_51; +reg dummy_d_53; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata_valid <= 1'd0; @@ -3612,12 +3641,12 @@ always @(*) begin litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off - dummy_d_51 = dummy_s; + dummy_d_53 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_52; +reg dummy_d_54; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_mask <= 4'd0; @@ -3627,12 +3656,12 @@ always @(*) begin litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off - dummy_d_52 = dummy_s; + dummy_d_54 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_53; +reg dummy_d_55; // synthesis translate_on always @(*) begin litedramcore_master_p3_rddata_en <= 1'd0; @@ -3642,12 +3671,12 @@ always @(*) begin litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off - dummy_d_53 = dummy_s; + dummy_d_55 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_54; +reg dummy_d_56; // synthesis translate_on always @(*) begin litedramcore_master_p0_address <= 14'd0; @@ -3657,12 +3686,12 @@ always @(*) begin litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off - dummy_d_54 = dummy_s; + dummy_d_56 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_55; +reg dummy_d_57; // synthesis translate_on always @(*) begin litedramcore_master_p0_bank <= 3'd0; @@ -3672,12 +3701,12 @@ always @(*) begin litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off - dummy_d_55 = dummy_s; + dummy_d_57 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_56; +reg dummy_d_58; // synthesis translate_on always @(*) begin litedramcore_master_p0_cas_n <= 1'd1; @@ -3687,12 +3716,12 @@ always @(*) begin litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off - dummy_d_56 = dummy_s; + dummy_d_58 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_57; +reg dummy_d_59; // synthesis translate_on always @(*) begin litedramcore_master_p0_cs_n <= 1'd1; @@ -3702,12 +3731,12 @@ always @(*) begin litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off - dummy_d_57 = dummy_s; + dummy_d_59 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_58; +reg dummy_d_60; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata <= 32'd0; @@ -3716,12 +3745,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_58 = dummy_s; + dummy_d_60 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_59; +reg dummy_d_61; // synthesis translate_on always @(*) begin litedramcore_master_p0_ras_n <= 1'd1; @@ -3731,41 +3760,41 @@ always @(*) begin litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off - dummy_d_59 = dummy_s; + dummy_d_61 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_60; +reg dummy_d_62; // synthesis translate_on always @(*) begin - litedramcore_slave_p0_rddata_valid <= 1'd0; + litedramcore_master_p0_we_n <= 1'd1; if (litedramcore_storage[0]) begin - litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; + litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; end else begin + litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_60 = dummy_s; + dummy_d_62 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_61; +reg dummy_d_63; // synthesis translate_on always @(*) begin - litedramcore_master_p0_we_n <= 1'd1; + litedramcore_slave_p0_rddata_valid <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n; + litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end else begin - litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_61 = dummy_s; + dummy_d_63 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_62; +reg dummy_d_64; // synthesis translate_on always @(*) begin litedramcore_master_p0_cke <= 1'd0; @@ -3775,12 +3804,12 @@ always @(*) begin litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off - dummy_d_62 = dummy_s; + dummy_d_64 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_63; +reg dummy_d_65; // synthesis translate_on always @(*) begin litedramcore_master_p0_odt <= 1'd0; @@ -3790,12 +3819,12 @@ always @(*) begin litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off - dummy_d_63 = dummy_s; + dummy_d_65 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_64; +reg dummy_d_66; // synthesis translate_on always @(*) begin litedramcore_master_p0_reset_n <= 1'd0; @@ -3805,12 +3834,12 @@ always @(*) begin litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off - dummy_d_64 = dummy_s; + dummy_d_66 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_65; +reg dummy_d_67; // synthesis translate_on always @(*) begin litedramcore_master_p0_act_n <= 1'd1; @@ -3820,12 +3849,12 @@ always @(*) begin litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off - dummy_d_65 = dummy_s; + dummy_d_67 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_66; +reg dummy_d_68; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata <= 32'd0; @@ -3835,12 +3864,12 @@ always @(*) begin litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off - dummy_d_66 = dummy_s; + dummy_d_68 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_67; +reg dummy_d_69; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata <= 32'd0; @@ -3849,12 +3878,12 @@ always @(*) begin litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off - dummy_d_67 = dummy_s; + dummy_d_69 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_68; +reg dummy_d_70; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_en <= 1'd0; @@ -3864,12 +3893,12 @@ always @(*) begin litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off - dummy_d_68 = dummy_s; + dummy_d_70 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_69; +reg dummy_d_71; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata_valid <= 1'd0; @@ -3878,12 +3907,12 @@ always @(*) begin litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off - dummy_d_69 = dummy_s; + dummy_d_71 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_70; +reg dummy_d_72; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_mask <= 4'd0; @@ -3893,12 +3922,12 @@ always @(*) begin litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off - dummy_d_70 = dummy_s; + dummy_d_72 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_71; +reg dummy_d_73; // synthesis translate_on always @(*) begin litedramcore_master_p0_rddata_en <= 1'd0; @@ -3908,12 +3937,12 @@ always @(*) begin litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off - dummy_d_71 = dummy_s; + dummy_d_73 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_72; +reg dummy_d_74; // synthesis translate_on always @(*) begin litedramcore_master_p1_address <= 14'd0; @@ -3923,12 +3952,12 @@ always @(*) begin litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off - dummy_d_72 = dummy_s; + dummy_d_74 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_73; +reg dummy_d_75; // synthesis translate_on always @(*) begin litedramcore_master_p1_bank <= 3'd0; @@ -3938,12 +3967,12 @@ always @(*) begin litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off - dummy_d_73 = dummy_s; + dummy_d_75 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_74; +reg dummy_d_76; // synthesis translate_on always @(*) begin litedramcore_master_p1_cas_n <= 1'd1; @@ -3953,26 +3982,12 @@ always @(*) begin litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off - dummy_d_74 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_75; -// synthesis translate_on -always @(*) begin - litedramcore_slave_p2_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; - end else begin - end -// synthesis translate_off - dummy_d_75 = dummy_s; + dummy_d_76 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_76; +reg dummy_d_77; // synthesis translate_on always @(*) begin litedramcore_master_p1_cs_n <= 1'd1; @@ -3982,12 +3997,12 @@ always @(*) begin litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off - dummy_d_76 = dummy_s; + dummy_d_77 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_77; +reg dummy_d_78; // synthesis translate_on always @(*) begin litedramcore_master_p1_ras_n <= 1'd1; @@ -3997,12 +4012,12 @@ always @(*) begin litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off - dummy_d_77 = dummy_s; + dummy_d_78 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_78; +reg dummy_d_79; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata <= 32'd0; @@ -4011,12 +4026,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_78 = dummy_s; + dummy_d_79 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_79; +reg dummy_d_80; // synthesis translate_on always @(*) begin litedramcore_master_p1_we_n <= 1'd1; @@ -4026,12 +4041,12 @@ always @(*) begin litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off - dummy_d_79 = dummy_s; + dummy_d_80 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_80; +reg dummy_d_81; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata_valid <= 1'd0; @@ -4040,12 +4055,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_80 = dummy_s; + dummy_d_81 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_81; +reg dummy_d_82; // synthesis translate_on always @(*) begin litedramcore_master_p1_cke <= 1'd0; @@ -4055,12 +4070,12 @@ always @(*) begin litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off - dummy_d_81 = dummy_s; + dummy_d_82 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_82; +reg dummy_d_83; // synthesis translate_on always @(*) begin litedramcore_master_p1_odt <= 1'd0; @@ -4070,41 +4085,41 @@ always @(*) begin litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off - dummy_d_82 = dummy_s; + dummy_d_83 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_83; +reg dummy_d_84; // synthesis translate_on always @(*) begin - litedramcore_slave_p2_rddata_valid <= 1'd0; + litedramcore_master_p1_reset_n <= 1'd0; if (litedramcore_storage[0]) begin - litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; end else begin + litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_83 = dummy_s; + dummy_d_84 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_84; +reg dummy_d_85; // synthesis translate_on always @(*) begin - litedramcore_master_p1_reset_n <= 1'd0; + litedramcore_slave_p2_rddata <= 32'd0; if (litedramcore_storage[0]) begin - litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n; + litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata; end else begin - litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_84 = dummy_s; + dummy_d_85 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_85; +reg dummy_d_86; // synthesis translate_on always @(*) begin litedramcore_master_p1_act_n <= 1'd1; @@ -4114,12 +4129,12 @@ always @(*) begin litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off - dummy_d_85 = dummy_s; + dummy_d_86 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_86; +reg dummy_d_87; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata <= 32'd0; @@ -4129,12 +4144,12 @@ always @(*) begin litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end // synthesis translate_off - dummy_d_86 = dummy_s; + dummy_d_87 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_87; +reg dummy_d_88; // synthesis translate_on always @(*) begin litedramcore_inti_p2_rddata <= 32'd0; @@ -4143,12 +4158,12 @@ always @(*) begin litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; end // synthesis translate_off - dummy_d_87 = dummy_s; + dummy_d_88 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_88; +reg dummy_d_89; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata_en <= 1'd0; @@ -4158,12 +4173,12 @@ always @(*) begin litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; end // synthesis translate_off - dummy_d_88 = dummy_s; + dummy_d_89 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_89; +reg dummy_d_90; // synthesis translate_on always @(*) begin litedramcore_inti_p2_rddata_valid <= 1'd0; @@ -4172,12 +4187,12 @@ always @(*) begin litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; end // synthesis translate_off - dummy_d_89 = dummy_s; + dummy_d_90 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_90; +reg dummy_d_91; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata_mask <= 4'd0; @@ -4187,12 +4202,12 @@ always @(*) begin litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; end // synthesis translate_off - dummy_d_90 = dummy_s; + dummy_d_91 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_91; +reg dummy_d_92; // synthesis translate_on always @(*) begin litedramcore_master_p1_rddata_en <= 1'd0; @@ -4202,12 +4217,12 @@ always @(*) begin litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; end // synthesis translate_off - dummy_d_91 = dummy_s; + dummy_d_92 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_92; +reg dummy_d_93; // synthesis translate_on always @(*) begin litedramcore_master_p2_address <= 14'd0; @@ -4217,12 +4232,12 @@ always @(*) begin litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off - dummy_d_92 = dummy_s; + dummy_d_93 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_93; +reg dummy_d_94; // synthesis translate_on always @(*) begin litedramcore_master_p2_bank <= 3'd0; @@ -4232,12 +4247,12 @@ always @(*) begin litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off - dummy_d_93 = dummy_s; + dummy_d_94 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_94; +reg dummy_d_95; // synthesis translate_on always @(*) begin litedramcore_master_p2_cas_n <= 1'd1; @@ -4247,12 +4262,12 @@ always @(*) begin litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_95 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_96; // synthesis translate_on always @(*) begin litedramcore_master_p2_cs_n <= 1'd1; @@ -4262,12 +4277,12 @@ always @(*) begin litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_96 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_97; // synthesis translate_on always @(*) begin litedramcore_master_p2_ras_n <= 1'd1; @@ -4276,21 +4291,6 @@ always @(*) begin end else begin litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end -// synthesis translate_off - dummy_d_96 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_97; -// synthesis translate_on -always @(*) begin - litedramcore_master_p2_we_n <= 1'd1; - if (litedramcore_storage[0]) begin - litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n; - end else begin - litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; - end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on @@ -4312,11 +4312,11 @@ assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; reg dummy_d_98; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4327,11 +4327,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; + litedramcore_inti_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4342,11 +4342,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4357,11 +4357,11 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -4378,11 +4378,11 @@ assign litedramcore_inti_p0_wrdata_mask = 1'd0; reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4393,11 +4393,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; + litedramcore_inti_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4408,11 +4408,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4423,11 +4423,11 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -4444,11 +4444,11 @@ assign litedramcore_inti_p1_wrdata_mask = 1'd0; reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4459,11 +4459,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; + litedramcore_inti_p2_cas_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4474,11 +4474,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4489,11 +4489,11 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -4510,11 +4510,11 @@ assign litedramcore_inti_p2_wrdata_mask = 1'd0; reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4525,11 +4525,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; + litedramcore_inti_p3_cas_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4540,11 +4540,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4555,11 +4555,11 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_113 = dummy_s; @@ -4918,38 +4918,83 @@ always @(*) begin bankmachine0_next_state <= 4'd8; end 4'd8: begin - bankmachine0_next_state <= 1'd0; + bankmachine0_next_state <= 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state <= 2'd2; + end + end else begin + bankmachine0_next_state <= 1'd1; + end + end else begin + bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +// synthesis translate_off + dummy_d_122 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_123; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin end default: begin if (litedramcore_bankmachine0_refresh_req) begin - bankmachine0_next_state <= 3'd4; end else begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin - bankmachine0_next_state <= 2'd2; + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; + end else begin end end else begin - bankmachine0_next_state <= 1'd1; end end else begin - bankmachine0_next_state <= 2'd3; end end end end endcase // synthesis translate_off - dummy_d_122 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_123; +reg dummy_d_124; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_rdata_valid <= 1'd0; + litedramcore_bankmachine0_req_wdata_ready <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -4974,8 +5019,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin - litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; end end else begin end @@ -4986,24 +5031,21 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_123 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_124; +reg dummy_d_125; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine0_req_rdata_valid <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -5016,15 +5058,30 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -5052,12 +5109,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -5099,39 +5156,6 @@ always @(*) begin end end endcase -// synthesis translate_off - dummy_d_126 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_127; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase // synthesis translate_off dummy_d_127 = dummy_s; // synthesis translate_on @@ -5141,18 +5165,18 @@ end reg dummy_d_128; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_row_close <= 1'd0; + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; case (bankmachine0_state) 1'd1: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5174,13 +5198,16 @@ end reg dummy_d_129; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine0_row_open <= 1'd0; case (bankmachine0_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end end 3'd4: begin end @@ -5193,18 +5220,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5216,21 +5231,18 @@ end reg dummy_d_130; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine0_row_close <= 1'd1; end 3'd5: begin end @@ -5252,12 +5264,9 @@ end reg dummy_d_131; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd0; + litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; case (bankmachine0_state) 1'd1: begin - if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -5279,10 +5288,7 @@ always @(*) begin if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine0_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -5300,22 +5306,21 @@ end reg dummy_d_132; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; case (bankmachine0_state) 1'd1: begin if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5337,9 +5342,12 @@ end reg dummy_d_133; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine0_cmd_payload_we <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -5362,8 +5370,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5382,15 +5390,22 @@ end reg dummy_d_134; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; case (bankmachine0_state) 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -5401,21 +5416,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine0_refresh_req) begin - end else begin - if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine0_row_opened) begin - if (litedramcore_bankmachine0_row_hit) begin - if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -5427,7 +5427,7 @@ end reg dummy_d_135; // synthesis translate_on always @(*) begin - litedramcore_bankmachine0_req_wdata_ready <= 1'd0; + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; case (bankmachine0_state) 1'd1: begin end @@ -5452,8 +5452,8 @@ always @(*) begin if (litedramcore_bankmachine0_row_opened) begin if (litedramcore_bankmachine0_row_hit) begin if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready; end else begin + litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1; end end else begin end @@ -5627,7 +5627,7 @@ end reg dummy_d_140; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_rdata_valid <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5652,8 +5652,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; end end else begin end @@ -5672,7 +5672,7 @@ end reg dummy_d_141; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd0; + litedramcore_bankmachine1_req_wdata_ready <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -5681,9 +5681,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine1_twtpcon_ready) begin - litedramcore_bankmachine1_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -5694,6 +5691,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -5705,19 +5717,13 @@ end reg dummy_d_142; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_valid <= 1'd0; + litedramcore_bankmachine1_req_rdata_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -5735,7 +5741,10 @@ always @(*) begin if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin - litedramcore_bankmachine1_cmd_valid <= 1'd1; + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready; + end end else begin end end else begin @@ -5753,15 +5762,51 @@ end reg dummy_d_143; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine1_refresh_gnt <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_143 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_144; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_cmd_valid <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine1_cmd_valid <= 1'd1; end end 3'd4: begin @@ -5775,15 +5820,27 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_open <= 1'd0; @@ -5811,12 +5868,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5844,12 +5901,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5886,12 +5943,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5921,54 +5978,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_147 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_148; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd0; - case (bankmachine1_state) - 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end - end - endcase // synthesis translate_off dummy_d_148 = dummy_s; // synthesis translate_on @@ -5978,22 +5987,18 @@ end reg dummy_d_149; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; case (bankmachine1_state) 1'd1: begin - if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6015,9 +6020,12 @@ end reg dummy_d_150; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine1_cmd_payload_we <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6040,8 +6048,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6060,15 +6068,22 @@ end reg dummy_d_151; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; case (bankmachine1_state) 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6079,21 +6094,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine1_refresh_req) begin - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6105,7 +6105,7 @@ end reg dummy_d_152; // synthesis translate_on always @(*) begin - litedramcore_bankmachine1_req_wdata_ready <= 1'd0; + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; case (bankmachine1_state) 1'd1: begin end @@ -6130,8 +6130,8 @@ always @(*) begin if (litedramcore_bankmachine1_row_opened) begin if (litedramcore_bankmachine1_row_hit) begin if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready; end else begin + litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6305,7 +6305,7 @@ end reg dummy_d_157; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_rdata_valid <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6330,8 +6330,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; end end else begin end @@ -6350,7 +6350,7 @@ end reg dummy_d_158; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd0; + litedramcore_bankmachine2_req_wdata_ready <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6359,9 +6359,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine2_twtpcon_ready) begin - litedramcore_bankmachine2_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -6372,6 +6369,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6383,18 +6395,15 @@ end reg dummy_d_159; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_valid <= 1'd0; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; + litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -6408,18 +6417,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6431,16 +6428,13 @@ end reg dummy_d_160; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; + litedramcore_bankmachine2_req_rdata_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end end 3'd4: begin end @@ -6453,6 +6447,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -6464,18 +6473,18 @@ end reg dummy_d_161; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_close <= 1'd0; + litedramcore_bankmachine2_refresh_gnt <= 1'd0; case (bankmachine2_state) 1'd1: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine2_row_close <= 1'd1; + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -6497,13 +6506,19 @@ end reg dummy_d_162; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine2_cmd_valid <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -6521,7 +6536,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine2_cmd_valid <= 1'd1; end else begin end end else begin @@ -6539,7 +6554,7 @@ end reg dummy_d_163; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine2_row_open <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6547,7 +6562,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine2_row_open <= 1'd1; end end 3'd4: begin @@ -6572,21 +6587,18 @@ end reg dummy_d_164; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine2_row_close <= 1'd1; end 3'd5: begin end @@ -6608,12 +6620,9 @@ end reg dummy_d_165; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd0; + litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; case (bankmachine2_state) 1'd1: begin - if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -6635,10 +6644,7 @@ always @(*) begin if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine2_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -6656,22 +6662,21 @@ end reg dummy_d_166; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; case (bankmachine2_state) 1'd1: begin if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6693,9 +6698,12 @@ end reg dummy_d_167; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine2_cmd_payload_we <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -6718,8 +6726,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6738,15 +6746,22 @@ end reg dummy_d_168; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; case (bankmachine2_state) 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -6757,21 +6772,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine2_refresh_req) begin - end else begin - if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine2_row_opened) begin - if (litedramcore_bankmachine2_row_hit) begin - if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -6783,7 +6783,7 @@ end reg dummy_d_169; // synthesis translate_on always @(*) begin - litedramcore_bankmachine2_req_wdata_ready <= 1'd0; + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; case (bankmachine2_state) 1'd1: begin end @@ -6808,8 +6808,8 @@ always @(*) begin if (litedramcore_bankmachine2_row_opened) begin if (litedramcore_bankmachine2_row_hit) begin if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready; end else begin + litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1; end end else begin end @@ -6983,7 +6983,7 @@ end reg dummy_d_174; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_rdata_valid <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7008,8 +7008,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; end end else begin end @@ -7028,7 +7028,7 @@ end reg dummy_d_175; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd0; + litedramcore_bankmachine3_req_wdata_ready <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7037,9 +7037,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine3_twtpcon_ready) begin - litedramcore_bankmachine3_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -7050,6 +7047,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7061,19 +7073,13 @@ end reg dummy_d_176; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_valid <= 1'd0; + litedramcore_bankmachine3_req_rdata_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7091,7 +7097,10 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_valid <= 1'd1; + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready; + end end else begin end end else begin @@ -7109,18 +7118,18 @@ end reg dummy_d_177; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; + litedramcore_bankmachine3_refresh_gnt <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -7142,18 +7151,21 @@ end reg dummy_d_178; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_close <= 1'd0; + litedramcore_bankmachine3_cmd_valid <= 1'd0; case (bankmachine3_state) 1'd1: begin - litedramcore_bankmachine3_row_close <= 1'd1; + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 2'd2: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7164,6 +7176,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7175,13 +7199,16 @@ end reg dummy_d_179; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; case (bankmachine3_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -7194,18 +7221,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7217,18 +7232,15 @@ end reg dummy_d_180; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine3_row_open <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine3_row_open <= 1'd1; end end 3'd4: begin @@ -7253,18 +7265,18 @@ end reg dummy_d_181; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd0; + litedramcore_bankmachine3_row_close <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine3_row_close <= 1'd1; end 3'd5: begin end @@ -7275,21 +7287,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7301,22 +7298,15 @@ end reg dummy_d_182; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; case (bankmachine3_state) 1'd1: begin - if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7327,6 +7317,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7338,13 +7340,19 @@ end reg dummy_d_183; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras <= 1'd1; + end end 3'd4: begin end @@ -7357,21 +7365,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7383,16 +7376,16 @@ end reg dummy_d_184; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine3_cmd_payload_we <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7405,6 +7398,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7416,15 +7424,22 @@ end reg dummy_d_185; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; case (bankmachine3_state) 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -7435,21 +7450,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine3_refresh_req) begin - end else begin - if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine3_row_opened) begin - if (litedramcore_bankmachine3_row_hit) begin - if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7461,7 +7461,7 @@ end reg dummy_d_186; // synthesis translate_on always @(*) begin - litedramcore_bankmachine3_req_wdata_ready <= 1'd0; + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; case (bankmachine3_state) 1'd1: begin end @@ -7486,8 +7486,8 @@ always @(*) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready; end else begin + litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1; end end else begin end @@ -7661,7 +7661,7 @@ end reg dummy_d_191; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_rdata_valid <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -7686,8 +7686,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; end end else begin end @@ -7706,16 +7706,13 @@ end reg dummy_d_192; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine4_req_wdata_ready <= 1'd0; case (bankmachine4_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -7728,6 +7725,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7739,19 +7751,13 @@ end reg dummy_d_193; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_valid <= 1'd0; + litedramcore_bankmachine4_req_rdata_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -7769,7 +7775,10 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_valid <= 1'd1; + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready; + end end else begin end end else begin @@ -7820,15 +7829,18 @@ end reg dummy_d_195; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; + litedramcore_bankmachine4_cmd_valid <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; + litedramcore_bankmachine4_cmd_valid <= 1'd1; end end 3'd4: begin @@ -7842,6 +7854,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -7853,18 +7877,18 @@ end reg dummy_d_196; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_row_close <= 1'd0; + litedramcore_bankmachine4_row_open <= 1'd0; case (bankmachine4_state) 1'd1: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7886,15 +7910,18 @@ end reg dummy_d_197; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) 1'd1: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine4_row_close <= 1'd1; end 3'd5: begin end @@ -7905,18 +7932,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -7928,18 +7943,15 @@ end reg dummy_d_198; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -7964,12 +7976,9 @@ end reg dummy_d_199; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd0; + litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; case (bankmachine4_state) 1'd1: begin - if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -7991,10 +8000,7 @@ always @(*) begin if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine4_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -8012,22 +8018,21 @@ end reg dummy_d_200; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; case (bankmachine4_state) 1'd1: begin if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine4_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8049,9 +8054,12 @@ end reg dummy_d_201; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine4_cmd_payload_we <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -8074,8 +8082,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8094,15 +8102,22 @@ end reg dummy_d_202; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; case (bankmachine4_state) 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -8113,21 +8128,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine4_refresh_req) begin - end else begin - if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine4_row_opened) begin - if (litedramcore_bankmachine4_row_hit) begin - if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8139,7 +8139,7 @@ end reg dummy_d_203; // synthesis translate_on always @(*) begin - litedramcore_bankmachine4_req_wdata_ready <= 1'd0; + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; case (bankmachine4_state) 1'd1: begin end @@ -8164,8 +8164,8 @@ always @(*) begin if (litedramcore_bankmachine4_row_opened) begin if (litedramcore_bankmachine4_row_hit) begin if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready; end else begin + litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1; end end else begin end @@ -8339,7 +8339,7 @@ end reg dummy_d_208; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_rdata_valid <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8364,8 +8364,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; end end else begin end @@ -8384,7 +8384,7 @@ end reg dummy_d_209; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd0; + litedramcore_bankmachine5_req_wdata_ready <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8393,9 +8393,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine5_twtpcon_ready) begin - litedramcore_bankmachine5_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -8406,6 +8403,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8417,19 +8429,13 @@ end reg dummy_d_210; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_valid <= 1'd0; + litedramcore_bankmachine5_req_rdata_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin - if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -8447,7 +8453,10 @@ always @(*) begin if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin - litedramcore_bankmachine5_cmd_valid <= 1'd1; + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready; + end end else begin end end else begin @@ -8465,18 +8474,18 @@ end reg dummy_d_211; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine5_refresh_gnt <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -8498,15 +8507,18 @@ end reg dummy_d_212; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; + litedramcore_bankmachine5_cmd_valid <= 1'd0; case (bankmachine5_state) 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; + litedramcore_bankmachine5_cmd_valid <= 1'd1; end end 3'd4: begin @@ -8520,6 +8532,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -8530,6 +8554,39 @@ end // synthesis translate_off reg dummy_d_213; // synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +// synthesis translate_off + dummy_d_213 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_214; +// synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; case (bankmachine5_state) @@ -8556,12 +8613,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8598,12 +8655,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8634,12 +8691,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8682,12 +8739,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8718,51 +8775,6 @@ always @(*) begin default: begin end endcase -// synthesis translate_off - dummy_d_217 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_218; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - end else begin - litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; - end - end else begin - end - end else begin - end - end - end - end - endcase // synthesis translate_off dummy_d_218 = dummy_s; // synthesis translate_on @@ -8772,13 +8784,16 @@ end reg dummy_d_219; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; case (bankmachine5_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin end @@ -8791,21 +8806,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine5_refresh_req) begin - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -8817,7 +8817,7 @@ end reg dummy_d_220; // synthesis translate_on always @(*) begin - litedramcore_bankmachine5_req_wdata_ready <= 1'd0; + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; case (bankmachine5_state) 1'd1: begin end @@ -8842,8 +8842,8 @@ always @(*) begin if (litedramcore_bankmachine5_row_opened) begin if (litedramcore_bankmachine5_row_hit) begin if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready; end else begin + litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9017,7 +9017,7 @@ end reg dummy_d_225; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_rdata_valid <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9042,8 +9042,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; end else begin - litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; end end else begin end @@ -9062,7 +9062,7 @@ end reg dummy_d_226; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd0; + litedramcore_bankmachine6_req_wdata_ready <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9071,9 +9071,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine6_twtpcon_ready) begin - litedramcore_bankmachine6_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9084,6 +9081,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9095,19 +9107,13 @@ end reg dummy_d_227; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_valid <= 1'd0; + litedramcore_bankmachine6_req_rdata_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; - end end 3'd4: begin end @@ -9125,7 +9131,10 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_valid <= 1'd1; + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready; + end end else begin end end else begin @@ -9143,7 +9152,7 @@ end reg dummy_d_228; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9151,7 +9160,7 @@ always @(*) begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; + litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; end end 3'd4: begin @@ -9176,18 +9185,18 @@ end reg dummy_d_229; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_close <= 1'd0; + litedramcore_bankmachine6_refresh_gnt <= 1'd0; case (bankmachine6_state) 1'd1: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin - litedramcore_bankmachine6_row_close <= 1'd1; + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9209,13 +9218,19 @@ end reg dummy_d_230; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine6_cmd_valid <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid <= 1'd1; + end end 3'd4: begin end @@ -9233,7 +9248,7 @@ always @(*) begin if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin - litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + litedramcore_bankmachine6_cmd_valid <= 1'd1; end else begin end end else begin @@ -9251,18 +9266,15 @@ end reg dummy_d_231; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine6_row_open <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; - end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + litedramcore_bankmachine6_row_open <= 1'd1; end end 3'd4: begin @@ -9287,18 +9299,18 @@ end reg dummy_d_232; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd0; + litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 2'd3: begin end 3'd4: begin + litedramcore_bankmachine6_row_close <= 1'd1; end 3'd5: begin end @@ -9309,21 +9321,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_we <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9335,22 +9332,15 @@ end reg dummy_d_233; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; case (bankmachine6_state) 1'd1: begin - if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; - end end 3'd4: begin - litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9361,6 +9351,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9372,15 +9374,18 @@ end reg dummy_d_234; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1; + litedramcore_bankmachine6_cmd_payload_ras <= 1'd1; end end 3'd4: begin @@ -9405,9 +9410,12 @@ end reg dummy_d_235; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine6_cmd_payload_we <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -9430,8 +9438,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9450,15 +9458,22 @@ end reg dummy_d_236; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; case (bankmachine6_state) 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -9469,21 +9484,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine6_refresh_req) begin - end else begin - if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine6_row_opened) begin - if (litedramcore_bankmachine6_row_hit) begin - if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9495,7 +9495,7 @@ end reg dummy_d_237; // synthesis translate_on always @(*) begin - litedramcore_bankmachine6_req_wdata_ready <= 1'd0; + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; case (bankmachine6_state) 1'd1: begin end @@ -9520,8 +9520,8 @@ always @(*) begin if (litedramcore_bankmachine6_row_opened) begin if (litedramcore_bankmachine6_row_hit) begin if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready; end else begin + litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1; end end else begin end @@ -9695,16 +9695,13 @@ end reg dummy_d_242; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; - end end 3'd4: begin end @@ -9717,6 +9714,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9728,7 +9740,7 @@ end reg dummy_d_243; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_rdata_valid <= 1'd0; + litedramcore_bankmachine7_req_wdata_ready <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9753,8 +9765,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin - litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; end end else begin end @@ -9773,7 +9785,7 @@ end reg dummy_d_244; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd0; + litedramcore_bankmachine7_req_rdata_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -9782,9 +9794,6 @@ always @(*) begin 2'd3: begin end 3'd4: begin - if (litedramcore_bankmachine7_twtpcon_ready) begin - litedramcore_bankmachine7_refresh_gnt <= 1'd1; - end end 3'd5: begin end @@ -9795,6 +9804,21 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9806,21 +9830,18 @@ end reg dummy_d_245; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_valid <= 1'd0; + litedramcore_bankmachine7_refresh_gnt <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 2'd2: begin end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end end 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt <= 1'd1; + end end 3'd5: begin end @@ -9831,18 +9852,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_valid <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9854,15 +9863,18 @@ end reg dummy_d_246; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; + litedramcore_bankmachine7_cmd_valid <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; + litedramcore_bankmachine7_cmd_valid <= 1'd1; end end 3'd4: begin @@ -9876,6 +9888,18 @@ always @(*) begin 4'd8: begin end default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid <= 1'd1; + end else begin + end + end else begin + end + end + end end endcase // synthesis translate_off @@ -9887,18 +9911,18 @@ end reg dummy_d_247; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_row_close <= 1'd0; + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; case (bankmachine7_state) 1'd1: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1; + end end 3'd4: begin - litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9920,13 +9944,16 @@ end reg dummy_d_248; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; + litedramcore_bankmachine7_row_open <= 1'd0; case (bankmachine7_state) 1'd1: begin end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end end 3'd4: begin end @@ -9939,18 +9966,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -9962,21 +9977,18 @@ end reg dummy_d_249; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; + litedramcore_bankmachine7_row_close <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd2: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; - end end 3'd4: begin + litedramcore_bankmachine7_row_close <= 1'd1; end 3'd5: begin end @@ -9998,12 +10010,9 @@ end reg dummy_d_250; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd0; + litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; case (bankmachine7_state) 1'd1: begin - if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end end 2'd2: begin end @@ -10025,10 +10034,7 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_we <= 1'd1; - end else begin - end + litedramcore_bankmachine7_cmd_payload_cas <= 1'd1; end else begin end end else begin @@ -10046,22 +10052,21 @@ end reg dummy_d_251; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; case (bankmachine7_state) 1'd1: begin if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 2'd2: begin end 2'd3: begin if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + litedramcore_bankmachine7_cmd_payload_ras <= 1'd1; end end 3'd4: begin - litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10083,9 +10088,12 @@ end reg dummy_d_252; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; + litedramcore_bankmachine7_cmd_payload_we <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; + end end 2'd2: begin end @@ -10108,8 +10116,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we <= 1'd1; end else begin - litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10128,15 +10136,22 @@ end reg dummy_d_253; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; case (bankmachine7_state) 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 2'd2: begin end 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end end 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1; end 3'd5: begin end @@ -10147,21 +10162,6 @@ always @(*) begin 4'd8: begin end default: begin - if (litedramcore_bankmachine7_refresh_req) begin - end else begin - if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine7_row_opened) begin - if (litedramcore_bankmachine7_row_hit) begin - if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1; - end else begin - end - end else begin - end - end else begin - end - end - end end endcase // synthesis translate_off @@ -10173,7 +10173,7 @@ end reg dummy_d_254; // synthesis translate_on always @(*) begin - litedramcore_bankmachine7_req_wdata_ready <= 1'd0; + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; case (bankmachine7_state) 1'd1: begin end @@ -10198,8 +10198,8 @@ always @(*) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin - litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready; end else begin + litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1; end end else begin end @@ -10581,10 +10581,10 @@ end reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin end @@ -10605,7 +10605,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off @@ -10617,9 +10617,13 @@ end reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end 2'd2: begin end @@ -10640,7 +10644,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end endcase // synthesis translate_off @@ -10652,12 +10659,12 @@ end reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10676,6 +10683,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10687,13 +10695,9 @@ end reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end 2'd2: begin end @@ -10714,10 +10718,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off @@ -10729,11 +10730,12 @@ end reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10752,7 +10754,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10764,10 +10765,13 @@ end reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10788,6 +10792,10 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off @@ -10799,14 +10807,9 @@ end reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end end 2'd2: begin end @@ -10827,11 +10830,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10843,10 +10842,10 @@ end reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10878,13 +10877,16 @@ end reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10903,7 +10905,11 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off @@ -10915,10 +10921,10 @@ end reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10939,7 +10945,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -10951,12 +10956,13 @@ end reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10975,7 +10981,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -10987,13 +10993,10 @@ end reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -11014,10 +11017,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -11072,13 +11072,13 @@ assign user_port_rdata_valid = new_master_rdata_valid8; reg dummy_d_284; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; + litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + litedramcore_interface_wdata <= 1'd0; end endcase // synthesis translate_off @@ -11090,13 +11090,13 @@ end reg dummy_d_285; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata <= 128'd0; + litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata <= 1'd0; + litedramcore_interface_wdata_we <= 1'd0; end endcase // synthesis translate_off @@ -11123,164 +11123,125 @@ assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on -always @(*) begin - csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); - if (interface0_bank_bus_adr[0]) begin - csrbank0_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on -end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on -always @(*) begin - csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); - if (interface1_bank_bus_adr[0]) begin - csrbank1_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on -end +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on -always @(*) begin - csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); - if (interface2_bank_bus_adr[0]) begin - csrbank2_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2)); assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4)); assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5)); assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); -assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8)); assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10)); assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11)); assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); -assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14)); assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16)); assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17)); assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); -assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20)); assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22)); assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23)); assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); -assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; @@ -11322,7 +11283,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_289; +reg dummy_d_286; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -11353,12 +11314,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_287; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 14'd0; @@ -11389,12 +11350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_288; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -11425,12 +11386,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -11461,12 +11422,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -11497,12 +11458,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11533,12 +11494,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_292; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11569,12 +11530,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_293; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11605,12 +11566,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_294; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11641,12 +11602,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_295; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11677,12 +11638,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_296; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 14'd0; @@ -11713,12 +11674,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_297; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11749,12 +11710,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11785,12 +11746,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11821,12 +11782,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11857,12 +11818,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_301; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11893,12 +11854,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_302; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11929,12 +11890,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_303; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11965,12 +11926,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_304; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 21'd0; @@ -11980,12 +11941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_305; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11995,12 +11956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_306; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -12010,12 +11971,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 21'd0; @@ -12025,12 +11986,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -12040,12 +12001,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -12055,12 +12016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 21'd0; @@ -12070,12 +12031,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -12085,12 +12046,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -12100,12 +12061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 21'd0; @@ -12115,12 +12076,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -12130,12 +12091,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -12145,12 +12106,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 21'd0; @@ -12160,12 +12121,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -12175,12 +12136,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -12190,12 +12151,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 21'd0; @@ -12205,12 +12166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -12220,12 +12181,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -12235,12 +12196,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 21'd0; @@ -12250,12 +12211,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -12265,12 +12226,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -12280,12 +12241,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 21'd0; @@ -12295,12 +12256,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -12310,12 +12271,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -12325,12 +12286,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_328; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -12349,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_329; // synthesis translate_on always @(*) begin array_muxed1 <= 14'd0; @@ -12373,12 +12334,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_330; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -12397,12 +12358,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -12421,12 +12382,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -12445,12 +12406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -12469,12 +12430,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -12493,12 +12454,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12517,12 +12478,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed8 <= 14'd0; @@ -12541,12 +12502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12565,12 +12526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12589,12 +12550,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12613,12 +12574,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12637,12 +12598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12661,12 +12622,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12685,12 +12646,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed15 <= 14'd0; @@ -12709,12 +12670,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12733,12 +12694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12757,12 +12718,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12781,12 +12742,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12805,12 +12766,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12829,12 +12790,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12853,12 +12814,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed22 <= 14'd0; @@ -12877,12 +12838,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12901,12 +12862,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12925,12 +12886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12949,12 +12910,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_356 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_357; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12973,12 +12934,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12997,7 +12958,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -14447,7 +14408,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[1]) + case (interface0_bank_bus_adr[0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14466,7 +14427,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[4:1]) + case (interface1_bank_bus_adr[3:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14513,7 +14474,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[5:1]) + case (interface2_bank_bus_adr[4:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14691,7 +14652,7 @@ always @(posedge sys_clk) begin a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; - litedramcore_storage <= 4'd0; + litedramcore_storage <= 4'd1; litedramcore_re <= 1'd0; litedramcore_phaseinjector0_command_storage <= 6'd0; litedramcore_phaseinjector0_command_re <= 1'd0; diff --git a/litedram/generated/nexys-video/litedram-initmem.vhdl b/litedram/generated/nexys-video/litedram-initmem.vhdl index f83d732..13bd0ce 100644 --- a/litedram/generated/nexys-video/litedram-initmem.vhdl +++ b/litedram/generated/nexys-video/litedram-initmem.vhdl @@ -5,66 +5,117 @@ use std.textio.all; library work; use work.wishbone_types.all; +use work.utils.all; entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); port ( clk : in std_ulogic; - wb_in : in wb_io_master_out; - wb_out : out wb_io_slave_out + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out ); end entity dram_init_mem; architecture rtl of dram_init_mem is - constant INIT_RAM_SIZE : integer := 16384; - constant INIT_RAM_ABITS :integer := 14; - constant INIT_RAM_FILE : string := "litedram_core.init"; + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram_core.init"; - type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; impure function init_load_ram(name : string) return ram_t is - file ram_file : text open read_mode is name; - variable temp_word : std_logic_vector(63 downto 0); - variable temp_ram : ram_t := (others => (others => '0')); - variable ram_line : line; + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; begin - for i in 0 to (INIT_RAM_SIZE/8)-1 loop - exit when endfile(ram_file); - readline(ram_file, ram_line); - hread(ram_line, temp_word); - temp_ram(i*2) := temp_word(31 downto 0); - temp_ram(i*2+1) := temp_word(63 downto 32); - end loop; - return temp_ram; + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; end function; - signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE); + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); attribute ram_style : string; attribute ram_style of init_ram: signal is "block"; + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; begin init_ram_0: process(clk) - variable adr : integer; + variable adr : integer; begin - if rising_edge(clk) then - wb_out.ack <= '0'; - if (wb_in.cyc and wb_in.stb) = '1' then - adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); - if wb_in.we = '0' then - wb_out.dat <= init_ram(adr); - else - for i in 0 to 3 loop - if wb_in.sel(i) = '1' then - init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= - wb_in.dat(((i + 1) * 8) - 1 downto i * 8); - end if; - end loop; - end if; - wb_out.ack <= '1'; - end if; - end if; + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; end process; wb_out.stall <= '0'; diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl deleted file mode 100644 index f12e3df..0000000 --- a/litedram/generated/nexys-video/litedram-wrapper.vhdl +++ /dev/null @@ -1,284 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use std.textio.all; - -library work; -use work.wishbone_types.all; - -entity litedram_wrapper is - generic ( - DRAM_ABITS : positive; - DRAM_ALINES : positive - ); - port( - -- LiteDRAM generates the system clock and reset - -- from the input clkin - clk_in : in std_ulogic; - rst : in std_ulogic; - system_clk : out std_ulogic; - system_reset : out std_ulogic; - core_alt_reset : out std_ulogic; - pll_locked : out std_ulogic; - - -- Wishbone ports: - wb_in : in wishbone_master_out; - wb_out : out wishbone_slave_out; - wb_ctrl_in : in wb_io_master_out; - wb_ctrl_out : out wb_io_slave_out; - wb_ctrl_is_csr : in std_ulogic; - wb_ctrl_is_init : in std_ulogic; - - -- Init core serial debug - serial_tx : out std_ulogic; - serial_rx : in std_ulogic; - - -- Misc - init_done : out std_ulogic; - init_error : out std_ulogic; - - -- DRAM wires - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic - ); -end entity litedram_wrapper; - -architecture behaviour of litedram_wrapper is - - component litedram_core port ( - clk : in std_ulogic; - rst : in std_ulogic; - pll_locked : out std_ulogic; - ddram_a : out std_ulogic_vector(DRAM_ALINES-1 downto 0); - ddram_ba : out std_ulogic_vector(2 downto 0); - ddram_ras_n : out std_ulogic; - ddram_cas_n : out std_ulogic; - ddram_we_n : out std_ulogic; - ddram_cs_n : out std_ulogic; - ddram_dm : out std_ulogic_vector(1 downto 0); - ddram_dq : inout std_ulogic_vector(15 downto 0); - ddram_dqs_p : inout std_ulogic_vector(1 downto 0); - ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; - ddram_cke : out std_ulogic; - ddram_odt : out std_ulogic; - ddram_reset_n : out std_ulogic; - init_done : out std_ulogic; - init_error : out std_ulogic; - user_clk : out std_ulogic; - user_rst : out std_ulogic; - wb_ctrl_adr : in std_ulogic_vector(29 downto 0); - wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); - wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); - wb_ctrl_sel : in std_ulogic_vector(3 downto 0); - wb_ctrl_cyc : in std_ulogic; - wb_ctrl_stb : in std_ulogic; - wb_ctrl_ack : out std_ulogic; - wb_ctrl_we : in std_ulogic; - wb_ctrl_cti : in std_ulogic_vector(2 downto 0); - wb_ctrl_bte : in std_ulogic_vector(1 downto 0); - wb_ctrl_err : out std_ulogic; - user_port_native_0_cmd_valid : in std_ulogic; - user_port_native_0_cmd_ready : out std_ulogic; - user_port_native_0_cmd_we : in std_ulogic; - user_port_native_0_cmd_addr : in std_ulogic_vector(DRAM_ABITS-1 downto 0); - user_port_native_0_wdata_valid : in std_ulogic; - user_port_native_0_wdata_ready : out std_ulogic; - user_port_native_0_wdata_we : in std_ulogic_vector(15 downto 0); - user_port_native_0_wdata_data : in std_ulogic_vector(127 downto 0); - user_port_native_0_rdata_valid : out std_ulogic; - user_port_native_0_rdata_ready : in std_ulogic; - user_port_native_0_rdata_data : out std_ulogic_vector(127 downto 0) - ); - end component; - - signal user_port0_cmd_valid : std_ulogic; - signal user_port0_cmd_ready : std_ulogic; - signal user_port0_cmd_we : std_ulogic; - signal user_port0_cmd_addr : std_ulogic_vector(DRAM_ABITS-1 downto 0); - signal user_port0_wdata_valid : std_ulogic; - signal user_port0_wdata_ready : std_ulogic; - signal user_port0_wdata_we : std_ulogic_vector(15 downto 0); - signal user_port0_wdata_data : std_ulogic_vector(127 downto 0); - signal user_port0_rdata_valid : std_ulogic; - signal user_port0_rdata_ready : std_ulogic; - signal user_port0_rdata_data : std_ulogic_vector(127 downto 0); - - signal ad3 : std_ulogic; - - signal wb_ctrl_adr : std_ulogic_vector(29 downto 0); - signal wb_ctrl_dat_w : std_ulogic_vector(31 downto 0); - signal wb_ctrl_dat_r : std_ulogic_vector(31 downto 0); - signal wb_ctrl_sel : std_ulogic_vector(3 downto 0); - signal wb_ctrl_cyc : std_ulogic; - signal wb_ctrl_stb : std_ulogic; - signal wb_ctrl_ack : std_ulogic; - signal wb_ctrl_we : std_ulogic; - - signal wb_init_in : wb_io_master_out; - signal wb_init_out : wb_io_slave_out; - - type state_t is (CMD, MWRITE, MREAD); - signal state : state_t; - -begin - - -- alternate core reset address set when DRAM is not initialized. - core_alt_reset <= not init_done; - - -- Init code BRAM memory slave - init_ram_0: entity work.dram_init_mem - port map( - clk => system_clk, - wb_in => wb_init_in, - wb_out => wb_init_out - ); - - -- - -- Control bus wishbone: This muxes the wishbone to the CSRs - -- and an internal small one to the init BRAM - -- - - -- Init DRAM wishbone IN signals - wb_init_in.adr <= wb_ctrl_in.adr; - wb_init_in.dat <= wb_ctrl_in.dat; - wb_init_in.sel <= wb_ctrl_in.sel; - wb_init_in.we <= wb_ctrl_in.we; - wb_init_in.stb <= wb_ctrl_in.stb; - wb_init_in.cyc <= wb_ctrl_in.cyc and wb_ctrl_is_init; - - -- DRAM CSR IN signals - wb_ctrl_adr <= x"0000" & wb_ctrl_in.adr(15 downto 2); - wb_ctrl_dat_w <= wb_ctrl_in.dat; - wb_ctrl_sel <= wb_ctrl_in.sel; - wb_ctrl_we <= wb_ctrl_in.we; - wb_ctrl_cyc <= wb_ctrl_in.cyc and wb_ctrl_is_csr; - wb_ctrl_stb <= wb_ctrl_in.stb and wb_ctrl_is_csr; - - -- Ctrl bus wishbone OUT signals - wb_ctrl_out.ack <= wb_ctrl_ack when wb_ctrl_is_csr = '1' - else wb_init_out.ack; - wb_ctrl_out.dat <= wb_ctrl_dat_r when wb_ctrl_is_csr = '1' - else wb_init_out.dat; - wb_ctrl_out.stall <= wb_init_out.stall when wb_ctrl_is_init else - '0' when wb_ctrl_in.cyc = '0' else not wb_ctrl_ack; - - -- - -- Data bus wishbone to LiteDRAM native port - -- - -- Address bit 3 selects the top or bottom half of the data - -- bus (64-bit wishbone vs. 128-bit DRAM interface) - -- - -- XXX TODO: Figure out how to pipeline this - -- - ad3 <= wb_in.adr(3); - - -- Wishbone port IN signals - user_port0_cmd_valid <= wb_in.cyc and wb_in.stb when state = CMD else '0'; - user_port0_cmd_we <= wb_in.we when state = CMD else '0'; - user_port0_wdata_valid <= '1' when state = MWRITE else '0'; - user_port0_rdata_ready <= '1' when state = MREAD else '0'; - user_port0_cmd_addr <= wb_in.adr(DRAM_ABITS+3 downto 4); - user_port0_wdata_data <= wb_in.dat & wb_in.dat; - user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else - "00000000" & wb_in.sel; - - -- Wishbone OUT signals - wb_out.ack <= user_port0_wdata_ready when state = MWRITE else - user_port0_rdata_valid when state = MREAD else '0'; - - wb_out.dat <= user_port0_rdata_data(127 downto 64) when ad3 = '1' else - user_port0_rdata_data(63 downto 0); - - -- We don't do pipelining yet. - wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack; - - -- DRAM user port State machine - sm: process(system_clk) - begin - - if rising_edge(system_clk) then - if system_reset = '1' then - state <= CMD; - else - case state is - when CMD => - if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then - state <= MWRITE when wb_in.we = '1' else MREAD; - end if; - when MWRITE => - if user_port0_wdata_ready = '1' then - state <= CMD; - end if; - when MREAD => - if user_port0_rdata_valid = '1' then - state <= CMD; - end if; - end case; - end if; - end if; - end process; - - litedram: litedram_core - port map( - clk => clk_in, - rst => rst, - pll_locked => pll_locked, - ddram_a => ddram_a, - ddram_ba => ddram_ba, - ddram_ras_n => ddram_ras_n, - ddram_cas_n => ddram_cas_n, - ddram_we_n => ddram_we_n, - ddram_cs_n => ddram_cs_n, - ddram_dm => ddram_dm, - ddram_dq => ddram_dq, - ddram_dqs_p => ddram_dqs_p, - ddram_dqs_n => ddram_dqs_n, - ddram_clk_p => ddram_clk_p, - ddram_clk_n => ddram_clk_n, - ddram_cke => ddram_cke, - ddram_odt => ddram_odt, - ddram_reset_n => ddram_reset_n, - init_done => init_done, - init_error => init_error, - user_clk => system_clk, - user_rst => system_reset, - wb_ctrl_adr => wb_ctrl_adr, - wb_ctrl_dat_w => wb_ctrl_dat_w, - wb_ctrl_dat_r => wb_ctrl_dat_r, - wb_ctrl_sel => wb_ctrl_sel, - wb_ctrl_cyc => wb_ctrl_cyc, - wb_ctrl_stb => wb_ctrl_stb, - wb_ctrl_ack => wb_ctrl_ack, - wb_ctrl_we => wb_ctrl_we, - wb_ctrl_cti => "000", - wb_ctrl_bte => "00", - wb_ctrl_err => open, - user_port_native_0_cmd_valid => user_port0_cmd_valid, - user_port_native_0_cmd_ready => user_port0_cmd_ready, - user_port_native_0_cmd_we => user_port0_cmd_we, - user_port_native_0_cmd_addr => user_port0_cmd_addr, - user_port_native_0_wdata_valid => user_port0_wdata_valid, - user_port_native_0_wdata_ready => user_port0_wdata_ready, - user_port_native_0_wdata_we => user_port0_wdata_we, - user_port_native_0_wdata_data => user_port0_wdata_data, - user_port_native_0_rdata_valid => user_port0_rdata_valid, - user_port_native_0_rdata_ready => user_port0_rdata_ready, - user_port_native_0_rdata_data => user_port0_rdata_data - ); - -end architecture behaviour; diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init index 22485ac..d20e710 100644 --- a/litedram/generated/nexys-video/litedram_core.init +++ b/litedram/generated/nexys-video/litedram_core.init @@ -7,7 +7,7 @@ a64b5a7d14004a39 6421f000782107c6 3d80000060213f00 798c07c6618c0000 -618c108c658cf000 +618c10a4658cf000 4e8004217d8903a6 0000000048000002 0000000000000000 @@ -510,7 +510,7 @@ a64b5a7d14004a39 0000000000000000 0000000000000000 0000000000000000 -38429f003c4c0001 +3842a1003c4c0001 fbc1fff07c0802a6 f8010010fbe1fff8 3be10020f821fe91 @@ -519,66 +519,88 @@ f8c101a838800140 38c101987c651b78 7fe3fb78f8e101b0 f92101c0f90101b8 -4800161df94101c8 +48001735f94101c8 7c7e1b7860000000 -480011a17fe3fb78 +4800124d7fe3fb78 3821017060000000 -48001bdc7fc3f378 +48001cf47fc3f378 0100000000000000 4e80002000000280 0000000000000000 +7c0007ac00000000 +4e8000204c00012c +0000000000000000 3c4c000100000000 -7c0802a638429e74 -7d908026fbe1fff8 -f801001091810008 -480010adf821ff91 +7c0802a63842a05c +7d800026fbe1fff8 +91810008f8010010 +48001141f821ff91 3c62ffff60000000 -4bffff4d38637d60 +4bffff3538637c78 548400023880ffff 7c8026ea7c0004ac 3fe0c0003c62ffff -63ff000838637d80 -3c62ffff4bffff29 -38637da07bff0020 -7c0004ac4bffff19 +63ff000838637c98 +3c62ffff4bffff11 +38637cb87bff0020 +7c0004ac4bffff01 73e900017fe0feea 3c62ffff41820010 -4bfffefd38637db8 -4e00000073e90002 +4bfffee538637cd0 +4d80000073e90002 3c62ffff41820010 -4bfffee538637dc0 -3bff7fa83fe2ffff -4bfffed57fe3fb78 -608400103c80c000 -7c0004ac78840020 -3c62ffff7c8026ea -38637dc87884b282 -419200284bfffeb1 -608400183c80c000 +4bfffecd38637cd8 +4e00000073e90004 +3c62ffff41820010 +4bfffeb538637ce0 +3bff7f203fe2ffff +4bfffea57fe3fb78 +3c80c00041920028 +7884002060840010 +7c8026ea7c0004ac +7884b2823c62ffff +4bfffe7d38637ce8 +3c80c000418e004c +7884002060840018 +7c8026ea7c0004ac +788465023c62ffff +4bfffe5538637d08 +608400303c80c000 7c0004ac78840020 3c62ffff7c8026ea -38637de878846502 -3d20c0004bfffe89 +38637d287884b282 +3d20c0004bfffe31 7929002061290020 7d204eea7c0004ac 3c62ffff3c80000f -38637e0860844240 -4bfffe5d7c892392 -4bfffe557fe3fb78 -3ca2ffff41920028 +38637d4860844240 +4bfffe057c892392 +4bfffdfd7fe3fb78 +3ca2ffff418e0028 3c62ffff3c82ffff -38847e3838a57e28 -4bfffe3538637e40 -6000000048000dd5 -38637e703c62ffff -382100704bfffe21 -7d90812081810008 -0000000048001a54 +38847d7838a57d68 +4bfffddd38637d80 +6000000048000e29 +3c62ffff41920020 +4bfffdc538637db0 +8181000838210070 +48001b107d818120 +38637dc83c62ffff +3c80f0004bfffda9 +6084400038a0ffff +7884002054a50422 +480011e53c604000 +3c62ffff60000000 +4bfffd7d38637de8 +e801001038210070 +ebe1fff881810008 +7d8181207c0803a6 +000000004bfffde4 0000018003000000 -612908083d20c010 +612908043d20c010 7c0004ac79290020 3d40c0107c604f2a -614a081039200001 +614a080839200001 7c0004ac794a0020 4e8000207d20572a 0000000000000000 @@ -588,29 +610,29 @@ f801001091810008 4e8000204200fffc 0000000000000000 3d20c01000000000 -6129002839400001 +6129001439400001 792900207d431830 7c604f2a7c0004ac -610800303d00c010 +610800183d00c010 7c0004ac79080020 394000007d40472a 7d404f2a7c0004ac 000000004e800020 0000000000000000 394000013d20c010 -7d43183061290028 +7d43183061290014 7c0004ac79290020 3d00c0107c604f2a -7908002061080038 +790800206108001c 7d40472a7c0004ac 7c0004ac39400000 4e8000207d404f2a 0000000000000000 3d40c01000000000 -614a086839200025 +614a083439200025 7c0004ac794a0020 3d40c0107d20572a -614a087039200001 +614a083839200001 7c0004ac794a0020 4e8000207d20572a 0000000000000000 @@ -631,11 +653,11 @@ f801001091810008 9864000099240001 000000004e800020 0000000000000000 -38429b383c4c0001 -480017ed7c0802a6 +38429c883c4c0001 +480018557c0802a6 7c7e1b78f821ff21 -38637f403c62ffff -600000004bfffc21 +38637eb83c62ffff +600000004bfffb71 390100603ca08020 3940000460a50003 7d1d43783920002a @@ -648,45 +670,45 @@ f801001091810008 394affff4200ffe0 794a002139080004 3d20c0104082ffc4 -612908183be00000 +6129080c3be00000 7c0004ac79290020 3d20c0107fe04f2a -7929002061290820 +7929002061290810 7fe04f2a7c0004ac 4bfffd8d38600009 4bfffdc13860000f 7fa4eb783c60c010 -7863002060630828 +7863002060630814 3c60c0104bfffead -6063085838810064 +6063082c38810064 4bfffe9978630020 388100683c60c010 -7863002060630888 +7863002060630844 3c60c0104bfffe85 -606308b83881006c +6063085c3881006c 4bfffe7178630020 -612908a83d20c010 +612908543d20c010 7c0004ac79290020 3d20c0107fe04f2a -79290020612908b0 +7929002061290858 7fe04f2a7c0004ac 392000173d40c010 -794a0020614a0898 +794a0020614a084c 7d20572a7c0004ac 392000013d40c010 -794a0020614a08a0 +794a0020614a0850 7d20572a7c0004ac -612908783d20c010 +6129083c3d20c010 7c0004ac79290020 3d20c0107fe04f2a -7929002061290880 +7929002061290840 7fe04f2a7c0004ac 22de00017fc3f378 213e00034bfffd0d 793500203ee2ffff 7d2907b47ed607b4 3b0100703be00000 -7f3db2143af77f68 +7f3db2143af77ee0 7f5d4a147ebdaa14 3860000f4bfffd75 4bfffca93b800000 @@ -727,57 +749,57 @@ f801001091810008 4bffffcc3b400000 7fbfe2142f9f0020 409e006c7fbd0e70 -38637f503c62ffff -600000004bfff939 +38637ec83c62ffff +600000004bfff889 3be000007fc3f378 7f9fe8004bfffb8d 3d40c010419c0070 -614a081839200000 +614a080c39200000 7c0004ac794a0020 3d40c0107d20572a -794a0020614a0820 +794a0020614a0810 7d20572a7c0004ac 4bfffaed3860000b 4bfffb213860000f -480014e4382100e0 +4800154c382100e0 3c62ffff7cbfe050 7ca501947ca50e70 -38637f587fa4eb78 -4bfff8bd7ca507b4 +38637ed07fa4eb78 +4bfff80d7ca507b4 4bffff8460000000 3bff00017fc3f378 7fff07b44bfffb59 000000004bffff7c 00000b8001000000 -384297883c4c0001 +384298d83c4c0001 3d40c0107c0802a6 3920000e614a0800 f8010010794a0020 7c0004acf821ffa1 -600000007d20572a -4bfff85d38628018 +3c62ffff7d20572a +4bfff7ad38637f90 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384297303c4c0001 +384298803c4c0001 3d40c0107c0802a6 39200001614a0800 f8010010794a0020 7c0004acf821ffa1 3c62ffff7d20572a -4bfff80538637f88 +4bfff75538637f00 3821006060000000 7c0803a6e8010010 000000004e800020 0000008001000000 -384296d83c4c0001 +384298283c4c0001 390000807c0802a6 3d40aaaa7d0903a6 614aaaaa3d204000 -f821ff8148001399 +f821ff8148001401 3929000491490000 -4bfff8214200fff8 +4bfff7714200fff8 3940008060000000 7d4903a63d00aaaa 3be000003d204000 @@ -789,7 +811,7 @@ f821ff8148001399 3d2040007d0903a6 91490000614a5555 4200fff839290004 -600000004bfff7c5 +600000004bfff715 3d00555539400080 3d2040007d4903a6 8149000061085555 @@ -798,8 +820,8 @@ f821ff8148001399 4200ffe839290004 419e001c2fbf0000 38a001003c62ffff -38637e887fe4fb78 -600000004bfff701 +38637e007fe4fb78 +600000004bfff651 3ce080203d000008 60e700037d0903a6 392000013d404000 @@ -807,7 +829,7 @@ f821ff8148001399 7d2900d0792907e0 7d293838394a0004 912afffc7d294278 -4bfff7314200ffe4 +4bfff6814200ffe4 3d00000860000000 7d0903a63ce08020 3d40400060e70003 @@ -821,13 +843,13 @@ f821ff8148001399 2fbd00004200ffd4 3c62ffff419e001c 7fa4eb783ca00008 -4bfff64d38637eb0 +4bfff59d38637e28 3920200060000000 7d2903a639400000 794800203d2a1000 394a000139290002 9109000079291764 -4bfff6914200ffe8 +4bfff5e14200ffe8 3920200060000000 7d2903a639400000 3d2a10003bc00000 @@ -838,314 +860,327 @@ f821ff8148001399 2fbe00004200ffdc 3c62ffff419e001c 7fc4f37838a02000 -4bfff5c538637ed8 +4bfff51538637e50 7fffea1460000000 7ffff21438600000 -409e00a82f9f0000 -38637f003c62ffff -600000004bfff5a1 -3d4000087c9602a6 +409e00a42f9f0000 +38637e783c62ffff +600000004bfff4f1 +3d4000047c9602a6 7d4903a678840020 -3d49100039200000 -794a176479280020 -910a000039290001 -7ff602a64200ffec -3fe064007c9f2050 -4bfff5d17fff2396 -7bff002060000000 -3d0000087d3602a6 -7d0903a679290020 -810a00003d404000 -4200fff8394a0004 -7d2548507cb602a6 -7ca54b963ca06400 -7fe4fb783c62ffff -78a5006038637f10 -600000004bfff511 -3821008038600001 -0000000048001128 -0000038001000000 -384293e83c4c0001 -480010817c0802a6 -3fe0c010f821fec1 -63ff00283bc00001 -4bfffc457bff0020 -4bfff72938600000 -7fc0ff2a7c0004ac -639c00403f80c010 -7c0004ac7b9c0020 -3ba000007fc0e72a +3d49080039200000 +f92a0000794a1f24 +4200fff039290001 +7c9f20507ff602a6 +7fff23963fe06400 +600000004bfff525 +7d3602a67bff0020 +792900203d000004 +3d4040007d0903a6 +394a0008e90a0000 +7cb602a64200fff8 +3ca064007d254850 +3c62ffff7ca54b96 +38637e887fe4fb78 +4bfff46578a50060 +3860000160000000 +4800119438210080 +0100000000000000 +3c4c000100000380 +7c0802a63842953c +f821fec1480010ed +3bc000013fe0c010 +7bff002063ff0014 +386000004bfffc49 +7c0004ac4bfff72d +3f80c0107fc0ff2a +7b9c0020639c0020 +7fc0e72a7c0004ac +7c0004ac3ba00000 +386000017fa0ff2a +392000024bfff6fd +7d20ff2a7c0004ac +7fc0e72a7c0004ac 7fa0ff2a7c0004ac -4bfff6f938600001 -7c0004ac39200002 -7c0004ac7d20ff2a -7c0004ac7fc0e72a -3c62ffff7fa0ff2a -38637fc83b810070 -4bfff4653e02ffff -3d22ffff60000000 -3de2fffffb810080 -3dc2ffff39297fd8 -3ae100633e42ffff -3ac10061f9210098 -3a107f683be00000 -39ce7ff039ef7fe8 -392100643a527fa8 -3e80c0103b200001 -f92100883ea0c010 -7f39f83039210068 -62b5082062940818 -3bc000007b330020 -3b000000f9210090 -7a9400203ba00000 -480000547ab50020 -2f9d000f7fbeeb78 -3d20c010419e029c -7929002061290028 -7e604f2a7c0004ac -394000013d00c010 -7908002061080048 -7d40472a7c0004ac -7c0004ac39400000 -3bbd00017d404f2a -7fbd07b47f78db78 -3900000439410060 -7d5a53783920002a -38c0000038e00004 -3ca080207ce903a6 -60a500037927f842 -7d2900d0792907e0 -7d29283878a50020 -78e900207d273a78 -38c600017cea31ae -3908ffff4200ffd4 -79080021394a0004 -3b6000004082ffb8 -7f60a72a7c0004ac -7f60af2a7c0004ac -4bfff51d38600009 -4bfff5513860000f -7f44d3783c60c010 -7863002060630828 -e88100884bfff63d -606308583c60c010 -4bfff62978630020 -3c60c010e8810090 -7863002060630888 -3c60c0104bfff615 -606308b83881006c -4bfff60178630020 -612908a83d20c010 +3b8100703c62ffff +3e02ffff38637f40 +600000004bfff3b9 +fb8100803d22ffff +39297f503de2ffff +3e42ffff3dc2ffff +f92100983ae10063 +3be000003ac10061 +39ef7f603a107ee0 +3a527f2039ce7f68 +3b20000139210064 +3ea0c0103e80c010 +39210068f9210088 +6294080c7f39f830 +7b33002062b50810 +f92100903bc00000 +3ba000003b000000 +7ab500207a940020 +7fbeeb7848000054 +419e029c2f9d000f +612900143d20c010 7c0004ac79290020 -3d20c0107f604f2a -79290020612908b0 +3d00c0107e604f2a +6108002439400001 +7c0004ac79080020 +394000007d40472a +7d404f2a7c0004ac +7f78db783bbd0001 +394100607fbd07b4 +3920002a39000004 +38e000047d5a5378 +7ce903a638c00000 +7927f8423ca08020 +792907e060a50003 +78a500207d2900d0 +7d273a787d292838 +7cea31ae78e90020 +4200ffd438c60001 +394a00043908ffff +4082ffb879080021 +7c0004ac3b600000 +7c0004ac7f60a72a +386000097f60af2a +3860000f4bfff521 +3c60c0104bfff555 +606308147f44d378 +4bfff64178630020 +3c60c010e8810088 +786300206063082c +e88100904bfff62d +606308443c60c010 +4bfff61978630020 +3881006c3c60c010 +786300206063085c +3d20c0104bfff605 +7929002061290854 7f604f2a7c0004ac -392000173d40c010 -794a0020614a0898 -7d20572a7c0004ac -392000013d40c010 -794a0020614a08a0 -7d20572a7c0004ac -612908783d20c010 +612908583d20c010 7c0004ac79290020 -3d20c0107f604f2a -7929002061290880 +3d40c0107f604f2a +614a084c39200017 +7c0004ac794a0020 +3d40c0107d20572a +614a085039200001 +7c0004ac794a0020 +3d20c0107d20572a +792900206129083c 7f604f2a7c0004ac -7fa5eb78e8610098 -3b4000207fe4fb78 -4bfff22d3b600000 -7fe3fb7860000000 -4bfff5194bfff485 -3a2000013860000f -394000004bfff44d -e881008079480fa4 -7c70402af94100a0 -e94100a04bfff581 -7d1650ae88fc0001 -409e00a07f883800 -88fc00037d1750ae -409e00907f883800 -2baa0010394a0004 -7e248b78409effc0 -4bfff1bd7de37b78 -3b5affff60000000 -4bfff45d7fe3fb78 -7f7b8a147b5a0021 -4082ff807f7b07b4 -4bfff1957dc37378 -3920000060000000 -7d20a72a7c0004ac -7d20af2a7c0004ac -4bfff3753860000b -4bfff3a93860000f -4bfff52d7fe3fb78 -4bfff15d7e439378 -7f98d80060000000 -7f1bc378419cfd70 -3a2000004bfffd6c -3c62ffff4bffff70 -7fe4fb787fc5f378 -4bfff12d38637ff8 -3d20c01060000000 -7929002061290028 -7f204f2a7c0004ac -394000013d00c010 -7908002061080040 -7d40472a7c0004ac -7c0004ac39400000 -7bde00207d404f2a -38de00013d00c010 -7cc903a661080048 -7908002039400001 -4200003438e00000 -3af7ffff7fe3fb78 -7e4393784bfff489 -4bfff0b53b9cffff -2f9f000160000000 -419e00283ad6ffff -4bfffc783be00001 -7e604f2a7c0004ac -7d40472a7c0004ac -7ce04f2a7c0004ac -382101404bffffb4 -48000c6038600001 -0100000000000000 -3c4c000100001280 -7c0802a638428f5c -38637fb03c62ffff -f821ff7148000c1d -3be000003f60c010 -7b7b0020637b1000 -600000004bfff039 -7fe0df2a7c0004ac -635a10083f40c010 -7c0004ac7b5a0020 -3fa0c0107fe0d72a -7bbd002063bd0818 -7fe0ef2a7c0004ac -63de08203fc0c010 -7c0004ac7bde0020 -3f80c0107fe0f72a -639c08003920000c -7c0004ac7b9c0020 -386000007d20e72a -4bfff2096063c350 -7fe0ef2a7c0004ac +612908403d20c010 +7c0004ac79290020 +e86100987f604f2a +7fe4fb787fa5eb78 +3b6000003b400020 +600000004bfff181 +4bfff4897fe3fb78 +3860000f4bfff51d +4bfff4513a200001 +79480fa439400000 +f94100a0e8810080 +4bfff5857c70402a +88fc0001e94100a0 +7f8838007d1650ae +7d1750ae409e00a0 +7f88380088fc0003 +394a0004409e0090 +409effc02baa0010 +7de37b787e248b78 +600000004bfff111 +7fe3fb783b5affff +7b5a00214bfff461 +7f7b07b47f7b8a14 +7dc373784082ff80 +600000004bfff0e9 +7c0004ac39200000 +7c0004ac7d20a72a +3860000b7d20af2a +3860000f4bfff379 +7fe3fb784bfff3ad +7e4393784bfff531 +600000004bfff0b1 +419cfd707f98d800 +4bfffd6c7f1bc378 +4bffff703a200000 +7fc5f3783c62ffff +38637f707fe4fb78 +600000004bfff081 +612900143d20c010 +7c0004ac79290020 +3d00c0107f204f2a +6108002039400001 +7c0004ac79080020 +394000007d40472a +7d404f2a7c0004ac +3d00c0107bde0020 +6108002438de0001 +394000017cc903a6 +38e0000079080020 +7fe3fb7842000034 +4bfff48d3af7ffff +3b9cffff7e439378 +600000004bfff009 +3ad6ffff2f9f0001 +3be00001419e0028 +7c0004ac4bfffc78 +7c0004ac7e604f2a +7c0004ac7d40472a +4bffffb47ce04f2a +3860000138210140 +0000000048000ccc +0000128001000000 +384290b03c4c0001 +3c62ffff7c0802a6 +48000c8938637f28 +3f60c010f821ff71 +637b10003be00000 +4bffef8d7b7b0020 +7c0004ac60000000 +3f40c0107fe0df2a +7b5a0020635a1004 +7fe0d72a7c0004ac +63bd080c3fa0c010 +7c0004ac7bbd0020 +3fc0c0107fe0ef2a +7bde002063de0810 7fe0f72a7c0004ac -7c0004ac3920000e -386027107d20e72a -392002004bfff1e5 -7d20ef2a7c0004ac -7c0004ac39200002 -3860000f7d20f72a -7c0004ac4bfff189 -392000037fe0ef2a +3920000c3f80c010 +7b9c0020639c0800 +7d20e72a7c0004ac +6063c35038600000 +7c0004ac4bfff20d +7c0004ac7fe0ef2a +3920000e7fe0f72a +7d20e72a7c0004ac +4bfff1e938602710 +7c0004ac39200200 +392000027d20ef2a 7d20f72a7c0004ac -4bfff16d3860000f -7c0004ac39200006 -3b8000017d20ef2a -7f80f72a7c0004ac -4bfff14d3860000f -7c0004ac39200920 -7c0004ac7d20ef2a -3860000f7fe0f72a -386000c84bfff131 -392004004bfff165 +4bfff18d3860000f +7fe0ef2a7c0004ac +7c0004ac39200003 +3860000f7d20f72a +392000064bfff171 +7d20ef2a7c0004ac +7c0004ac3b800001 +3860000f7f80f72a +392009204bfff151 7d20ef2a7c0004ac 7fe0f72a7c0004ac -4bfff10d38600003 -4bfff141386000c8 -4bfff6cd4bfffa19 -2c2300004bfff721 -7c0004ac4082001c -7c0004ac7f80df2a -382100907f80d72a -7c0004ac48000af4 -386000017f80df2a -000000004bffffec -0000068001000000 -38428db03c4c0001 -600000003d20c000 -7929002061292000 -3d20c000f9228090 -7929002061290020 +4bfff1353860000f +4bfff169386000c8 +7c0004ac39200400 +7c0004ac7d20ef2a +386000037fe0f72a +386000c84bfff111 +4bfffa194bfff145 +4bfff7254bfff6d1 +4082001c2c230000 +7f80df2a7c0004ac +7f80d72a7c0004ac +48000b6038210090 +7f80df2a7c0004ac +4bffffec38600001 +0100000000000000 +3c4c000100000680 +3d20c00038428f04 +6129200060000000 +f922800879290020 +612900203d20c000 +7c0004ac79290020 +3d40001c7d204eea +7d295392614a2000 +394a0018e9428008 +7c0004ac3929ffff +4e8000207d2057ea +0000000000000000 +3c4c000100000000 +6000000038428ea4 +39290010e9228008 7d204eea7c0004ac -614a20003d40001c -e94280907d295392 -3929ffff394a0018 +4082ffe871290008 +e94280085469063e 7d2057ea7c0004ac 000000004e800020 0000000000000000 -38428d503c4c0001 -e922809060000000 -7c0004ac39290010 -712900087d204eea -5469063e4082ffe8 -7c0004ace9428090 -4e8000207d2057ea -0000000000000000 -3c4c000100000000 -7c0802a638428d0c -fbe1fff8fbc1fff0 -f80100103bc3ffff -8ffe0001f821ffd1 -409e00102fbf0000 -3860000038210030 -2b9f000a48000a20 -3860000d409e000c -7fe3fb784bffff81 -4bffffd04bffff79 -0100000000000000 -2c24000000000280 -3881fff040820008 -f86400002b850024 -4d9d002038600000 -78c683e43cc00001 -e924000060c62600 -2b8a002089490000 -7cc75436419d002c -4082001470e80001 -409e00542fa50000 -4800005c38a0000a -f924000039290001 -2fa500004bffffcc -2b8a0030409e0038 -409e003c38a0000a -2f8a007889490001 -89490001409e0030 -2f8a007838a00010 -39290002409e0020 -48000014f9240000 -409e000c2f850010 -419effd82b8a0030 -4800003038600000 -54ca063e38c9ffd0 -419d00342b8a0009 -7f8928007cc90734 -38e700014c9c0020 -f8e400007c6519d2 -e8e400007c691a14 -2fa9000089270000 -4e800020409effc8 -554a063e3949ff9f -419d00102b8a0019 -7d2907343929ffa9 -3949ffbf4bffffbc +38428e603c4c0001 +fbc1fff07c0802a6 +3bc3fffffbe1fff8 +f821ffd1f8010010 +2fbf00008ffe0001 +38210030409e0010 +48000a8c38600000 +409e000c2b9f000a +4bffff813860000d +4bffff797fe3fb78 +000000004bffffd0 +0000028001000000 +408200082c240000 +2b8500243881fff0 +38600000f8640000 +3cc000014d9d0020 +60c6260078c683e4 +89490000e9240000 +419d002c2b8a0020 +70e800017cc75436 +2fa5000040820014 +38a0000a409e0054 +392900014800005c +4bffffccf9240000 +409e00382fa50000 +38a0000a2b8a0030 +89490001409e003c +409e00302f8a0078 +38a0001089490001 +409e00202f8a0078 +f924000039290002 +2f85001048000014 +2b8a0030409e000c +38600000419effd8 +38c9ffd048000030 +2b8a000954ca063e +7cc90734419d0034 +4c9c00207f892800 +7c6519d238e70001 +7c691a14f8e40000 +89270000e8e40000 +409effc82fa90000 +3949ff9f4e800020 2b8a0019554a063e -3929ffc94d9d0020 -000000004bffffe4 -0000000000000000 -7d4348ae39200000 -409e000c2f8a0000 -4e8000207d234b78 -4bffffe839290001 +3929ffa9419d0010 +4bffffbc7d290734 +554a063e3949ffbf +4d9d00202b8a0019 +4bffffe43929ffc9 +0000000000000000 +3920000000000000 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 +0000000000000000 +3900000078aae8c2 +7d2903a6392a0001 +78a9e8c242000030 +1d29fff8792a1f24 +7c8452147d035214 +392000007ca92a14 +7d4903a639450001 +4e80002042000018 +7d23412a7d24402a +4bffffc439080008 +7d4849ae7d4448ae +4bffffdc39290001 0000000000000000 3923ff9f00000000 4d9d00202b890019 7c6307b43863ffe0 000000004e800020 0000000000000000 -38428b283c4c0001 +38428c103c4c0001 3d2037367c0802a6 612935347d908026 65293332792907c6 @@ -1179,12 +1214,12 @@ fbfd00007fe9fa14 4bfffff07d29f392 0300000000000000 3c4c000100000580 -7c0802a638428a1c +7c0802a638428b04 f821ffb1480006e9 7c7f1b78eb630000 7cbd2b787c9c2378 7fa3eb783bc00000 -600000004bfffe79 +600000004bfffe0d 409d00147fa3f040 7d3b5050e95f0000 419c00107fa9e040 @@ -1195,14 +1230,14 @@ f821ffb1480006e9 4bffffb8f93f0000 0100000000000000 3c4c000100000580 -7c0802a63842899c +7c0802a638428a84 f821ffa148000661 7c9b23787c7d1b78 388000007ca32b78 7cde337838a0000a 7cfc3b78eb5d0000 7d3f4b787d194378 -600000004bfffcb5 +600000004bfffc49 7c6307b439400000 409e006c2fbe0000 409e00082faa0000 @@ -1226,16 +1261,16 @@ e95d00009b270000 f95d0000394a0001 000000004bffffa8 0000078001000000 -384288a03c4c0001 +384289883c4c0001 480005397c0802a6 7c741b79f821fed1 38600000f8610060 2fa4000041820068 39210040419e0060 -3ac4ffff60000000 +3ac4ffff3e42ffff f92100703b410020 3ae0000060000000 -3a42804039228088 +3a527fb839228000 f92100783ba10060 ebc1006089250000 419e00102fa90000 @@ -1363,9 +1398,9 @@ e88100604bfffb35 38a0000a7d21e214 f9410088f9010090 7f43d37838800000 -4bfff7a99ae90020 +4bfff73d9ae90020 f861008060000000 -4bfff8cd7f63db78 +4bfff8617f63db78 e921008060000000 409d00407fa91840 e94100887c634850 @@ -1431,6 +1466,7 @@ e8010010ebc1fff0 0000000000000000 0000002054524155 000000204d415244 +000000204d415242 2020202020202020 203a4d4152422020 0a424b20646c6c25 @@ -1439,13 +1475,17 @@ e8010010ebc1fff0 203a4d4152442020 0a424d20646c6c25 0000000000000000 +4152442020202020 +203a54494e49204d +0a424b20646c6c25 +0000000000000000 2020202020202020 203a4b4c43202020 7a484d20646c6c25 000000000000000a -6138393331393333 +3163616539333236 0000000000000000 -0033306536316430 +0039326232623162 4d4152446574694c 6620746c69756220 6567694d206d6f72 @@ -1455,6 +1495,13 @@ e8010010ebc1fff0 20676e69746f6f42 415242206d6f7266 0000000a2e2e2e4d +20676e6979706f43 +2064616f6c796170 +2e4d415244206f74 +00000000000a2e2e +20676e69746f6f42 +415244206d6f7266 +0000000a2e2e2e4d 20747365746d654d 6c69616620737562 252f6425203a6465 @@ -1483,10 +1530,10 @@ e8010010ebc1fff0 000000000000002d 30252d2b64323025 0000000000006432 +00000000c0100818 00000000c0100830 +00000000c0100848 00000000c0100860 -00000000c0100890 -00000000c01008c0 6f6e204d41524453 207265646e752077 6572617764726168 diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v index 5a34a36..e135402 100644 --- a/litedram/generated/nexys-video/litedram_core.v +++ b/litedram/generated/nexys-video/litedram_core.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-21 19:21:29 +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:52 //-------------------------------------------------------------------------------- module litedram_core( input wire clk, @@ -540,7 +540,7 @@ reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; reg litedramcore_master_p3_rddata_en = 1'd0; wire [31:0] litedramcore_master_p3_rddata; wire litedramcore_master_p3_rddata_valid; -reg [3:0] litedramcore_storage = 4'd0; +reg [3:0] litedramcore_storage = 4'd1; reg litedramcore_re = 1'd0; reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; reg litedramcore_phaseinjector0_command_re = 1'd0; @@ -1607,7 +1607,7 @@ wire csrbank0_init_error0_re; wire csrbank0_init_error0_r; wire csrbank0_init_error0_we; wire csrbank0_init_error0_w; -reg csrbank0_sel = 1'd0; +wire csrbank0_sel; wire [13:0] interface1_bank_bus_adr; wire interface1_bank_bus_we; wire [31:0] interface1_bank_bus_dat_w; @@ -1624,7 +1624,7 @@ wire csrbank1_dly_sel0_re; wire [1:0] csrbank1_dly_sel0_r; wire csrbank1_dly_sel0_we; wire [1:0] csrbank1_dly_sel0_w; -reg csrbank1_sel = 1'd0; +wire csrbank1_sel; wire [13:0] interface2_bank_bus_adr; wire interface2_bank_bus_we; wire [31:0] interface2_bank_bus_dat_w; @@ -1713,7 +1713,7 @@ wire csrbank2_dfii_pi3_rddata_re; wire [31:0] csrbank2_dfii_pi3_rddata_r; wire csrbank2_dfii_pi3_rddata_we; wire [31:0] csrbank2_dfii_pi3_rddata_w; -reg csrbank2_sel = 1'd0; +wire csrbank2_sel; wire [13:0] adr; wire we; wire [31:0] dat_w; @@ -1857,13 +1857,13 @@ end reg dummy_d_1; // synthesis translate_on always @(*) begin - litedramcore_adr <= 14'd0; + litedramcore_we <= 1'd0; case (state) 1'd1: begin end default: begin if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_adr <= litedramcore_wishbone_adr; + litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); end end endcase @@ -1876,14 +1876,12 @@ end reg dummy_d_2; // synthesis translate_on always @(*) begin - litedramcore_we <= 1'd0; + litedramcore_wishbone_ack <= 1'd0; case (state) 1'd1: begin + litedramcore_wishbone_ack <= 1'd1; end default: begin - if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin - litedramcore_we <= litedramcore_wishbone_we; - end end endcase // synthesis translate_off @@ -1895,12 +1893,14 @@ end reg dummy_d_3; // synthesis translate_on always @(*) begin - litedramcore_wishbone_ack <= 1'd0; + litedramcore_adr <= 14'd0; case (state) 1'd1: begin - litedramcore_wishbone_ack <= 1'd1; end default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr <= litedramcore_wishbone_adr; + end end endcase // synthesis translate_off @@ -3235,65 +3235,6 @@ assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; // synthesis translate_off reg dummy_d_26; // synthesis translate_on -always @(*) begin - litedramcore_master_p1_wrdata_en <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; - end else begin - litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; - end -// synthesis translate_off - dummy_d_26 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_27; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p2_rddata_valid <= 1'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; - end -// synthesis translate_off - dummy_d_27 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_28; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_wrdata_mask <= 4'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; - end else begin - litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; - end -// synthesis translate_off - dummy_d_28 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_29; -// synthesis translate_on -always @(*) begin - litedramcore_master_p1_rddata_en <= 1'd0; - if (litedramcore_storage[0]) begin - litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; - end else begin - litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; - end -// synthesis translate_off - dummy_d_29 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_30; -// synthesis translate_on always @(*) begin litedramcore_master_p2_address <= 15'd0; if (litedramcore_storage[0]) begin @@ -3302,12 +3243,12 @@ always @(*) begin litedramcore_master_p2_address <= litedramcore_inti_p2_address; end // synthesis translate_off - dummy_d_30 = dummy_s; + dummy_d_26 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_31; +reg dummy_d_27; // synthesis translate_on always @(*) begin litedramcore_master_p2_bank <= 3'd0; @@ -3317,12 +3258,12 @@ always @(*) begin litedramcore_master_p2_bank <= litedramcore_inti_p2_bank; end // synthesis translate_off - dummy_d_31 = dummy_s; + dummy_d_27 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_32; +reg dummy_d_28; // synthesis translate_on always @(*) begin litedramcore_master_p2_cas_n <= 1'd1; @@ -3332,12 +3273,12 @@ always @(*) begin litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n; end // synthesis translate_off - dummy_d_32 = dummy_s; + dummy_d_28 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_33; +reg dummy_d_29; // synthesis translate_on always @(*) begin litedramcore_master_p2_cs_n <= 1'd1; @@ -3347,12 +3288,12 @@ always @(*) begin litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n; end // synthesis translate_off - dummy_d_33 = dummy_s; + dummy_d_29 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_34; +reg dummy_d_30; // synthesis translate_on always @(*) begin litedramcore_master_p2_ras_n <= 1'd1; @@ -3362,12 +3303,12 @@ always @(*) begin litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n; end // synthesis translate_off - dummy_d_34 = dummy_s; + dummy_d_30 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_35; +reg dummy_d_31; // synthesis translate_on always @(*) begin litedramcore_slave_p2_rddata <= 32'd0; @@ -3376,12 +3317,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_35 = dummy_s; + dummy_d_31 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_36; +reg dummy_d_32; // synthesis translate_on always @(*) begin litedramcore_master_p2_we_n <= 1'd1; @@ -3391,12 +3332,12 @@ always @(*) begin litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n; end // synthesis translate_off - dummy_d_36 = dummy_s; + dummy_d_32 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_37; +reg dummy_d_33; // synthesis translate_on always @(*) begin litedramcore_slave_p2_rddata_valid <= 1'd0; @@ -3405,12 +3346,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_37 = dummy_s; + dummy_d_33 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_38; +reg dummy_d_34; // synthesis translate_on always @(*) begin litedramcore_master_p2_cke <= 1'd0; @@ -3420,26 +3361,12 @@ always @(*) begin litedramcore_master_p2_cke <= litedramcore_inti_p2_cke; end // synthesis translate_off - dummy_d_38 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_39; -// synthesis translate_on -always @(*) begin - litedramcore_inti_p2_rddata <= 32'd0; - if (litedramcore_storage[0]) begin - end else begin - litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; - end -// synthesis translate_off - dummy_d_39 = dummy_s; + dummy_d_34 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_40; +reg dummy_d_35; // synthesis translate_on always @(*) begin litedramcore_master_p2_odt <= 1'd0; @@ -3449,12 +3376,12 @@ always @(*) begin litedramcore_master_p2_odt <= litedramcore_inti_p2_odt; end // synthesis translate_off - dummy_d_40 = dummy_s; + dummy_d_35 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_41; +reg dummy_d_36; // synthesis translate_on always @(*) begin litedramcore_master_p2_reset_n <= 1'd0; @@ -3464,12 +3391,12 @@ always @(*) begin litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n; end // synthesis translate_off - dummy_d_41 = dummy_s; + dummy_d_36 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_42; +reg dummy_d_37; // synthesis translate_on always @(*) begin litedramcore_master_p2_act_n <= 1'd1; @@ -3479,12 +3406,12 @@ always @(*) begin litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n; end // synthesis translate_off - dummy_d_42 = dummy_s; + dummy_d_37 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_43; +reg dummy_d_38; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata <= 32'd0; @@ -3494,12 +3421,12 @@ always @(*) begin litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata; end // synthesis translate_off - dummy_d_43 = dummy_s; + dummy_d_38 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_44; +reg dummy_d_39; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata <= 32'd0; @@ -3508,12 +3435,12 @@ always @(*) begin litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata; end // synthesis translate_off - dummy_d_44 = dummy_s; + dummy_d_39 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_45; +reg dummy_d_40; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_en <= 1'd0; @@ -3523,12 +3450,12 @@ always @(*) begin litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en; end // synthesis translate_off - dummy_d_45 = dummy_s; + dummy_d_40 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_46; +reg dummy_d_41; // synthesis translate_on always @(*) begin litedramcore_inti_p3_rddata_valid <= 1'd0; @@ -3537,12 +3464,12 @@ always @(*) begin litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid; end // synthesis translate_off - dummy_d_46 = dummy_s; + dummy_d_41 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_47; +reg dummy_d_42; // synthesis translate_on always @(*) begin litedramcore_master_p2_wrdata_mask <= 4'd0; @@ -3552,12 +3479,12 @@ always @(*) begin litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask; end // synthesis translate_off - dummy_d_47 = dummy_s; + dummy_d_42 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_48; +reg dummy_d_43; // synthesis translate_on always @(*) begin litedramcore_master_p2_rddata_en <= 1'd0; @@ -3567,12 +3494,12 @@ always @(*) begin litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en; end // synthesis translate_off - dummy_d_48 = dummy_s; + dummy_d_43 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_49; +reg dummy_d_44; // synthesis translate_on always @(*) begin litedramcore_master_p3_address <= 15'd0; @@ -3582,12 +3509,12 @@ always @(*) begin litedramcore_master_p3_address <= litedramcore_inti_p3_address; end // synthesis translate_off - dummy_d_49 = dummy_s; + dummy_d_44 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_50; +reg dummy_d_45; // synthesis translate_on always @(*) begin litedramcore_master_p3_bank <= 3'd0; @@ -3597,12 +3524,12 @@ always @(*) begin litedramcore_master_p3_bank <= litedramcore_inti_p3_bank; end // synthesis translate_off - dummy_d_50 = dummy_s; + dummy_d_45 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_51; +reg dummy_d_46; // synthesis translate_on always @(*) begin litedramcore_master_p3_cas_n <= 1'd1; @@ -3612,12 +3539,12 @@ always @(*) begin litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n; end // synthesis translate_off - dummy_d_51 = dummy_s; + dummy_d_46 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_52; +reg dummy_d_47; // synthesis translate_on always @(*) begin litedramcore_master_p3_cs_n <= 1'd1; @@ -3627,12 +3554,12 @@ always @(*) begin litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n; end // synthesis translate_off - dummy_d_52 = dummy_s; + dummy_d_47 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_53; +reg dummy_d_48; // synthesis translate_on always @(*) begin litedramcore_master_p3_ras_n <= 1'd1; @@ -3642,12 +3569,12 @@ always @(*) begin litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n; end // synthesis translate_off - dummy_d_53 = dummy_s; + dummy_d_48 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_54; +reg dummy_d_49; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata <= 32'd0; @@ -3656,12 +3583,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_54 = dummy_s; + dummy_d_49 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_55; +reg dummy_d_50; // synthesis translate_on always @(*) begin litedramcore_master_p3_we_n <= 1'd1; @@ -3671,12 +3598,12 @@ always @(*) begin litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n; end // synthesis translate_off - dummy_d_55 = dummy_s; + dummy_d_50 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_56; +reg dummy_d_51; // synthesis translate_on always @(*) begin litedramcore_slave_p3_rddata_valid <= 1'd0; @@ -3685,12 +3612,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_56 = dummy_s; + dummy_d_51 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_57; +reg dummy_d_52; // synthesis translate_on always @(*) begin litedramcore_master_p3_cke <= 1'd0; @@ -3700,12 +3627,12 @@ always @(*) begin litedramcore_master_p3_cke <= litedramcore_inti_p3_cke; end // synthesis translate_off - dummy_d_57 = dummy_s; + dummy_d_52 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_58; +reg dummy_d_53; // synthesis translate_on always @(*) begin litedramcore_master_p3_odt <= 1'd0; @@ -3715,12 +3642,12 @@ always @(*) begin litedramcore_master_p3_odt <= litedramcore_inti_p3_odt; end // synthesis translate_off - dummy_d_58 = dummy_s; + dummy_d_53 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_59; +reg dummy_d_54; // synthesis translate_on always @(*) begin litedramcore_master_p3_reset_n <= 1'd0; @@ -3730,12 +3657,12 @@ always @(*) begin litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n; end // synthesis translate_off - dummy_d_59 = dummy_s; + dummy_d_54 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_60; +reg dummy_d_55; // synthesis translate_on always @(*) begin litedramcore_master_p3_act_n <= 1'd1; @@ -3745,12 +3672,12 @@ always @(*) begin litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n; end // synthesis translate_off - dummy_d_60 = dummy_s; + dummy_d_55 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_61; +reg dummy_d_56; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata <= 32'd0; @@ -3760,12 +3687,12 @@ always @(*) begin litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata; end // synthesis translate_off - dummy_d_61 = dummy_s; + dummy_d_56 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_62; +reg dummy_d_57; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata <= 32'd0; @@ -3774,12 +3701,12 @@ always @(*) begin litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata; end // synthesis translate_off - dummy_d_62 = dummy_s; + dummy_d_57 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_63; +reg dummy_d_58; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_en <= 1'd0; @@ -3789,12 +3716,12 @@ always @(*) begin litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en; end // synthesis translate_off - dummy_d_63 = dummy_s; + dummy_d_58 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_64; +reg dummy_d_59; // synthesis translate_on always @(*) begin litedramcore_inti_p0_rddata_valid <= 1'd0; @@ -3803,12 +3730,12 @@ always @(*) begin litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid; end // synthesis translate_off - dummy_d_64 = dummy_s; + dummy_d_59 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_65; +reg dummy_d_60; // synthesis translate_on always @(*) begin litedramcore_master_p3_wrdata_mask <= 4'd0; @@ -3818,12 +3745,12 @@ always @(*) begin litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask; end // synthesis translate_off - dummy_d_65 = dummy_s; + dummy_d_60 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_66; +reg dummy_d_61; // synthesis translate_on always @(*) begin litedramcore_master_p3_rddata_en <= 1'd0; @@ -3833,12 +3760,12 @@ always @(*) begin litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en; end // synthesis translate_off - dummy_d_66 = dummy_s; + dummy_d_61 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_67; +reg dummy_d_62; // synthesis translate_on always @(*) begin litedramcore_master_p0_address <= 15'd0; @@ -3848,12 +3775,12 @@ always @(*) begin litedramcore_master_p0_address <= litedramcore_inti_p0_address; end // synthesis translate_off - dummy_d_67 = dummy_s; + dummy_d_62 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_68; +reg dummy_d_63; // synthesis translate_on always @(*) begin litedramcore_master_p0_bank <= 3'd0; @@ -3863,12 +3790,12 @@ always @(*) begin litedramcore_master_p0_bank <= litedramcore_inti_p0_bank; end // synthesis translate_off - dummy_d_68 = dummy_s; + dummy_d_63 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_69; +reg dummy_d_64; // synthesis translate_on always @(*) begin litedramcore_master_p0_cas_n <= 1'd1; @@ -3878,12 +3805,12 @@ always @(*) begin litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n; end // synthesis translate_off - dummy_d_69 = dummy_s; + dummy_d_64 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_70; +reg dummy_d_65; // synthesis translate_on always @(*) begin litedramcore_master_p0_cs_n <= 1'd1; @@ -3893,12 +3820,12 @@ always @(*) begin litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n; end // synthesis translate_off - dummy_d_70 = dummy_s; + dummy_d_65 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_71; +reg dummy_d_66; // synthesis translate_on always @(*) begin litedramcore_master_p0_ras_n <= 1'd1; @@ -3908,12 +3835,12 @@ always @(*) begin litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n; end // synthesis translate_off - dummy_d_71 = dummy_s; + dummy_d_66 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_72; +reg dummy_d_67; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata <= 32'd0; @@ -3922,12 +3849,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_72 = dummy_s; + dummy_d_67 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_73; +reg dummy_d_68; // synthesis translate_on always @(*) begin litedramcore_master_p0_we_n <= 1'd1; @@ -3937,12 +3864,12 @@ always @(*) begin litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n; end // synthesis translate_off - dummy_d_73 = dummy_s; + dummy_d_68 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_74; +reg dummy_d_69; // synthesis translate_on always @(*) begin litedramcore_slave_p0_rddata_valid <= 1'd0; @@ -3951,12 +3878,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_74 = dummy_s; + dummy_d_69 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_75; +reg dummy_d_70; // synthesis translate_on always @(*) begin litedramcore_master_p0_cke <= 1'd0; @@ -3966,12 +3893,12 @@ always @(*) begin litedramcore_master_p0_cke <= litedramcore_inti_p0_cke; end // synthesis translate_off - dummy_d_75 = dummy_s; + dummy_d_70 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_76; +reg dummy_d_71; // synthesis translate_on always @(*) begin litedramcore_master_p0_odt <= 1'd0; @@ -3981,12 +3908,12 @@ always @(*) begin litedramcore_master_p0_odt <= litedramcore_inti_p0_odt; end // synthesis translate_off - dummy_d_76 = dummy_s; + dummy_d_71 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_77; +reg dummy_d_72; // synthesis translate_on always @(*) begin litedramcore_master_p0_reset_n <= 1'd0; @@ -3996,12 +3923,12 @@ always @(*) begin litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n; end // synthesis translate_off - dummy_d_77 = dummy_s; + dummy_d_72 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_78; +reg dummy_d_73; // synthesis translate_on always @(*) begin litedramcore_master_p0_act_n <= 1'd1; @@ -4011,12 +3938,12 @@ always @(*) begin litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n; end // synthesis translate_off - dummy_d_78 = dummy_s; + dummy_d_73 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_79; +reg dummy_d_74; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata <= 32'd0; @@ -4026,12 +3953,12 @@ always @(*) begin litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata; end // synthesis translate_off - dummy_d_79 = dummy_s; + dummy_d_74 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_80; +reg dummy_d_75; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata <= 32'd0; @@ -4040,12 +3967,12 @@ always @(*) begin litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata; end // synthesis translate_off - dummy_d_80 = dummy_s; + dummy_d_75 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_81; +reg dummy_d_76; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_en <= 1'd0; @@ -4055,12 +3982,12 @@ always @(*) begin litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en; end // synthesis translate_off - dummy_d_81 = dummy_s; + dummy_d_76 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_82; +reg dummy_d_77; // synthesis translate_on always @(*) begin litedramcore_inti_p1_rddata_valid <= 1'd0; @@ -4069,12 +3996,12 @@ always @(*) begin litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid; end // synthesis translate_off - dummy_d_82 = dummy_s; + dummy_d_77 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_83; +reg dummy_d_78; // synthesis translate_on always @(*) begin litedramcore_master_p0_wrdata_mask <= 4'd0; @@ -4084,12 +4011,12 @@ always @(*) begin litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask; end // synthesis translate_off - dummy_d_83 = dummy_s; + dummy_d_78 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_84; +reg dummy_d_79; // synthesis translate_on always @(*) begin litedramcore_master_p0_rddata_en <= 1'd0; @@ -4099,12 +4026,12 @@ always @(*) begin litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en; end // synthesis translate_off - dummy_d_84 = dummy_s; + dummy_d_79 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_85; +reg dummy_d_80; // synthesis translate_on always @(*) begin litedramcore_master_p1_address <= 15'd0; @@ -4114,12 +4041,12 @@ always @(*) begin litedramcore_master_p1_address <= litedramcore_inti_p1_address; end // synthesis translate_off - dummy_d_85 = dummy_s; + dummy_d_80 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_86; +reg dummy_d_81; // synthesis translate_on always @(*) begin litedramcore_master_p1_bank <= 3'd0; @@ -4129,12 +4056,12 @@ always @(*) begin litedramcore_master_p1_bank <= litedramcore_inti_p1_bank; end // synthesis translate_off - dummy_d_86 = dummy_s; + dummy_d_81 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_87; +reg dummy_d_82; // synthesis translate_on always @(*) begin litedramcore_master_p1_cas_n <= 1'd1; @@ -4144,12 +4071,12 @@ always @(*) begin litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n; end // synthesis translate_off - dummy_d_87 = dummy_s; + dummy_d_82 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_88; +reg dummy_d_83; // synthesis translate_on always @(*) begin litedramcore_master_p1_cs_n <= 1'd1; @@ -4159,12 +4086,12 @@ always @(*) begin litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n; end // synthesis translate_off - dummy_d_88 = dummy_s; + dummy_d_83 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_89; +reg dummy_d_84; // synthesis translate_on always @(*) begin litedramcore_master_p1_ras_n <= 1'd1; @@ -4174,12 +4101,12 @@ always @(*) begin litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n; end // synthesis translate_off - dummy_d_89 = dummy_s; + dummy_d_84 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_90; +reg dummy_d_85; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata <= 32'd0; @@ -4188,12 +4115,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_90 = dummy_s; + dummy_d_85 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_91; +reg dummy_d_86; // synthesis translate_on always @(*) begin litedramcore_master_p1_we_n <= 1'd1; @@ -4203,12 +4130,12 @@ always @(*) begin litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n; end // synthesis translate_off - dummy_d_91 = dummy_s; + dummy_d_86 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_92; +reg dummy_d_87; // synthesis translate_on always @(*) begin litedramcore_slave_p1_rddata_valid <= 1'd0; @@ -4217,12 +4144,12 @@ always @(*) begin end else begin end // synthesis translate_off - dummy_d_92 = dummy_s; + dummy_d_87 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_93; +reg dummy_d_88; // synthesis translate_on always @(*) begin litedramcore_master_p1_cke <= 1'd0; @@ -4232,12 +4159,26 @@ always @(*) begin litedramcore_master_p1_cke <= litedramcore_inti_p1_cke; end // synthesis translate_off - dummy_d_93 = dummy_s; + dummy_d_88 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_94; +reg dummy_d_89; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p2_rddata <= 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata; + end +// synthesis translate_off + dummy_d_89 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_90; // synthesis translate_on always @(*) begin litedramcore_master_p1_odt <= 1'd0; @@ -4247,12 +4188,12 @@ always @(*) begin litedramcore_master_p1_odt <= litedramcore_inti_p1_odt; end // synthesis translate_off - dummy_d_94 = dummy_s; + dummy_d_90 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_95; +reg dummy_d_91; // synthesis translate_on always @(*) begin litedramcore_master_p1_reset_n <= 1'd0; @@ -4262,12 +4203,12 @@ always @(*) begin litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n; end // synthesis translate_off - dummy_d_95 = dummy_s; + dummy_d_91 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_96; +reg dummy_d_92; // synthesis translate_on always @(*) begin litedramcore_master_p1_act_n <= 1'd1; @@ -4277,12 +4218,12 @@ always @(*) begin litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n; end // synthesis translate_off - dummy_d_96 = dummy_s; + dummy_d_92 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_97; +reg dummy_d_93; // synthesis translate_on always @(*) begin litedramcore_master_p1_wrdata <= 32'd0; @@ -4291,6 +4232,65 @@ always @(*) begin end else begin litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata; end +// synthesis translate_off + dummy_d_93 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_94; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en; + end +// synthesis translate_off + dummy_d_94 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_95; +// synthesis translate_on +always @(*) begin + litedramcore_inti_p2_rddata_valid <= 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid; + end +// synthesis translate_off + dummy_d_95 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_96; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_wrdata_mask <= 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask; + end +// synthesis translate_off + dummy_d_96 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_97; +// synthesis translate_on +always @(*) begin + litedramcore_master_p1_rddata_en <= 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en; + end // synthesis translate_off dummy_d_97 = dummy_s; // synthesis translate_on @@ -4312,11 +4312,11 @@ assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; reg dummy_d_98; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cs_n <= 1'd1; + litedramcore_inti_p0_cas_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); end else begin - litedramcore_inti_p0_cs_n <= {1{1'd1}}; + litedramcore_inti_p0_cas_n <= 1'd1; end // synthesis translate_off dummy_d_98 = dummy_s; @@ -4327,11 +4327,11 @@ end reg dummy_d_99; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); + litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}}; end else begin - litedramcore_inti_p0_ras_n <= 1'd1; + litedramcore_inti_p0_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_99 = dummy_s; @@ -4342,11 +4342,11 @@ end reg dummy_d_100; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); + litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]); end else begin - litedramcore_inti_p0_we_n <= 1'd1; + litedramcore_inti_p0_ras_n <= 1'd1; end // synthesis translate_off dummy_d_100 = dummy_s; @@ -4357,11 +4357,11 @@ end reg dummy_d_101; // synthesis translate_on always @(*) begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; if (litedramcore_phaseinjector0_command_issue_re) begin - litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]); + litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]); end else begin - litedramcore_inti_p0_cas_n <= 1'd1; + litedramcore_inti_p0_we_n <= 1'd1; end // synthesis translate_off dummy_d_101 = dummy_s; @@ -4378,11 +4378,11 @@ assign litedramcore_inti_p0_wrdata_mask = 1'd0; reg dummy_d_102; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cs_n <= 1'd1; + litedramcore_inti_p1_cas_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); end else begin - litedramcore_inti_p1_cs_n <= {1{1'd1}}; + litedramcore_inti_p1_cas_n <= 1'd1; end // synthesis translate_off dummy_d_102 = dummy_s; @@ -4393,11 +4393,11 @@ end reg dummy_d_103; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); + litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}}; end else begin - litedramcore_inti_p1_ras_n <= 1'd1; + litedramcore_inti_p1_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_103 = dummy_s; @@ -4408,11 +4408,11 @@ end reg dummy_d_104; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); + litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]); end else begin - litedramcore_inti_p1_we_n <= 1'd1; + litedramcore_inti_p1_ras_n <= 1'd1; end // synthesis translate_off dummy_d_104 = dummy_s; @@ -4423,11 +4423,11 @@ end reg dummy_d_105; // synthesis translate_on always @(*) begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; if (litedramcore_phaseinjector1_command_issue_re) begin - litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]); + litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]); end else begin - litedramcore_inti_p1_cas_n <= 1'd1; + litedramcore_inti_p1_we_n <= 1'd1; end // synthesis translate_off dummy_d_105 = dummy_s; @@ -4444,11 +4444,11 @@ assign litedramcore_inti_p1_wrdata_mask = 1'd0; reg dummy_d_106; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cs_n <= 1'd1; + litedramcore_inti_p2_cas_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); end else begin - litedramcore_inti_p2_cs_n <= {1{1'd1}}; + litedramcore_inti_p2_cas_n <= 1'd1; end // synthesis translate_off dummy_d_106 = dummy_s; @@ -4459,11 +4459,11 @@ end reg dummy_d_107; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); + litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}}; end else begin - litedramcore_inti_p2_ras_n <= 1'd1; + litedramcore_inti_p2_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_107 = dummy_s; @@ -4474,11 +4474,11 @@ end reg dummy_d_108; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); + litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]); end else begin - litedramcore_inti_p2_we_n <= 1'd1; + litedramcore_inti_p2_ras_n <= 1'd1; end // synthesis translate_off dummy_d_108 = dummy_s; @@ -4489,11 +4489,11 @@ end reg dummy_d_109; // synthesis translate_on always @(*) begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; if (litedramcore_phaseinjector2_command_issue_re) begin - litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]); + litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]); end else begin - litedramcore_inti_p2_cas_n <= 1'd1; + litedramcore_inti_p2_we_n <= 1'd1; end // synthesis translate_off dummy_d_109 = dummy_s; @@ -4510,11 +4510,11 @@ assign litedramcore_inti_p2_wrdata_mask = 1'd0; reg dummy_d_110; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cs_n <= 1'd1; + litedramcore_inti_p3_cas_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); end else begin - litedramcore_inti_p3_cs_n <= {1{1'd1}}; + litedramcore_inti_p3_cas_n <= 1'd1; end // synthesis translate_off dummy_d_110 = dummy_s; @@ -4525,11 +4525,11 @@ end reg dummy_d_111; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); + litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}}; end else begin - litedramcore_inti_p3_ras_n <= 1'd1; + litedramcore_inti_p3_cs_n <= {1{1'd1}}; end // synthesis translate_off dummy_d_111 = dummy_s; @@ -4540,11 +4540,11 @@ end reg dummy_d_112; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); + litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]); end else begin - litedramcore_inti_p3_we_n <= 1'd1; + litedramcore_inti_p3_ras_n <= 1'd1; end // synthesis translate_off dummy_d_112 = dummy_s; @@ -4555,11 +4555,11 @@ end reg dummy_d_113; // synthesis translate_on always @(*) begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; if (litedramcore_phaseinjector3_command_issue_re) begin - litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]); + litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]); end else begin - litedramcore_inti_p3_cas_n <= 1'd1; + litedramcore_inti_p3_we_n <= 1'd1; end // synthesis translate_off dummy_d_113 = dummy_s; @@ -4948,39 +4948,6 @@ end // synthesis translate_off reg dummy_d_123; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine0_row_open <= 1'd0; - case (bankmachine0_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine0_trccon_ready) begin - litedramcore_bankmachine0_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_123 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_124; -// synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_close <= 1'd0; case (bankmachine0_state) @@ -5007,12 +4974,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_124 = dummy_s; + dummy_d_123 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_125; +reg dummy_d_124; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_cas <= 1'd0; @@ -5049,12 +5016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_125 = dummy_s; + dummy_d_124 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_126; +reg dummy_d_125; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_ras <= 1'd0; @@ -5085,12 +5052,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_126 = dummy_s; + dummy_d_125 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_127; +reg dummy_d_126; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_we <= 1'd0; @@ -5133,12 +5100,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_127 = dummy_s; + dummy_d_126 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_128; +reg dummy_d_127; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0; @@ -5166,12 +5133,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_128 = dummy_s; + dummy_d_127 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_129; +reg dummy_d_128; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0; @@ -5203,12 +5170,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_129 = dummy_s; + dummy_d_128 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_130; +reg dummy_d_129; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0; @@ -5248,12 +5215,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_130 = dummy_s; + dummy_d_129 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_131; +reg dummy_d_130; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0; @@ -5293,12 +5260,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_131 = dummy_s; + dummy_d_130 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_132; +reg dummy_d_131; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_wdata_ready <= 1'd0; @@ -5338,12 +5305,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_132 = dummy_s; + dummy_d_131 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_133; +reg dummy_d_132; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_req_rdata_valid <= 1'd0; @@ -5383,12 +5350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_133 = dummy_s; + dummy_d_132 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_134; +reg dummy_d_133; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_refresh_gnt <= 1'd0; @@ -5416,12 +5383,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_134 = dummy_s; + dummy_d_133 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_135; +reg dummy_d_134; // synthesis translate_on always @(*) begin litedramcore_bankmachine0_cmd_valid <= 1'd0; @@ -5463,6 +5430,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_134 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_135; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine0_row_open <= 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_135 = dummy_s; // synthesis translate_on @@ -5587,77 +5587,44 @@ always @(*) begin end end 3'd5: begin - bankmachine1_next_state <= 3'd6; - end - 3'd6: begin - bankmachine1_next_state <= 2'd3; - end - 3'd7: begin - bankmachine1_next_state <= 4'd8; - end - 4'd8: begin - bankmachine1_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine1_refresh_req) begin - bankmachine1_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine1_row_opened) begin - if (litedramcore_bankmachine1_row_hit) begin - if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin - bankmachine1_next_state <= 2'd2; - end - end else begin - bankmachine1_next_state <= 1'd1; - end - end else begin - bankmachine1_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_139 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_140; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine1_row_open <= 1'd0; - case (bankmachine1_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine1_trccon_ready) begin - litedramcore_bankmachine1_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin + bankmachine1_next_state <= 3'd6; end 3'd6: begin + bankmachine1_next_state <= 2'd3; end 3'd7: begin + bankmachine1_next_state <= 4'd8; end 4'd8: begin + bankmachine1_next_state <= 1'd0; end default: begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state <= 2'd2; + end + end else begin + bankmachine1_next_state <= 1'd1; + end + end else begin + bankmachine1_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_140 = dummy_s; + dummy_d_139 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_141; +reg dummy_d_140; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_close <= 1'd0; @@ -5685,12 +5652,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_141 = dummy_s; + dummy_d_140 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_142; +reg dummy_d_141; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_cas <= 1'd0; @@ -5727,12 +5694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_142 = dummy_s; + dummy_d_141 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_143; +reg dummy_d_142; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_ras <= 1'd0; @@ -5763,12 +5730,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_143 = dummy_s; + dummy_d_142 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_144; +reg dummy_d_143; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_we <= 1'd0; @@ -5811,12 +5778,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_144 = dummy_s; + dummy_d_143 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_145; +reg dummy_d_144; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0; @@ -5844,12 +5811,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_145 = dummy_s; + dummy_d_144 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_146; +reg dummy_d_145; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0; @@ -5881,12 +5848,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_146 = dummy_s; + dummy_d_145 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_147; +reg dummy_d_146; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0; @@ -5926,12 +5893,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_147 = dummy_s; + dummy_d_146 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_148; +reg dummy_d_147; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0; @@ -5971,12 +5938,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_148 = dummy_s; + dummy_d_147 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_149; +reg dummy_d_148; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_wdata_ready <= 1'd0; @@ -6016,12 +5983,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_149 = dummy_s; + dummy_d_148 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_150; +reg dummy_d_149; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_req_rdata_valid <= 1'd0; @@ -6061,12 +6028,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_150 = dummy_s; + dummy_d_149 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_151; +reg dummy_d_150; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_refresh_gnt <= 1'd0; @@ -6094,12 +6061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_151 = dummy_s; + dummy_d_150 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_152; +reg dummy_d_151; // synthesis translate_on always @(*) begin litedramcore_bankmachine1_cmd_valid <= 1'd0; @@ -6141,6 +6108,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_151 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_152; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine1_row_open <= 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_152 = dummy_s; // synthesis translate_on @@ -6304,39 +6304,6 @@ end // synthesis translate_off reg dummy_d_157; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine2_row_open <= 1'd0; - case (bankmachine2_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine2_trccon_ready) begin - litedramcore_bankmachine2_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_157 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_158; -// synthesis translate_on always @(*) begin litedramcore_bankmachine2_row_close <= 1'd0; case (bankmachine2_state) @@ -6363,12 +6330,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_158 = dummy_s; + dummy_d_157 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_159; +reg dummy_d_158; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_cas <= 1'd0; @@ -6405,12 +6372,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_159 = dummy_s; + dummy_d_158 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_160; +reg dummy_d_159; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_ras <= 1'd0; @@ -6441,12 +6408,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_160 = dummy_s; + dummy_d_159 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_161; +reg dummy_d_160; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_we <= 1'd0; @@ -6489,12 +6456,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_161 = dummy_s; + dummy_d_160 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_162; +reg dummy_d_161; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0; @@ -6522,12 +6489,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_162 = dummy_s; + dummy_d_161 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_163; +reg dummy_d_162; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0; @@ -6559,12 +6526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_163 = dummy_s; + dummy_d_162 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_164; +reg dummy_d_163; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0; @@ -6604,12 +6571,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_164 = dummy_s; + dummy_d_163 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_165; +reg dummy_d_164; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0; @@ -6649,12 +6616,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_165 = dummy_s; + dummy_d_164 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_166; +reg dummy_d_165; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_wdata_ready <= 1'd0; @@ -6694,12 +6661,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_166 = dummy_s; + dummy_d_165 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_167; +reg dummy_d_166; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_req_rdata_valid <= 1'd0; @@ -6739,12 +6706,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_167 = dummy_s; + dummy_d_166 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_168; +reg dummy_d_167; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_refresh_gnt <= 1'd0; @@ -6772,12 +6739,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_168 = dummy_s; + dummy_d_167 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_169; +reg dummy_d_168; // synthesis translate_on always @(*) begin litedramcore_bankmachine2_cmd_valid <= 1'd0; @@ -6819,6 +6786,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_168 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_169; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine2_row_open <= 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_169 = dummy_s; // synthesis translate_on @@ -6961,59 +6961,26 @@ always @(*) begin if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin if (litedramcore_bankmachine3_row_opened) begin if (litedramcore_bankmachine3_row_hit) begin - if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin - bankmachine3_next_state <= 2'd2; - end - end else begin - bankmachine3_next_state <= 1'd1; - end - end else begin - bankmachine3_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_173 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_174; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine3_row_open <= 1'd0; - case (bankmachine3_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine3_trccon_ready) begin - litedramcore_bankmachine3_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state <= 2'd2; + end + end else begin + bankmachine3_next_state <= 1'd1; + end + end else begin + bankmachine3_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_174 = dummy_s; + dummy_d_173 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_175; +reg dummy_d_174; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_close <= 1'd0; @@ -7041,12 +7008,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_175 = dummy_s; + dummy_d_174 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_176; +reg dummy_d_175; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_cas <= 1'd0; @@ -7083,12 +7050,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_176 = dummy_s; + dummy_d_175 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_177; +reg dummy_d_176; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_ras <= 1'd0; @@ -7119,12 +7086,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_177 = dummy_s; + dummy_d_176 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_178; +reg dummy_d_177; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_we <= 1'd0; @@ -7167,12 +7134,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_178 = dummy_s; + dummy_d_177 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_179; +reg dummy_d_178; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0; @@ -7200,12 +7167,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_179 = dummy_s; + dummy_d_178 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_180; +reg dummy_d_179; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0; @@ -7237,12 +7204,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_180 = dummy_s; + dummy_d_179 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_181; +reg dummy_d_180; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0; @@ -7282,12 +7249,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_181 = dummy_s; + dummy_d_180 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_182; +reg dummy_d_181; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0; @@ -7327,12 +7294,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_182 = dummy_s; + dummy_d_181 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_183; +reg dummy_d_182; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_wdata_ready <= 1'd0; @@ -7372,12 +7339,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_183 = dummy_s; + dummy_d_182 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_184; +reg dummy_d_183; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_req_rdata_valid <= 1'd0; @@ -7417,12 +7384,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_184 = dummy_s; + dummy_d_183 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_185; +reg dummy_d_184; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_refresh_gnt <= 1'd0; @@ -7450,12 +7417,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_185 = dummy_s; + dummy_d_184 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_186; +reg dummy_d_185; // synthesis translate_on always @(*) begin litedramcore_bankmachine3_cmd_valid <= 1'd0; @@ -7497,6 +7464,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_185 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_186; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine3_row_open <= 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_186 = dummy_s; // synthesis translate_on @@ -7660,39 +7660,6 @@ end // synthesis translate_off reg dummy_d_191; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine4_row_open <= 1'd0; - case (bankmachine4_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine4_trccon_ready) begin - litedramcore_bankmachine4_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_191 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_192; -// synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_close <= 1'd0; case (bankmachine4_state) @@ -7719,12 +7686,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_192 = dummy_s; + dummy_d_191 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_193; +reg dummy_d_192; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_cas <= 1'd0; @@ -7761,12 +7728,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_193 = dummy_s; + dummy_d_192 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_194; +reg dummy_d_193; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_ras <= 1'd0; @@ -7797,12 +7764,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_194 = dummy_s; + dummy_d_193 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_195; +reg dummy_d_194; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_we <= 1'd0; @@ -7845,12 +7812,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_195 = dummy_s; + dummy_d_194 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_196; +reg dummy_d_195; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0; @@ -7878,12 +7845,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_196 = dummy_s; + dummy_d_195 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_197; +reg dummy_d_196; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0; @@ -7915,12 +7882,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_197 = dummy_s; + dummy_d_196 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_198; +reg dummy_d_197; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0; @@ -7960,12 +7927,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_198 = dummy_s; + dummy_d_197 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_199; +reg dummy_d_198; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0; @@ -8005,12 +7972,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_199 = dummy_s; + dummy_d_198 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_200; +reg dummy_d_199; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_wdata_ready <= 1'd0; @@ -8050,12 +8017,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_200 = dummy_s; + dummy_d_199 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_201; +reg dummy_d_200; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_req_rdata_valid <= 1'd0; @@ -8095,12 +8062,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_201 = dummy_s; + dummy_d_200 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_202; +reg dummy_d_201; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_refresh_gnt <= 1'd0; @@ -8128,12 +8095,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_202 = dummy_s; + dummy_d_201 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_203; +reg dummy_d_202; // synthesis translate_on always @(*) begin litedramcore_bankmachine4_cmd_valid <= 1'd0; @@ -8175,6 +8142,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_202 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_203; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine4_row_open <= 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_203 = dummy_s; // synthesis translate_on @@ -8299,77 +8299,44 @@ always @(*) begin end end 3'd5: begin - bankmachine5_next_state <= 3'd6; - end - 3'd6: begin - bankmachine5_next_state <= 2'd3; - end - 3'd7: begin - bankmachine5_next_state <= 4'd8; - end - 4'd8: begin - bankmachine5_next_state <= 1'd0; - end - default: begin - if (litedramcore_bankmachine5_refresh_req) begin - bankmachine5_next_state <= 3'd4; - end else begin - if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin - if (litedramcore_bankmachine5_row_opened) begin - if (litedramcore_bankmachine5_row_hit) begin - if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin - bankmachine5_next_state <= 2'd2; - end - end else begin - bankmachine5_next_state <= 1'd1; - end - end else begin - bankmachine5_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_207 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_208; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine5_row_open <= 1'd0; - case (bankmachine5_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine5_trccon_ready) begin - litedramcore_bankmachine5_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin + bankmachine5_next_state <= 3'd6; end 3'd6: begin + bankmachine5_next_state <= 2'd3; end 3'd7: begin + bankmachine5_next_state <= 4'd8; end 4'd8: begin + bankmachine5_next_state <= 1'd0; end default: begin + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state <= 3'd4; + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state <= 2'd2; + end + end else begin + bankmachine5_next_state <= 1'd1; + end + end else begin + bankmachine5_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_208 = dummy_s; + dummy_d_207 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_209; +reg dummy_d_208; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_close <= 1'd0; @@ -8397,12 +8364,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_209 = dummy_s; + dummy_d_208 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_210; +reg dummy_d_209; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_cas <= 1'd0; @@ -8439,12 +8406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_210 = dummy_s; + dummy_d_209 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_211; +reg dummy_d_210; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_ras <= 1'd0; @@ -8475,12 +8442,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_211 = dummy_s; + dummy_d_210 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_212; +reg dummy_d_211; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_we <= 1'd0; @@ -8523,12 +8490,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_212 = dummy_s; + dummy_d_211 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_213; +reg dummy_d_212; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0; @@ -8556,12 +8523,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_213 = dummy_s; + dummy_d_212 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_214; +reg dummy_d_213; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0; @@ -8593,12 +8560,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_214 = dummy_s; + dummy_d_213 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_215; +reg dummy_d_214; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0; @@ -8638,12 +8605,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_215 = dummy_s; + dummy_d_214 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_216; +reg dummy_d_215; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0; @@ -8683,12 +8650,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_216 = dummy_s; + dummy_d_215 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_217; +reg dummy_d_216; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_wdata_ready <= 1'd0; @@ -8728,12 +8695,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_217 = dummy_s; + dummy_d_216 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_218; +reg dummy_d_217; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_req_rdata_valid <= 1'd0; @@ -8773,12 +8740,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_218 = dummy_s; + dummy_d_217 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_219; +reg dummy_d_218; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_refresh_gnt <= 1'd0; @@ -8806,12 +8773,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_219 = dummy_s; + dummy_d_218 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_220; +reg dummy_d_219; // synthesis translate_on always @(*) begin litedramcore_bankmachine5_cmd_valid <= 1'd0; @@ -8853,6 +8820,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_219 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_220; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine5_row_open <= 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_220 = dummy_s; // synthesis translate_on @@ -9016,39 +9016,6 @@ end // synthesis translate_off reg dummy_d_225; // synthesis translate_on -always @(*) begin - litedramcore_bankmachine6_row_open <= 1'd0; - case (bankmachine6_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine6_trccon_ready) begin - litedramcore_bankmachine6_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin - end - endcase -// synthesis translate_off - dummy_d_225 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_226; -// synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_close <= 1'd0; case (bankmachine6_state) @@ -9075,12 +9042,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_226 = dummy_s; + dummy_d_225 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_227; +reg dummy_d_226; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_cas <= 1'd0; @@ -9117,12 +9084,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_227 = dummy_s; + dummy_d_226 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_228; +reg dummy_d_227; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_ras <= 1'd0; @@ -9153,12 +9120,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_228 = dummy_s; + dummy_d_227 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_229; +reg dummy_d_228; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_we <= 1'd0; @@ -9201,12 +9168,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_229 = dummy_s; + dummy_d_228 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_230; +reg dummy_d_229; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0; @@ -9234,12 +9201,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_230 = dummy_s; + dummy_d_229 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_231; +reg dummy_d_230; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0; @@ -9271,12 +9238,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_231 = dummy_s; + dummy_d_230 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_232; +reg dummy_d_231; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0; @@ -9316,12 +9283,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_232 = dummy_s; + dummy_d_231 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_233; +reg dummy_d_232; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0; @@ -9361,12 +9328,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_233 = dummy_s; + dummy_d_232 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_234; +reg dummy_d_233; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_wdata_ready <= 1'd0; @@ -9406,12 +9373,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_234 = dummy_s; + dummy_d_233 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_235; +reg dummy_d_234; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_req_rdata_valid <= 1'd0; @@ -9451,12 +9418,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_235 = dummy_s; + dummy_d_234 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_236; +reg dummy_d_235; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_refresh_gnt <= 1'd0; @@ -9484,12 +9451,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_236 = dummy_s; + dummy_d_235 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_237; +reg dummy_d_236; // synthesis translate_on always @(*) begin litedramcore_bankmachine6_cmd_valid <= 1'd0; @@ -9531,6 +9498,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_236 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_237; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine6_row_open <= 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_237 = dummy_s; // synthesis translate_on @@ -9673,59 +9673,26 @@ always @(*) begin if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin if (litedramcore_bankmachine7_row_opened) begin if (litedramcore_bankmachine7_row_hit) begin - if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin - bankmachine7_next_state <= 2'd2; - end - end else begin - bankmachine7_next_state <= 1'd1; - end - end else begin - bankmachine7_next_state <= 2'd3; - end - end - end - end - endcase -// synthesis translate_off - dummy_d_241 = dummy_s; -// synthesis translate_on -end - -// synthesis translate_off -reg dummy_d_242; -// synthesis translate_on -always @(*) begin - litedramcore_bankmachine7_row_open <= 1'd0; - case (bankmachine7_state) - 1'd1: begin - end - 2'd2: begin - end - 2'd3: begin - if (litedramcore_bankmachine7_trccon_ready) begin - litedramcore_bankmachine7_row_open <= 1'd1; - end - end - 3'd4: begin - end - 3'd5: begin - end - 3'd6: begin - end - 3'd7: begin - end - 4'd8: begin - end - default: begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state <= 2'd2; + end + end else begin + bankmachine7_next_state <= 1'd1; + end + end else begin + bankmachine7_next_state <= 2'd3; + end + end + end end endcase // synthesis translate_off - dummy_d_242 = dummy_s; + dummy_d_241 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_243; +reg dummy_d_242; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_close <= 1'd0; @@ -9753,12 +9720,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_243 = dummy_s; + dummy_d_242 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_244; +reg dummy_d_243; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_cas <= 1'd0; @@ -9795,12 +9762,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_244 = dummy_s; + dummy_d_243 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_245; +reg dummy_d_244; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_ras <= 1'd0; @@ -9831,12 +9798,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_245 = dummy_s; + dummy_d_244 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_246; +reg dummy_d_245; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_we <= 1'd0; @@ -9879,12 +9846,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_246 = dummy_s; + dummy_d_245 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_247; +reg dummy_d_246; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0; @@ -9912,12 +9879,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_247 = dummy_s; + dummy_d_246 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_248; +reg dummy_d_247; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0; @@ -9949,12 +9916,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_248 = dummy_s; + dummy_d_247 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_249; +reg dummy_d_248; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0; @@ -9994,12 +9961,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_249 = dummy_s; + dummy_d_248 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_250; +reg dummy_d_249; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0; @@ -10039,12 +10006,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_250 = dummy_s; + dummy_d_249 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_251; +reg dummy_d_250; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_wdata_ready <= 1'd0; @@ -10084,12 +10051,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_251 = dummy_s; + dummy_d_250 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_252; +reg dummy_d_251; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_req_rdata_valid <= 1'd0; @@ -10129,12 +10096,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_252 = dummy_s; + dummy_d_251 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_253; +reg dummy_d_252; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_refresh_gnt <= 1'd0; @@ -10162,12 +10129,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_253 = dummy_s; + dummy_d_252 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_254; +reg dummy_d_253; // synthesis translate_on always @(*) begin litedramcore_bankmachine7_cmd_valid <= 1'd0; @@ -10209,6 +10176,39 @@ always @(*) begin end end endcase +// synthesis translate_off + dummy_d_253 = dummy_s; +// synthesis translate_on +end + +// synthesis translate_off +reg dummy_d_254; +// synthesis translate_on +always @(*) begin + litedramcore_bankmachine7_row_open <= 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase // synthesis translate_off dummy_d_254 = dummy_s; // synthesis translate_on @@ -10581,16 +10581,13 @@ end reg dummy_d_272; // synthesis translate_on always @(*) begin - litedramcore_choose_req_cmd_ready <= 1'd0; + litedramcore_steerer_sel0 <= 2'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_steerer_sel0 <= 1'd0; end 2'd2: begin + litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10609,11 +10606,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); - end else begin - litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; - end + litedramcore_steerer_sel0 <= 1'd0; end endcase // synthesis translate_off @@ -10625,10 +10618,10 @@ end reg dummy_d_273; // synthesis translate_on always @(*) begin - litedramcore_en1 <= 1'd0; + litedramcore_steerer_sel1 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_en1 <= 1'd1; + litedramcore_steerer_sel1 <= 1'd0; end 2'd2: begin end @@ -10649,6 +10642,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_steerer_sel1 <= 1'd1; end endcase // synthesis translate_off @@ -10660,13 +10654,12 @@ end reg dummy_d_274; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel0 <= 2'd0; + litedramcore_steerer_sel2 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_steerer_sel2 <= 1'd1; end 2'd2: begin - litedramcore_steerer_sel0 <= 2'd3; end 2'd3: begin end @@ -10685,7 +10678,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel0 <= 1'd0; + litedramcore_steerer_sel2 <= 2'd2; end endcase // synthesis translate_off @@ -10697,10 +10690,13 @@ end reg dummy_d_275; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel1 <= 2'd0; + litedramcore_choose_cmd_want_activates <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel1 <= 1'd0; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end 2'd2: begin end @@ -10721,7 +10717,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel1 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; + end end endcase // synthesis translate_off @@ -10733,10 +10732,10 @@ end reg dummy_d_276; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel2 <= 2'd0; + litedramcore_steerer_sel3 <= 2'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel2 <= 1'd1; + litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin end @@ -10757,7 +10756,7 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel2 <= 2'd2; + litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10769,13 +10768,9 @@ end reg dummy_d_277; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_want_activates <= 1'd0; + litedramcore_en0 <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end end 2'd2: begin end @@ -10796,10 +10791,7 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed; - end + litedramcore_en0 <= 1'd1; end endcase // synthesis translate_off @@ -10811,12 +10803,12 @@ end reg dummy_d_278; // synthesis translate_on always @(*) begin - litedramcore_steerer_sel3 <= 2'd0; + litedramcore_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_steerer_sel3 <= 2'd2; end 2'd2: begin + litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10835,7 +10827,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_steerer_sel3 <= 1'd0; end endcase // synthesis translate_off @@ -10847,9 +10838,13 @@ end reg dummy_d_279; // synthesis translate_on always @(*) begin - litedramcore_en0 <= 1'd0; + litedramcore_choose_cmd_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end 2'd2: begin end @@ -10870,7 +10865,10 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_en0 <= 1'd1; + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end end endcase // synthesis translate_off @@ -10882,12 +10880,11 @@ end reg dummy_d_280; // synthesis translate_on always @(*) begin - litedramcore_cmd_ready <= 1'd0; + litedramcore_choose_req_want_reads <= 1'd0; case (multiplexer_state) 1'd1: begin end 2'd2: begin - litedramcore_cmd_ready <= 1'd1; end 2'd3: begin end @@ -10906,6 +10903,7 @@ always @(*) begin 4'd10: begin end default: begin + litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10917,13 +10915,10 @@ end reg dummy_d_281; // synthesis translate_on always @(*) begin - litedramcore_choose_cmd_cmd_ready <= 1'd0; + litedramcore_choose_req_want_writes <= 1'd0; case (multiplexer_state) 1'd1: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end + litedramcore_choose_req_want_writes <= 1'd1; end 2'd2: begin end @@ -10944,10 +10939,6 @@ always @(*) begin 4'd10: begin end default: begin - if (1'd0) begin - end else begin - litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); - end end endcase // synthesis translate_off @@ -10959,9 +10950,10 @@ end reg dummy_d_282; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_reads <= 1'd0; + litedramcore_en1 <= 1'd0; case (multiplexer_state) 1'd1: begin + litedramcore_en1 <= 1'd1; end 2'd2: begin end @@ -10982,7 +10974,6 @@ always @(*) begin 4'd10: begin end default: begin - litedramcore_choose_req_want_reads <= 1'd1; end endcase // synthesis translate_off @@ -10994,10 +10985,14 @@ end reg dummy_d_283; // synthesis translate_on always @(*) begin - litedramcore_choose_req_want_writes <= 1'd0; + litedramcore_choose_req_cmd_ready <= 1'd0; case (multiplexer_state) 1'd1: begin - litedramcore_choose_req_want_writes <= 1'd1; + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end 2'd2: begin end @@ -11018,6 +11013,11 @@ always @(*) begin 4'd10: begin end default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed; + end end endcase // synthesis translate_off @@ -11072,13 +11072,13 @@ assign user_port_rdata_valid = new_master_rdata_valid8; reg dummy_d_284; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata <= 128'd0; + litedramcore_interface_wdata_we <= 16'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata <= user_port_wdata_payload_data; + litedramcore_interface_wdata_we <= user_port_wdata_payload_we; end default: begin - litedramcore_interface_wdata <= 1'd0; + litedramcore_interface_wdata_we <= 1'd0; end endcase // synthesis translate_off @@ -11090,13 +11090,13 @@ end reg dummy_d_285; // synthesis translate_on always @(*) begin - litedramcore_interface_wdata_we <= 16'd0; + litedramcore_interface_wdata <= 128'd0; case ({new_master_wdata_ready2}) 1'd1: begin - litedramcore_interface_wdata_we <= user_port_wdata_payload_we; + litedramcore_interface_wdata <= user_port_wdata_payload_data; end default: begin - litedramcore_interface_wdata_we <= 1'd0; + litedramcore_interface_wdata <= 1'd0; end endcase // synthesis translate_off @@ -11123,164 +11123,125 @@ assign litedramcore_wishbone_we = wb_bus_we; assign litedramcore_wishbone_cti = wb_bus_cti; assign litedramcore_wishbone_bte = wb_bus_bte; assign wb_bus_err = litedramcore_wishbone_err; - -// synthesis translate_off -reg dummy_d_286; -// synthesis translate_on -always @(*) begin - csrbank0_sel <= 1'd0; - csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2); - if (interface0_bank_bus_adr[0]) begin - csrbank0_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_286 = dummy_s; -// synthesis translate_on -end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0)); -assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0)); +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; -assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1)); -assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1)); +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); assign csrbank0_init_done0_w = init_done_storage; assign csrbank0_init_error0_w = init_error_storage; - -// synthesis translate_off -reg dummy_d_287; -// synthesis translate_on -always @(*) begin - csrbank1_sel <= 1'd0; - csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0); - if (interface1_bank_bus_adr[0]) begin - csrbank1_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_287 = dummy_s; -// synthesis translate_on -end +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0); assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0]; -assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0)); -assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0)); +assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0)); +assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0)); assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0]; -assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1)); -assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1)); +assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1)); +assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1)); assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2)); -assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2)); +assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2)); +assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2)); assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3)); -assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3)); +assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3)); +assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3)); assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4)); -assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4)); +assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4)); +assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4)); assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0]; -assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5)); -assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5)); +assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5)); +assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5)); assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6)); -assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6)); +assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6)); assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7)); -assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7)); +assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7)); assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8)); -assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8)); +assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8)); assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0]; -assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9)); -assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9)); +assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9)); assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0]; assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage; assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0]; - -// synthesis translate_off -reg dummy_d_288; -// synthesis translate_on -always @(*) begin - csrbank2_sel <= 1'd0; - csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1); - if (interface2_bank_bus_adr[0]) begin - csrbank2_sel <= 1'd0; - end -// synthesis translate_off - dummy_d_288 = dummy_s; -// synthesis translate_on -end +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1); assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0]; -assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0)); -assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0)); +assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0)); +assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0)); assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1)); -assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1)); +assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1)); +assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1)); assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2)); -assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2)); assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3)); -assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3)); +assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3)); +assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3)); assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4)); -assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4)); +assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4)); assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5)); -assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5)); +assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5)); assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6)); -assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6)); +assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6)); assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7)); -assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7)); +assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7)); +assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7)); assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8)); -assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8)); assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9)); -assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9)); +assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9)); +assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9)); assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10)); -assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10)); +assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10)); assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11)); -assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11)); +assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11)); assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12)); -assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12)); +assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12)); assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13)); -assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13)); +assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13)); +assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13)); assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14)); -assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14)); assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15)); -assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15)); +assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15)); +assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15)); assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16)); -assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16)); +assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16)); assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17)); -assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17)); +assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17)); assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18)); -assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18)); +assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18)); assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0]; -assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19)); -assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19)); +assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19)); +assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19)); assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0]; -assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20)); -assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20)); assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0]; -assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21)); -assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21)); +assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21)); +assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21)); assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0]; -assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22)); -assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22)); +assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22)); assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23)); -assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23)); +assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23)); assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0]; -assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24)); -assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24)); +assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24)); assign csrbank2_dfii_control0_w = litedramcore_storage[3:0]; assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0]; @@ -11322,7 +11283,7 @@ assign interface2_bank_bus_dat_w = dat_w; assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r); // synthesis translate_off -reg dummy_d_289; +reg dummy_d_286; // synthesis translate_on always @(*) begin rhs_array_muxed0 <= 1'd0; @@ -11353,12 +11314,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_289 = dummy_s; + dummy_d_286 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_290; +reg dummy_d_287; // synthesis translate_on always @(*) begin rhs_array_muxed1 <= 15'd0; @@ -11389,12 +11350,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_290 = dummy_s; + dummy_d_287 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_291; +reg dummy_d_288; // synthesis translate_on always @(*) begin rhs_array_muxed2 <= 3'd0; @@ -11425,12 +11386,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_291 = dummy_s; + dummy_d_288 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_292; +reg dummy_d_289; // synthesis translate_on always @(*) begin rhs_array_muxed3 <= 1'd0; @@ -11461,12 +11422,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_292 = dummy_s; + dummy_d_289 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_293; +reg dummy_d_290; // synthesis translate_on always @(*) begin rhs_array_muxed4 <= 1'd0; @@ -11497,12 +11458,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_293 = dummy_s; + dummy_d_290 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_294; +reg dummy_d_291; // synthesis translate_on always @(*) begin rhs_array_muxed5 <= 1'd0; @@ -11533,12 +11494,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_294 = dummy_s; + dummy_d_291 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_295; +reg dummy_d_292; // synthesis translate_on always @(*) begin t_array_muxed0 <= 1'd0; @@ -11569,12 +11530,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_295 = dummy_s; + dummy_d_292 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_296; +reg dummy_d_293; // synthesis translate_on always @(*) begin t_array_muxed1 <= 1'd0; @@ -11605,12 +11566,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_296 = dummy_s; + dummy_d_293 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_297; +reg dummy_d_294; // synthesis translate_on always @(*) begin t_array_muxed2 <= 1'd0; @@ -11641,12 +11602,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_297 = dummy_s; + dummy_d_294 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_298; +reg dummy_d_295; // synthesis translate_on always @(*) begin rhs_array_muxed6 <= 1'd0; @@ -11677,12 +11638,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_298 = dummy_s; + dummy_d_295 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_299; +reg dummy_d_296; // synthesis translate_on always @(*) begin rhs_array_muxed7 <= 15'd0; @@ -11713,12 +11674,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_299 = dummy_s; + dummy_d_296 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_300; +reg dummy_d_297; // synthesis translate_on always @(*) begin rhs_array_muxed8 <= 3'd0; @@ -11749,12 +11710,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_300 = dummy_s; + dummy_d_297 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_301; +reg dummy_d_298; // synthesis translate_on always @(*) begin rhs_array_muxed9 <= 1'd0; @@ -11785,12 +11746,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_301 = dummy_s; + dummy_d_298 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_302; +reg dummy_d_299; // synthesis translate_on always @(*) begin rhs_array_muxed10 <= 1'd0; @@ -11821,12 +11782,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_302 = dummy_s; + dummy_d_299 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_303; +reg dummy_d_300; // synthesis translate_on always @(*) begin rhs_array_muxed11 <= 1'd0; @@ -11857,12 +11818,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_303 = dummy_s; + dummy_d_300 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_304; +reg dummy_d_301; // synthesis translate_on always @(*) begin t_array_muxed3 <= 1'd0; @@ -11893,12 +11854,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_304 = dummy_s; + dummy_d_301 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_305; +reg dummy_d_302; // synthesis translate_on always @(*) begin t_array_muxed4 <= 1'd0; @@ -11929,12 +11890,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_305 = dummy_s; + dummy_d_302 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_306; +reg dummy_d_303; // synthesis translate_on always @(*) begin t_array_muxed5 <= 1'd0; @@ -11965,12 +11926,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_306 = dummy_s; + dummy_d_303 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_307; +reg dummy_d_304; // synthesis translate_on always @(*) begin rhs_array_muxed12 <= 22'd0; @@ -11980,12 +11941,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_307 = dummy_s; + dummy_d_304 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_308; +reg dummy_d_305; // synthesis translate_on always @(*) begin rhs_array_muxed13 <= 1'd0; @@ -11995,12 +11956,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_308 = dummy_s; + dummy_d_305 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_309; +reg dummy_d_306; // synthesis translate_on always @(*) begin rhs_array_muxed14 <= 1'd0; @@ -12010,12 +11971,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_309 = dummy_s; + dummy_d_306 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_310; +reg dummy_d_307; // synthesis translate_on always @(*) begin rhs_array_muxed15 <= 22'd0; @@ -12025,12 +11986,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_310 = dummy_s; + dummy_d_307 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_311; +reg dummy_d_308; // synthesis translate_on always @(*) begin rhs_array_muxed16 <= 1'd0; @@ -12040,12 +12001,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_311 = dummy_s; + dummy_d_308 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_312; +reg dummy_d_309; // synthesis translate_on always @(*) begin rhs_array_muxed17 <= 1'd0; @@ -12055,12 +12016,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_312 = dummy_s; + dummy_d_309 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_313; +reg dummy_d_310; // synthesis translate_on always @(*) begin rhs_array_muxed18 <= 22'd0; @@ -12070,12 +12031,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_313 = dummy_s; + dummy_d_310 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_314; +reg dummy_d_311; // synthesis translate_on always @(*) begin rhs_array_muxed19 <= 1'd0; @@ -12085,12 +12046,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_314 = dummy_s; + dummy_d_311 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_315; +reg dummy_d_312; // synthesis translate_on always @(*) begin rhs_array_muxed20 <= 1'd0; @@ -12100,12 +12061,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_315 = dummy_s; + dummy_d_312 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_316; +reg dummy_d_313; // synthesis translate_on always @(*) begin rhs_array_muxed21 <= 22'd0; @@ -12115,12 +12076,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_316 = dummy_s; + dummy_d_313 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_317; +reg dummy_d_314; // synthesis translate_on always @(*) begin rhs_array_muxed22 <= 1'd0; @@ -12130,12 +12091,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_317 = dummy_s; + dummy_d_314 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_318; +reg dummy_d_315; // synthesis translate_on always @(*) begin rhs_array_muxed23 <= 1'd0; @@ -12145,12 +12106,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_318 = dummy_s; + dummy_d_315 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_319; +reg dummy_d_316; // synthesis translate_on always @(*) begin rhs_array_muxed24 <= 22'd0; @@ -12160,12 +12121,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_319 = dummy_s; + dummy_d_316 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_320; +reg dummy_d_317; // synthesis translate_on always @(*) begin rhs_array_muxed25 <= 1'd0; @@ -12175,12 +12136,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_320 = dummy_s; + dummy_d_317 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_321; +reg dummy_d_318; // synthesis translate_on always @(*) begin rhs_array_muxed26 <= 1'd0; @@ -12190,12 +12151,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_321 = dummy_s; + dummy_d_318 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_322; +reg dummy_d_319; // synthesis translate_on always @(*) begin rhs_array_muxed27 <= 22'd0; @@ -12205,12 +12166,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_322 = dummy_s; + dummy_d_319 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_323; +reg dummy_d_320; // synthesis translate_on always @(*) begin rhs_array_muxed28 <= 1'd0; @@ -12220,12 +12181,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_323 = dummy_s; + dummy_d_320 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_324; +reg dummy_d_321; // synthesis translate_on always @(*) begin rhs_array_muxed29 <= 1'd0; @@ -12235,12 +12196,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_324 = dummy_s; + dummy_d_321 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_325; +reg dummy_d_322; // synthesis translate_on always @(*) begin rhs_array_muxed30 <= 22'd0; @@ -12250,12 +12211,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_325 = dummy_s; + dummy_d_322 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_326; +reg dummy_d_323; // synthesis translate_on always @(*) begin rhs_array_muxed31 <= 1'd0; @@ -12265,12 +12226,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_326 = dummy_s; + dummy_d_323 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_327; +reg dummy_d_324; // synthesis translate_on always @(*) begin rhs_array_muxed32 <= 1'd0; @@ -12280,12 +12241,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_327 = dummy_s; + dummy_d_324 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_328; +reg dummy_d_325; // synthesis translate_on always @(*) begin rhs_array_muxed33 <= 22'd0; @@ -12295,12 +12256,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_328 = dummy_s; + dummy_d_325 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_329; +reg dummy_d_326; // synthesis translate_on always @(*) begin rhs_array_muxed34 <= 1'd0; @@ -12310,12 +12271,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_329 = dummy_s; + dummy_d_326 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_330; +reg dummy_d_327; // synthesis translate_on always @(*) begin rhs_array_muxed35 <= 1'd0; @@ -12325,12 +12286,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_330 = dummy_s; + dummy_d_327 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_331; +reg dummy_d_328; // synthesis translate_on always @(*) begin array_muxed0 <= 3'd0; @@ -12349,12 +12310,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_331 = dummy_s; + dummy_d_328 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_332; +reg dummy_d_329; // synthesis translate_on always @(*) begin array_muxed1 <= 15'd0; @@ -12373,12 +12334,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_332 = dummy_s; + dummy_d_329 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_333; +reg dummy_d_330; // synthesis translate_on always @(*) begin array_muxed2 <= 1'd0; @@ -12397,12 +12358,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_333 = dummy_s; + dummy_d_330 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_334; +reg dummy_d_331; // synthesis translate_on always @(*) begin array_muxed3 <= 1'd0; @@ -12421,12 +12382,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_334 = dummy_s; + dummy_d_331 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_335; +reg dummy_d_332; // synthesis translate_on always @(*) begin array_muxed4 <= 1'd0; @@ -12445,12 +12406,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_335 = dummy_s; + dummy_d_332 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_336; +reg dummy_d_333; // synthesis translate_on always @(*) begin array_muxed5 <= 1'd0; @@ -12469,12 +12430,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_336 = dummy_s; + dummy_d_333 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_337; +reg dummy_d_334; // synthesis translate_on always @(*) begin array_muxed6 <= 1'd0; @@ -12493,12 +12454,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_337 = dummy_s; + dummy_d_334 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_338; +reg dummy_d_335; // synthesis translate_on always @(*) begin array_muxed7 <= 3'd0; @@ -12517,12 +12478,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_338 = dummy_s; + dummy_d_335 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_339; +reg dummy_d_336; // synthesis translate_on always @(*) begin array_muxed8 <= 15'd0; @@ -12541,12 +12502,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_339 = dummy_s; + dummy_d_336 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_340; +reg dummy_d_337; // synthesis translate_on always @(*) begin array_muxed9 <= 1'd0; @@ -12565,12 +12526,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_340 = dummy_s; + dummy_d_337 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_341; +reg dummy_d_338; // synthesis translate_on always @(*) begin array_muxed10 <= 1'd0; @@ -12589,12 +12550,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_341 = dummy_s; + dummy_d_338 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_342; +reg dummy_d_339; // synthesis translate_on always @(*) begin array_muxed11 <= 1'd0; @@ -12613,12 +12574,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_342 = dummy_s; + dummy_d_339 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_343; +reg dummy_d_340; // synthesis translate_on always @(*) begin array_muxed12 <= 1'd0; @@ -12637,12 +12598,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_343 = dummy_s; + dummy_d_340 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_344; +reg dummy_d_341; // synthesis translate_on always @(*) begin array_muxed13 <= 1'd0; @@ -12661,12 +12622,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_344 = dummy_s; + dummy_d_341 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_345; +reg dummy_d_342; // synthesis translate_on always @(*) begin array_muxed14 <= 3'd0; @@ -12685,12 +12646,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_345 = dummy_s; + dummy_d_342 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_346; +reg dummy_d_343; // synthesis translate_on always @(*) begin array_muxed15 <= 15'd0; @@ -12709,12 +12670,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_346 = dummy_s; + dummy_d_343 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_347; +reg dummy_d_344; // synthesis translate_on always @(*) begin array_muxed16 <= 1'd0; @@ -12733,12 +12694,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_347 = dummy_s; + dummy_d_344 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_348; +reg dummy_d_345; // synthesis translate_on always @(*) begin array_muxed17 <= 1'd0; @@ -12757,12 +12718,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_348 = dummy_s; + dummy_d_345 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_349; +reg dummy_d_346; // synthesis translate_on always @(*) begin array_muxed18 <= 1'd0; @@ -12781,12 +12742,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_349 = dummy_s; + dummy_d_346 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_350; +reg dummy_d_347; // synthesis translate_on always @(*) begin array_muxed19 <= 1'd0; @@ -12805,12 +12766,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_350 = dummy_s; + dummy_d_347 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_351; +reg dummy_d_348; // synthesis translate_on always @(*) begin array_muxed20 <= 1'd0; @@ -12829,12 +12790,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_351 = dummy_s; + dummy_d_348 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_352; +reg dummy_d_349; // synthesis translate_on always @(*) begin array_muxed21 <= 3'd0; @@ -12853,12 +12814,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_352 = dummy_s; + dummy_d_349 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_353; +reg dummy_d_350; // synthesis translate_on always @(*) begin array_muxed22 <= 15'd0; @@ -12877,12 +12838,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_353 = dummy_s; + dummy_d_350 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_354; +reg dummy_d_351; // synthesis translate_on always @(*) begin array_muxed23 <= 1'd0; @@ -12901,12 +12862,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_354 = dummy_s; + dummy_d_351 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_355; +reg dummy_d_352; // synthesis translate_on always @(*) begin array_muxed24 <= 1'd0; @@ -12925,12 +12886,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_355 = dummy_s; + dummy_d_352 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_356; +reg dummy_d_353; // synthesis translate_on always @(*) begin array_muxed25 <= 1'd0; @@ -12949,12 +12910,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_356 = dummy_s; + dummy_d_353 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_357; +reg dummy_d_354; // synthesis translate_on always @(*) begin array_muxed26 <= 1'd0; @@ -12973,12 +12934,12 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_357 = dummy_s; + dummy_d_354 = dummy_s; // synthesis translate_on end // synthesis translate_off -reg dummy_d_358; +reg dummy_d_355; // synthesis translate_on always @(*) begin array_muxed27 <= 1'd0; @@ -12997,7 +12958,7 @@ always @(*) begin end endcase // synthesis translate_off - dummy_d_358 = dummy_s; + dummy_d_355 = dummy_s; // synthesis translate_on end assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset); @@ -14447,7 +14408,7 @@ always @(posedge sys_clk) begin new_master_rdata_valid8 <= new_master_rdata_valid7; interface0_bank_bus_dat_r <= 1'd0; if (csrbank0_sel) begin - case (interface0_bank_bus_adr[1]) + case (interface0_bank_bus_adr[0]) 1'd0: begin interface0_bank_bus_dat_r <= csrbank0_init_done0_w; end @@ -14466,7 +14427,7 @@ always @(posedge sys_clk) begin init_error_re <= csrbank0_init_error0_re; interface1_bank_bus_dat_r <= 1'd0; if (csrbank1_sel) begin - case (interface1_bank_bus_adr[4:1]) + case (interface1_bank_bus_adr[3:0]) 1'd0: begin interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w; end @@ -14513,7 +14474,7 @@ always @(posedge sys_clk) begin a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re; interface2_bank_bus_dat_r <= 1'd0; if (csrbank2_sel) begin - case (interface2_bank_bus_adr[5:1]) + case (interface2_bank_bus_adr[4:0]) 1'd0: begin interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w; end @@ -14691,7 +14652,7 @@ always @(posedge sys_clk) begin a7ddrphy_bitslip15_value <= 4'd0; a7ddrphy_rddata_en_last <= 8'd0; a7ddrphy_wrdata_en_last <= 4'd0; - litedramcore_storage <= 4'd0; + litedramcore_storage <= 4'd1; litedramcore_re <= 1'd0; litedramcore_phaseinjector0_command_storage <= 6'd0; litedramcore_phaseinjector0_command_re <= 1'd0; diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl new file mode 100644 index 0000000..7abaf48 --- /dev/null +++ b/litedram/generated/sim/litedram-initmem.vhdl @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +library work; +use work.wishbone_types.all; +use work.utils.all; + +entity dram_init_mem is + generic ( + EXTRA_PAYLOAD_FILE : string := ""; + EXTRA_PAYLOAD_SIZE : integer := 0 + ); + port ( + clk : in std_ulogic; + wb_in : in wb_io_master_out; + wb_out : out wb_io_slave_out + ); +end entity dram_init_mem; + +architecture rtl of dram_init_mem is + + constant INIT_RAM_SIZE : integer := 16384; + constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); + constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init"; + + type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); + + -- XXX FIXME: Have a single init function called twice with + -- an offset as argument + procedure init_load_payload(ram: inout ram_t; filename: string) is + file payload_file : text open read_mode is filename; + variable ram_line : line; + variable temp_word : std_logic_vector(63 downto 0); + begin + for i in 0 to RND_PAYLOAD_SIZE-1 loop + exit when endfile(payload_file); + readline(payload_file, ram_line); + hread(ram_line, temp_word); + ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0); + ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32); + end loop; + assert endfile(payload_file) report "Payload too big !" severity failure; + end procedure; + + impure function init_load_ram(name : string) return ram_t is + file ram_file : text open read_mode is name; + variable temp_word : std_logic_vector(63 downto 0); + variable temp_ram : ram_t := (others => (others => '0')); + variable ram_line : line; + begin + report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) & + " rounded to:" & integer'image(RND_PAYLOAD_SIZE); + report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) & + " bytes using " & integer'image(INIT_RAM_ABITS) & + " address bits"; + for i in 0 to (INIT_RAM_SIZE/8)-1 loop + exit when endfile(ram_file); + readline(ram_file, ram_line); + hread(ram_line, temp_word); + temp_ram(i*2) := temp_word(31 downto 0); + temp_ram(i*2+1) := temp_word(63 downto 32); + end loop; + if RND_PAYLOAD_SIZE /= 0 then + init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE); + end if; + return temp_ram; + end function; + + impure function init_zero return ram_t is + variable temp_ram : ram_t := (others => (others => '0')); + begin + return temp_ram; + end function; + + impure function initialize_ram(filename: string) return ram_t is + begin + report "Opening file " & filename; + if filename'length = 0 then + return init_zero; + else + return init_load_ram(filename); + end if; + end function; + signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE); + + attribute ram_style : string; + attribute ram_style of init_ram: signal is "block"; + + signal obuf : std_ulogic_vector(31 downto 0); + signal oack : std_ulogic; +begin + + init_ram_0: process(clk) + variable adr : integer; + begin + if rising_edge(clk) then + oack <= '0'; + if (wb_in.cyc and wb_in.stb) = '1' then + adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2)))); + if wb_in.we = '0' then + obuf <= init_ram(adr); + else + for i in 0 to 3 loop + if wb_in.sel(i) = '1' then + init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <= + wb_in.dat(((i + 1) * 8) - 1 downto i * 8); + end if; + end loop; + end if; + oack <= '1'; + end if; + wb_out.ack <= oack; + wb_out.dat <= obuf; + end if; + end process; + + wb_out.stall <= '0'; + +end architecture rtl; diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init new file mode 100644 index 0000000..bfc17ca --- /dev/null +++ b/litedram/generated/sim/litedram_core.init @@ -0,0 +1,1218 @@ +4800002408000048 +01006b69a600607d +a602487d05009f42 +a64b5a7d14004a39 +2402004ca64b7b7d +602100003c200000 +6421f000782107c6 +3d80000060213f00 +798c07c6618c0000 +618c10a4658cf000 +4e8004217d8903a6 +0000000048000002 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000048000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +384296003c4c0001 +fbc1fff07c0802a6 +f8010010fbe1fff8 +3be10020f821fe91 +f8a101a0f8810198 +f8c101a838800140 +38c101987c651b78 +7fe3fb78f8e101b0 +f92101c0f90101b8 +48000cfdf94101c8 +7c7e1b7860000000 +480008157fe3fb78 +3821017060000000 +480012bc7fc3f378 +0100000000000000 +4e80002000000280 +0000000000000000 +7c0007ac00000000 +4e8000204c00012c +0000000000000000 +3c4c000100000000 +7c0802a63842955c +7d800026fbe1fff8 +91810008f8010010 +48000709f821ff91 +3c62ffff60000000 +4bffff3538637d40 +548400023880ffff +7c8026ea7c0004ac +3fe0c0003c62ffff +63ff000838637d60 +3c62ffff4bffff11 +38637d807bff0020 +7c0004ac4bffff01 +73e900017fe0feea +3c62ffff41820010 +4bfffee538637d98 +4d80000073e90002 +3c62ffff41820010 +4bfffecd38637da0 +4e00000073e90004 +3c62ffff41820010 +4bfffeb538637da8 +3bff7fa03fe2ffff +4bfffea57fe3fb78 +3c80c00041920028 +7884002060840010 +7c8026ea7c0004ac +7884b2823c62ffff +4bfffe7d38637db0 +3c80c000418e004c +7884002060840018 +7c8026ea7c0004ac +788465023c62ffff +4bfffe5538637dd0 +608400303c80c000 +7c0004ac78840020 +3c62ffff7c8026ea +38637df07884b282 +3d20c0004bfffe31 +7929002061290020 +7d204eea7c0004ac +3c62ffff3c80000f +38637e1060844240 +4bfffe057c892392 +4bfffdfd7fe3fb78 +3ca2ffff418e0028 +3c62ffff3c82ffff +38847e4038a57e30 +4bfffddd38637e48 +6000000048000419 +3c62ffff41920020 +4bfffdc538637e78 +8181000838210070 +480010d87d818120 +38637e903c62ffff +3c80f0004bfffda9 +6084400038a0ffff +7884002054a50422 +480007ad3c604000 +3c62ffff60000000 +4bfffd7d38637eb0 +e801001038210070 +ebe1fff881810008 +7d8181207c0803a6 +000000004bfffde4 +0000018003000000 +612908043d20c010 +7c0004ac79290020 +3d40c0107c604f2a +614a080839200001 +7c0004ac794a0020 +4e8000207d20572a +0000000000000000 +3c4c000100000000 +7c0802a63842930c +614a08003d40c010 +794a002039200001 +f821ffa1f8010010 +7d20572a7c0004ac +38637f803c62ffff +600000004bfffce1 +e801001038210060 +4e8000207c0803a6 +0100000000000000 +3c4c000100000080 +7c0802a6384292b4 +7d0903a639000080 +3d2040003d40aaaa +48000f55614aaaaa +91490000f821ff81 +4200fff839290004 +600000004bfffcfd +3d00aaaa39400080 +3d2040007d4903a6 +6108aaaa3be00000 +7f8a400081490000 +3bff0001419e000c +392900047fff07b4 +390000804200ffe8 +7d0903a63d405555 +614a55553d204000 +3929000491490000 +4bfffca14200fff8 +3940008060000000 +7d4903a63d005555 +610855553d204000 +7f8a400081490000 +3bff0001419e000c +392900047fff07b4 +2fbf00004200ffe8 +3c62ffff419e001c +7fe4fb7838a00100 +4bfffbdd38637ec8 +3900010060000000 +7d0903a63ce08020 +3d40400060e70003 +78e7002039200001 +792907e07928f842 +394a00047d2900d0 +7d2942787d293838 +4200ffe4912afffc +600000004bfffc0d +3ce0802039000100 +60e700037d0903a6 +3ba000003d404000 +78e7002039200001 +792907e07928f842 +7d2938387d2900d0 +810a00007d294278 +419e000c7f884840 +7fbd07b43bbd0001 +4200ffd4394a0004 +419e001c2fbd0000 +38a001003c62ffff +38637ef07fa4eb78 +600000004bfffb29 +3940000039200020 +3d2a10007d2903a6 +3929000279480020 +79291764394a0001 +4200ffe891090000 +600000004bfffb6d +3940000039200020 +3bc000007d2903a6 +792917643d2a1000 +5529043e81290008 +419e000c7f895000 +7fde07b43bde0001 +4200ffdc394a0001 +419e001c2fbe0000 +38a000203c62ffff +38637f187fc4f378 +600000004bfffaa1 +386000007fffea14 +2f9f00007ffff214 +3c62ffff409e00ac +4bfffa7d38637f40 +7c9602a660000000 +7884002039400080 +392000007d4903a6 +794a1f243d490800 +39290001f92a0000 +7ff602a64200fff0 +3fe0000c7c9f2050 +7fff239663ff8000 +600000004bfffaad +7d3602a67bff0020 +7929002039000080 +3d4040007d0903a6 +394a0008e90a0000 +7cb602a64200fff8 +3ca0000c7d254850 +3c62ffff60a58000 +7fe4fb787ca54b96 +78a5032038637f50 +600000004bfff9e9 +3821008038600001 +0000000048000ce0 +0000038001000000 +38428fc03c4c0001 +3c62ffff7c0802a6 +48000c6138637fa8 +3f60c010f821ff71 +637b10003be00000 +4bfff99d7b7b0020 +7c0004ac60000000 +3f40c0107fe0df2a +7b5a0020635a1004 +7fe0d72a7c0004ac +63bd080c3fa0c010 +7c0004ac7bbd0020 +3fc0c0107fe0ef2a +7bde002063de0810 +7fe0f72a7c0004ac +3940000c3d20c010 +7929002061290800 +7d404f2a7c0004ac +7fe0ef2a7c0004ac +7fe0f72a7c0004ac +7c0004ac3940000e +392002007d404f2a +7d20ef2a7c0004ac +7c0004ac39200002 +3860000f7d20f72a +7c0004ac4bfffbb1 +392000037fe0ef2a +7d20f72a7c0004ac +4bfffb953860000f +7c0004ac39200006 +3b8000017d20ef2a +7f80f72a7c0004ac +4bfffb753860000f +7c0004ac39200920 +7c0004ac7d20ef2a +3860000f7fe0f72a +392004004bfffb59 +7d20ef2a7c0004ac +7fe0f72a7c0004ac +4bfffb3d38600003 +4bfffbd14bfffb7d +4082001c2c230000 +7f80df2a7c0004ac +7f80d72a7c0004ac +48000b6038210090 +7f80df2a7c0004ac +4bffffec38600001 +0100000000000000 +3c4c000100000680 +3d20c00038428e3c +6129200060000000 +f922801079290020 +612900203d20c000 +7c0004ac79290020 +3d40001c7d204eea +7d295392614a2000 +394a0018e9428010 +7c0004ac3929ffff +4e8000207d2057ea +0000000000000000 +3c4c000100000000 +6000000038428ddc +39290010e9228010 +7d204eea7c0004ac +4082ffe871290008 +e94280105469063e +7d2057ea7c0004ac +000000004e800020 +0000000000000000 +38428d983c4c0001 +fbc1fff07c0802a6 +3bc3fffffbe1fff8 +f821ffd1f8010010 +2fbf00008ffe0001 +38210030409e0010 +48000a8c38600000 +409e000c2b9f000a +4bffff813860000d +4bffff797fe3fb78 +000000004bffffd0 +0000028001000000 +408200082c240000 +2b8500243881fff0 +38600000f8640000 +3cc000014d9d0020 +60c6260078c683e4 +89490000e9240000 +419d002c2b8a0020 +70e800017cc75436 +2fa5000040820014 +38a0000a409e0054 +392900014800005c +4bffffccf9240000 +409e00382fa50000 +38a0000a2b8a0030 +89490001409e003c +409e00302f8a0078 +38a0001089490001 +409e00202f8a0078 +f924000039290002 +2f85001048000014 +2b8a0030409e000c +38600000419effd8 +38c9ffd048000030 +2b8a000954ca063e +7cc90734419d0034 +4c9c00207f892800 +7c6519d238e70001 +7c691a14f8e40000 +89270000e8e40000 +409effc82fa90000 +3949ff9f4e800020 +2b8a0019554a063e +3929ffa9419d0010 +4bffffbc7d290734 +554a063e3949ffbf +4d9d00202b8a0019 +4bffffe43929ffc9 +0000000000000000 +3920000000000000 +2f8a00007d4348ae +7d234b78409e000c +392900014e800020 +000000004bffffe8 +0000000000000000 +3900000078aae8c2 +7d2903a6392a0001 +78a9e8c242000030 +1d29fff8792a1f24 +7c8452147d035214 +392000007ca92a14 +7d4903a639450001 +4e80002042000018 +7d23412a7d24402a +4bffffc439080008 +7d4849ae7d4448ae +4bffffdc39290001 +0000000000000000 +3923ff9f00000000 +4d9d00202b890019 +7c6307b43863ffe0 +000000004e800020 +0000000000000000 +38428b483c4c0001 +3d2037367c0802a6 +612935347d908026 +65293332792907c6 +6129313091810008 +f821ffa1480007d9 +7cde33787c7d1b78 +f92100203be00000 +612964633d206665 +65296261792907c6 +f921002861293938 +2fa900007ca92b78 +2fbf0000409e0080 +3be00001409e0008 +386000007fbf2040 +2e270000419d0058 +7f65f3923b9fffff +7ca928507d3bf1d2 +886500207ca12a14 +4bffff4141920010 +5463063e60000000 +e93d00002fbb0000 +7c69e1ae7f65db78 +409effc83b9cffff +38600001e93d0000 +fbfd00007fe9fa14 +8181000838210060 +480007747d908120 +409e00142b9e0010 +3bff00017929e102 +4bffff687fff07b4 +4bfffff07d29f392 +0300000000000000 +3c4c000100000580 +7c0802a638428a3c +f821ffb1480006e9 +7c7f1b78eb630000 +7cbd2b787c9c2378 +7fa3eb783bc00000 +600000004bfffe0d +409d00147fa3f040 +7d3b5050e95f0000 +419c00107fa9e040 +3860000138210050 +7d3df0ae480006f0 +992a00003bde0001 +39290001e93f0000 +4bffffb8f93f0000 +0100000000000000 +3c4c000100000580 +7c0802a6384289bc +f821ffa148000661 +7c9b23787c7d1b78 +388000007ca32b78 +7cde337838a0000a +7cfc3b78eb5d0000 +7d3f4b787d194378 +600000004bfffc49 +7c6307b439400000 +409e006c2fbe0000 +409e00082faa0000 +7d3f521439400001 +7d2a07b47f834800 +7c6a1850409d0044 +786900202f830000 +419c001039290001 +7f8350003d408000 +39200001409e0008 +3929ffff2c290001 +e8fd000041820014 +7faad8407d5a3850 +38210060419c0030 +4800060438600000 +409e00142b9c0010 +394a00017bdee102 +4bffff7c7d4a07b4 +4bfffff07fdee392 +e95d00009b270000 +f95d0000394a0001 +000000004bffffa8 +0000078001000000 +384288c03c4c0001 +480005397c0802a6 +7c741b79f821fed1 +38600000f8610060 +2fa4000041820068 +39210040419e0060 +3ac4ffff3e42ffff +f92100703b410020 +3ae0000060000000 +3a527fc039228008 +f92100783ba10060 +ebc1006089250000 +419e00102fa90000 +7fbfb0407ff4f050 +39200000419c0020 +e8610060993e0000 +7e8307b47e941850 +4800050838210130 +394500012b890025 +38e00000409e0488 +e901007089250000 +7cea07b4f8a10068 +390700017d2741ae +7d0807b48d250001 +419e00582b890064 +419e00502b890069 +419e00482b890075 +419e00402b890078 +419e00382b890058 +419e00302b890070 +419e00282b890063 +419e00202b890073 +419e00182b890025 +419e00102b89004f +38e700012b89006f +394a0002409eff88 +7d4a07b42b890025 +7d5a52147d1a4214 +9aea002099280020 +393e0001409e0020 +39200025f9210060 +e9210068993e0000 +4bffff0438a90002 +7fffb05089210041 +eb6600003a260008 +3b0100423a600030 +712900fd3929ffd2 +3aa000004082039c +3b8000003b200004 +39e0002d3a000001 +480001087ddb00d0 +38d800012b89006c +419e033c88f80001 +2b890063419d0118 +419d0038419e0240 +419e01e82b89004f +419e01882b890058 +554a063e3949ffd0 +419d00c42b8a0009 +7f81e214395c0001 +795c0020993c0020 +2b890068480000b0 +2b890069419e0304 +2b890064419e000c +2b890075409effc8 +9aea00207d41e214 +419e00347f6adb78 +3929ffff57291838 +7f6948397e094836 +99e8000041820020 +39290001e9210060 +7b291f24f9210060 +7dca50387d52482a +7d465378e8810060 +f941008038e0000a +392000007f45d378 +7fa3eb787e689b78 +7c84f8507c9e2050 +e88100604bfffc9d +7ea7ab78e9410080 +7c9e205038c0000a +7c84f8507d455378 +4bfffaed7fa3eb78 +893800003b180001 +2fa90000e9010060 +7d5e4050419e0010 +419dfee47fbf5040 +4bfffe907e268b78 +419e016c2b890073 +2b89006f419d006c +2b890070419e00d4 +7d21e214409efef0 +7f66db7838e00010 +9ae900207c8af850 +3920000239000020 +7fa3eb787f45d378 +e88100604bfffc0d +7fa3eb78e8a10078 +7c84f8507c9e2050 +e88100604bfffb75 +38c000107ea7ab78 +7c9e20507f65db78 +2b8900784bffff5c +2b89007a419e0018 +2b890075419e01cc +3aa000014bfffeb8 +38e000107d21e214 +7e689b787c8af850 +7b291f249ae90020 +7fa3eb787f45d378 +392000007d72482a +7d665b787f6b5838 +4bfffb89f9610080 +7ea7ab78e8810060 +7c9e205038c00010 +7d655b78e9610080 +7d21e2144bfffeec +7c8af85038e00008 +9ae900207e689b78 +7f45d3787b291f24 +7d72482a7fa3eb78 +7f6b583839200000 +f96100807d665b78 +e88100604bfffb35 +38c000087ea7ab78 +4bffffac7c9e2050 +390000207d21e214 +38c0000138e0000a +7f45d3789ae90020 +7c8af85039200000 +4bfffaf97fa3eb78 +9b690000e9210060 +39290001e9210060 +4bfffe6cf9210060 +38a0000a7d21e214 +f9410088f9010090 +7f43d37838800000 +4bfff73d9ae90020 +f861008060000000 +4bfff8617f63db78 +e921008060000000 +409d00407fa91840 +e94100887c634850 +2fa30000e9010090 +7d4af85039230001 +39200001409e0008 +e8c100602c290001 +418200103929ffff +7faa38407ce83050 +e8810060419d0020 +7fa3eb787f65db78 +7c84f8507c9e2050 +4bfffdd44bfff9cd +98e6000038e00020 +38e70001e8e10060 +4bffffb4f8e10060 +3b2000082b87006c +7cd83378409efdb0 +2b8700684bfffda8 +409efd9c3b200002 +3b2000017cd83378 +3b2000084bfffd90 +3a6000204bfffd88 +4bfffc603b010041 +7d455378993e0000 +39290001e9210060 +4bfffb24f9210060 +0100000000000000 +f9c1ff7000001280 +fa01ff80f9e1ff78 +fa41ff90fa21ff88 +fa81ffa0fa61ff98 +fac1ffb0faa1ffa8 +fb01ffc0fae1ffb8 +fb41ffd0fb21ffc8 +fb81ffe0fb61ffd8 +fbc1fff0fba1ffe8 +f8010010fbe1fff8 +e9c1ff704e800020 +ea01ff80e9e1ff78 +ea41ff90ea21ff88 +ea81ffa0ea61ff98 +eac1ffb0eaa1ffa8 +eb01ffc0eae1ffb8 +eb41ffd0eb21ffc8 +eb81ffe0eb61ffd8 +eba1ffe8e8010010 +ebc1fff07c0803a6 +4e800020ebe1fff8 +e8010010ebc1fff0 +7c0803a6ebe1fff8 +000000004e800020 +6d6f636c65570a0a +63694d206f742065 +2120747461776f72 +0000000000000a0a +67697320636f5320 +203a65727574616e +0a786c6c36313025 +0000000000000000 +656620636f532020 +203a736572757461 +0000000000000000 +0000002054524155 +000000204d415244 +000000204d415242 +2020202020202020 +203a4d4152422020 +0a424b20646c6c25 +0000000000000000 +2020202020202020 +203a4d4152442020 +0a424d20646c6c25 +0000000000000000 +4152442020202020 +203a54494e49204d +0a424b20646c6c25 +0000000000000000 +2020202020202020 +203a4b4c43202020 +7a484d20646c6c25 +000000000000000a +3163616539333236 +0000000000000000 +0039326232623162 +4d4152446574694c +6620746c69756220 +6567694d206d6f72 +646e61207325206e +2520586574694c20 +0000000000000a73 +20676e69746f6f42 +415242206d6f7266 +0000000a2e2e2e4d +20676e6979706f43 +2064616f6c796170 +2e4d415244206f74 +00000000000a2e2e +20676e69746f6f42 +415244206d6f7266 +0000000a2e2e2e4d +20747365746d654d +6c69616620737562 +252f6425203a6465 +73726f7272652064 +000000000000000a +20747365746d654d +6961662061746164 +2f6425203a64656c +726f727265206425 +0000000000000a73 +20747365746d654d +6961662072646461 +2f6425203a64656c +726f727265206425 +0000000000000a73 +20747365746d654d +00000000000a4b4f +64656570736d654d +3a73657469725720 +7370624d646c2520 +203a736461655220 +0a7370624d646c25 +0000000000000000 +6f6e204d41524453 +207265646e752077 +6572617764726168 +6c6f72746e6f6320 +000000000000000a +696c616974696e49 +52445320676e697a +00000a2e2e2e4d41 +0000000000000000 +00000000000000ff +000000000000ffff +0000000000ffffff +00000000ffffffff +000000ffffffffff +0000ffffffffffff +00ffffffffffffff +ffffffffffffffff +0000000000007830 diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v new file mode 100644 index 0000000..1e93917 --- /dev/null +++ b/litedram/generated/sim/litedram_core.v @@ -0,0 +1,13430 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-05 11:21:54 +//-------------------------------------------------------------------------------- +module litedram_core( + input wire clk, + output wire init_done, + output wire init_error, + input wire [29:0] wb_ctrl_adr, + input wire [31:0] wb_ctrl_dat_w, + output wire [31:0] wb_ctrl_dat_r, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_cyc, + input wire wb_ctrl_stb, + output wire wb_ctrl_ack, + input wire wb_ctrl_we, + input wire [2:0] wb_ctrl_cti, + input wire [1:0] wb_ctrl_bte, + output wire wb_ctrl_err, + output wire user_clk, + output wire user_rst, + input wire user_port_native_0_cmd_valid, + output wire user_port_native_0_cmd_ready, + input wire user_port_native_0_cmd_we, + input wire [23:0] user_port_native_0_cmd_addr, + input wire user_port_native_0_wdata_valid, + output wire user_port_native_0_wdata_ready, + input wire [15:0] user_port_native_0_wdata_we, + input wire [127:0] user_port_native_0_wdata_data, + output wire user_port_native_0_rdata_valid, + input wire user_port_native_0_rdata_ready, + output wire [127:0] user_port_native_0_rdata_data +); + +reg [13:0] litedramcore_adr = 14'd0; +reg litedramcore_we = 1'd0; +wire [31:0] litedramcore_dat_w; +wire [31:0] litedramcore_dat_r; +wire [29:0] litedramcore_wishbone_adr; +wire [31:0] litedramcore_wishbone_dat_w; +wire [31:0] litedramcore_wishbone_dat_r; +wire [3:0] litedramcore_wishbone_sel; +wire litedramcore_wishbone_cyc; +wire litedramcore_wishbone_stb; +reg litedramcore_wishbone_ack = 1'd0; +wire litedramcore_wishbone_we; +wire [2:0] litedramcore_wishbone_cti; +wire [1:0] litedramcore_wishbone_bte; +reg litedramcore_wishbone_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire por_clk; +reg int_rst = 1'd1; +wire [13:0] ddrphy_dfi_p0_address; +wire [2:0] ddrphy_dfi_p0_bank; +wire ddrphy_dfi_p0_cas_n; +wire ddrphy_dfi_p0_cs_n; +wire ddrphy_dfi_p0_ras_n; +wire ddrphy_dfi_p0_we_n; +wire ddrphy_dfi_p0_cke; +wire ddrphy_dfi_p0_odt; +wire ddrphy_dfi_p0_reset_n; +wire ddrphy_dfi_p0_act_n; +wire [31:0] ddrphy_dfi_p0_wrdata; +wire ddrphy_dfi_p0_wrdata_en; +wire [3:0] ddrphy_dfi_p0_wrdata_mask; +wire ddrphy_dfi_p0_rddata_en; +wire [31:0] ddrphy_dfi_p0_rddata; +wire ddrphy_dfi_p0_rddata_valid; +wire [13:0] ddrphy_dfi_p1_address; +wire [2:0] ddrphy_dfi_p1_bank; +wire ddrphy_dfi_p1_cas_n; +wire ddrphy_dfi_p1_cs_n; +wire ddrphy_dfi_p1_ras_n; +wire ddrphy_dfi_p1_we_n; +wire ddrphy_dfi_p1_cke; +wire ddrphy_dfi_p1_odt; +wire ddrphy_dfi_p1_reset_n; +wire ddrphy_dfi_p1_act_n; +wire [31:0] ddrphy_dfi_p1_wrdata; +wire ddrphy_dfi_p1_wrdata_en; +wire [3:0] ddrphy_dfi_p1_wrdata_mask; +wire ddrphy_dfi_p1_rddata_en; +wire [31:0] ddrphy_dfi_p1_rddata; +wire ddrphy_dfi_p1_rddata_valid; +wire [13:0] ddrphy_dfi_p2_address; +wire [2:0] ddrphy_dfi_p2_bank; +wire ddrphy_dfi_p2_cas_n; +wire ddrphy_dfi_p2_cs_n; +wire ddrphy_dfi_p2_ras_n; +wire ddrphy_dfi_p2_we_n; +wire ddrphy_dfi_p2_cke; +wire ddrphy_dfi_p2_odt; +wire ddrphy_dfi_p2_reset_n; +wire ddrphy_dfi_p2_act_n; +wire [31:0] ddrphy_dfi_p2_wrdata; +wire ddrphy_dfi_p2_wrdata_en; +wire [3:0] ddrphy_dfi_p2_wrdata_mask; +wire ddrphy_dfi_p2_rddata_en; +wire [31:0] ddrphy_dfi_p2_rddata; +wire ddrphy_dfi_p2_rddata_valid; +wire [13:0] ddrphy_dfi_p3_address; +wire [2:0] ddrphy_dfi_p3_bank; +wire ddrphy_dfi_p3_cas_n; +wire ddrphy_dfi_p3_cs_n; +wire ddrphy_dfi_p3_ras_n; +wire ddrphy_dfi_p3_we_n; +wire ddrphy_dfi_p3_cke; +wire ddrphy_dfi_p3_odt; +wire ddrphy_dfi_p3_reset_n; +wire ddrphy_dfi_p3_act_n; +wire [31:0] ddrphy_dfi_p3_wrdata; +wire ddrphy_dfi_p3_wrdata_en; +wire [3:0] ddrphy_dfi_p3_wrdata_mask; +wire ddrphy_dfi_p3_rddata_en; +wire [31:0] ddrphy_dfi_p3_rddata; +wire ddrphy_dfi_p3_rddata_valid; +reg ddrphy_dfiphasemodel0_activate = 1'd0; +reg ddrphy_dfiphasemodel0_precharge = 1'd0; +reg ddrphy_dfiphasemodel0_write = 1'd0; +reg ddrphy_dfiphasemodel0_read = 1'd0; +reg ddrphy_dfiphasemodel1_activate = 1'd0; +reg ddrphy_dfiphasemodel1_precharge = 1'd0; +reg ddrphy_dfiphasemodel1_write = 1'd0; +reg ddrphy_dfiphasemodel1_read = 1'd0; +reg ddrphy_dfiphasemodel2_activate = 1'd0; +reg ddrphy_dfiphasemodel2_precharge = 1'd0; +reg ddrphy_dfiphasemodel2_write = 1'd0; +reg ddrphy_dfiphasemodel2_read = 1'd0; +reg ddrphy_dfiphasemodel3_activate = 1'd0; +reg ddrphy_dfiphasemodel3_precharge = 1'd0; +reg ddrphy_dfiphasemodel3_write = 1'd0; +reg ddrphy_dfiphasemodel3_read = 1'd0; +reg ddrphy_bankmodel0_activate = 1'd0; +reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0; +reg ddrphy_bankmodel0_precharge = 1'd0; +wire ddrphy_bankmodel0_write; +wire [9:0] ddrphy_bankmodel0_write_col; +wire [127:0] ddrphy_bankmodel0_write_data; +wire [15:0] ddrphy_bankmodel0_write_mask; +reg ddrphy_bankmodel0_read = 1'd0; +reg [9:0] ddrphy_bankmodel0_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel0_read_data = 128'd0; +reg ddrphy_bankmodel0_active = 1'd0; +reg [13:0] ddrphy_bankmodel0_row = 14'd0; +reg [20:0] ddrphy_bankmodel0_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel0_write_port_dat_r; +reg [15:0] ddrphy_bankmodel0_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel0_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel0_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel0_read_port_dat_r; +wire [20:0] ddrphy_bankmodel0_wraddr; +wire [20:0] ddrphy_bankmodel0_rdaddr; +reg ddrphy_bankmodel1_activate = 1'd0; +reg [13:0] ddrphy_bankmodel1_activate_row = 14'd0; +reg ddrphy_bankmodel1_precharge = 1'd0; +wire ddrphy_bankmodel1_write; +wire [9:0] ddrphy_bankmodel1_write_col; +wire [127:0] ddrphy_bankmodel1_write_data; +wire [15:0] ddrphy_bankmodel1_write_mask; +reg ddrphy_bankmodel1_read = 1'd0; +reg [9:0] ddrphy_bankmodel1_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel1_read_data = 128'd0; +reg ddrphy_bankmodel1_active = 1'd0; +reg [13:0] ddrphy_bankmodel1_row = 14'd0; +reg [20:0] ddrphy_bankmodel1_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel1_write_port_dat_r; +reg [15:0] ddrphy_bankmodel1_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel1_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel1_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel1_read_port_dat_r; +wire [20:0] ddrphy_bankmodel1_wraddr; +wire [20:0] ddrphy_bankmodel1_rdaddr; +reg ddrphy_bankmodel2_activate = 1'd0; +reg [13:0] ddrphy_bankmodel2_activate_row = 14'd0; +reg ddrphy_bankmodel2_precharge = 1'd0; +wire ddrphy_bankmodel2_write; +wire [9:0] ddrphy_bankmodel2_write_col; +wire [127:0] ddrphy_bankmodel2_write_data; +wire [15:0] ddrphy_bankmodel2_write_mask; +reg ddrphy_bankmodel2_read = 1'd0; +reg [9:0] ddrphy_bankmodel2_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel2_read_data = 128'd0; +reg ddrphy_bankmodel2_active = 1'd0; +reg [13:0] ddrphy_bankmodel2_row = 14'd0; +reg [20:0] ddrphy_bankmodel2_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel2_write_port_dat_r; +reg [15:0] ddrphy_bankmodel2_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel2_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel2_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel2_read_port_dat_r; +wire [20:0] ddrphy_bankmodel2_wraddr; +wire [20:0] ddrphy_bankmodel2_rdaddr; +reg ddrphy_bankmodel3_activate = 1'd0; +reg [13:0] ddrphy_bankmodel3_activate_row = 14'd0; +reg ddrphy_bankmodel3_precharge = 1'd0; +wire ddrphy_bankmodel3_write; +wire [9:0] ddrphy_bankmodel3_write_col; +wire [127:0] ddrphy_bankmodel3_write_data; +wire [15:0] ddrphy_bankmodel3_write_mask; +reg ddrphy_bankmodel3_read = 1'd0; +reg [9:0] ddrphy_bankmodel3_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel3_read_data = 128'd0; +reg ddrphy_bankmodel3_active = 1'd0; +reg [13:0] ddrphy_bankmodel3_row = 14'd0; +reg [20:0] ddrphy_bankmodel3_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel3_write_port_dat_r; +reg [15:0] ddrphy_bankmodel3_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel3_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel3_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel3_read_port_dat_r; +wire [20:0] ddrphy_bankmodel3_wraddr; +wire [20:0] ddrphy_bankmodel3_rdaddr; +reg ddrphy_bankmodel4_activate = 1'd0; +reg [13:0] ddrphy_bankmodel4_activate_row = 14'd0; +reg ddrphy_bankmodel4_precharge = 1'd0; +wire ddrphy_bankmodel4_write; +wire [9:0] ddrphy_bankmodel4_write_col; +wire [127:0] ddrphy_bankmodel4_write_data; +wire [15:0] ddrphy_bankmodel4_write_mask; +reg ddrphy_bankmodel4_read = 1'd0; +reg [9:0] ddrphy_bankmodel4_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel4_read_data = 128'd0; +reg ddrphy_bankmodel4_active = 1'd0; +reg [13:0] ddrphy_bankmodel4_row = 14'd0; +reg [20:0] ddrphy_bankmodel4_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel4_write_port_dat_r; +reg [15:0] ddrphy_bankmodel4_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel4_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel4_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel4_read_port_dat_r; +wire [20:0] ddrphy_bankmodel4_wraddr; +wire [20:0] ddrphy_bankmodel4_rdaddr; +reg ddrphy_bankmodel5_activate = 1'd0; +reg [13:0] ddrphy_bankmodel5_activate_row = 14'd0; +reg ddrphy_bankmodel5_precharge = 1'd0; +wire ddrphy_bankmodel5_write; +wire [9:0] ddrphy_bankmodel5_write_col; +wire [127:0] ddrphy_bankmodel5_write_data; +wire [15:0] ddrphy_bankmodel5_write_mask; +reg ddrphy_bankmodel5_read = 1'd0; +reg [9:0] ddrphy_bankmodel5_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel5_read_data = 128'd0; +reg ddrphy_bankmodel5_active = 1'd0; +reg [13:0] ddrphy_bankmodel5_row = 14'd0; +reg [20:0] ddrphy_bankmodel5_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel5_write_port_dat_r; +reg [15:0] ddrphy_bankmodel5_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel5_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel5_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel5_read_port_dat_r; +wire [20:0] ddrphy_bankmodel5_wraddr; +wire [20:0] ddrphy_bankmodel5_rdaddr; +reg ddrphy_bankmodel6_activate = 1'd0; +reg [13:0] ddrphy_bankmodel6_activate_row = 14'd0; +reg ddrphy_bankmodel6_precharge = 1'd0; +wire ddrphy_bankmodel6_write; +wire [9:0] ddrphy_bankmodel6_write_col; +wire [127:0] ddrphy_bankmodel6_write_data; +wire [15:0] ddrphy_bankmodel6_write_mask; +reg ddrphy_bankmodel6_read = 1'd0; +reg [9:0] ddrphy_bankmodel6_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel6_read_data = 128'd0; +reg ddrphy_bankmodel6_active = 1'd0; +reg [13:0] ddrphy_bankmodel6_row = 14'd0; +reg [20:0] ddrphy_bankmodel6_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel6_write_port_dat_r; +reg [15:0] ddrphy_bankmodel6_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel6_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel6_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel6_read_port_dat_r; +wire [20:0] ddrphy_bankmodel6_wraddr; +wire [20:0] ddrphy_bankmodel6_rdaddr; +reg ddrphy_bankmodel7_activate = 1'd0; +reg [13:0] ddrphy_bankmodel7_activate_row = 14'd0; +reg ddrphy_bankmodel7_precharge = 1'd0; +wire ddrphy_bankmodel7_write; +wire [9:0] ddrphy_bankmodel7_write_col; +wire [127:0] ddrphy_bankmodel7_write_data; +wire [15:0] ddrphy_bankmodel7_write_mask; +reg ddrphy_bankmodel7_read = 1'd0; +reg [9:0] ddrphy_bankmodel7_read_col = 10'd0; +reg [127:0] ddrphy_bankmodel7_read_data = 128'd0; +reg ddrphy_bankmodel7_active = 1'd0; +reg [13:0] ddrphy_bankmodel7_row = 14'd0; +reg [20:0] ddrphy_bankmodel7_write_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel7_write_port_dat_r; +reg [15:0] ddrphy_bankmodel7_write_port_we = 16'd0; +reg [127:0] ddrphy_bankmodel7_write_port_dat_w = 128'd0; +reg [20:0] ddrphy_bankmodel7_read_port_adr = 21'd0; +wire [127:0] ddrphy_bankmodel7_read_port_dat_r; +wire [20:0] ddrphy_bankmodel7_wraddr; +wire [20:0] ddrphy_bankmodel7_rdaddr; +reg [3:0] ddrphy_activates0 = 4'd0; +reg [3:0] ddrphy_precharges0 = 4'd0; +reg ddrphy_bank_write0 = 1'd0; +reg [9:0] ddrphy_bank_write_col0 = 10'd0; +reg [3:0] ddrphy_writes0 = 4'd0; +reg ddrphy_new_bank_write0 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col0 = 10'd0; +reg ddrphy_new_bank_write1 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col1 = 10'd0; +reg [3:0] ddrphy_reads0 = 4'd0; +reg [3:0] ddrphy_activates1 = 4'd0; +reg [3:0] ddrphy_precharges1 = 4'd0; +reg ddrphy_bank_write1 = 1'd0; +reg [9:0] ddrphy_bank_write_col1 = 10'd0; +reg [3:0] ddrphy_writes1 = 4'd0; +reg ddrphy_new_bank_write2 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col2 = 10'd0; +reg ddrphy_new_bank_write3 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col3 = 10'd0; +reg [3:0] ddrphy_reads1 = 4'd0; +reg [3:0] ddrphy_activates2 = 4'd0; +reg [3:0] ddrphy_precharges2 = 4'd0; +reg ddrphy_bank_write2 = 1'd0; +reg [9:0] ddrphy_bank_write_col2 = 10'd0; +reg [3:0] ddrphy_writes2 = 4'd0; +reg ddrphy_new_bank_write4 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col4 = 10'd0; +reg ddrphy_new_bank_write5 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col5 = 10'd0; +reg [3:0] ddrphy_reads2 = 4'd0; +reg [3:0] ddrphy_activates3 = 4'd0; +reg [3:0] ddrphy_precharges3 = 4'd0; +reg ddrphy_bank_write3 = 1'd0; +reg [9:0] ddrphy_bank_write_col3 = 10'd0; +reg [3:0] ddrphy_writes3 = 4'd0; +reg ddrphy_new_bank_write6 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col6 = 10'd0; +reg ddrphy_new_bank_write7 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col7 = 10'd0; +reg [3:0] ddrphy_reads3 = 4'd0; +reg [3:0] ddrphy_activates4 = 4'd0; +reg [3:0] ddrphy_precharges4 = 4'd0; +reg ddrphy_bank_write4 = 1'd0; +reg [9:0] ddrphy_bank_write_col4 = 10'd0; +reg [3:0] ddrphy_writes4 = 4'd0; +reg ddrphy_new_bank_write8 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col8 = 10'd0; +reg ddrphy_new_bank_write9 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col9 = 10'd0; +reg [3:0] ddrphy_reads4 = 4'd0; +reg [3:0] ddrphy_activates5 = 4'd0; +reg [3:0] ddrphy_precharges5 = 4'd0; +reg ddrphy_bank_write5 = 1'd0; +reg [9:0] ddrphy_bank_write_col5 = 10'd0; +reg [3:0] ddrphy_writes5 = 4'd0; +reg ddrphy_new_bank_write10 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col10 = 10'd0; +reg ddrphy_new_bank_write11 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col11 = 10'd0; +reg [3:0] ddrphy_reads5 = 4'd0; +reg [3:0] ddrphy_activates6 = 4'd0; +reg [3:0] ddrphy_precharges6 = 4'd0; +reg ddrphy_bank_write6 = 1'd0; +reg [9:0] ddrphy_bank_write_col6 = 10'd0; +reg [3:0] ddrphy_writes6 = 4'd0; +reg ddrphy_new_bank_write12 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col12 = 10'd0; +reg ddrphy_new_bank_write13 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col13 = 10'd0; +reg [3:0] ddrphy_reads6 = 4'd0; +reg [3:0] ddrphy_activates7 = 4'd0; +reg [3:0] ddrphy_precharges7 = 4'd0; +reg ddrphy_bank_write7 = 1'd0; +reg [9:0] ddrphy_bank_write_col7 = 10'd0; +reg [3:0] ddrphy_writes7 = 4'd0; +reg ddrphy_new_bank_write14 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col14 = 10'd0; +reg ddrphy_new_bank_write15 = 1'd0; +reg [9:0] ddrphy_new_bank_write_col15 = 10'd0; +reg [3:0] ddrphy_reads7 = 4'd0; +wire ddrphy_banks_read; +wire [127:0] ddrphy_banks_read_data; +reg ddrphy_new_banks_read0 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data0 = 128'd0; +reg ddrphy_new_banks_read1 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data1 = 128'd0; +reg ddrphy_new_banks_read2 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data2 = 128'd0; +reg ddrphy_new_banks_read3 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data3 = 128'd0; +reg ddrphy_new_banks_read4 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data4 = 128'd0; +reg ddrphy_new_banks_read5 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data5 = 128'd0; +reg ddrphy_new_banks_read6 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data6 = 128'd0; +reg ddrphy_new_banks_read7 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data7 = 128'd0; +reg ddrphy_new_banks_read8 = 1'd0; +reg [127:0] ddrphy_new_banks_read_data8 = 128'd0; +wire [13:0] litedramcore_inti_p0_address; +wire [2:0] litedramcore_inti_p0_bank; +reg litedramcore_inti_p0_cas_n = 1'd1; +reg litedramcore_inti_p0_cs_n = 1'd1; +reg litedramcore_inti_p0_ras_n = 1'd1; +reg litedramcore_inti_p0_we_n = 1'd1; +wire litedramcore_inti_p0_cke; +wire litedramcore_inti_p0_odt; +wire litedramcore_inti_p0_reset_n; +reg litedramcore_inti_p0_act_n = 1'd1; +wire [31:0] litedramcore_inti_p0_wrdata; +wire litedramcore_inti_p0_wrdata_en; +wire [3:0] litedramcore_inti_p0_wrdata_mask; +wire litedramcore_inti_p0_rddata_en; +reg [31:0] litedramcore_inti_p0_rddata = 32'd0; +reg litedramcore_inti_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p1_address; +wire [2:0] litedramcore_inti_p1_bank; +reg litedramcore_inti_p1_cas_n = 1'd1; +reg litedramcore_inti_p1_cs_n = 1'd1; +reg litedramcore_inti_p1_ras_n = 1'd1; +reg litedramcore_inti_p1_we_n = 1'd1; +wire litedramcore_inti_p1_cke; +wire litedramcore_inti_p1_odt; +wire litedramcore_inti_p1_reset_n; +reg litedramcore_inti_p1_act_n = 1'd1; +wire [31:0] litedramcore_inti_p1_wrdata; +wire litedramcore_inti_p1_wrdata_en; +wire [3:0] litedramcore_inti_p1_wrdata_mask; +wire litedramcore_inti_p1_rddata_en; +reg [31:0] litedramcore_inti_p1_rddata = 32'd0; +reg litedramcore_inti_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p2_address; +wire [2:0] litedramcore_inti_p2_bank; +reg litedramcore_inti_p2_cas_n = 1'd1; +reg litedramcore_inti_p2_cs_n = 1'd1; +reg litedramcore_inti_p2_ras_n = 1'd1; +reg litedramcore_inti_p2_we_n = 1'd1; +wire litedramcore_inti_p2_cke; +wire litedramcore_inti_p2_odt; +wire litedramcore_inti_p2_reset_n; +reg litedramcore_inti_p2_act_n = 1'd1; +wire [31:0] litedramcore_inti_p2_wrdata; +wire litedramcore_inti_p2_wrdata_en; +wire [3:0] litedramcore_inti_p2_wrdata_mask; +wire litedramcore_inti_p2_rddata_en; +reg [31:0] litedramcore_inti_p2_rddata = 32'd0; +reg litedramcore_inti_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_inti_p3_address; +wire [2:0] litedramcore_inti_p3_bank; +reg litedramcore_inti_p3_cas_n = 1'd1; +reg litedramcore_inti_p3_cs_n = 1'd1; +reg litedramcore_inti_p3_ras_n = 1'd1; +reg litedramcore_inti_p3_we_n = 1'd1; +wire litedramcore_inti_p3_cke; +wire litedramcore_inti_p3_odt; +wire litedramcore_inti_p3_reset_n; +reg litedramcore_inti_p3_act_n = 1'd1; +wire [31:0] litedramcore_inti_p3_wrdata; +wire litedramcore_inti_p3_wrdata_en; +wire [3:0] litedramcore_inti_p3_wrdata_mask; +wire litedramcore_inti_p3_rddata_en; +reg [31:0] litedramcore_inti_p3_rddata = 32'd0; +reg litedramcore_inti_p3_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p0_address; +wire [2:0] litedramcore_slave_p0_bank; +wire litedramcore_slave_p0_cas_n; +wire litedramcore_slave_p0_cs_n; +wire litedramcore_slave_p0_ras_n; +wire litedramcore_slave_p0_we_n; +wire litedramcore_slave_p0_cke; +wire litedramcore_slave_p0_odt; +wire litedramcore_slave_p0_reset_n; +wire litedramcore_slave_p0_act_n; +wire [31:0] litedramcore_slave_p0_wrdata; +wire litedramcore_slave_p0_wrdata_en; +wire [3:0] litedramcore_slave_p0_wrdata_mask; +wire litedramcore_slave_p0_rddata_en; +reg [31:0] litedramcore_slave_p0_rddata = 32'd0; +reg litedramcore_slave_p0_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p1_address; +wire [2:0] litedramcore_slave_p1_bank; +wire litedramcore_slave_p1_cas_n; +wire litedramcore_slave_p1_cs_n; +wire litedramcore_slave_p1_ras_n; +wire litedramcore_slave_p1_we_n; +wire litedramcore_slave_p1_cke; +wire litedramcore_slave_p1_odt; +wire litedramcore_slave_p1_reset_n; +wire litedramcore_slave_p1_act_n; +wire [31:0] litedramcore_slave_p1_wrdata; +wire litedramcore_slave_p1_wrdata_en; +wire [3:0] litedramcore_slave_p1_wrdata_mask; +wire litedramcore_slave_p1_rddata_en; +reg [31:0] litedramcore_slave_p1_rddata = 32'd0; +reg litedramcore_slave_p1_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p2_address; +wire [2:0] litedramcore_slave_p2_bank; +wire litedramcore_slave_p2_cas_n; +wire litedramcore_slave_p2_cs_n; +wire litedramcore_slave_p2_ras_n; +wire litedramcore_slave_p2_we_n; +wire litedramcore_slave_p2_cke; +wire litedramcore_slave_p2_odt; +wire litedramcore_slave_p2_reset_n; +wire litedramcore_slave_p2_act_n; +wire [31:0] litedramcore_slave_p2_wrdata; +wire litedramcore_slave_p2_wrdata_en; +wire [3:0] litedramcore_slave_p2_wrdata_mask; +wire litedramcore_slave_p2_rddata_en; +reg [31:0] litedramcore_slave_p2_rddata = 32'd0; +reg litedramcore_slave_p2_rddata_valid = 1'd0; +wire [13:0] litedramcore_slave_p3_address; +wire [2:0] litedramcore_slave_p3_bank; +wire litedramcore_slave_p3_cas_n; +wire litedramcore_slave_p3_cs_n; +wire litedramcore_slave_p3_ras_n; +wire litedramcore_slave_p3_we_n; +wire litedramcore_slave_p3_cke; +wire litedramcore_slave_p3_odt; +wire litedramcore_slave_p3_reset_n; +wire litedramcore_slave_p3_act_n; +wire [31:0] litedramcore_slave_p3_wrdata; +wire litedramcore_slave_p3_wrdata_en; +wire [3:0] litedramcore_slave_p3_wrdata_mask; +wire litedramcore_slave_p3_rddata_en; +reg [31:0] litedramcore_slave_p3_rddata = 32'd0; +reg litedramcore_slave_p3_rddata_valid = 1'd0; +reg [13:0] litedramcore_master_p0_address = 14'd0; +reg [2:0] litedramcore_master_p0_bank = 3'd0; +reg litedramcore_master_p0_cas_n = 1'd1; +reg litedramcore_master_p0_cs_n = 1'd1; +reg litedramcore_master_p0_ras_n = 1'd1; +reg litedramcore_master_p0_we_n = 1'd1; +reg litedramcore_master_p0_cke = 1'd0; +reg litedramcore_master_p0_odt = 1'd0; +reg litedramcore_master_p0_reset_n = 1'd0; +reg litedramcore_master_p0_act_n = 1'd1; +reg [31:0] litedramcore_master_p0_wrdata = 32'd0; +reg litedramcore_master_p0_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0; +reg litedramcore_master_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p0_rddata; +wire litedramcore_master_p0_rddata_valid; +reg [13:0] litedramcore_master_p1_address = 14'd0; +reg [2:0] litedramcore_master_p1_bank = 3'd0; +reg litedramcore_master_p1_cas_n = 1'd1; +reg litedramcore_master_p1_cs_n = 1'd1; +reg litedramcore_master_p1_ras_n = 1'd1; +reg litedramcore_master_p1_we_n = 1'd1; +reg litedramcore_master_p1_cke = 1'd0; +reg litedramcore_master_p1_odt = 1'd0; +reg litedramcore_master_p1_reset_n = 1'd0; +reg litedramcore_master_p1_act_n = 1'd1; +reg [31:0] litedramcore_master_p1_wrdata = 32'd0; +reg litedramcore_master_p1_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0; +reg litedramcore_master_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p1_rddata; +wire litedramcore_master_p1_rddata_valid; +reg [13:0] litedramcore_master_p2_address = 14'd0; +reg [2:0] litedramcore_master_p2_bank = 3'd0; +reg litedramcore_master_p2_cas_n = 1'd1; +reg litedramcore_master_p2_cs_n = 1'd1; +reg litedramcore_master_p2_ras_n = 1'd1; +reg litedramcore_master_p2_we_n = 1'd1; +reg litedramcore_master_p2_cke = 1'd0; +reg litedramcore_master_p2_odt = 1'd0; +reg litedramcore_master_p2_reset_n = 1'd0; +reg litedramcore_master_p2_act_n = 1'd1; +reg [31:0] litedramcore_master_p2_wrdata = 32'd0; +reg litedramcore_master_p2_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0; +reg litedramcore_master_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p2_rddata; +wire litedramcore_master_p2_rddata_valid; +reg [13:0] litedramcore_master_p3_address = 14'd0; +reg [2:0] litedramcore_master_p3_bank = 3'd0; +reg litedramcore_master_p3_cas_n = 1'd1; +reg litedramcore_master_p3_cs_n = 1'd1; +reg litedramcore_master_p3_ras_n = 1'd1; +reg litedramcore_master_p3_we_n = 1'd1; +reg litedramcore_master_p3_cke = 1'd0; +reg litedramcore_master_p3_odt = 1'd0; +reg litedramcore_master_p3_reset_n = 1'd0; +reg litedramcore_master_p3_act_n = 1'd1; +reg [31:0] litedramcore_master_p3_wrdata = 32'd0; +reg litedramcore_master_p3_wrdata_en = 1'd0; +reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0; +reg litedramcore_master_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_master_p3_rddata; +wire litedramcore_master_p3_rddata_valid; +reg [3:0] litedramcore_storage = 4'd1; +reg litedramcore_re = 1'd0; +reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0; +reg litedramcore_phaseinjector0_command_re = 1'd0; +wire litedramcore_phaseinjector0_command_issue_re; +wire litedramcore_phaseinjector0_command_issue_r; +wire litedramcore_phaseinjector0_command_issue_we; +reg litedramcore_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0; +reg litedramcore_phaseinjector0_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0; +reg litedramcore_phaseinjector0_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector0_status = 32'd0; +wire litedramcore_phaseinjector0_we; +reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0; +reg litedramcore_phaseinjector1_command_re = 1'd0; +wire litedramcore_phaseinjector1_command_issue_re; +wire litedramcore_phaseinjector1_command_issue_r; +wire litedramcore_phaseinjector1_command_issue_we; +reg litedramcore_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0; +reg litedramcore_phaseinjector1_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0; +reg litedramcore_phaseinjector1_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector1_status = 32'd0; +wire litedramcore_phaseinjector1_we; +reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0; +reg litedramcore_phaseinjector2_command_re = 1'd0; +wire litedramcore_phaseinjector2_command_issue_re; +wire litedramcore_phaseinjector2_command_issue_r; +wire litedramcore_phaseinjector2_command_issue_we; +reg litedramcore_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0; +reg litedramcore_phaseinjector2_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0; +reg litedramcore_phaseinjector2_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector2_status = 32'd0; +wire litedramcore_phaseinjector2_we; +reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0; +reg litedramcore_phaseinjector3_command_re = 1'd0; +wire litedramcore_phaseinjector3_command_issue_re; +wire litedramcore_phaseinjector3_command_issue_r; +wire litedramcore_phaseinjector3_command_issue_we; +reg litedramcore_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0; +reg litedramcore_phaseinjector3_address_re = 1'd0; +reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0; +reg litedramcore_phaseinjector3_baddress_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0; +reg litedramcore_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] litedramcore_phaseinjector3_status = 32'd0; +wire litedramcore_phaseinjector3_we; +wire litedramcore_interface_bank0_valid; +wire litedramcore_interface_bank0_ready; +wire litedramcore_interface_bank0_we; +wire [20:0] litedramcore_interface_bank0_addr; +wire litedramcore_interface_bank0_lock; +wire litedramcore_interface_bank0_wdata_ready; +wire litedramcore_interface_bank0_rdata_valid; +wire litedramcore_interface_bank1_valid; +wire litedramcore_interface_bank1_ready; +wire litedramcore_interface_bank1_we; +wire [20:0] litedramcore_interface_bank1_addr; +wire litedramcore_interface_bank1_lock; +wire litedramcore_interface_bank1_wdata_ready; +wire litedramcore_interface_bank1_rdata_valid; +wire litedramcore_interface_bank2_valid; +wire litedramcore_interface_bank2_ready; +wire litedramcore_interface_bank2_we; +wire [20:0] litedramcore_interface_bank2_addr; +wire litedramcore_interface_bank2_lock; +wire litedramcore_interface_bank2_wdata_ready; +wire litedramcore_interface_bank2_rdata_valid; +wire litedramcore_interface_bank3_valid; +wire litedramcore_interface_bank3_ready; +wire litedramcore_interface_bank3_we; +wire [20:0] litedramcore_interface_bank3_addr; +wire litedramcore_interface_bank3_lock; +wire litedramcore_interface_bank3_wdata_ready; +wire litedramcore_interface_bank3_rdata_valid; +wire litedramcore_interface_bank4_valid; +wire litedramcore_interface_bank4_ready; +wire litedramcore_interface_bank4_we; +wire [20:0] litedramcore_interface_bank4_addr; +wire litedramcore_interface_bank4_lock; +wire litedramcore_interface_bank4_wdata_ready; +wire litedramcore_interface_bank4_rdata_valid; +wire litedramcore_interface_bank5_valid; +wire litedramcore_interface_bank5_ready; +wire litedramcore_interface_bank5_we; +wire [20:0] litedramcore_interface_bank5_addr; +wire litedramcore_interface_bank5_lock; +wire litedramcore_interface_bank5_wdata_ready; +wire litedramcore_interface_bank5_rdata_valid; +wire litedramcore_interface_bank6_valid; +wire litedramcore_interface_bank6_ready; +wire litedramcore_interface_bank6_we; +wire [20:0] litedramcore_interface_bank6_addr; +wire litedramcore_interface_bank6_lock; +wire litedramcore_interface_bank6_wdata_ready; +wire litedramcore_interface_bank6_rdata_valid; +wire litedramcore_interface_bank7_valid; +wire litedramcore_interface_bank7_ready; +wire litedramcore_interface_bank7_we; +wire [20:0] litedramcore_interface_bank7_addr; +wire litedramcore_interface_bank7_lock; +wire litedramcore_interface_bank7_wdata_ready; +wire litedramcore_interface_bank7_rdata_valid; +reg [127:0] litedramcore_interface_wdata = 128'd0; +reg [15:0] litedramcore_interface_wdata_we = 16'd0; +wire [127:0] litedramcore_interface_rdata; +reg [13:0] litedramcore_dfi_p0_address = 14'd0; +reg [2:0] litedramcore_dfi_p0_bank = 3'd0; +reg litedramcore_dfi_p0_cas_n = 1'd1; +reg litedramcore_dfi_p0_cs_n = 1'd1; +reg litedramcore_dfi_p0_ras_n = 1'd1; +reg litedramcore_dfi_p0_we_n = 1'd1; +wire litedramcore_dfi_p0_cke; +wire litedramcore_dfi_p0_odt; +wire litedramcore_dfi_p0_reset_n; +reg litedramcore_dfi_p0_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p0_wrdata; +reg litedramcore_dfi_p0_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p0_wrdata_mask; +reg litedramcore_dfi_p0_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p0_rddata; +wire litedramcore_dfi_p0_rddata_valid; +reg [13:0] litedramcore_dfi_p1_address = 14'd0; +reg [2:0] litedramcore_dfi_p1_bank = 3'd0; +reg litedramcore_dfi_p1_cas_n = 1'd1; +reg litedramcore_dfi_p1_cs_n = 1'd1; +reg litedramcore_dfi_p1_ras_n = 1'd1; +reg litedramcore_dfi_p1_we_n = 1'd1; +wire litedramcore_dfi_p1_cke; +wire litedramcore_dfi_p1_odt; +wire litedramcore_dfi_p1_reset_n; +reg litedramcore_dfi_p1_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p1_wrdata; +reg litedramcore_dfi_p1_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p1_wrdata_mask; +reg litedramcore_dfi_p1_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p1_rddata; +wire litedramcore_dfi_p1_rddata_valid; +reg [13:0] litedramcore_dfi_p2_address = 14'd0; +reg [2:0] litedramcore_dfi_p2_bank = 3'd0; +reg litedramcore_dfi_p2_cas_n = 1'd1; +reg litedramcore_dfi_p2_cs_n = 1'd1; +reg litedramcore_dfi_p2_ras_n = 1'd1; +reg litedramcore_dfi_p2_we_n = 1'd1; +wire litedramcore_dfi_p2_cke; +wire litedramcore_dfi_p2_odt; +wire litedramcore_dfi_p2_reset_n; +reg litedramcore_dfi_p2_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p2_wrdata; +reg litedramcore_dfi_p2_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p2_wrdata_mask; +reg litedramcore_dfi_p2_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p2_rddata; +wire litedramcore_dfi_p2_rddata_valid; +reg [13:0] litedramcore_dfi_p3_address = 14'd0; +reg [2:0] litedramcore_dfi_p3_bank = 3'd0; +reg litedramcore_dfi_p3_cas_n = 1'd1; +reg litedramcore_dfi_p3_cs_n = 1'd1; +reg litedramcore_dfi_p3_ras_n = 1'd1; +reg litedramcore_dfi_p3_we_n = 1'd1; +wire litedramcore_dfi_p3_cke; +wire litedramcore_dfi_p3_odt; +wire litedramcore_dfi_p3_reset_n; +reg litedramcore_dfi_p3_act_n = 1'd1; +wire [31:0] litedramcore_dfi_p3_wrdata; +reg litedramcore_dfi_p3_wrdata_en = 1'd0; +wire [3:0] litedramcore_dfi_p3_wrdata_mask; +reg litedramcore_dfi_p3_rddata_en = 1'd0; +wire [31:0] litedramcore_dfi_p3_rddata; +wire litedramcore_dfi_p3_rddata_valid; +reg litedramcore_cmd_valid = 1'd0; +reg litedramcore_cmd_ready = 1'd0; +reg litedramcore_cmd_last = 1'd0; +reg [13:0] litedramcore_cmd_payload_a = 14'd0; +reg [2:0] litedramcore_cmd_payload_ba = 3'd0; +reg litedramcore_cmd_payload_cas = 1'd0; +reg litedramcore_cmd_payload_ras = 1'd0; +reg litedramcore_cmd_payload_we = 1'd0; +reg litedramcore_cmd_payload_is_read = 1'd0; +reg litedramcore_cmd_payload_is_write = 1'd0; +wire litedramcore_wants_refresh; +wire litedramcore_wants_zqcs; +wire litedramcore_timer_wait; +wire litedramcore_timer_done0; +wire [9:0] litedramcore_timer_count0; +wire litedramcore_timer_done1; +reg [9:0] litedramcore_timer_count1 = 10'd781; +wire litedramcore_postponer_req_i; +reg litedramcore_postponer_req_o = 1'd0; +reg litedramcore_postponer_count = 1'd0; +reg litedramcore_sequencer_start0 = 1'd0; +wire litedramcore_sequencer_done0; +wire litedramcore_sequencer_start1; +reg litedramcore_sequencer_done1 = 1'd0; +reg [5:0] litedramcore_sequencer_counter = 6'd0; +reg litedramcore_sequencer_count = 1'd0; +wire litedramcore_zqcs_timer_wait; +wire litedramcore_zqcs_timer_done0; +wire [26:0] litedramcore_zqcs_timer_count0; +wire litedramcore_zqcs_timer_done1; +reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999; +reg litedramcore_zqcs_executer_start = 1'd0; +reg litedramcore_zqcs_executer_done = 1'd0; +reg [4:0] litedramcore_zqcs_executer_counter = 5'd0; +wire litedramcore_bankmachine0_req_valid; +wire litedramcore_bankmachine0_req_ready; +wire litedramcore_bankmachine0_req_we; +wire [20:0] litedramcore_bankmachine0_req_addr; +wire litedramcore_bankmachine0_req_lock; +reg litedramcore_bankmachine0_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine0_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine0_refresh_req; +reg litedramcore_bankmachine0_refresh_gnt = 1'd0; +reg litedramcore_bankmachine0_cmd_valid = 1'd0; +reg litedramcore_bankmachine0_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine0_cmd_payload_ba; +reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine0_auto_precharge = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_valid; +wire litedramcore_bankmachine0_cmd_buffer_sink_ready; +wire litedramcore_bankmachine0_cmd_buffer_sink_first; +wire litedramcore_bankmachine0_cmd_buffer_sink_last; +wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine0_cmd_buffer_source_ready; +reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine0_row = 14'd0; +reg litedramcore_bankmachine0_row_opened = 1'd0; +wire litedramcore_bankmachine0_row_hit; +reg litedramcore_bankmachine0_row_open = 1'd0; +reg litedramcore_bankmachine0_row_close = 1'd0; +reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine0_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0; +wire litedramcore_bankmachine0_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0; +wire litedramcore_bankmachine0_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0; +wire litedramcore_bankmachine1_req_valid; +wire litedramcore_bankmachine1_req_ready; +wire litedramcore_bankmachine1_req_we; +wire [20:0] litedramcore_bankmachine1_req_addr; +wire litedramcore_bankmachine1_req_lock; +reg litedramcore_bankmachine1_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine1_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine1_refresh_req; +reg litedramcore_bankmachine1_refresh_gnt = 1'd0; +reg litedramcore_bankmachine1_cmd_valid = 1'd0; +reg litedramcore_bankmachine1_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine1_cmd_payload_ba; +reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine1_auto_precharge = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_valid; +wire litedramcore_bankmachine1_cmd_buffer_sink_ready; +wire litedramcore_bankmachine1_cmd_buffer_sink_first; +wire litedramcore_bankmachine1_cmd_buffer_sink_last; +wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine1_cmd_buffer_source_ready; +reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine1_row = 14'd0; +reg litedramcore_bankmachine1_row_opened = 1'd0; +wire litedramcore_bankmachine1_row_hit; +reg litedramcore_bankmachine1_row_open = 1'd0; +reg litedramcore_bankmachine1_row_close = 1'd0; +reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine1_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0; +wire litedramcore_bankmachine1_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0; +wire litedramcore_bankmachine1_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0; +wire litedramcore_bankmachine2_req_valid; +wire litedramcore_bankmachine2_req_ready; +wire litedramcore_bankmachine2_req_we; +wire [20:0] litedramcore_bankmachine2_req_addr; +wire litedramcore_bankmachine2_req_lock; +reg litedramcore_bankmachine2_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine2_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine2_refresh_req; +reg litedramcore_bankmachine2_refresh_gnt = 1'd0; +reg litedramcore_bankmachine2_cmd_valid = 1'd0; +reg litedramcore_bankmachine2_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine2_cmd_payload_ba; +reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine2_auto_precharge = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_valid; +wire litedramcore_bankmachine2_cmd_buffer_sink_ready; +wire litedramcore_bankmachine2_cmd_buffer_sink_first; +wire litedramcore_bankmachine2_cmd_buffer_sink_last; +wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine2_cmd_buffer_source_ready; +reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine2_row = 14'd0; +reg litedramcore_bankmachine2_row_opened = 1'd0; +wire litedramcore_bankmachine2_row_hit; +reg litedramcore_bankmachine2_row_open = 1'd0; +reg litedramcore_bankmachine2_row_close = 1'd0; +reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine2_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0; +wire litedramcore_bankmachine2_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0; +wire litedramcore_bankmachine2_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0; +wire litedramcore_bankmachine3_req_valid; +wire litedramcore_bankmachine3_req_ready; +wire litedramcore_bankmachine3_req_we; +wire [20:0] litedramcore_bankmachine3_req_addr; +wire litedramcore_bankmachine3_req_lock; +reg litedramcore_bankmachine3_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine3_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine3_refresh_req; +reg litedramcore_bankmachine3_refresh_gnt = 1'd0; +reg litedramcore_bankmachine3_cmd_valid = 1'd0; +reg litedramcore_bankmachine3_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine3_cmd_payload_ba; +reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine3_auto_precharge = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_valid; +wire litedramcore_bankmachine3_cmd_buffer_sink_ready; +wire litedramcore_bankmachine3_cmd_buffer_sink_first; +wire litedramcore_bankmachine3_cmd_buffer_sink_last; +wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine3_cmd_buffer_source_ready; +reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine3_row = 14'd0; +reg litedramcore_bankmachine3_row_opened = 1'd0; +wire litedramcore_bankmachine3_row_hit; +reg litedramcore_bankmachine3_row_open = 1'd0; +reg litedramcore_bankmachine3_row_close = 1'd0; +reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine3_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0; +wire litedramcore_bankmachine3_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0; +wire litedramcore_bankmachine3_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0; +wire litedramcore_bankmachine4_req_valid; +wire litedramcore_bankmachine4_req_ready; +wire litedramcore_bankmachine4_req_we; +wire [20:0] litedramcore_bankmachine4_req_addr; +wire litedramcore_bankmachine4_req_lock; +reg litedramcore_bankmachine4_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine4_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine4_refresh_req; +reg litedramcore_bankmachine4_refresh_gnt = 1'd0; +reg litedramcore_bankmachine4_cmd_valid = 1'd0; +reg litedramcore_bankmachine4_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine4_cmd_payload_ba; +reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine4_auto_precharge = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_valid; +wire litedramcore_bankmachine4_cmd_buffer_sink_ready; +wire litedramcore_bankmachine4_cmd_buffer_sink_first; +wire litedramcore_bankmachine4_cmd_buffer_sink_last; +wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine4_cmd_buffer_source_ready; +reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine4_row = 14'd0; +reg litedramcore_bankmachine4_row_opened = 1'd0; +wire litedramcore_bankmachine4_row_hit; +reg litedramcore_bankmachine4_row_open = 1'd0; +reg litedramcore_bankmachine4_row_close = 1'd0; +reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine4_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0; +wire litedramcore_bankmachine4_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0; +wire litedramcore_bankmachine4_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0; +wire litedramcore_bankmachine5_req_valid; +wire litedramcore_bankmachine5_req_ready; +wire litedramcore_bankmachine5_req_we; +wire [20:0] litedramcore_bankmachine5_req_addr; +wire litedramcore_bankmachine5_req_lock; +reg litedramcore_bankmachine5_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine5_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine5_refresh_req; +reg litedramcore_bankmachine5_refresh_gnt = 1'd0; +reg litedramcore_bankmachine5_cmd_valid = 1'd0; +reg litedramcore_bankmachine5_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine5_cmd_payload_ba; +reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine5_auto_precharge = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_valid; +wire litedramcore_bankmachine5_cmd_buffer_sink_ready; +wire litedramcore_bankmachine5_cmd_buffer_sink_first; +wire litedramcore_bankmachine5_cmd_buffer_sink_last; +wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine5_cmd_buffer_source_ready; +reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine5_row = 14'd0; +reg litedramcore_bankmachine5_row_opened = 1'd0; +wire litedramcore_bankmachine5_row_hit; +reg litedramcore_bankmachine5_row_open = 1'd0; +reg litedramcore_bankmachine5_row_close = 1'd0; +reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine5_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0; +wire litedramcore_bankmachine5_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0; +wire litedramcore_bankmachine5_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0; +wire litedramcore_bankmachine6_req_valid; +wire litedramcore_bankmachine6_req_ready; +wire litedramcore_bankmachine6_req_we; +wire [20:0] litedramcore_bankmachine6_req_addr; +wire litedramcore_bankmachine6_req_lock; +reg litedramcore_bankmachine6_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine6_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine6_refresh_req; +reg litedramcore_bankmachine6_refresh_gnt = 1'd0; +reg litedramcore_bankmachine6_cmd_valid = 1'd0; +reg litedramcore_bankmachine6_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine6_cmd_payload_ba; +reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine6_auto_precharge = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_valid; +wire litedramcore_bankmachine6_cmd_buffer_sink_ready; +wire litedramcore_bankmachine6_cmd_buffer_sink_first; +wire litedramcore_bankmachine6_cmd_buffer_sink_last; +wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine6_cmd_buffer_source_ready; +reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine6_row = 14'd0; +reg litedramcore_bankmachine6_row_opened = 1'd0; +wire litedramcore_bankmachine6_row_hit; +reg litedramcore_bankmachine6_row_open = 1'd0; +reg litedramcore_bankmachine6_row_close = 1'd0; +reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine6_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0; +wire litedramcore_bankmachine6_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0; +wire litedramcore_bankmachine6_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0; +wire litedramcore_bankmachine7_req_valid; +wire litedramcore_bankmachine7_req_ready; +wire litedramcore_bankmachine7_req_we; +wire [20:0] litedramcore_bankmachine7_req_addr; +wire litedramcore_bankmachine7_req_lock; +reg litedramcore_bankmachine7_req_wdata_ready = 1'd0; +reg litedramcore_bankmachine7_req_rdata_valid = 1'd0; +wire litedramcore_bankmachine7_refresh_req; +reg litedramcore_bankmachine7_refresh_gnt = 1'd0; +reg litedramcore_bankmachine7_cmd_valid = 1'd0; +reg litedramcore_bankmachine7_cmd_ready = 1'd0; +reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] litedramcore_bankmachine7_cmd_payload_ba; +reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_we = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; +reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; +reg litedramcore_bankmachine7_auto_precharge = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0; +reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0; +reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read; +wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_valid; +wire litedramcore_bankmachine7_cmd_buffer_sink_ready; +wire litedramcore_bankmachine7_cmd_buffer_sink_first; +wire litedramcore_bankmachine7_cmd_buffer_sink_last; +wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; +reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0; +wire litedramcore_bankmachine7_cmd_buffer_source_ready; +reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0; +reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +reg [13:0] litedramcore_bankmachine7_row = 14'd0; +reg litedramcore_bankmachine7_row_opened = 1'd0; +wire litedramcore_bankmachine7_row_hit; +reg litedramcore_bankmachine7_row_open = 1'd0; +reg litedramcore_bankmachine7_row_close = 1'd0; +reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; +wire litedramcore_bankmachine7_twtpcon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0; +wire litedramcore_bankmachine7_trccon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0; +wire litedramcore_bankmachine7_trascon_valid; +(* no_retiming = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0; +reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0; +wire litedramcore_ras_allowed; +wire litedramcore_cas_allowed; +reg litedramcore_choose_cmd_want_reads = 1'd0; +reg litedramcore_choose_cmd_want_writes = 1'd0; +reg litedramcore_choose_cmd_want_cmds = 1'd0; +reg litedramcore_choose_cmd_want_activates = 1'd0; +wire litedramcore_choose_cmd_cmd_valid; +reg litedramcore_choose_cmd_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_cmd_cmd_payload_a; +wire [2:0] litedramcore_choose_cmd_cmd_payload_ba; +reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0; +reg litedramcore_choose_cmd_cmd_payload_we = 1'd0; +wire litedramcore_choose_cmd_cmd_payload_is_cmd; +wire litedramcore_choose_cmd_cmd_payload_is_read; +wire litedramcore_choose_cmd_cmd_payload_is_write; +reg [7:0] litedramcore_choose_cmd_valids = 8'd0; +wire [7:0] litedramcore_choose_cmd_request; +reg [2:0] litedramcore_choose_cmd_grant = 3'd0; +wire litedramcore_choose_cmd_ce; +reg litedramcore_choose_req_want_reads = 1'd0; +reg litedramcore_choose_req_want_writes = 1'd0; +reg litedramcore_choose_req_want_cmds = 1'd0; +reg litedramcore_choose_req_want_activates = 1'd0; +wire litedramcore_choose_req_cmd_valid; +reg litedramcore_choose_req_cmd_ready = 1'd0; +wire [13:0] litedramcore_choose_req_cmd_payload_a; +wire [2:0] litedramcore_choose_req_cmd_payload_ba; +reg litedramcore_choose_req_cmd_payload_cas = 1'd0; +reg litedramcore_choose_req_cmd_payload_ras = 1'd0; +reg litedramcore_choose_req_cmd_payload_we = 1'd0; +wire litedramcore_choose_req_cmd_payload_is_cmd; +wire litedramcore_choose_req_cmd_payload_is_read; +wire litedramcore_choose_req_cmd_payload_is_write; +reg [7:0] litedramcore_choose_req_valids = 8'd0; +wire [7:0] litedramcore_choose_req_request; +reg [2:0] litedramcore_choose_req_grant = 3'd0; +wire litedramcore_choose_req_ce; +reg [13:0] litedramcore_nop_a = 14'd0; +reg [2:0] litedramcore_nop_ba = 3'd0; +reg [1:0] litedramcore_steerer_sel0 = 2'd0; +reg [1:0] litedramcore_steerer_sel1 = 2'd0; +reg [1:0] litedramcore_steerer_sel2 = 2'd0; +reg [1:0] litedramcore_steerer_sel3 = 2'd0; +reg litedramcore_steerer0 = 1'd1; +reg litedramcore_steerer1 = 1'd1; +reg litedramcore_steerer2 = 1'd1; +reg litedramcore_steerer3 = 1'd1; +reg litedramcore_steerer4 = 1'd1; +reg litedramcore_steerer5 = 1'd1; +reg litedramcore_steerer6 = 1'd1; +reg litedramcore_steerer7 = 1'd1; +wire litedramcore_trrdcon_valid; +(* no_retiming = "true" *) reg litedramcore_trrdcon_ready = 1'd0; +reg litedramcore_trrdcon_count = 1'd0; +wire litedramcore_tfawcon_valid; +(* no_retiming = "true" *) reg litedramcore_tfawcon_ready = 1'd1; +wire [2:0] litedramcore_tfawcon_count; +reg [4:0] litedramcore_tfawcon_window = 5'd0; +wire litedramcore_tccdcon_valid; +(* no_retiming = "true" *) reg litedramcore_tccdcon_ready = 1'd0; +reg litedramcore_tccdcon_count = 1'd0; +wire litedramcore_twtrcon_valid; +(* no_retiming = "true" *) reg litedramcore_twtrcon_ready = 1'd0; +reg [2:0] litedramcore_twtrcon_count = 3'd0; +wire litedramcore_read_available; +wire litedramcore_write_available; +reg litedramcore_en0 = 1'd0; +wire litedramcore_max_time0; +reg [4:0] litedramcore_time0 = 5'd0; +reg litedramcore_en1 = 1'd0; +wire litedramcore_max_time1; +reg [3:0] litedramcore_time1 = 4'd0; +wire litedramcore_go_to_refresh; +reg init_done_storage = 1'd0; +reg init_done_re = 1'd0; +reg init_error_storage = 1'd0; +reg init_error_re = 1'd0; +wire [29:0] wb_bus_adr; +wire [31:0] wb_bus_dat_w; +wire [31:0] wb_bus_dat_r; +wire [3:0] wb_bus_sel; +wire wb_bus_cyc; +wire wb_bus_stb; +wire wb_bus_ack; +wire wb_bus_we; +wire [2:0] wb_bus_cti; +wire [1:0] wb_bus_bte; +wire wb_bus_err; +wire user_port_cmd_valid; +wire user_port_cmd_ready; +wire user_port_cmd_payload_we; +wire [23:0] user_port_cmd_payload_addr; +wire user_port_wdata_valid; +wire user_port_wdata_ready; +wire [127:0] user_port_wdata_payload_data; +wire [15:0] user_port_wdata_payload_we; +wire user_port_rdata_valid; +wire user_port_rdata_ready; +wire [127:0] user_port_rdata_payload_data; +reg state = 1'd0; +reg next_state = 1'd0; +reg [1:0] refresher_state = 2'd0; +reg [1:0] refresher_next_state = 2'd0; +reg [3:0] bankmachine0_state = 4'd0; +reg [3:0] bankmachine0_next_state = 4'd0; +reg [3:0] bankmachine1_state = 4'd0; +reg [3:0] bankmachine1_next_state = 4'd0; +reg [3:0] bankmachine2_state = 4'd0; +reg [3:0] bankmachine2_next_state = 4'd0; +reg [3:0] bankmachine3_state = 4'd0; +reg [3:0] bankmachine3_next_state = 4'd0; +reg [3:0] bankmachine4_state = 4'd0; +reg [3:0] bankmachine4_next_state = 4'd0; +reg [3:0] bankmachine5_state = 4'd0; +reg [3:0] bankmachine5_next_state = 4'd0; +reg [3:0] bankmachine6_state = 4'd0; +reg [3:0] bankmachine6_next_state = 4'd0; +reg [3:0] bankmachine7_state = 4'd0; +reg [3:0] bankmachine7_next_state = 4'd0; +reg [3:0] multiplexer_state = 4'd0; +reg [3:0] multiplexer_next_state = 4'd0; +wire roundrobin0_request; +wire roundrobin0_grant; +wire roundrobin0_ce; +wire roundrobin1_request; +wire roundrobin1_grant; +wire roundrobin1_ce; +wire roundrobin2_request; +wire roundrobin2_grant; +wire roundrobin2_ce; +wire roundrobin3_request; +wire roundrobin3_grant; +wire roundrobin3_ce; +wire roundrobin4_request; +wire roundrobin4_grant; +wire roundrobin4_ce; +wire roundrobin5_request; +wire roundrobin5_grant; +wire roundrobin5_ce; +wire roundrobin6_request; +wire roundrobin6_grant; +wire roundrobin6_ce; +wire roundrobin7_request; +wire roundrobin7_grant; +wire roundrobin7_ce; +reg locked0 = 1'd0; +reg locked1 = 1'd0; +reg locked2 = 1'd0; +reg locked3 = 1'd0; +reg locked4 = 1'd0; +reg locked5 = 1'd0; +reg locked6 = 1'd0; +reg locked7 = 1'd0; +reg new_master_wdata_ready0 = 1'd0; +reg new_master_wdata_ready1 = 1'd0; +reg new_master_wdata_ready2 = 1'd0; +reg new_master_rdata_valid0 = 1'd0; +reg new_master_rdata_valid1 = 1'd0; +reg new_master_rdata_valid2 = 1'd0; +reg new_master_rdata_valid3 = 1'd0; +reg new_master_rdata_valid4 = 1'd0; +reg new_master_rdata_valid5 = 1'd0; +reg new_master_rdata_valid6 = 1'd0; +reg new_master_rdata_valid7 = 1'd0; +reg new_master_rdata_valid8 = 1'd0; +reg new_master_rdata_valid9 = 1'd0; +wire [13:0] interface0_bank_bus_adr; +wire interface0_bank_bus_we; +wire [31:0] interface0_bank_bus_dat_w; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire csrbank0_init_done0_re; +wire csrbank0_init_done0_r; +wire csrbank0_init_done0_we; +wire csrbank0_init_done0_w; +wire csrbank0_init_error0_re; +wire csrbank0_init_error0_r; +wire csrbank0_init_error0_we; +wire csrbank0_init_error0_w; +wire csrbank0_sel; +wire [13:0] interface1_bank_bus_adr; +wire interface1_bank_bus_we; +wire [31:0] interface1_bank_bus_dat_w; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire csrbank1_dfii_control0_re; +wire [3:0] csrbank1_dfii_control0_r; +wire csrbank1_dfii_control0_we; +wire [3:0] csrbank1_dfii_control0_w; +wire csrbank1_dfii_pi0_command0_re; +wire [5:0] csrbank1_dfii_pi0_command0_r; +wire csrbank1_dfii_pi0_command0_we; +wire [5:0] csrbank1_dfii_pi0_command0_w; +wire csrbank1_dfii_pi0_address0_re; +wire [13:0] csrbank1_dfii_pi0_address0_r; +wire csrbank1_dfii_pi0_address0_we; +wire [13:0] csrbank1_dfii_pi0_address0_w; +wire csrbank1_dfii_pi0_baddress0_re; +wire [2:0] csrbank1_dfii_pi0_baddress0_r; +wire csrbank1_dfii_pi0_baddress0_we; +wire [2:0] csrbank1_dfii_pi0_baddress0_w; +wire csrbank1_dfii_pi0_wrdata0_re; +wire [31:0] csrbank1_dfii_pi0_wrdata0_r; +wire csrbank1_dfii_pi0_wrdata0_we; +wire [31:0] csrbank1_dfii_pi0_wrdata0_w; +wire csrbank1_dfii_pi0_rddata_re; +wire [31:0] csrbank1_dfii_pi0_rddata_r; +wire csrbank1_dfii_pi0_rddata_we; +wire [31:0] csrbank1_dfii_pi0_rddata_w; +wire csrbank1_dfii_pi1_command0_re; +wire [5:0] csrbank1_dfii_pi1_command0_r; +wire csrbank1_dfii_pi1_command0_we; +wire [5:0] csrbank1_dfii_pi1_command0_w; +wire csrbank1_dfii_pi1_address0_re; +wire [13:0] csrbank1_dfii_pi1_address0_r; +wire csrbank1_dfii_pi1_address0_we; +wire [13:0] csrbank1_dfii_pi1_address0_w; +wire csrbank1_dfii_pi1_baddress0_re; +wire [2:0] csrbank1_dfii_pi1_baddress0_r; +wire csrbank1_dfii_pi1_baddress0_we; +wire [2:0] csrbank1_dfii_pi1_baddress0_w; +wire csrbank1_dfii_pi1_wrdata0_re; +wire [31:0] csrbank1_dfii_pi1_wrdata0_r; +wire csrbank1_dfii_pi1_wrdata0_we; +wire [31:0] csrbank1_dfii_pi1_wrdata0_w; +wire csrbank1_dfii_pi1_rddata_re; +wire [31:0] csrbank1_dfii_pi1_rddata_r; +wire csrbank1_dfii_pi1_rddata_we; +wire [31:0] csrbank1_dfii_pi1_rddata_w; +wire csrbank1_dfii_pi2_command0_re; +wire [5:0] csrbank1_dfii_pi2_command0_r; +wire csrbank1_dfii_pi2_command0_we; +wire [5:0] csrbank1_dfii_pi2_command0_w; +wire csrbank1_dfii_pi2_address0_re; +wire [13:0] csrbank1_dfii_pi2_address0_r; +wire csrbank1_dfii_pi2_address0_we; +wire [13:0] csrbank1_dfii_pi2_address0_w; +wire csrbank1_dfii_pi2_baddress0_re; +wire [2:0] csrbank1_dfii_pi2_baddress0_r; +wire csrbank1_dfii_pi2_baddress0_we; +wire [2:0] csrbank1_dfii_pi2_baddress0_w; +wire csrbank1_dfii_pi2_wrdata0_re; +wire [31:0] csrbank1_dfii_pi2_wrdata0_r; +wire csrbank1_dfii_pi2_wrdata0_we; +wire [31:0] csrbank1_dfii_pi2_wrdata0_w; +wire csrbank1_dfii_pi2_rddata_re; +wire [31:0] csrbank1_dfii_pi2_rddata_r; +wire csrbank1_dfii_pi2_rddata_we; +wire [31:0] csrbank1_dfii_pi2_rddata_w; +wire csrbank1_dfii_pi3_command0_re; +wire [5:0] csrbank1_dfii_pi3_command0_r; +wire csrbank1_dfii_pi3_command0_we; +wire [5:0] csrbank1_dfii_pi3_command0_w; +wire csrbank1_dfii_pi3_address0_re; +wire [13:0] csrbank1_dfii_pi3_address0_r; +wire csrbank1_dfii_pi3_address0_we; +wire [13:0] csrbank1_dfii_pi3_address0_w; +wire csrbank1_dfii_pi3_baddress0_re; +wire [2:0] csrbank1_dfii_pi3_baddress0_r; +wire csrbank1_dfii_pi3_baddress0_we; +wire [2:0] csrbank1_dfii_pi3_baddress0_w; +wire csrbank1_dfii_pi3_wrdata0_re; +wire [31:0] csrbank1_dfii_pi3_wrdata0_r; +wire csrbank1_dfii_pi3_wrdata0_we; +wire [31:0] csrbank1_dfii_pi3_wrdata0_w; +wire csrbank1_dfii_pi3_rddata_re; +wire [31:0] csrbank1_dfii_pi3_rddata_r; +wire csrbank1_dfii_pi3_rddata_we; +wire [31:0] csrbank1_dfii_pi3_rddata_w; +wire csrbank1_sel; +wire [13:0] adr; +wire we; +wire [31:0] dat_w; +wire [31:0] dat_r; +wire [24:0] slice_proxy0; +wire [24:0] slice_proxy1; +wire [24:0] slice_proxy2; +wire [24:0] slice_proxy3; +wire [24:0] slice_proxy4; +wire [24:0] slice_proxy5; +wire [24:0] slice_proxy6; +wire [24:0] slice_proxy7; +wire [24:0] slice_proxy8; +wire [24:0] slice_proxy9; +wire [24:0] slice_proxy10; +wire [24:0] slice_proxy11; +wire [24:0] slice_proxy12; +wire [24:0] slice_proxy13; +wire [24:0] slice_proxy14; +wire [24:0] slice_proxy15; +reg rhs_array_muxed0 = 1'd0; +reg [13:0] rhs_array_muxed1 = 14'd0; +reg [2:0] rhs_array_muxed2 = 3'd0; +reg rhs_array_muxed3 = 1'd0; +reg rhs_array_muxed4 = 1'd0; +reg rhs_array_muxed5 = 1'd0; +reg t_array_muxed0 = 1'd0; +reg t_array_muxed1 = 1'd0; +reg t_array_muxed2 = 1'd0; +reg rhs_array_muxed6 = 1'd0; +reg [13:0] rhs_array_muxed7 = 14'd0; +reg [2:0] rhs_array_muxed8 = 3'd0; +reg rhs_array_muxed9 = 1'd0; +reg rhs_array_muxed10 = 1'd0; +reg rhs_array_muxed11 = 1'd0; +reg t_array_muxed3 = 1'd0; +reg t_array_muxed4 = 1'd0; +reg t_array_muxed5 = 1'd0; +reg [20:0] rhs_array_muxed12 = 21'd0; +reg rhs_array_muxed13 = 1'd0; +reg rhs_array_muxed14 = 1'd0; +reg [20:0] rhs_array_muxed15 = 21'd0; +reg rhs_array_muxed16 = 1'd0; +reg rhs_array_muxed17 = 1'd0; +reg [20:0] rhs_array_muxed18 = 21'd0; +reg rhs_array_muxed19 = 1'd0; +reg rhs_array_muxed20 = 1'd0; +reg [20:0] rhs_array_muxed21 = 21'd0; +reg rhs_array_muxed22 = 1'd0; +reg rhs_array_muxed23 = 1'd0; +reg [20:0] rhs_array_muxed24 = 21'd0; +reg rhs_array_muxed25 = 1'd0; +reg rhs_array_muxed26 = 1'd0; +reg [20:0] rhs_array_muxed27 = 21'd0; +reg rhs_array_muxed28 = 1'd0; +reg rhs_array_muxed29 = 1'd0; +reg [20:0] rhs_array_muxed30 = 21'd0; +reg rhs_array_muxed31 = 1'd0; +reg rhs_array_muxed32 = 1'd0; +reg [20:0] rhs_array_muxed33 = 21'd0; +reg rhs_array_muxed34 = 1'd0; +reg rhs_array_muxed35 = 1'd0; +reg [2:0] array_muxed0 = 3'd0; +reg [13:0] array_muxed1 = 14'd0; +reg array_muxed2 = 1'd0; +reg array_muxed3 = 1'd0; +reg array_muxed4 = 1'd0; +reg array_muxed5 = 1'd0; +reg array_muxed6 = 1'd0; +reg [2:0] array_muxed7 = 3'd0; +reg [13:0] array_muxed8 = 14'd0; +reg array_muxed9 = 1'd0; +reg array_muxed10 = 1'd0; +reg array_muxed11 = 1'd0; +reg array_muxed12 = 1'd0; +reg array_muxed13 = 1'd0; +reg [2:0] array_muxed14 = 3'd0; +reg [13:0] array_muxed15 = 14'd0; +reg array_muxed16 = 1'd0; +reg array_muxed17 = 1'd0; +reg array_muxed18 = 1'd0; +reg array_muxed19 = 1'd0; +reg array_muxed20 = 1'd0; +reg [2:0] array_muxed21 = 3'd0; +reg [13:0] array_muxed22 = 14'd0; +reg array_muxed23 = 1'd0; +reg array_muxed24 = 1'd0; +reg array_muxed25 = 1'd0; +reg array_muxed26 = 1'd0; +reg array_muxed27 = 1'd0; + +assign init_done = init_done_storage; +assign init_error = init_error_storage; +assign wb_bus_adr = wb_ctrl_adr; +assign wb_bus_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_bus_dat_r; +assign wb_bus_sel = wb_ctrl_sel; +assign wb_bus_cyc = wb_ctrl_cyc; +assign wb_bus_stb = wb_ctrl_stb; +assign wb_ctrl_ack = wb_bus_ack; +assign wb_bus_we = wb_ctrl_we; +assign wb_bus_cti = wb_ctrl_cti; +assign wb_bus_bte = wb_ctrl_bte; +assign wb_ctrl_err = wb_bus_err; +assign user_clk = sys_clk; +assign user_rst = sys_rst; +assign user_port_cmd_valid = user_port_native_0_cmd_valid; +assign user_port_native_0_cmd_ready = user_port_cmd_ready; +assign user_port_cmd_payload_we = user_port_native_0_cmd_we; +assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr; +assign user_port_wdata_valid = user_port_native_0_wdata_valid; +assign user_port_native_0_wdata_ready = user_port_wdata_ready; +assign user_port_wdata_payload_we = user_port_native_0_wdata_we; +assign user_port_wdata_payload_data = user_port_native_0_wdata_data; +assign user_port_native_0_rdata_valid = user_port_rdata_valid; +assign user_port_rdata_ready = user_port_native_0_rdata_ready; +assign user_port_native_0_rdata_data = user_port_rdata_payload_data; +assign litedramcore_dat_w = litedramcore_wishbone_dat_w; +assign litedramcore_wishbone_dat_r = litedramcore_dat_r; +always @(*) begin + next_state = 1'd0; + next_state = state; + case (state) + 1'd1: begin + next_state = 1'd0; + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + next_state = 1'd1; + end + end + endcase +end +always @(*) begin + litedramcore_we = 1'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0)); + end + end + endcase +end +always @(*) begin + litedramcore_wishbone_ack = 1'd0; + case (state) + 1'd1: begin + litedramcore_wishbone_ack = 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_adr = 14'd0; + case (state) + 1'd1: begin + end + default: begin + if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin + litedramcore_adr = litedramcore_wishbone_adr; + end + end + endcase +end +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +always @(*) begin + ddrphy_activates0 = 4'd0; + ddrphy_activates0[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates0[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates0[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates0[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel0_activate = 1'd0; + case (ddrphy_activates0) + 1'd1: begin + ddrphy_bankmodel0_activate = (ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + ddrphy_bankmodel0_activate = (ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + ddrphy_bankmodel0_activate = (ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + ddrphy_bankmodel0_activate = (ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +always @(*) begin + ddrphy_bankmodel0_activate_row = 14'd0; + case (ddrphy_activates0) + 1'd1: begin + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel0_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges0 = 4'd0; + ddrphy_precharges0[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges0[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges0[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges0[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel0_precharge = 1'd0; + case (ddrphy_precharges0) + 1'd1: begin + ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel0_precharge = ((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes0 = 4'd0; + ddrphy_writes0[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes0[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes0[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write_col0 = 10'd0; + case (ddrphy_writes0) + 1'd1: begin + ddrphy_bank_write_col0 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col0 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col0 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col0 = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bank_write0 = 1'd0; + case (ddrphy_writes0) + 1'd1: begin + ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +assign ddrphy_bankmodel0_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel0_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel0_write = ddrphy_new_bank_write1; +assign ddrphy_bankmodel0_write_col = ddrphy_new_bank_write_col1; +always @(*) begin + ddrphy_reads0 = 4'd0; + ddrphy_reads0[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads0[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads0[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel0_read = 1'd0; + case (ddrphy_reads0) + 1'd1: begin + ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0); + end + 2'd2: begin + ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0); + end + 3'd4: begin + ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0); + end + 4'd8: begin + ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0); + end + endcase +end +always @(*) begin + ddrphy_bankmodel0_read_col = 10'd0; + case (ddrphy_reads0) + 1'd1: begin + ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_activates1 = 4'd0; + ddrphy_activates1[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates1[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates1[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates1[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel1_activate = 1'd0; + case (ddrphy_activates1) + 1'd1: begin + ddrphy_bankmodel1_activate = (ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + ddrphy_bankmodel1_activate = (ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + ddrphy_bankmodel1_activate = (ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + ddrphy_bankmodel1_activate = (ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + ddrphy_bankmodel1_activate_row = 14'd0; + case (ddrphy_activates1) + 1'd1: begin + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel1_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges1 = 4'd0; + ddrphy_precharges1[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges1[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges1[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges1[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel1_precharge = 1'd0; + case (ddrphy_precharges1) + 1'd1: begin + ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel1_precharge = ((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes1 = 4'd0; + ddrphy_writes1[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes1[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes1[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes1[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write1 = 1'd0; + case (ddrphy_writes1) + 1'd1: begin + ddrphy_bank_write1 = (ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + ddrphy_bank_write1 = (ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + ddrphy_bank_write1 = (ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + ddrphy_bank_write1 = (ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col1 = 10'd0; + case (ddrphy_writes1) + 1'd1: begin + ddrphy_bank_write_col1 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col1 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col1 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col1 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel1_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel1_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel1_write = ddrphy_new_bank_write3; +assign ddrphy_bankmodel1_write_col = ddrphy_new_bank_write_col3; +always @(*) begin + ddrphy_reads1 = 4'd0; + ddrphy_reads1[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads1[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads1[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads1[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel1_read = 1'd0; + case (ddrphy_reads1) + 1'd1: begin + ddrphy_bankmodel1_read = (ddrphy_dfi_p0_bank == 1'd1); + end + 2'd2: begin + ddrphy_bankmodel1_read = (ddrphy_dfi_p1_bank == 1'd1); + end + 3'd4: begin + ddrphy_bankmodel1_read = (ddrphy_dfi_p2_bank == 1'd1); + end + 4'd8: begin + ddrphy_bankmodel1_read = (ddrphy_dfi_p3_bank == 1'd1); + end + endcase +end +always @(*) begin + ddrphy_bankmodel1_read_col = 10'd0; + case (ddrphy_reads1) + 1'd1: begin + ddrphy_bankmodel1_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel1_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel1_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel1_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_activates2 = 4'd0; + ddrphy_activates2[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates2[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates2[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel2_activate = 1'd0; + case (ddrphy_activates2) + 1'd1: begin + ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2); + end + endcase +end +always @(*) begin + ddrphy_bankmodel2_activate_row = 14'd0; + case (ddrphy_activates2) + 1'd1: begin + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges2 = 4'd0; + ddrphy_precharges2[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges2[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges2[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges2[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel2_precharge = 1'd0; + case (ddrphy_precharges2) + 1'd1: begin + ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel2_precharge = ((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes2 = 4'd0; + ddrphy_writes2[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes2[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes2[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes2[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write2 = 1'd0; + case (ddrphy_writes2) + 1'd1: begin + ddrphy_bank_write2 = (ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + ddrphy_bank_write2 = (ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + ddrphy_bank_write2 = (ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + ddrphy_bank_write2 = (ddrphy_dfi_p3_bank == 2'd2); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col2 = 10'd0; + case (ddrphy_writes2) + 1'd1: begin + ddrphy_bank_write_col2 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col2 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col2 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col2 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel2_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel2_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel2_write = ddrphy_new_bank_write5; +assign ddrphy_bankmodel2_write_col = ddrphy_new_bank_write_col5; +always @(*) begin + ddrphy_reads2 = 4'd0; + ddrphy_reads2[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads2[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads2[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel2_read_col = 10'd0; + case (ddrphy_reads2) + 1'd1: begin + ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bankmodel2_read = 1'd0; + case (ddrphy_reads2) + 1'd1: begin + ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2); + end + 2'd2: begin + ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2); + end + 3'd4: begin + ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2); + end + 4'd8: begin + ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2); + end + endcase +end +always @(*) begin + ddrphy_activates3 = 4'd0; + ddrphy_activates3[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates3[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates3[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates3[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel3_activate = 1'd0; + case (ddrphy_activates3) + 1'd1: begin + ddrphy_bankmodel3_activate = (ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + ddrphy_bankmodel3_activate = (ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + ddrphy_bankmodel3_activate = (ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + ddrphy_bankmodel3_activate = (ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + ddrphy_bankmodel3_activate_row = 14'd0; + case (ddrphy_activates3) + 1'd1: begin + ddrphy_bankmodel3_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel3_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel3_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel3_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges3 = 4'd0; + ddrphy_precharges3[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges3[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges3[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges3[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel3_precharge = 1'd0; + case (ddrphy_precharges3) + 1'd1: begin + ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel3_precharge = ((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes3 = 4'd0; + ddrphy_writes3[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes3[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes3[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write3 = 1'd0; + case (ddrphy_writes3) + 1'd1: begin + ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col3 = 10'd0; + case (ddrphy_writes3) + 1'd1: begin + ddrphy_bank_write_col3 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col3 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col3 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col3 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel3_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel3_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel3_write = ddrphy_new_bank_write7; +assign ddrphy_bankmodel3_write_col = ddrphy_new_bank_write_col7; +always @(*) begin + ddrphy_reads3 = 4'd0; + ddrphy_reads3[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads3[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads3[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads3[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel3_read = 1'd0; + case (ddrphy_reads3) + 1'd1: begin + ddrphy_bankmodel3_read = (ddrphy_dfi_p0_bank == 2'd3); + end + 2'd2: begin + ddrphy_bankmodel3_read = (ddrphy_dfi_p1_bank == 2'd3); + end + 3'd4: begin + ddrphy_bankmodel3_read = (ddrphy_dfi_p2_bank == 2'd3); + end + 4'd8: begin + ddrphy_bankmodel3_read = (ddrphy_dfi_p3_bank == 2'd3); + end + endcase +end +always @(*) begin + ddrphy_bankmodel3_read_col = 10'd0; + case (ddrphy_reads3) + 1'd1: begin + ddrphy_bankmodel3_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel3_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel3_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel3_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_activates4 = 4'd0; + ddrphy_activates4[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates4[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates4[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel4_activate_row = 14'd0; + case (ddrphy_activates4) + 1'd1: begin + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bankmodel4_activate = 1'd0; + case (ddrphy_activates4) + 1'd1: begin + ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +always @(*) begin + ddrphy_precharges4 = 4'd0; + ddrphy_precharges4[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges4[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges4[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges4[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel4_precharge = 1'd0; + case (ddrphy_precharges4) + 1'd1: begin + ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel4_precharge = ((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes4 = 4'd0; + ddrphy_writes4[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes4[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes4[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write_col4 = 10'd0; + case (ddrphy_writes4) + 1'd1: begin + ddrphy_bank_write_col4 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col4 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col4 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col4 = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bank_write4 = 1'd0; + case (ddrphy_writes4) + 1'd1: begin + ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +assign ddrphy_bankmodel4_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel4_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel4_write = ddrphy_new_bank_write9; +assign ddrphy_bankmodel4_write_col = ddrphy_new_bank_write_col9; +always @(*) begin + ddrphy_reads4 = 4'd0; + ddrphy_reads4[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads4[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads4[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads4[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel4_read = 1'd0; + case (ddrphy_reads4) + 1'd1: begin + ddrphy_bankmodel4_read = (ddrphy_dfi_p0_bank == 3'd4); + end + 2'd2: begin + ddrphy_bankmodel4_read = (ddrphy_dfi_p1_bank == 3'd4); + end + 3'd4: begin + ddrphy_bankmodel4_read = (ddrphy_dfi_p2_bank == 3'd4); + end + 4'd8: begin + ddrphy_bankmodel4_read = (ddrphy_dfi_p3_bank == 3'd4); + end + endcase +end +always @(*) begin + ddrphy_bankmodel4_read_col = 10'd0; + case (ddrphy_reads4) + 1'd1: begin + ddrphy_bankmodel4_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel4_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel4_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel4_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_activates5 = 4'd0; + ddrphy_activates5[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates5[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates5[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates5[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel5_activate = 1'd0; + case (ddrphy_activates5) + 1'd1: begin + ddrphy_bankmodel5_activate = (ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + ddrphy_bankmodel5_activate = (ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + ddrphy_bankmodel5_activate = (ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + ddrphy_bankmodel5_activate = (ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + ddrphy_bankmodel5_activate_row = 14'd0; + case (ddrphy_activates5) + 1'd1: begin + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel5_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges5 = 4'd0; + ddrphy_precharges5[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges5[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges5[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges5[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel5_precharge = 1'd0; + case (ddrphy_precharges5) + 1'd1: begin + ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel5_precharge = ((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes5 = 4'd0; + ddrphy_writes5[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes5[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes5[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes5[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write5 = 1'd0; + case (ddrphy_writes5) + 1'd1: begin + ddrphy_bank_write5 = (ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + ddrphy_bank_write5 = (ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + ddrphy_bank_write5 = (ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + ddrphy_bank_write5 = (ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col5 = 10'd0; + case (ddrphy_writes5) + 1'd1: begin + ddrphy_bank_write_col5 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col5 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col5 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col5 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel5_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel5_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel5_write = ddrphy_new_bank_write11; +assign ddrphy_bankmodel5_write_col = ddrphy_new_bank_write_col11; +always @(*) begin + ddrphy_reads5 = 4'd0; + ddrphy_reads5[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads5[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads5[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads5[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel5_read_col = 10'd0; + case (ddrphy_reads5) + 1'd1: begin + ddrphy_bankmodel5_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel5_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel5_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel5_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bankmodel5_read = 1'd0; + case (ddrphy_reads5) + 1'd1: begin + ddrphy_bankmodel5_read = (ddrphy_dfi_p0_bank == 3'd5); + end + 2'd2: begin + ddrphy_bankmodel5_read = (ddrphy_dfi_p1_bank == 3'd5); + end + 3'd4: begin + ddrphy_bankmodel5_read = (ddrphy_dfi_p2_bank == 3'd5); + end + 4'd8: begin + ddrphy_bankmodel5_read = (ddrphy_dfi_p3_bank == 3'd5); + end + endcase +end +always @(*) begin + ddrphy_activates6 = 4'd0; + ddrphy_activates6[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates6[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates6[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates6[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel6_activate = 1'd0; + case (ddrphy_activates6) + 1'd1: begin + ddrphy_bankmodel6_activate = (ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + ddrphy_bankmodel6_activate = (ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + ddrphy_bankmodel6_activate = (ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + ddrphy_bankmodel6_activate = (ddrphy_dfi_p3_bank == 3'd6); + end + endcase +end +always @(*) begin + ddrphy_bankmodel6_activate_row = 14'd0; + case (ddrphy_activates6) + 1'd1: begin + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel6_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_precharges6 = 4'd0; + ddrphy_precharges6[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges6[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges6[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges6[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel6_precharge = 1'd0; + case (ddrphy_precharges6) + 1'd1: begin + ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel6_precharge = ((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes6 = 4'd0; + ddrphy_writes6[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes6[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes6[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes6[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write6 = 1'd0; + case (ddrphy_writes6) + 1'd1: begin + ddrphy_bank_write6 = (ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + ddrphy_bank_write6 = (ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + ddrphy_bank_write6 = (ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + ddrphy_bank_write6 = (ddrphy_dfi_p3_bank == 3'd6); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col6 = 10'd0; + case (ddrphy_writes6) + 1'd1: begin + ddrphy_bank_write_col6 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col6 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col6 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col6 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel6_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel6_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel6_write = ddrphy_new_bank_write13; +assign ddrphy_bankmodel6_write_col = ddrphy_new_bank_write_col13; +always @(*) begin + ddrphy_reads6 = 4'd0; + ddrphy_reads6[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads6[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads6[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads6[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel6_read = 1'd0; + case (ddrphy_reads6) + 1'd1: begin + ddrphy_bankmodel6_read = (ddrphy_dfi_p0_bank == 3'd6); + end + 2'd2: begin + ddrphy_bankmodel6_read = (ddrphy_dfi_p1_bank == 3'd6); + end + 3'd4: begin + ddrphy_bankmodel6_read = (ddrphy_dfi_p2_bank == 3'd6); + end + 4'd8: begin + ddrphy_bankmodel6_read = (ddrphy_dfi_p3_bank == 3'd6); + end + endcase +end +always @(*) begin + ddrphy_bankmodel6_read_col = 10'd0; + case (ddrphy_reads6) + 1'd1: begin + ddrphy_bankmodel6_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel6_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel6_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel6_read_col = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_activates7 = 4'd0; + ddrphy_activates7[0] = ddrphy_dfiphasemodel0_activate; + ddrphy_activates7[1] = ddrphy_dfiphasemodel1_activate; + ddrphy_activates7[2] = ddrphy_dfiphasemodel2_activate; + ddrphy_activates7[3] = ddrphy_dfiphasemodel3_activate; +end +always @(*) begin + ddrphy_bankmodel7_activate_row = 14'd0; + case (ddrphy_activates7) + 1'd1: begin + ddrphy_bankmodel7_activate_row = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel7_activate_row = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel7_activate_row = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel7_activate_row = ddrphy_dfi_p3_address; + end + endcase +end +always @(*) begin + ddrphy_bankmodel7_activate = 1'd0; + case (ddrphy_activates7) + 1'd1: begin + ddrphy_bankmodel7_activate = (ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + ddrphy_bankmodel7_activate = (ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + ddrphy_bankmodel7_activate = (ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + ddrphy_bankmodel7_activate = (ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + ddrphy_precharges7 = 4'd0; + ddrphy_precharges7[0] = ddrphy_dfiphasemodel0_precharge; + ddrphy_precharges7[1] = ddrphy_dfiphasemodel1_precharge; + ddrphy_precharges7[2] = ddrphy_dfiphasemodel2_precharge; + ddrphy_precharges7[3] = ddrphy_dfiphasemodel3_precharge; +end +always @(*) begin + ddrphy_bankmodel7_precharge = 1'd0; + case (ddrphy_precharges7) + 1'd1: begin + ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfi_p0_address[10]); + end + 2'd2: begin + ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfi_p1_address[10]); + end + 3'd4: begin + ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfi_p2_address[10]); + end + 4'd8: begin + ddrphy_bankmodel7_precharge = ((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfi_p3_address[10]); + end + endcase +end +always @(*) begin + ddrphy_writes7 = 4'd0; + ddrphy_writes7[0] = ddrphy_dfiphasemodel0_write; + ddrphy_writes7[1] = ddrphy_dfiphasemodel1_write; + ddrphy_writes7[2] = ddrphy_dfiphasemodel2_write; + ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write; +end +always @(*) begin + ddrphy_bank_write7 = 1'd0; + case (ddrphy_writes7) + 1'd1: begin + ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + ddrphy_bank_write_col7 = 10'd0; + case (ddrphy_writes7) + 1'd1: begin + ddrphy_bank_write_col7 = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bank_write_col7 = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bank_write_col7 = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bank_write_col7 = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_bankmodel7_write_data = {ddrphy_dfi_p3_wrdata, ddrphy_dfi_p2_wrdata, ddrphy_dfi_p1_wrdata, ddrphy_dfi_p0_wrdata}; +assign ddrphy_bankmodel7_write_mask = {ddrphy_dfi_p3_wrdata_mask, ddrphy_dfi_p2_wrdata_mask, ddrphy_dfi_p1_wrdata_mask, ddrphy_dfi_p0_wrdata_mask}; +assign ddrphy_bankmodel7_write = ddrphy_new_bank_write15; +assign ddrphy_bankmodel7_write_col = ddrphy_new_bank_write_col15; +always @(*) begin + ddrphy_reads7 = 4'd0; + ddrphy_reads7[0] = ddrphy_dfiphasemodel0_read; + ddrphy_reads7[1] = ddrphy_dfiphasemodel1_read; + ddrphy_reads7[2] = ddrphy_dfiphasemodel2_read; + ddrphy_reads7[3] = ddrphy_dfiphasemodel3_read; +end +always @(*) begin + ddrphy_bankmodel7_read = 1'd0; + case (ddrphy_reads7) + 1'd1: begin + ddrphy_bankmodel7_read = (ddrphy_dfi_p0_bank == 3'd7); + end + 2'd2: begin + ddrphy_bankmodel7_read = (ddrphy_dfi_p1_bank == 3'd7); + end + 3'd4: begin + ddrphy_bankmodel7_read = (ddrphy_dfi_p2_bank == 3'd7); + end + 4'd8: begin + ddrphy_bankmodel7_read = (ddrphy_dfi_p3_bank == 3'd7); + end + endcase +end +always @(*) begin + ddrphy_bankmodel7_read_col = 10'd0; + case (ddrphy_reads7) + 1'd1: begin + ddrphy_bankmodel7_read_col = ddrphy_dfi_p0_address; + end + 2'd2: begin + ddrphy_bankmodel7_read_col = ddrphy_dfi_p1_address; + end + 3'd4: begin + ddrphy_bankmodel7_read_col = ddrphy_dfi_p2_address; + end + 4'd8: begin + ddrphy_bankmodel7_read_col = ddrphy_dfi_p3_address; + end + endcase +end +assign ddrphy_banks_read = (((((((ddrphy_bankmodel0_read | ddrphy_bankmodel1_read) | ddrphy_bankmodel2_read) | ddrphy_bankmodel3_read) | ddrphy_bankmodel4_read) | ddrphy_bankmodel5_read) | ddrphy_bankmodel6_read) | ddrphy_bankmodel7_read); +assign ddrphy_banks_read_data = (((((((ddrphy_bankmodel0_read_data | ddrphy_bankmodel1_read_data) | ddrphy_bankmodel2_read_data) | ddrphy_bankmodel3_read_data) | ddrphy_bankmodel4_read_data) | ddrphy_bankmodel5_read_data) | ddrphy_bankmodel6_read_data) | ddrphy_bankmodel7_read_data); +assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; +assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; +assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; +assign {ddrphy_dfi_p3_rddata_valid, ddrphy_dfi_p2_rddata_valid, ddrphy_dfi_p1_rddata_valid, ddrphy_dfi_p0_rddata_valid} = ddrphy_new_banks_read8; +assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; +assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; +assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; +assign {ddrphy_dfi_p3_rddata, ddrphy_dfi_p2_rddata, ddrphy_dfi_p1_rddata, ddrphy_dfi_p0_rddata} = ddrphy_new_banks_read_data8; +always @(*) begin + ddrphy_dfiphasemodel0_activate = 1'd0; + if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin + ddrphy_dfiphasemodel0_activate = ddrphy_dfi_p0_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel0_precharge = 1'd0; + if ((((~ddrphy_dfi_p0_cs_n) & (~ddrphy_dfi_p0_ras_n)) & ddrphy_dfi_p0_cas_n)) begin + ddrphy_dfiphasemodel0_precharge = (~ddrphy_dfi_p0_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel0_read = 1'd0; + if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin + ddrphy_dfiphasemodel0_read = ddrphy_dfi_p0_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel0_write = 1'd0; + if ((((~ddrphy_dfi_p0_cs_n) & ddrphy_dfi_p0_ras_n) & (~ddrphy_dfi_p0_cas_n))) begin + ddrphy_dfiphasemodel0_write = (~ddrphy_dfi_p0_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel1_activate = 1'd0; + if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin + ddrphy_dfiphasemodel1_activate = ddrphy_dfi_p1_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel1_precharge = 1'd0; + if ((((~ddrphy_dfi_p1_cs_n) & (~ddrphy_dfi_p1_ras_n)) & ddrphy_dfi_p1_cas_n)) begin + ddrphy_dfiphasemodel1_precharge = (~ddrphy_dfi_p1_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel1_write = 1'd0; + if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin + ddrphy_dfiphasemodel1_write = (~ddrphy_dfi_p1_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel1_read = 1'd0; + if ((((~ddrphy_dfi_p1_cs_n) & ddrphy_dfi_p1_ras_n) & (~ddrphy_dfi_p1_cas_n))) begin + ddrphy_dfiphasemodel1_read = ddrphy_dfi_p1_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel2_precharge = 1'd0; + if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin + ddrphy_dfiphasemodel2_precharge = (~ddrphy_dfi_p2_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel2_activate = 1'd0; + if ((((~ddrphy_dfi_p2_cs_n) & (~ddrphy_dfi_p2_ras_n)) & ddrphy_dfi_p2_cas_n)) begin + ddrphy_dfiphasemodel2_activate = ddrphy_dfi_p2_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel2_write = 1'd0; + if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin + ddrphy_dfiphasemodel2_write = (~ddrphy_dfi_p2_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel2_read = 1'd0; + if ((((~ddrphy_dfi_p2_cs_n) & ddrphy_dfi_p2_ras_n) & (~ddrphy_dfi_p2_cas_n))) begin + ddrphy_dfiphasemodel2_read = ddrphy_dfi_p2_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel3_activate = 1'd0; + if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin + ddrphy_dfiphasemodel3_activate = ddrphy_dfi_p3_we_n; + end +end +always @(*) begin + ddrphy_dfiphasemodel3_precharge = 1'd0; + if ((((~ddrphy_dfi_p3_cs_n) & (~ddrphy_dfi_p3_ras_n)) & ddrphy_dfi_p3_cas_n)) begin + ddrphy_dfiphasemodel3_precharge = (~ddrphy_dfi_p3_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel3_write = 1'd0; + if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin + ddrphy_dfiphasemodel3_write = (~ddrphy_dfi_p3_we_n); + end +end +always @(*) begin + ddrphy_dfiphasemodel3_read = 1'd0; + if ((((~ddrphy_dfi_p3_cs_n) & ddrphy_dfi_p3_ras_n) & (~ddrphy_dfi_p3_cas_n))) begin + ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n; + end +end +assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3]; +assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3]; +always @(*) begin + ddrphy_bankmodel0_read_data = 128'd0; + if (ddrphy_bankmodel0_active) begin + if (ddrphy_bankmodel0_read) begin + ddrphy_bankmodel0_read_data = ddrphy_bankmodel0_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel0_write_port_adr = 21'd0; + if (ddrphy_bankmodel0_active) begin + ddrphy_bankmodel0_write_port_adr = ddrphy_bankmodel0_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel0_write_port_we = 16'd0; + if (ddrphy_bankmodel0_active) begin + if (4'd8) begin + ddrphy_bankmodel0_write_port_we = ({16{ddrphy_bankmodel0_write}} & (~ddrphy_bankmodel0_write_mask)); + end else begin + ddrphy_bankmodel0_write_port_we = ddrphy_bankmodel0_write; + end + end +end +always @(*) begin + ddrphy_bankmodel0_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel0_active) begin + ddrphy_bankmodel0_write_port_dat_w = ddrphy_bankmodel0_write_data; + end +end +always @(*) begin + ddrphy_bankmodel0_read_port_adr = 21'd0; + if (ddrphy_bankmodel0_active) begin + if (ddrphy_bankmodel0_read) begin + ddrphy_bankmodel0_read_port_adr = ddrphy_bankmodel0_rdaddr; + end + end +end +assign ddrphy_bankmodel1_wraddr = slice_proxy2[24:3]; +assign ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3]; +always @(*) begin + ddrphy_bankmodel1_write_port_adr = 21'd0; + if (ddrphy_bankmodel1_active) begin + ddrphy_bankmodel1_write_port_adr = ddrphy_bankmodel1_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel1_write_port_we = 16'd0; + if (ddrphy_bankmodel1_active) begin + if (4'd8) begin + ddrphy_bankmodel1_write_port_we = ({16{ddrphy_bankmodel1_write}} & (~ddrphy_bankmodel1_write_mask)); + end else begin + ddrphy_bankmodel1_write_port_we = ddrphy_bankmodel1_write; + end + end +end +always @(*) begin + ddrphy_bankmodel1_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel1_active) begin + ddrphy_bankmodel1_write_port_dat_w = ddrphy_bankmodel1_write_data; + end +end +always @(*) begin + ddrphy_bankmodel1_read_port_adr = 21'd0; + if (ddrphy_bankmodel1_active) begin + if (ddrphy_bankmodel1_read) begin + ddrphy_bankmodel1_read_port_adr = ddrphy_bankmodel1_rdaddr; + end + end +end +always @(*) begin + ddrphy_bankmodel1_read_data = 128'd0; + if (ddrphy_bankmodel1_active) begin + if (ddrphy_bankmodel1_read) begin + ddrphy_bankmodel1_read_data = ddrphy_bankmodel1_read_port_dat_r; + end + end +end +assign ddrphy_bankmodel2_wraddr = slice_proxy4[24:3]; +assign ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3]; +always @(*) begin + ddrphy_bankmodel2_write_port_adr = 21'd0; + if (ddrphy_bankmodel2_active) begin + ddrphy_bankmodel2_write_port_adr = ddrphy_bankmodel2_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel2_write_port_we = 16'd0; + if (ddrphy_bankmodel2_active) begin + if (4'd8) begin + ddrphy_bankmodel2_write_port_we = ({16{ddrphy_bankmodel2_write}} & (~ddrphy_bankmodel2_write_mask)); + end else begin + ddrphy_bankmodel2_write_port_we = ddrphy_bankmodel2_write; + end + end +end +always @(*) begin + ddrphy_bankmodel2_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel2_active) begin + ddrphy_bankmodel2_write_port_dat_w = ddrphy_bankmodel2_write_data; + end +end +always @(*) begin + ddrphy_bankmodel2_read_port_adr = 21'd0; + if (ddrphy_bankmodel2_active) begin + if (ddrphy_bankmodel2_read) begin + ddrphy_bankmodel2_read_port_adr = ddrphy_bankmodel2_rdaddr; + end + end +end +always @(*) begin + ddrphy_bankmodel2_read_data = 128'd0; + if (ddrphy_bankmodel2_active) begin + if (ddrphy_bankmodel2_read) begin + ddrphy_bankmodel2_read_data = ddrphy_bankmodel2_read_port_dat_r; + end + end +end +assign ddrphy_bankmodel3_wraddr = slice_proxy6[24:3]; +assign ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3]; +always @(*) begin + ddrphy_bankmodel3_write_port_we = 16'd0; + if (ddrphy_bankmodel3_active) begin + if (4'd8) begin + ddrphy_bankmodel3_write_port_we = ({16{ddrphy_bankmodel3_write}} & (~ddrphy_bankmodel3_write_mask)); + end else begin + ddrphy_bankmodel3_write_port_we = ddrphy_bankmodel3_write; + end + end +end +always @(*) begin + ddrphy_bankmodel3_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel3_active) begin + ddrphy_bankmodel3_write_port_dat_w = ddrphy_bankmodel3_write_data; + end +end +always @(*) begin + ddrphy_bankmodel3_read_port_adr = 21'd0; + if (ddrphy_bankmodel3_active) begin + if (ddrphy_bankmodel3_read) begin + ddrphy_bankmodel3_read_port_adr = ddrphy_bankmodel3_rdaddr; + end + end +end +always @(*) begin + ddrphy_bankmodel3_read_data = 128'd0; + if (ddrphy_bankmodel3_active) begin + if (ddrphy_bankmodel3_read) begin + ddrphy_bankmodel3_read_data = ddrphy_bankmodel3_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel3_write_port_adr = 21'd0; + if (ddrphy_bankmodel3_active) begin + ddrphy_bankmodel3_write_port_adr = ddrphy_bankmodel3_wraddr; + end +end +assign ddrphy_bankmodel4_wraddr = slice_proxy8[24:3]; +assign ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3]; +always @(*) begin + ddrphy_bankmodel4_read_port_adr = 21'd0; + if (ddrphy_bankmodel4_active) begin + if (ddrphy_bankmodel4_read) begin + ddrphy_bankmodel4_read_port_adr = ddrphy_bankmodel4_rdaddr; + end + end +end +always @(*) begin + ddrphy_bankmodel4_read_data = 128'd0; + if (ddrphy_bankmodel4_active) begin + if (ddrphy_bankmodel4_read) begin + ddrphy_bankmodel4_read_data = ddrphy_bankmodel4_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel4_write_port_adr = 21'd0; + if (ddrphy_bankmodel4_active) begin + ddrphy_bankmodel4_write_port_adr = ddrphy_bankmodel4_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel4_write_port_we = 16'd0; + if (ddrphy_bankmodel4_active) begin + if (4'd8) begin + ddrphy_bankmodel4_write_port_we = ({16{ddrphy_bankmodel4_write}} & (~ddrphy_bankmodel4_write_mask)); + end else begin + ddrphy_bankmodel4_write_port_we = ddrphy_bankmodel4_write; + end + end +end +always @(*) begin + ddrphy_bankmodel4_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel4_active) begin + ddrphy_bankmodel4_write_port_dat_w = ddrphy_bankmodel4_write_data; + end +end +assign ddrphy_bankmodel5_wraddr = slice_proxy10[24:3]; +assign ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3]; +always @(*) begin + ddrphy_bankmodel5_read_data = 128'd0; + if (ddrphy_bankmodel5_active) begin + if (ddrphy_bankmodel5_read) begin + ddrphy_bankmodel5_read_data = ddrphy_bankmodel5_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel5_write_port_adr = 21'd0; + if (ddrphy_bankmodel5_active) begin + ddrphy_bankmodel5_write_port_adr = ddrphy_bankmodel5_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel5_write_port_we = 16'd0; + if (ddrphy_bankmodel5_active) begin + if (4'd8) begin + ddrphy_bankmodel5_write_port_we = ({16{ddrphy_bankmodel5_write}} & (~ddrphy_bankmodel5_write_mask)); + end else begin + ddrphy_bankmodel5_write_port_we = ddrphy_bankmodel5_write; + end + end +end +always @(*) begin + ddrphy_bankmodel5_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel5_active) begin + ddrphy_bankmodel5_write_port_dat_w = ddrphy_bankmodel5_write_data; + end +end +always @(*) begin + ddrphy_bankmodel5_read_port_adr = 21'd0; + if (ddrphy_bankmodel5_active) begin + if (ddrphy_bankmodel5_read) begin + ddrphy_bankmodel5_read_port_adr = ddrphy_bankmodel5_rdaddr; + end + end +end +assign ddrphy_bankmodel6_wraddr = slice_proxy12[24:3]; +assign ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3]; +always @(*) begin + ddrphy_bankmodel6_read_data = 128'd0; + if (ddrphy_bankmodel6_active) begin + if (ddrphy_bankmodel6_read) begin + ddrphy_bankmodel6_read_data = ddrphy_bankmodel6_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel6_write_port_adr = 21'd0; + if (ddrphy_bankmodel6_active) begin + ddrphy_bankmodel6_write_port_adr = ddrphy_bankmodel6_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel6_write_port_we = 16'd0; + if (ddrphy_bankmodel6_active) begin + if (4'd8) begin + ddrphy_bankmodel6_write_port_we = ({16{ddrphy_bankmodel6_write}} & (~ddrphy_bankmodel6_write_mask)); + end else begin + ddrphy_bankmodel6_write_port_we = ddrphy_bankmodel6_write; + end + end +end +always @(*) begin + ddrphy_bankmodel6_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel6_active) begin + ddrphy_bankmodel6_write_port_dat_w = ddrphy_bankmodel6_write_data; + end +end +always @(*) begin + ddrphy_bankmodel6_read_port_adr = 21'd0; + if (ddrphy_bankmodel6_active) begin + if (ddrphy_bankmodel6_read) begin + ddrphy_bankmodel6_read_port_adr = ddrphy_bankmodel6_rdaddr; + end + end +end +assign ddrphy_bankmodel7_wraddr = slice_proxy14[24:3]; +assign ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3]; +always @(*) begin + ddrphy_bankmodel7_read_data = 128'd0; + if (ddrphy_bankmodel7_active) begin + if (ddrphy_bankmodel7_read) begin + ddrphy_bankmodel7_read_data = ddrphy_bankmodel7_read_port_dat_r; + end + end +end +always @(*) begin + ddrphy_bankmodel7_write_port_adr = 21'd0; + if (ddrphy_bankmodel7_active) begin + ddrphy_bankmodel7_write_port_adr = ddrphy_bankmodel7_wraddr; + end +end +always @(*) begin + ddrphy_bankmodel7_write_port_we = 16'd0; + if (ddrphy_bankmodel7_active) begin + if (4'd8) begin + ddrphy_bankmodel7_write_port_we = ({16{ddrphy_bankmodel7_write}} & (~ddrphy_bankmodel7_write_mask)); + end else begin + ddrphy_bankmodel7_write_port_we = ddrphy_bankmodel7_write; + end + end +end +always @(*) begin + ddrphy_bankmodel7_write_port_dat_w = 128'd0; + if (ddrphy_bankmodel7_active) begin + ddrphy_bankmodel7_write_port_dat_w = ddrphy_bankmodel7_write_data; + end +end +always @(*) begin + ddrphy_bankmodel7_read_port_adr = 21'd0; + if (ddrphy_bankmodel7_active) begin + if (ddrphy_bankmodel7_read) begin + ddrphy_bankmodel7_read_port_adr = ddrphy_bankmodel7_rdaddr; + end + end +end +assign ddrphy_dfi_p0_address = litedramcore_master_p0_address; +assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank; +assign ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n; +assign ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n; +assign ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n; +assign ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n; +assign ddrphy_dfi_p0_cke = litedramcore_master_p0_cke; +assign ddrphy_dfi_p0_odt = litedramcore_master_p0_odt; +assign ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n; +assign ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n; +assign ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata; +assign ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en; +assign ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask; +assign ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en; +assign litedramcore_master_p0_rddata = ddrphy_dfi_p0_rddata; +assign litedramcore_master_p0_rddata_valid = ddrphy_dfi_p0_rddata_valid; +assign ddrphy_dfi_p1_address = litedramcore_master_p1_address; +assign ddrphy_dfi_p1_bank = litedramcore_master_p1_bank; +assign ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n; +assign ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n; +assign ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n; +assign ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n; +assign ddrphy_dfi_p1_cke = litedramcore_master_p1_cke; +assign ddrphy_dfi_p1_odt = litedramcore_master_p1_odt; +assign ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n; +assign ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n; +assign ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata; +assign ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en; +assign ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask; +assign ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en; +assign litedramcore_master_p1_rddata = ddrphy_dfi_p1_rddata; +assign litedramcore_master_p1_rddata_valid = ddrphy_dfi_p1_rddata_valid; +assign ddrphy_dfi_p2_address = litedramcore_master_p2_address; +assign ddrphy_dfi_p2_bank = litedramcore_master_p2_bank; +assign ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n; +assign ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n; +assign ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n; +assign ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n; +assign ddrphy_dfi_p2_cke = litedramcore_master_p2_cke; +assign ddrphy_dfi_p2_odt = litedramcore_master_p2_odt; +assign ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n; +assign ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n; +assign ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata; +assign ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en; +assign ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask; +assign ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en; +assign litedramcore_master_p2_rddata = ddrphy_dfi_p2_rddata; +assign litedramcore_master_p2_rddata_valid = ddrphy_dfi_p2_rddata_valid; +assign ddrphy_dfi_p3_address = litedramcore_master_p3_address; +assign ddrphy_dfi_p3_bank = litedramcore_master_p3_bank; +assign ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n; +assign ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n; +assign ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n; +assign ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n; +assign ddrphy_dfi_p3_cke = litedramcore_master_p3_cke; +assign ddrphy_dfi_p3_odt = litedramcore_master_p3_odt; +assign ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n; +assign ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n; +assign ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata; +assign ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en; +assign ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask; +assign ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en; +assign litedramcore_master_p3_rddata = ddrphy_dfi_p3_rddata; +assign litedramcore_master_p3_rddata_valid = ddrphy_dfi_p3_rddata_valid; +assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address; +assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank; +assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n; +assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n; +assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n; +assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n; +assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke; +assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt; +assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n; +assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n; +assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata; +assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en; +assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask; +assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en; +assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata; +assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid; +assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address; +assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank; +assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n; +assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n; +assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n; +assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n; +assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke; +assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt; +assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n; +assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n; +assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata; +assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en; +assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask; +assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en; +assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata; +assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid; +assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address; +assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank; +assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n; +assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n; +assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n; +assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n; +assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke; +assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt; +assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n; +assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n; +assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata; +assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en; +assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask; +assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en; +assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata; +assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid; +assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address; +assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank; +assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n; +assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n; +assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n; +assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n; +assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke; +assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt; +assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n; +assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n; +assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata; +assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en; +assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask; +assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en; +assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata; +assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid; +always @(*) begin + litedramcore_master_p1_cs_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n; + end else begin + litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n; + end +end +always @(*) begin + litedramcore_master_p1_ras_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n; + end else begin + litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n; + end +end +always @(*) begin + litedramcore_slave_p1_rddata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata; + end else begin + end +end +always @(*) begin + litedramcore_master_p1_we_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n; + end else begin + litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n; + end +end +always @(*) begin + litedramcore_slave_p1_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p1_cke = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cke = litedramcore_slave_p1_cke; + end else begin + litedramcore_master_p1_cke = litedramcore_inti_p1_cke; + end +end +always @(*) begin + litedramcore_master_p1_odt = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_odt = litedramcore_slave_p1_odt; + end else begin + litedramcore_master_p1_odt = litedramcore_inti_p1_odt; + end +end +always @(*) begin + litedramcore_master_p1_reset_n = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n; + end else begin + litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n; + end +end +always @(*) begin + litedramcore_master_p1_act_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n; + end else begin + litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n; + end +end +always @(*) begin + litedramcore_master_p1_wrdata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata; + end else begin + litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata; + end +end +always @(*) begin + litedramcore_inti_p2_rddata = 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en; + end else begin + litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en; + end +end +always @(*) begin + litedramcore_inti_p2_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p1_wrdata_mask = 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask; + end else begin + litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p1_rddata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en; + end else begin + litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en; + end +end +always @(*) begin + litedramcore_master_p2_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_address = litedramcore_slave_p2_address; + end else begin + litedramcore_master_p2_address = litedramcore_inti_p2_address; + end +end +always @(*) begin + litedramcore_master_p2_bank = 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_bank = litedramcore_slave_p2_bank; + end else begin + litedramcore_master_p2_bank = litedramcore_inti_p2_bank; + end +end +always @(*) begin + litedramcore_master_p2_cas_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n; + end else begin + litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n; + end +end +always @(*) begin + litedramcore_master_p2_cs_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n; + end else begin + litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n; + end +end +always @(*) begin + litedramcore_master_p2_ras_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n; + end else begin + litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n; + end +end +always @(*) begin + litedramcore_slave_p2_rddata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata; + end else begin + end +end +always @(*) begin + litedramcore_master_p2_we_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n; + end else begin + litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n; + end +end +always @(*) begin + litedramcore_slave_p2_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p2_cke = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_cke = litedramcore_slave_p2_cke; + end else begin + litedramcore_master_p2_cke = litedramcore_inti_p2_cke; + end +end +always @(*) begin + litedramcore_master_p2_odt = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_odt = litedramcore_slave_p2_odt; + end else begin + litedramcore_master_p2_odt = litedramcore_inti_p2_odt; + end +end +always @(*) begin + litedramcore_master_p2_reset_n = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n; + end else begin + litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n; + end +end +always @(*) begin + litedramcore_master_p2_act_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n; + end else begin + litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n; + end +end +always @(*) begin + litedramcore_master_p2_wrdata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata; + end else begin + litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata; + end +end +always @(*) begin + litedramcore_inti_p3_rddata = 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en; + end else begin + litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en; + end +end +always @(*) begin + litedramcore_inti_p3_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p2_wrdata_mask = 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask; + end else begin + litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p2_rddata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en; + end else begin + litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en; + end +end +always @(*) begin + litedramcore_master_p3_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_address = litedramcore_slave_p3_address; + end else begin + litedramcore_master_p3_address = litedramcore_inti_p3_address; + end +end +always @(*) begin + litedramcore_master_p3_bank = 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_bank = litedramcore_slave_p3_bank; + end else begin + litedramcore_master_p3_bank = litedramcore_inti_p3_bank; + end +end +always @(*) begin + litedramcore_master_p3_cas_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cas_n = litedramcore_slave_p3_cas_n; + end else begin + litedramcore_master_p3_cas_n = litedramcore_inti_p3_cas_n; + end +end +always @(*) begin + litedramcore_master_p3_cs_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cs_n = litedramcore_slave_p3_cs_n; + end else begin + litedramcore_master_p3_cs_n = litedramcore_inti_p3_cs_n; + end +end +always @(*) begin + litedramcore_master_p3_ras_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_ras_n = litedramcore_slave_p3_ras_n; + end else begin + litedramcore_master_p3_ras_n = litedramcore_inti_p3_ras_n; + end +end +always @(*) begin + litedramcore_slave_p3_rddata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata = litedramcore_master_p3_rddata; + end else begin + end +end +always @(*) begin + litedramcore_master_p3_we_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_we_n = litedramcore_slave_p3_we_n; + end else begin + litedramcore_master_p3_we_n = litedramcore_inti_p3_we_n; + end +end +always @(*) begin + litedramcore_slave_p3_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p3_rddata_valid = litedramcore_master_p3_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p3_cke = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_cke = litedramcore_slave_p3_cke; + end else begin + litedramcore_master_p3_cke = litedramcore_inti_p3_cke; + end +end +always @(*) begin + litedramcore_master_p3_odt = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_odt = litedramcore_slave_p3_odt; + end else begin + litedramcore_master_p3_odt = litedramcore_inti_p3_odt; + end +end +always @(*) begin + litedramcore_master_p3_reset_n = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_reset_n = litedramcore_slave_p3_reset_n; + end else begin + litedramcore_master_p3_reset_n = litedramcore_inti_p3_reset_n; + end +end +always @(*) begin + litedramcore_master_p3_act_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_act_n = litedramcore_slave_p3_act_n; + end else begin + litedramcore_master_p3_act_n = litedramcore_inti_p3_act_n; + end +end +always @(*) begin + litedramcore_master_p3_wrdata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata = litedramcore_slave_p3_wrdata; + end else begin + litedramcore_master_p3_wrdata = litedramcore_inti_p3_wrdata; + end +end +always @(*) begin + litedramcore_inti_p0_rddata = 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p0_rddata = litedramcore_master_p0_rddata; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_en = litedramcore_slave_p3_wrdata_en; + end else begin + litedramcore_master_p3_wrdata_en = litedramcore_inti_p3_wrdata_en; + end +end +always @(*) begin + litedramcore_inti_p0_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p3_wrdata_mask = 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_wrdata_mask = litedramcore_slave_p3_wrdata_mask; + end else begin + litedramcore_master_p3_wrdata_mask = litedramcore_inti_p3_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p3_rddata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p3_rddata_en = litedramcore_slave_p3_rddata_en; + end else begin + litedramcore_master_p3_rddata_en = litedramcore_inti_p3_rddata_en; + end +end +always @(*) begin + litedramcore_master_p0_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_address = litedramcore_slave_p0_address; + end else begin + litedramcore_master_p0_address = litedramcore_inti_p0_address; + end +end +always @(*) begin + litedramcore_master_p0_bank = 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_bank = litedramcore_slave_p0_bank; + end else begin + litedramcore_master_p0_bank = litedramcore_inti_p0_bank; + end +end +always @(*) begin + litedramcore_master_p0_cas_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cas_n = litedramcore_slave_p0_cas_n; + end else begin + litedramcore_master_p0_cas_n = litedramcore_inti_p0_cas_n; + end +end +always @(*) begin + litedramcore_master_p0_cs_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cs_n = litedramcore_slave_p0_cs_n; + end else begin + litedramcore_master_p0_cs_n = litedramcore_inti_p0_cs_n; + end +end +always @(*) begin + litedramcore_master_p0_ras_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_ras_n = litedramcore_slave_p0_ras_n; + end else begin + litedramcore_master_p0_ras_n = litedramcore_inti_p0_ras_n; + end +end +always @(*) begin + litedramcore_slave_p0_rddata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata = litedramcore_master_p0_rddata; + end else begin + end +end +always @(*) begin + litedramcore_master_p0_we_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_we_n = litedramcore_slave_p0_we_n; + end else begin + litedramcore_master_p0_we_n = litedramcore_inti_p0_we_n; + end +end +always @(*) begin + litedramcore_slave_p0_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_slave_p0_rddata_valid = litedramcore_master_p0_rddata_valid; + end else begin + end +end +always @(*) begin + litedramcore_master_p0_cke = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_cke = litedramcore_slave_p0_cke; + end else begin + litedramcore_master_p0_cke = litedramcore_inti_p0_cke; + end +end +always @(*) begin + litedramcore_master_p0_odt = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_odt = litedramcore_slave_p0_odt; + end else begin + litedramcore_master_p0_odt = litedramcore_inti_p0_odt; + end +end +always @(*) begin + litedramcore_master_p0_reset_n = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_reset_n = litedramcore_slave_p0_reset_n; + end else begin + litedramcore_master_p0_reset_n = litedramcore_inti_p0_reset_n; + end +end +always @(*) begin + litedramcore_master_p0_act_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_act_n = litedramcore_slave_p0_act_n; + end else begin + litedramcore_master_p0_act_n = litedramcore_inti_p0_act_n; + end +end +always @(*) begin + litedramcore_master_p0_wrdata = 32'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata = litedramcore_slave_p0_wrdata; + end else begin + litedramcore_master_p0_wrdata = litedramcore_inti_p0_wrdata; + end +end +always @(*) begin + litedramcore_inti_p1_rddata = 32'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p1_rddata = litedramcore_master_p1_rddata; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_en = litedramcore_slave_p0_wrdata_en; + end else begin + litedramcore_master_p0_wrdata_en = litedramcore_inti_p0_wrdata_en; + end +end +always @(*) begin + litedramcore_inti_p1_rddata_valid = 1'd0; + if (litedramcore_storage[0]) begin + end else begin + litedramcore_inti_p1_rddata_valid = litedramcore_master_p1_rddata_valid; + end +end +always @(*) begin + litedramcore_master_p0_wrdata_mask = 4'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_wrdata_mask = litedramcore_slave_p0_wrdata_mask; + end else begin + litedramcore_master_p0_wrdata_mask = litedramcore_inti_p0_wrdata_mask; + end +end +always @(*) begin + litedramcore_master_p0_rddata_en = 1'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p0_rddata_en = litedramcore_slave_p0_rddata_en; + end else begin + litedramcore_master_p0_rddata_en = litedramcore_inti_p0_rddata_en; + end +end +always @(*) begin + litedramcore_master_p1_address = 14'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_address = litedramcore_slave_p1_address; + end else begin + litedramcore_master_p1_address = litedramcore_inti_p1_address; + end +end +always @(*) begin + litedramcore_master_p1_bank = 3'd0; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_bank = litedramcore_slave_p1_bank; + end else begin + litedramcore_master_p1_bank = litedramcore_inti_p1_bank; + end +end +always @(*) begin + litedramcore_master_p1_cas_n = 1'd1; + if (litedramcore_storage[0]) begin + litedramcore_master_p1_cas_n = litedramcore_slave_p1_cas_n; + end else begin + litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n; + end +end +assign litedramcore_inti_p0_cke = litedramcore_storage[1]; +assign litedramcore_inti_p1_cke = litedramcore_storage[1]; +assign litedramcore_inti_p2_cke = litedramcore_storage[1]; +assign litedramcore_inti_p3_cke = litedramcore_storage[1]; +assign litedramcore_inti_p0_odt = litedramcore_storage[2]; +assign litedramcore_inti_p1_odt = litedramcore_storage[2]; +assign litedramcore_inti_p2_odt = litedramcore_storage[2]; +assign litedramcore_inti_p3_odt = litedramcore_storage[2]; +assign litedramcore_inti_p0_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p1_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p2_reset_n = litedramcore_storage[3]; +assign litedramcore_inti_p3_reset_n = litedramcore_storage[3]; +always @(*) begin + litedramcore_inti_p0_cs_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}}; + end else begin + litedramcore_inti_p0_cs_n = {1{1'd1}}; + end +end +always @(*) begin + litedramcore_inti_p0_ras_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]); + end else begin + litedramcore_inti_p0_ras_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p0_we_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]); + end else begin + litedramcore_inti_p0_we_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p0_cas_n = 1'd1; + if (litedramcore_phaseinjector0_command_issue_re) begin + litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]); + end else begin + litedramcore_inti_p0_cas_n = 1'd1; + end +end +assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage; +assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage; +assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]); +assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]); +assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage; +assign litedramcore_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p1_cs_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}}; + end else begin + litedramcore_inti_p1_cs_n = {1{1'd1}}; + end +end +always @(*) begin + litedramcore_inti_p1_ras_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]); + end else begin + litedramcore_inti_p1_ras_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p1_we_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]); + end else begin + litedramcore_inti_p1_we_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p1_cas_n = 1'd1; + if (litedramcore_phaseinjector1_command_issue_re) begin + litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]); + end else begin + litedramcore_inti_p1_cas_n = 1'd1; + end +end +assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage; +assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage; +assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]); +assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]); +assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage; +assign litedramcore_inti_p1_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p2_cs_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}}; + end else begin + litedramcore_inti_p2_cs_n = {1{1'd1}}; + end +end +always @(*) begin + litedramcore_inti_p2_ras_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]); + end else begin + litedramcore_inti_p2_ras_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p2_we_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]); + end else begin + litedramcore_inti_p2_we_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p2_cas_n = 1'd1; + if (litedramcore_phaseinjector2_command_issue_re) begin + litedramcore_inti_p2_cas_n = (~litedramcore_phaseinjector2_command_storage[2]); + end else begin + litedramcore_inti_p2_cas_n = 1'd1; + end +end +assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage; +assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage; +assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]); +assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]); +assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage; +assign litedramcore_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + litedramcore_inti_p3_cs_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}}; + end else begin + litedramcore_inti_p3_cs_n = {1{1'd1}}; + end +end +always @(*) begin + litedramcore_inti_p3_ras_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_ras_n = (~litedramcore_phaseinjector3_command_storage[3]); + end else begin + litedramcore_inti_p3_ras_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p3_we_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_we_n = (~litedramcore_phaseinjector3_command_storage[1]); + end else begin + litedramcore_inti_p3_we_n = 1'd1; + end +end +always @(*) begin + litedramcore_inti_p3_cas_n = 1'd1; + if (litedramcore_phaseinjector3_command_issue_re) begin + litedramcore_inti_p3_cas_n = (~litedramcore_phaseinjector3_command_storage[2]); + end else begin + litedramcore_inti_p3_cas_n = 1'd1; + end +end +assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage; +assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage; +assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]); +assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]); +assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage; +assign litedramcore_inti_p3_wrdata_mask = 1'd0; +assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid; +assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready; +assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we; +assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr; +assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock; +assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready; +assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid; +assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid; +assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready; +assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we; +assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr; +assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock; +assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready; +assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid; +assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid; +assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready; +assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we; +assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr; +assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock; +assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready; +assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid; +assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid; +assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready; +assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we; +assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr; +assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock; +assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready; +assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid; +assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid; +assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready; +assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we; +assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr; +assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock; +assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready; +assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid; +assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid; +assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready; +assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we; +assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr; +assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock; +assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready; +assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid; +assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid; +assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready; +assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we; +assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr; +assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock; +assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready; +assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid; +assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid; +assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready; +assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we; +assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr; +assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock; +assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready; +assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid; +assign litedramcore_timer_wait = (~litedramcore_timer_done0); +assign litedramcore_postponer_req_i = litedramcore_timer_done0; +assign litedramcore_wants_refresh = litedramcore_postponer_req_o; +assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0; +assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done); +assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0); +assign litedramcore_timer_done0 = litedramcore_timer_done1; +assign litedramcore_timer_count0 = litedramcore_timer_count1; +assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0)); +assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0)); +assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0); +assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1; +assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1; +always @(*) begin + refresher_next_state = 2'd0; + refresher_next_state = refresher_state; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + refresher_next_state = 2'd2; + end + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + refresher_next_state = 2'd3; + end else begin + refresher_next_state = 1'd0; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + refresher_next_state = 1'd0; + end + end + default: begin + if (1'd1) begin + if (litedramcore_wants_refresh) begin + refresher_next_state = 1'd1; + end + end + end + endcase +end +always @(*) begin + litedramcore_cmd_valid = 1'd0; + case (refresher_state) + 1'd1: begin + litedramcore_cmd_valid = 1'd1; + end + 2'd2: begin + litedramcore_cmd_valid = 1'd1; + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_valid = 1'd0; + end + end + end + 2'd3: begin + litedramcore_cmd_valid = 1'd1; + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_valid = 1'd0; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_zqcs_executer_start = 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + litedramcore_zqcs_executer_start = 1'd1; + end else begin + end + end + end + 2'd3: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_cmd_last = 1'd0; + case (refresher_state) + 1'd1: begin + end + 2'd2: begin + if (litedramcore_sequencer_done0) begin + if (litedramcore_wants_zqcs) begin + end else begin + litedramcore_cmd_last = 1'd1; + end + end + end + 2'd3: begin + if (litedramcore_zqcs_executer_done) begin + litedramcore_cmd_last = 1'd1; + end + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_sequencer_start0 = 1'd0; + case (refresher_state) + 1'd1: begin + if (litedramcore_cmd_ready) begin + litedramcore_sequencer_start0 = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid; +assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr; +assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready; +assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid); +assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid); +assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + litedramcore_bankmachine0_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine0_row_col_n_addr_sel) begin + litedramcore_bankmachine0_cmd_payload_a = litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine0_cmd_payload_a = ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write); +assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open); +always @(*) begin + litedramcore_bankmachine0_auto_precharge = 1'd0; + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine0_auto_precharge = (litedramcore_bankmachine0_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready); +always @(*) begin + bankmachine0_next_state = 4'd0; + bankmachine0_next_state = bankmachine0_state; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + bankmachine0_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + if (litedramcore_bankmachine0_cmd_ready) begin + bankmachine0_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine0_refresh_req)) begin + bankmachine0_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine0_next_state = 3'd6; + end + 3'd6: begin + bankmachine0_next_state = 2'd3; + end + 3'd7: begin + bankmachine0_next_state = 4'd8; + end + 4'd8: begin + bankmachine0_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + bankmachine0_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin + bankmachine0_next_state = 2'd2; + end + end else begin + bankmachine0_next_state = 1'd1; + end + end else begin + bankmachine0_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_read = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_write = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_wdata_ready = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_req_wdata_ready = litedramcore_bankmachine0_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_req_rdata_valid = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine0_req_rdata_valid = litedramcore_bankmachine0_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_refresh_gnt = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine0_twtpcon_ready) begin + litedramcore_bankmachine0_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_valid = 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_open = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_row_close = 1'd0; + case (bankmachine0_state) + 1'd1: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine0_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_cas = 1'd0; + case (bankmachine0_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + litedramcore_bankmachine0_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_ras = 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_we = 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine0_refresh_req) begin + end else begin + if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine0_row_opened) begin + if (litedramcore_bankmachine0_row_hit) begin + if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine0_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0; + case (bankmachine0_state) + 1'd1: begin + if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine0_trccon_ready) begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid; +assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr; +assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready; +assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid); +assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid); +assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + litedramcore_bankmachine1_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine1_row_col_n_addr_sel) begin + litedramcore_bankmachine1_cmd_payload_a = litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine1_cmd_payload_a = ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write); +assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open); +always @(*) begin + litedramcore_bankmachine1_auto_precharge = 1'd0; + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine1_auto_precharge = (litedramcore_bankmachine1_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready); +always @(*) begin + bankmachine1_next_state = 4'd0; + bankmachine1_next_state = bankmachine1_state; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + bankmachine1_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + if (litedramcore_bankmachine1_cmd_ready) begin + bankmachine1_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine1_refresh_req)) begin + bankmachine1_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine1_next_state = 3'd6; + end + 3'd6: begin + bankmachine1_next_state = 2'd3; + end + 3'd7: begin + bankmachine1_next_state = 4'd8; + end + 4'd8: begin + bankmachine1_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + bankmachine1_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin + bankmachine1_next_state = 2'd2; + end + end else begin + bankmachine1_next_state = 1'd1; + end + end else begin + bankmachine1_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_read = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_write = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_wdata_ready = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_req_wdata_ready = litedramcore_bankmachine1_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_req_rdata_valid = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine1_req_rdata_valid = litedramcore_bankmachine1_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_refresh_gnt = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine1_twtpcon_ready) begin + litedramcore_bankmachine1_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_valid = 1'd0; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_open = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_row_close = 1'd0; + case (bankmachine1_state) + 1'd1: begin + litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine1_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine1_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_cas = 1'd0; + case (bankmachine1_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + litedramcore_bankmachine1_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_ras = 1'd0; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_we = 1'd0; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine1_refresh_req) begin + end else begin + if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine1_row_opened) begin + if (litedramcore_bankmachine1_row_hit) begin + if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine1_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0; + case (bankmachine1_state) + 1'd1: begin + if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine1_trccon_ready) begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid; +assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr; +assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready; +assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid); +assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid); +assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + litedramcore_bankmachine2_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine2_row_col_n_addr_sel) begin + litedramcore_bankmachine2_cmd_payload_a = litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine2_cmd_payload_a = ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write); +assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open); +always @(*) begin + litedramcore_bankmachine2_auto_precharge = 1'd0; + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine2_auto_precharge = (litedramcore_bankmachine2_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready); +always @(*) begin + bankmachine2_next_state = 4'd0; + bankmachine2_next_state = bankmachine2_state; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + bankmachine2_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + if (litedramcore_bankmachine2_cmd_ready) begin + bankmachine2_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine2_refresh_req)) begin + bankmachine2_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine2_next_state = 3'd6; + end + 3'd6: begin + bankmachine2_next_state = 2'd3; + end + 3'd7: begin + bankmachine2_next_state = 4'd8; + end + 4'd8: begin + bankmachine2_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + bankmachine2_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin + bankmachine2_next_state = 2'd2; + end + end else begin + bankmachine2_next_state = 1'd1; + end + end else begin + bankmachine2_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_read = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_write = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_wdata_ready = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_req_wdata_ready = litedramcore_bankmachine2_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_req_rdata_valid = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine2_req_rdata_valid = litedramcore_bankmachine2_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_refresh_gnt = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine2_twtpcon_ready) begin + litedramcore_bankmachine2_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_valid = 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_open = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_close = 1'd0; + case (bankmachine2_state) + 1'd1: begin + litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine2_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine2_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_cas = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + litedramcore_bankmachine2_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_ras = 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_we = 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine2_refresh_req) begin + end else begin + if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine2_row_opened) begin + if (litedramcore_bankmachine2_row_hit) begin + if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine2_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0; + case (bankmachine2_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0; + case (bankmachine2_state) + 1'd1: begin + if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine2_trccon_ready) begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid; +assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr; +assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready; +assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid); +assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid); +assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + litedramcore_bankmachine3_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine3_row_col_n_addr_sel) begin + litedramcore_bankmachine3_cmd_payload_a = litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine3_cmd_payload_a = ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write); +assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open); +always @(*) begin + litedramcore_bankmachine3_auto_precharge = 1'd0; + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine3_auto_precharge = (litedramcore_bankmachine3_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready); +always @(*) begin + bankmachine3_next_state = 4'd0; + bankmachine3_next_state = bankmachine3_state; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + bankmachine3_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + if (litedramcore_bankmachine3_cmd_ready) begin + bankmachine3_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine3_refresh_req)) begin + bankmachine3_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine3_next_state = 3'd6; + end + 3'd6: begin + bankmachine3_next_state = 2'd3; + end + 3'd7: begin + bankmachine3_next_state = 4'd8; + end + 4'd8: begin + bankmachine3_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + bankmachine3_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin + bankmachine3_next_state = 2'd2; + end + end else begin + bankmachine3_next_state = 1'd1; + end + end else begin + bankmachine3_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_read = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_write = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_wdata_ready = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_req_wdata_ready = litedramcore_bankmachine3_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_req_rdata_valid = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine3_req_rdata_valid = litedramcore_bankmachine3_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_refresh_gnt = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine3_twtpcon_ready) begin + litedramcore_bankmachine3_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_valid = 1'd0; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_open = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_row_close = 1'd0; + case (bankmachine3_state) + 1'd1: begin + litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine3_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine3_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_cas = 1'd0; + case (bankmachine3_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + litedramcore_bankmachine3_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_ras = 1'd0; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_we = 1'd0; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine3_refresh_req) begin + end else begin + if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine3_row_opened) begin + if (litedramcore_bankmachine3_row_hit) begin + if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine3_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0; + case (bankmachine3_state) + 1'd1: begin + if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine3_trccon_ready) begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid; +assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr; +assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready; +assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid); +assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid); +assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + litedramcore_bankmachine4_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine4_row_col_n_addr_sel) begin + litedramcore_bankmachine4_cmd_payload_a = litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine4_cmd_payload_a = ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write); +assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open); +always @(*) begin + litedramcore_bankmachine4_auto_precharge = 1'd0; + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine4_auto_precharge = (litedramcore_bankmachine4_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready); +always @(*) begin + bankmachine4_next_state = 4'd0; + bankmachine4_next_state = bankmachine4_state; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + bankmachine4_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + if (litedramcore_bankmachine4_cmd_ready) begin + bankmachine4_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine4_refresh_req)) begin + bankmachine4_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine4_next_state = 3'd6; + end + 3'd6: begin + bankmachine4_next_state = 2'd3; + end + 3'd7: begin + bankmachine4_next_state = 4'd8; + end + 4'd8: begin + bankmachine4_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + bankmachine4_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin + bankmachine4_next_state = 2'd2; + end + end else begin + bankmachine4_next_state = 1'd1; + end + end else begin + bankmachine4_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_read = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_write = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_wdata_ready = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_req_wdata_ready = litedramcore_bankmachine4_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_req_rdata_valid = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine4_req_rdata_valid = litedramcore_bankmachine4_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_refresh_gnt = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine4_twtpcon_ready) begin + litedramcore_bankmachine4_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_valid = 1'd0; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_open = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_row_close = 1'd0; + case (bankmachine4_state) + 1'd1: begin + litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine4_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine4_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_cas = 1'd0; + case (bankmachine4_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + litedramcore_bankmachine4_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_ras = 1'd0; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_we = 1'd0; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine4_refresh_req) begin + end else begin + if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine4_row_opened) begin + if (litedramcore_bankmachine4_row_hit) begin + if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine4_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0; + case (bankmachine4_state) + 1'd1: begin + if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine4_trccon_ready) begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid; +assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr; +assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready; +assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid); +assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid); +assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + litedramcore_bankmachine5_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine5_row_col_n_addr_sel) begin + litedramcore_bankmachine5_cmd_payload_a = litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine5_cmd_payload_a = ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write); +assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open); +always @(*) begin + litedramcore_bankmachine5_auto_precharge = 1'd0; + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine5_auto_precharge = (litedramcore_bankmachine5_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready); +always @(*) begin + bankmachine5_next_state = 4'd0; + bankmachine5_next_state = bankmachine5_state; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + bankmachine5_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + if (litedramcore_bankmachine5_cmd_ready) begin + bankmachine5_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine5_refresh_req)) begin + bankmachine5_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine5_next_state = 3'd6; + end + 3'd6: begin + bankmachine5_next_state = 2'd3; + end + 3'd7: begin + bankmachine5_next_state = 4'd8; + end + 4'd8: begin + bankmachine5_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + bankmachine5_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin + bankmachine5_next_state = 2'd2; + end + end else begin + bankmachine5_next_state = 1'd1; + end + end else begin + bankmachine5_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_read = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_write = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_wdata_ready = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_req_wdata_ready = litedramcore_bankmachine5_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_req_rdata_valid = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine5_req_rdata_valid = litedramcore_bankmachine5_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_refresh_gnt = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine5_twtpcon_ready) begin + litedramcore_bankmachine5_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_valid = 1'd0; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_open = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_row_close = 1'd0; + case (bankmachine5_state) + 1'd1: begin + litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine5_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine5_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_cas = 1'd0; + case (bankmachine5_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + litedramcore_bankmachine5_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_ras = 1'd0; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_we = 1'd0; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine5_refresh_req) begin + end else begin + if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine5_row_opened) begin + if (litedramcore_bankmachine5_row_hit) begin + if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine5_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0; + case (bankmachine5_state) + 1'd1: begin + if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine5_trccon_ready) begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid; +assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr; +assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready; +assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid); +assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid); +assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + litedramcore_bankmachine6_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine6_row_col_n_addr_sel) begin + litedramcore_bankmachine6_cmd_payload_a = litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine6_cmd_payload_a = ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write); +assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open); +always @(*) begin + litedramcore_bankmachine6_auto_precharge = 1'd0; + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine6_auto_precharge = (litedramcore_bankmachine6_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready); +always @(*) begin + bankmachine6_next_state = 4'd0; + bankmachine6_next_state = bankmachine6_state; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + bankmachine6_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + if (litedramcore_bankmachine6_cmd_ready) begin + bankmachine6_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine6_refresh_req)) begin + bankmachine6_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine6_next_state = 3'd6; + end + 3'd6: begin + bankmachine6_next_state = 2'd3; + end + 3'd7: begin + bankmachine6_next_state = 4'd8; + end + 4'd8: begin + bankmachine6_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + bankmachine6_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin + bankmachine6_next_state = 2'd2; + end + end else begin + bankmachine6_next_state = 1'd1; + end + end else begin + bankmachine6_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_read = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_write = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_wdata_ready = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_req_rdata_valid = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine6_req_rdata_valid = litedramcore_bankmachine6_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_refresh_gnt = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine6_twtpcon_ready) begin + litedramcore_bankmachine6_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_valid = 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_open = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_row_close = 1'd0; + case (bankmachine6_state) + 1'd1: begin + litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine6_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine6_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_cas = 1'd0; + case (bankmachine6_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + litedramcore_bankmachine6_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_ras = 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_we = 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine6_refresh_req) begin + end else begin + if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine6_row_opened) begin + if (litedramcore_bankmachine6_row_hit) begin + if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine6_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0; + case (bankmachine6_state) + 1'd1: begin + if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine6_trccon_ready) begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid; +assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr; +assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready; +assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first; +assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid); +assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid); +assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + litedramcore_bankmachine7_cmd_payload_a = 14'd0; + if (litedramcore_bankmachine7_row_col_n_addr_sel) begin + litedramcore_bankmachine7_cmd_payload_a = litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + litedramcore_bankmachine7_cmd_payload_a = ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write); +assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open); +always @(*) begin + litedramcore_bankmachine7_auto_precharge = 1'd0; + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin + if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + litedramcore_bankmachine7_auto_precharge = (litedramcore_bankmachine7_row_close == 1'd0); + end + end +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready; +always @(*) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0; + if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_produce; + end +end +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace)); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16); +assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready); +always @(*) begin + bankmachine7_next_state = 4'd0; + bankmachine7_next_state = bankmachine7_state; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd5; + end + end + end + 2'd2: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + bankmachine7_next_state = 3'd5; + end + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + if (litedramcore_bankmachine7_cmd_ready) begin + bankmachine7_next_state = 3'd7; + end + end + end + 3'd4: begin + if ((~litedramcore_bankmachine7_refresh_req)) begin + bankmachine7_next_state = 1'd0; + end + end + 3'd5: begin + bankmachine7_next_state = 3'd6; + end + 3'd6: begin + bankmachine7_next_state = 2'd3; + end + 3'd7: begin + bankmachine7_next_state = 4'd8; + end + 4'd8: begin + bankmachine7_next_state = 1'd0; + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + bankmachine7_next_state = 3'd4; + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin + bankmachine7_next_state = 2'd2; + end + end else begin + bankmachine7_next_state = 1'd1; + end + end else begin + bankmachine7_next_state = 2'd3; + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_read = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_cmd_payload_is_read = 1'd1; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_write = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_is_write = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_wdata_ready = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_req_wdata_ready = litedramcore_bankmachine7_cmd_ready; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_req_rdata_valid = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + end else begin + litedramcore_bankmachine7_req_rdata_valid = litedramcore_bankmachine7_cmd_ready; + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_refresh_gnt = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (litedramcore_bankmachine7_twtpcon_ready) begin + litedramcore_bankmachine7_refresh_gnt = 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_valid = 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_valid = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_open = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_row_open = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_row_close = 1'd0; + case (bankmachine7_state) + 1'd1: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd2: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + litedramcore_bankmachine7_row_close = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_cas = 1'd0; + case (bankmachine7_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + litedramcore_bankmachine7_cmd_payload_cas = 1'd1; + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_ras = 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_ras = 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_we = 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + if (litedramcore_bankmachine7_refresh_req) begin + end else begin + if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin + if (litedramcore_bankmachine7_row_opened) begin + if (litedramcore_bankmachine7_row_hit) begin + if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin + litedramcore_bankmachine7_cmd_payload_we = 1'd1; + end else begin + end + end else begin + end + end else begin + end + end + end + end + endcase +end +always @(*) begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0; + case (bankmachine7_state) + 1'd1: begin + if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + if (litedramcore_bankmachine7_trccon_ready) begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end + end + 3'd4: begin + litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd1; + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + default: begin + end + endcase +end +assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))); +assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready); +assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read)); +assign litedramcore_cas_allowed = litedramcore_tccdcon_ready; +assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); +assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read)); +assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write)); +assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0); +assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0); +assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid; +assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid; +assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt); +assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata}; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata; +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we); +always @(*) begin + litedramcore_choose_cmd_valids = 8'd0; + litedramcore_choose_cmd_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); + litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes)))); +end +assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids; +assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0; +assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1; +assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2; +assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; +assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; +assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; +always @(*) begin + litedramcore_choose_cmd_cmd_payload_cas = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_ras = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1; + end +end +always @(*) begin + litedramcore_choose_cmd_cmd_payload_we = 1'd0; + if (litedramcore_choose_cmd_cmd_valid) begin + litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2; + end +end +always @(*) begin + litedramcore_bankmachine0_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin + litedramcore_bankmachine0_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine1_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin + litedramcore_bankmachine1_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine2_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin + litedramcore_bankmachine2_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine3_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin + litedramcore_bankmachine3_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine4_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin + litedramcore_bankmachine4_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine5_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin + litedramcore_bankmachine5_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine6_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin + litedramcore_bankmachine6_cmd_ready = 1'd1; + end +end +always @(*) begin + litedramcore_bankmachine7_cmd_ready = 1'd0; + if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready = 1'd1; + end + if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin + litedramcore_bankmachine7_cmd_ready = 1'd1; + end +end +assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid)); +always @(*) begin + litedramcore_choose_req_valids = 8'd0; + litedramcore_choose_req_valids[0] = (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[1] = (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[2] = (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[3] = (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[4] = (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[5] = (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[6] = (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); + litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes)))); +end +assign litedramcore_choose_req_request = litedramcore_choose_req_valids; +assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6; +assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7; +assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8; +assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9; +assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10; +assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; +always @(*) begin + litedramcore_choose_req_cmd_payload_cas = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_cas = t_array_muxed3; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_ras = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_ras = t_array_muxed4; + end +end +always @(*) begin + litedramcore_choose_req_cmd_payload_we = 1'd0; + if (litedramcore_choose_req_cmd_valid) begin + litedramcore_choose_req_cmd_payload_we = t_array_muxed5; + end +end +assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid)); +assign litedramcore_dfi_p0_reset_n = 1'd1; +assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}}; +assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}}; +assign litedramcore_dfi_p1_reset_n = 1'd1; +assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}}; +assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}}; +assign litedramcore_dfi_p2_reset_n = 1'd1; +assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}}; +assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}}; +assign litedramcore_dfi_p3_reset_n = 1'd1; +assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}}; +assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}}; +assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]); +always @(*) begin + multiplexer_next_state = 4'd0; + multiplexer_next_state = multiplexer_state; + case (multiplexer_state) + 1'd1: begin + if (litedramcore_read_available) begin + if (((~litedramcore_write_available) | litedramcore_max_time1)) begin + multiplexer_next_state = 2'd3; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + 2'd2: begin + if (litedramcore_cmd_last) begin + multiplexer_next_state = 1'd0; + end + end + 2'd3: begin + if (litedramcore_twtrcon_ready) begin + multiplexer_next_state = 1'd0; + end + end + 3'd4: begin + multiplexer_next_state = 3'd5; + end + 3'd5: begin + multiplexer_next_state = 3'd6; + end + 3'd6: begin + multiplexer_next_state = 3'd7; + end + 3'd7: begin + multiplexer_next_state = 4'd8; + end + 4'd8: begin + multiplexer_next_state = 4'd9; + end + 4'd9: begin + multiplexer_next_state = 4'd10; + end + 4'd10: begin + multiplexer_next_state = 4'd11; + end + 4'd11: begin + multiplexer_next_state = 1'd1; + end + default: begin + if (litedramcore_write_available) begin + if (((~litedramcore_read_available) | litedramcore_max_time0)) begin + multiplexer_next_state = 3'd4; + end + end + if (litedramcore_go_to_refresh) begin + multiplexer_next_state = 2'd2; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel1 = 2'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel1 = 1'd0; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_steerer_sel1 = 1'd1; + end + endcase +end +always @(*) begin + litedramcore_steerer_sel2 = 2'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel2 = 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_steerer_sel2 = 2'd2; + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_want_activates = 1'd0; + case (multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_want_activates = litedramcore_ras_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_steerer_sel3 = 2'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel3 = 2'd2; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_steerer_sel3 = 1'd0; + end + endcase +end +always @(*) begin + litedramcore_en0 = 1'd0; + case (multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_en0 = 1'd1; + end + endcase +end +always @(*) begin + litedramcore_cmd_ready = 1'd0; + case (multiplexer_state) + 1'd1: begin + end + 2'd2: begin + litedramcore_cmd_ready = 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_cmd_cmd_ready = 1'd0; + case (multiplexer_state) + 1'd1: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + if (1'd0) begin + end else begin + litedramcore_choose_cmd_cmd_ready = ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed); + end + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_reads = 1'd0; + case (multiplexer_state) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_choose_req_want_reads = 1'd1; + end + endcase +end +always @(*) begin + litedramcore_choose_req_want_writes = 1'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_choose_req_want_writes = 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_choose_req_cmd_ready = 1'd0; + case (multiplexer_state) + 1'd1: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + if (1'd0) begin + litedramcore_choose_req_cmd_ready = (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed)); + end else begin + litedramcore_choose_req_cmd_ready = litedramcore_cas_allowed; + end + end + endcase +end +always @(*) begin + litedramcore_en1 = 1'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_en1 = 1'd1; + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + end + endcase +end +always @(*) begin + litedramcore_steerer_sel0 = 2'd0; + case (multiplexer_state) + 1'd1: begin + litedramcore_steerer_sel0 = 1'd0; + end + 2'd2: begin + litedramcore_steerer_sel0 = 2'd3; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + 3'd7: begin + end + 4'd8: begin + end + 4'd9: begin + end + 4'd10: begin + end + 4'd11: begin + end + default: begin + litedramcore_steerer_sel0 = 1'd0; + end + endcase +end +assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock)); +assign litedramcore_interface_bank0_addr = rhs_array_muxed12; +assign litedramcore_interface_bank0_we = rhs_array_muxed13; +assign litedramcore_interface_bank0_valid = rhs_array_muxed14; +assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock)); +assign litedramcore_interface_bank1_addr = rhs_array_muxed15; +assign litedramcore_interface_bank1_we = rhs_array_muxed16; +assign litedramcore_interface_bank1_valid = rhs_array_muxed17; +assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock)); +assign litedramcore_interface_bank2_addr = rhs_array_muxed18; +assign litedramcore_interface_bank2_we = rhs_array_muxed19; +assign litedramcore_interface_bank2_valid = rhs_array_muxed20; +assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock)); +assign litedramcore_interface_bank3_addr = rhs_array_muxed21; +assign litedramcore_interface_bank3_we = rhs_array_muxed22; +assign litedramcore_interface_bank3_valid = rhs_array_muxed23; +assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock)); +assign litedramcore_interface_bank4_addr = rhs_array_muxed24; +assign litedramcore_interface_bank4_we = rhs_array_muxed25; +assign litedramcore_interface_bank4_valid = rhs_array_muxed26; +assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock)); +assign litedramcore_interface_bank5_addr = rhs_array_muxed27; +assign litedramcore_interface_bank5_we = rhs_array_muxed28; +assign litedramcore_interface_bank5_valid = rhs_array_muxed29; +assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock)); +assign litedramcore_interface_bank6_addr = rhs_array_muxed30; +assign litedramcore_interface_bank6_we = rhs_array_muxed31; +assign litedramcore_interface_bank6_valid = rhs_array_muxed32; +assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)}; +assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock)); +assign litedramcore_interface_bank7_addr = rhs_array_muxed33; +assign litedramcore_interface_bank7_we = rhs_array_muxed34; +assign litedramcore_interface_bank7_valid = rhs_array_muxed35; +assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready)); +assign user_port_wdata_ready = new_master_wdata_ready2; +assign user_port_rdata_valid = new_master_rdata_valid9; +always @(*) begin + litedramcore_interface_wdata = 128'd0; + case ({new_master_wdata_ready2}) + 1'd1: begin + litedramcore_interface_wdata = user_port_wdata_payload_data; + end + default: begin + litedramcore_interface_wdata = 1'd0; + end + endcase +end +always @(*) begin + litedramcore_interface_wdata_we = 16'd0; + case ({new_master_wdata_ready2}) + 1'd1: begin + litedramcore_interface_wdata_we = user_port_wdata_payload_we; + end + default: begin + litedramcore_interface_wdata_we = 1'd0; + end + endcase +end +assign user_port_rdata_payload_data = litedramcore_interface_rdata; +assign roundrobin0_grant = 1'd0; +assign roundrobin1_grant = 1'd0; +assign roundrobin2_grant = 1'd0; +assign roundrobin3_grant = 1'd0; +assign roundrobin4_grant = 1'd0; +assign roundrobin5_grant = 1'd0; +assign roundrobin6_grant = 1'd0; +assign roundrobin7_grant = 1'd0; +assign litedramcore_wishbone_adr = wb_bus_adr; +assign litedramcore_wishbone_dat_w = wb_bus_dat_w; +assign wb_bus_dat_r = litedramcore_wishbone_dat_r; +assign litedramcore_wishbone_sel = wb_bus_sel; +assign litedramcore_wishbone_cyc = wb_bus_cyc; +assign litedramcore_wishbone_stb = wb_bus_stb; +assign wb_bus_ack = litedramcore_wishbone_ack; +assign litedramcore_wishbone_we = wb_bus_we; +assign litedramcore_wishbone_cti = wb_bus_cti; +assign litedramcore_wishbone_bte = wb_bus_bte; +assign wb_bus_err = litedramcore_wishbone_err; +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2); +assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0)); +assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0]; +assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1)); +assign csrbank0_init_done0_w = init_done_storage; +assign csrbank0_init_error0_w = init_error_storage; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0]; +assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0)); +assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0)); +assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1)); +assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1)); +assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2)); +assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2)); +assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0]; +assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3)); +assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3)); +assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4)); +assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4)); +assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5)); +assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5)); +assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6)); +assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6)); +assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7)); +assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7)); +assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8)); +assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8)); +assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0]; +assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9)); +assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9)); +assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10)); +assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10)); +assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11)); +assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11)); +assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12)); +assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12)); +assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13)); +assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13)); +assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14)); +assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14)); +assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0]; +assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15)); +assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15)); +assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16)); +assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16)); +assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd17)); +assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd17)); +assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd18)); +assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd18)); +assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0]; +assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd19)); +assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd19)); +assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0]; +assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd20)); +assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd20)); +assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0]; +assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd21)); +assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd21)); +assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0]; +assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd22)); +assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd22)); +assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd23)); +assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd23)); +assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0]; +assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd24)); +assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd24)); +assign csrbank1_dfii_control0_w = litedramcore_storage[3:0]; +assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0]; +assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0]; +assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0]; +assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0]; +assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0]; +assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we; +assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0]; +assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0]; +assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0]; +assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0]; +assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0]; +assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we; +assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0]; +assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0]; +assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0]; +assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0]; +assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0]; +assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we; +assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0]; +assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0]; +assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0]; +assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0]; +assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0]; +assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we; +assign adr = litedramcore_adr; +assign we = litedramcore_we; +assign dat_w = litedramcore_dat_w; +assign litedramcore_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign dat_r = (interface0_bank_bus_dat_r | interface1_bank_bus_dat_r); +assign slice_proxy0 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_write_col); +assign slice_proxy1 = ((ddrphy_bankmodel0_row * 11'd1024) | ddrphy_bankmodel0_read_col); +assign slice_proxy2 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_write_col); +assign slice_proxy3 = ((ddrphy_bankmodel1_row * 11'd1024) | ddrphy_bankmodel1_read_col); +assign slice_proxy4 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_write_col); +assign slice_proxy5 = ((ddrphy_bankmodel2_row * 11'd1024) | ddrphy_bankmodel2_read_col); +assign slice_proxy6 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_write_col); +assign slice_proxy7 = ((ddrphy_bankmodel3_row * 11'd1024) | ddrphy_bankmodel3_read_col); +assign slice_proxy8 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_write_col); +assign slice_proxy9 = ((ddrphy_bankmodel4_row * 11'd1024) | ddrphy_bankmodel4_read_col); +assign slice_proxy10 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_write_col); +assign slice_proxy11 = ((ddrphy_bankmodel5_row * 11'd1024) | ddrphy_bankmodel5_read_col); +assign slice_proxy12 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_write_col); +assign slice_proxy13 = ((ddrphy_bankmodel6_row * 11'd1024) | ddrphy_bankmodel6_read_col); +assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col); +assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col); +always @(*) begin + rhs_array_muxed0 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[0]; + end + 1'd1: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[1]; + end + 2'd2: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[2]; + end + 2'd3: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[3]; + end + 3'd4: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[4]; + end + 3'd5: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[5]; + end + 3'd6: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[6]; + end + default: begin + rhs_array_muxed0 = litedramcore_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed1 = 14'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed2 = 3'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed3 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed4 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed5 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed0 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed1 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed2 = 1'd0; + case (litedramcore_choose_cmd_grant) + 1'd0: begin + t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed6 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[0]; + end + 1'd1: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[1]; + end + 2'd2: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[2]; + end + 2'd3: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[3]; + end + 3'd4: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[4]; + end + 3'd5: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[5]; + end + 3'd6: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[6]; + end + default: begin + rhs_array_muxed6 = litedramcore_choose_req_valids[7]; + end + endcase +end +always @(*) begin + rhs_array_muxed7 = 14'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a; + end + 1'd1: begin + rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a; + end + 2'd2: begin + rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a; + end + 2'd3: begin + rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a; + end + 3'd4: begin + rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a; + end + 3'd5: begin + rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a; + end + 3'd6: begin + rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a; + end + default: begin + rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + rhs_array_muxed8 = 3'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba; + end + default: begin + rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + rhs_array_muxed9 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read; + end + default: begin + rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + rhs_array_muxed10 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write; + end + default: begin + rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + rhs_array_muxed11 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd; + end + default: begin + rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + t_array_muxed3 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas; + end + default: begin + t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + t_array_muxed4 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras; + end + default: begin + t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + t_array_muxed5 = 1'd0; + case (litedramcore_choose_req_grant) + 1'd0: begin + t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we; + end + 1'd1: begin + t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we; + end + 2'd2: begin + t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we; + end + 2'd3: begin + t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we; + end + 3'd4: begin + t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we; + end + 3'd5: begin + t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we; + end + 3'd6: begin + t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we; + end + default: begin + t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed12 = 21'd0; + case (roundrobin0_grant) + default: begin + rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed13 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_array_muxed13 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed14 = 1'd0; + case (roundrobin0_grant) + default: begin + rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed15 = 21'd0; + case (roundrobin1_grant) + default: begin + rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed16 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_array_muxed16 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed17 = 1'd0; + case (roundrobin1_grant) + default: begin + rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed18 = 21'd0; + case (roundrobin2_grant) + default: begin + rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed19 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_array_muxed19 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed20 = 1'd0; + case (roundrobin2_grant) + default: begin + rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed21 = 21'd0; + case (roundrobin3_grant) + default: begin + rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed22 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_array_muxed22 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed23 = 1'd0; + case (roundrobin3_grant) + default: begin + rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed24 = 21'd0; + case (roundrobin4_grant) + default: begin + rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed25 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_array_muxed25 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed26 = 1'd0; + case (roundrobin4_grant) + default: begin + rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed27 = 21'd0; + case (roundrobin5_grant) + default: begin + rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed28 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_array_muxed28 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed29 = 1'd0; + case (roundrobin5_grant) + default: begin + rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed30 = 21'd0; + case (roundrobin6_grant) + default: begin + rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed31 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_array_muxed31 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed32 = 1'd0; + case (roundrobin6_grant) + default: begin + rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + rhs_array_muxed33 = 21'd0; + case (roundrobin7_grant) + default: begin + rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + rhs_array_muxed34 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_array_muxed34 = user_port_cmd_payload_we; + end + endcase +end +always @(*) begin + rhs_array_muxed35 = 1'd0; + case (roundrobin7_grant) + default: begin + rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid); + end + endcase +end +always @(*) begin + array_muxed0 = 3'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed0 = litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed0 = litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed1 = 14'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed1 = litedramcore_nop_a; + end + 1'd1: begin + array_muxed1 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed1 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed1 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed2 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed2 = 1'd0; + end + 1'd1: begin + array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed3 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed3 = 1'd0; + end + 1'd1: begin + array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed4 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed4 = 1'd0; + end + 1'd1: begin + array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed5 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed5 = 1'd0; + end + 1'd1: begin + array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed6 = 1'd0; + case (litedramcore_steerer_sel0) + 1'd0: begin + array_muxed6 = 1'd0; + end + 1'd1: begin + array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed7 = 3'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed7 = litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed7 = litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed8 = 14'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed8 = litedramcore_nop_a; + end + 1'd1: begin + array_muxed8 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed8 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed8 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed9 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed9 = 1'd0; + end + 1'd1: begin + array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed10 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed10 = 1'd0; + end + 1'd1: begin + array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed11 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed11 = 1'd0; + end + 1'd1: begin + array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed12 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed12 = 1'd0; + end + 1'd1: begin + array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed13 = 1'd0; + case (litedramcore_steerer_sel1) + 1'd0: begin + array_muxed13 = 1'd0; + end + 1'd1: begin + array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed14 = 3'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed14 = litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed14 = litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed15 = 14'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed15 = litedramcore_nop_a; + end + 1'd1: begin + array_muxed15 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed15 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed15 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed16 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed16 = 1'd0; + end + 1'd1: begin + array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed17 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed17 = 1'd0; + end + 1'd1: begin + array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed18 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed18 = 1'd0; + end + 1'd1: begin + array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed19 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed19 = 1'd0; + end + 1'd1: begin + array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed20 = 1'd0; + case (litedramcore_steerer_sel2) + 1'd0: begin + array_muxed20 = 1'd0; + end + 1'd1: begin + array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end +always @(*) begin + array_muxed21 = 3'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed21 = litedramcore_nop_ba[2:0]; + end + 1'd1: begin + array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0]; + end + default: begin + array_muxed21 = litedramcore_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + array_muxed22 = 14'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed22 = litedramcore_nop_a; + end + 1'd1: begin + array_muxed22 = litedramcore_choose_cmd_cmd_payload_a; + end + 2'd2: begin + array_muxed22 = litedramcore_choose_req_cmd_payload_a; + end + default: begin + array_muxed22 = litedramcore_cmd_payload_a; + end + endcase +end +always @(*) begin + array_muxed23 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed23 = 1'd0; + end + 1'd1: begin + array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas); + end + default: begin + array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas); + end + endcase +end +always @(*) begin + array_muxed24 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed24 = 1'd0; + end + 1'd1: begin + array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras); + end + default: begin + array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras); + end + endcase +end +always @(*) begin + array_muxed25 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed25 = 1'd0; + end + 1'd1: begin + array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we); + end + 2'd2: begin + array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we); + end + default: begin + array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we); + end + endcase +end +always @(*) begin + array_muxed26 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed26 = 1'd0; + end + 1'd1: begin + array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read); + end + default: begin + array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read); + end + endcase +end +always @(*) begin + array_muxed27 = 1'd0; + case (litedramcore_steerer_sel3) + 1'd0: begin + array_muxed27 = 1'd0; + end + 1'd1: begin + array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write); + end + default: begin + array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write); + end + endcase +end + +always @(posedge por_clk) begin + int_rst <= 1'd0; +end + +always @(posedge sys_clk) begin + state <= next_state; + ddrphy_new_bank_write0 <= ddrphy_bank_write0; + ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0; + ddrphy_new_bank_write1 <= ddrphy_new_bank_write0; + ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0; + ddrphy_new_bank_write2 <= ddrphy_bank_write1; + ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1; + ddrphy_new_bank_write3 <= ddrphy_new_bank_write2; + ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2; + ddrphy_new_bank_write4 <= ddrphy_bank_write2; + ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2; + ddrphy_new_bank_write5 <= ddrphy_new_bank_write4; + ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4; + ddrphy_new_bank_write6 <= ddrphy_bank_write3; + ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3; + ddrphy_new_bank_write7 <= ddrphy_new_bank_write6; + ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6; + ddrphy_new_bank_write8 <= ddrphy_bank_write4; + ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4; + ddrphy_new_bank_write9 <= ddrphy_new_bank_write8; + ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8; + ddrphy_new_bank_write10 <= ddrphy_bank_write5; + ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5; + ddrphy_new_bank_write11 <= ddrphy_new_bank_write10; + ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10; + ddrphy_new_bank_write12 <= ddrphy_bank_write6; + ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6; + ddrphy_new_bank_write13 <= ddrphy_new_bank_write12; + ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12; + ddrphy_new_bank_write14 <= ddrphy_bank_write7; + ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7; + ddrphy_new_bank_write15 <= ddrphy_new_bank_write14; + ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14; + ddrphy_new_banks_read0 <= ddrphy_banks_read; + ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data; + ddrphy_new_banks_read1 <= ddrphy_new_banks_read0; + ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0; + ddrphy_new_banks_read2 <= ddrphy_new_banks_read1; + ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1; + ddrphy_new_banks_read3 <= ddrphy_new_banks_read2; + ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2; + ddrphy_new_banks_read4 <= ddrphy_new_banks_read3; + ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3; + ddrphy_new_banks_read5 <= ddrphy_new_banks_read4; + ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4; + ddrphy_new_banks_read6 <= ddrphy_new_banks_read5; + ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5; + ddrphy_new_banks_read7 <= ddrphy_new_banks_read6; + ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6; + ddrphy_new_banks_read8 <= ddrphy_new_banks_read7; + ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7; + if (ddrphy_bankmodel0_precharge) begin + ddrphy_bankmodel0_active <= 1'd0; + end else begin + if (ddrphy_bankmodel0_activate) begin + ddrphy_bankmodel0_active <= 1'd1; + ddrphy_bankmodel0_row <= ddrphy_bankmodel0_activate_row; + end + end + if (ddrphy_bankmodel1_precharge) begin + ddrphy_bankmodel1_active <= 1'd0; + end else begin + if (ddrphy_bankmodel1_activate) begin + ddrphy_bankmodel1_active <= 1'd1; + ddrphy_bankmodel1_row <= ddrphy_bankmodel1_activate_row; + end + end + if (ddrphy_bankmodel2_precharge) begin + ddrphy_bankmodel2_active <= 1'd0; + end else begin + if (ddrphy_bankmodel2_activate) begin + ddrphy_bankmodel2_active <= 1'd1; + ddrphy_bankmodel2_row <= ddrphy_bankmodel2_activate_row; + end + end + if (ddrphy_bankmodel3_precharge) begin + ddrphy_bankmodel3_active <= 1'd0; + end else begin + if (ddrphy_bankmodel3_activate) begin + ddrphy_bankmodel3_active <= 1'd1; + ddrphy_bankmodel3_row <= ddrphy_bankmodel3_activate_row; + end + end + if (ddrphy_bankmodel4_precharge) begin + ddrphy_bankmodel4_active <= 1'd0; + end else begin + if (ddrphy_bankmodel4_activate) begin + ddrphy_bankmodel4_active <= 1'd1; + ddrphy_bankmodel4_row <= ddrphy_bankmodel4_activate_row; + end + end + if (ddrphy_bankmodel5_precharge) begin + ddrphy_bankmodel5_active <= 1'd0; + end else begin + if (ddrphy_bankmodel5_activate) begin + ddrphy_bankmodel5_active <= 1'd1; + ddrphy_bankmodel5_row <= ddrphy_bankmodel5_activate_row; + end + end + if (ddrphy_bankmodel6_precharge) begin + ddrphy_bankmodel6_active <= 1'd0; + end else begin + if (ddrphy_bankmodel6_activate) begin + ddrphy_bankmodel6_active <= 1'd1; + ddrphy_bankmodel6_row <= ddrphy_bankmodel6_activate_row; + end + end + if (ddrphy_bankmodel7_precharge) begin + ddrphy_bankmodel7_active <= 1'd0; + end else begin + if (ddrphy_bankmodel7_activate) begin + ddrphy_bankmodel7_active <= 1'd1; + ddrphy_bankmodel7_row <= ddrphy_bankmodel7_activate_row; + end + end + if (litedramcore_inti_p0_rddata_valid) begin + litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata; + end + if (litedramcore_inti_p1_rddata_valid) begin + litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata; + end + if (litedramcore_inti_p2_rddata_valid) begin + litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata; + end + if (litedramcore_inti_p3_rddata_valid) begin + litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata; + end + if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin + litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1); + end else begin + litedramcore_timer_count1 <= 10'd781; + end + litedramcore_postponer_req_o <= 1'd0; + if (litedramcore_postponer_req_i) begin + litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1); + if ((litedramcore_postponer_count == 1'd0)) begin + litedramcore_postponer_count <= 1'd0; + litedramcore_postponer_req_o <= 1'd1; + end + end + if (litedramcore_sequencer_start0) begin + litedramcore_sequencer_count <= 1'd0; + end else begin + if (litedramcore_sequencer_done1) begin + if ((litedramcore_sequencer_count != 1'd0)) begin + litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1); + end + end + end + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_sequencer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd1; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd0; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_sequencer_done1 <= 1'd1; + end + if ((litedramcore_sequencer_counter == 6'd35)) begin + litedramcore_sequencer_counter <= 1'd0; + end else begin + if ((litedramcore_sequencer_counter != 1'd0)) begin + litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1); + end else begin + if (litedramcore_sequencer_start1) begin + litedramcore_sequencer_counter <= 1'd1; + end + end + end + if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin + litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1); + end else begin + litedramcore_zqcs_timer_count1 <= 27'd99999999; + end + litedramcore_zqcs_executer_done <= 1'd0; + if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin + litedramcore_cmd_payload_a <= 11'd1024; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd1; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 2'd3)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_cmd_payload_a <= 1'd0; + litedramcore_cmd_payload_ba <= 1'd0; + litedramcore_cmd_payload_cas <= 1'd0; + litedramcore_cmd_payload_ras <= 1'd0; + litedramcore_cmd_payload_we <= 1'd0; + litedramcore_zqcs_executer_done <= 1'd1; + end + if ((litedramcore_zqcs_executer_counter == 5'd19)) begin + litedramcore_zqcs_executer_counter <= 1'd0; + end else begin + if ((litedramcore_zqcs_executer_counter != 1'd0)) begin + litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1); + end else begin + if (litedramcore_zqcs_executer_start) begin + litedramcore_zqcs_executer_counter <= 1'd1; + end + end + end + refresher_state <= refresher_next_state; + if (litedramcore_bankmachine0_row_close) begin + litedramcore_bankmachine0_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine0_row_open) begin + litedramcore_bankmachine0_row_opened <= 1'd1; + litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin + litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid; + litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first; + litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last; + litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we; + litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine0_twtpcon_valid) begin + litedramcore_bankmachine0_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_twtpcon_ready)) begin + litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trccon_valid) begin + litedramcore_bankmachine0_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trccon_ready)) begin + litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1); + if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin + litedramcore_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine0_trascon_valid) begin + litedramcore_bankmachine0_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine0_trascon_ready)) begin + litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1); + if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin + litedramcore_bankmachine0_trascon_ready <= 1'd1; + end + end + end + bankmachine0_state <= bankmachine0_next_state; + if (litedramcore_bankmachine1_row_close) begin + litedramcore_bankmachine1_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine1_row_open) begin + litedramcore_bankmachine1_row_opened <= 1'd1; + litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin + litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid; + litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first; + litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last; + litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we; + litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine1_twtpcon_valid) begin + litedramcore_bankmachine1_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_twtpcon_ready)) begin + litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trccon_valid) begin + litedramcore_bankmachine1_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trccon_ready)) begin + litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1); + if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin + litedramcore_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine1_trascon_valid) begin + litedramcore_bankmachine1_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine1_trascon_ready)) begin + litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1); + if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin + litedramcore_bankmachine1_trascon_ready <= 1'd1; + end + end + end + bankmachine1_state <= bankmachine1_next_state; + if (litedramcore_bankmachine2_row_close) begin + litedramcore_bankmachine2_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine2_row_open) begin + litedramcore_bankmachine2_row_opened <= 1'd1; + litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin + litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid; + litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first; + litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last; + litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we; + litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine2_twtpcon_valid) begin + litedramcore_bankmachine2_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_twtpcon_ready)) begin + litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trccon_valid) begin + litedramcore_bankmachine2_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trccon_ready)) begin + litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1); + if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin + litedramcore_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine2_trascon_valid) begin + litedramcore_bankmachine2_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine2_trascon_ready)) begin + litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1); + if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin + litedramcore_bankmachine2_trascon_ready <= 1'd1; + end + end + end + bankmachine2_state <= bankmachine2_next_state; + if (litedramcore_bankmachine3_row_close) begin + litedramcore_bankmachine3_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine3_row_open) begin + litedramcore_bankmachine3_row_opened <= 1'd1; + litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin + litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid; + litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first; + litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last; + litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we; + litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine3_twtpcon_valid) begin + litedramcore_bankmachine3_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_twtpcon_ready)) begin + litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trccon_valid) begin + litedramcore_bankmachine3_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trccon_ready)) begin + litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1); + if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin + litedramcore_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine3_trascon_valid) begin + litedramcore_bankmachine3_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine3_trascon_ready)) begin + litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1); + if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin + litedramcore_bankmachine3_trascon_ready <= 1'd1; + end + end + end + bankmachine3_state <= bankmachine3_next_state; + if (litedramcore_bankmachine4_row_close) begin + litedramcore_bankmachine4_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine4_row_open) begin + litedramcore_bankmachine4_row_opened <= 1'd1; + litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin + litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid; + litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first; + litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last; + litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we; + litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine4_twtpcon_valid) begin + litedramcore_bankmachine4_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_twtpcon_ready)) begin + litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trccon_valid) begin + litedramcore_bankmachine4_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trccon_ready)) begin + litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1); + if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin + litedramcore_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine4_trascon_valid) begin + litedramcore_bankmachine4_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine4_trascon_ready)) begin + litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1); + if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin + litedramcore_bankmachine4_trascon_ready <= 1'd1; + end + end + end + bankmachine4_state <= bankmachine4_next_state; + if (litedramcore_bankmachine5_row_close) begin + litedramcore_bankmachine5_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine5_row_open) begin + litedramcore_bankmachine5_row_opened <= 1'd1; + litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin + litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid; + litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first; + litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last; + litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we; + litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine5_twtpcon_valid) begin + litedramcore_bankmachine5_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_twtpcon_ready)) begin + litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trccon_valid) begin + litedramcore_bankmachine5_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trccon_ready)) begin + litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1); + if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin + litedramcore_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine5_trascon_valid) begin + litedramcore_bankmachine5_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine5_trascon_ready)) begin + litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1); + if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin + litedramcore_bankmachine5_trascon_ready <= 1'd1; + end + end + end + bankmachine5_state <= bankmachine5_next_state; + if (litedramcore_bankmachine6_row_close) begin + litedramcore_bankmachine6_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine6_row_open) begin + litedramcore_bankmachine6_row_opened <= 1'd1; + litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin + litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid; + litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first; + litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last; + litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we; + litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine6_twtpcon_valid) begin + litedramcore_bankmachine6_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_twtpcon_ready)) begin + litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trccon_valid) begin + litedramcore_bankmachine6_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trccon_ready)) begin + litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1); + if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin + litedramcore_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine6_trascon_valid) begin + litedramcore_bankmachine6_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine6_trascon_ready)) begin + litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1); + if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin + litedramcore_bankmachine6_trascon_ready <= 1'd1; + end + end + end + bankmachine6_state <= bankmachine6_next_state; + if (litedramcore_bankmachine7_row_close) begin + litedramcore_bankmachine7_row_opened <= 1'd0; + end else begin + if (litedramcore_bankmachine7_row_open) begin + litedramcore_bankmachine7_row_opened <= 1'd1; + litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin + litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid; + litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first; + litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last; + litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we; + litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (litedramcore_bankmachine7_twtpcon_valid) begin + litedramcore_bankmachine7_twtpcon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_twtpcon_ready)) begin + litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1); + if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin + litedramcore_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trccon_valid) begin + litedramcore_bankmachine7_trccon_count <= 3'd5; + if (1'd0) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trccon_ready)) begin + litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1); + if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin + litedramcore_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (litedramcore_bankmachine7_trascon_valid) begin + litedramcore_bankmachine7_trascon_count <= 3'd4; + if (1'd0) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end else begin + litedramcore_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_bankmachine7_trascon_ready)) begin + litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1); + if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin + litedramcore_bankmachine7_trascon_ready <= 1'd1; + end + end + end + bankmachine7_state <= bankmachine7_next_state; + if ((~litedramcore_en0)) begin + litedramcore_time0 <= 5'd31; + end else begin + if ((~litedramcore_max_time0)) begin + litedramcore_time0 <= (litedramcore_time0 - 1'd1); + end + end + if ((~litedramcore_en1)) begin + litedramcore_time1 <= 4'd15; + end else begin + if ((~litedramcore_max_time1)) begin + litedramcore_time1 <= (litedramcore_time1 - 1'd1); + end + end + if (litedramcore_choose_cmd_ce) begin + case (litedramcore_choose_cmd_grant) + 1'd0: begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end else begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_cmd_request[7]) begin + litedramcore_choose_cmd_grant <= 3'd7; + end else begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_cmd_request[0]) begin + litedramcore_choose_cmd_grant <= 1'd0; + end else begin + if (litedramcore_choose_cmd_request[1]) begin + litedramcore_choose_cmd_grant <= 1'd1; + end else begin + if (litedramcore_choose_cmd_request[2]) begin + litedramcore_choose_cmd_grant <= 2'd2; + end else begin + if (litedramcore_choose_cmd_request[3]) begin + litedramcore_choose_cmd_grant <= 2'd3; + end else begin + if (litedramcore_choose_cmd_request[4]) begin + litedramcore_choose_cmd_grant <= 3'd4; + end else begin + if (litedramcore_choose_cmd_request[5]) begin + litedramcore_choose_cmd_grant <= 3'd5; + end else begin + if (litedramcore_choose_cmd_request[6]) begin + litedramcore_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (litedramcore_choose_req_ce) begin + case (litedramcore_choose_req_grant) + 1'd0: begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end else begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (litedramcore_choose_req_request[7]) begin + litedramcore_choose_req_grant <= 3'd7; + end else begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (litedramcore_choose_req_request[0]) begin + litedramcore_choose_req_grant <= 1'd0; + end else begin + if (litedramcore_choose_req_request[1]) begin + litedramcore_choose_req_grant <= 1'd1; + end else begin + if (litedramcore_choose_req_request[2]) begin + litedramcore_choose_req_grant <= 2'd2; + end else begin + if (litedramcore_choose_req_request[3]) begin + litedramcore_choose_req_grant <= 2'd3; + end else begin + if (litedramcore_choose_req_request[4]) begin + litedramcore_choose_req_grant <= 3'd4; + end else begin + if (litedramcore_choose_req_request[5]) begin + litedramcore_choose_req_grant <= 3'd5; + end else begin + if (litedramcore_choose_req_request[6]) begin + litedramcore_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + litedramcore_dfi_p0_cs_n <= 1'd0; + litedramcore_dfi_p0_bank <= array_muxed0; + litedramcore_dfi_p0_address <= array_muxed1; + litedramcore_dfi_p0_cas_n <= (~array_muxed2); + litedramcore_dfi_p0_ras_n <= (~array_muxed3); + litedramcore_dfi_p0_we_n <= (~array_muxed4); + litedramcore_dfi_p0_rddata_en <= array_muxed5; + litedramcore_dfi_p0_wrdata_en <= array_muxed6; + litedramcore_dfi_p1_cs_n <= 1'd0; + litedramcore_dfi_p1_bank <= array_muxed7; + litedramcore_dfi_p1_address <= array_muxed8; + litedramcore_dfi_p1_cas_n <= (~array_muxed9); + litedramcore_dfi_p1_ras_n <= (~array_muxed10); + litedramcore_dfi_p1_we_n <= (~array_muxed11); + litedramcore_dfi_p1_rddata_en <= array_muxed12; + litedramcore_dfi_p1_wrdata_en <= array_muxed13; + litedramcore_dfi_p2_cs_n <= 1'd0; + litedramcore_dfi_p2_bank <= array_muxed14; + litedramcore_dfi_p2_address <= array_muxed15; + litedramcore_dfi_p2_cas_n <= (~array_muxed16); + litedramcore_dfi_p2_ras_n <= (~array_muxed17); + litedramcore_dfi_p2_we_n <= (~array_muxed18); + litedramcore_dfi_p2_rddata_en <= array_muxed19; + litedramcore_dfi_p2_wrdata_en <= array_muxed20; + litedramcore_dfi_p3_cs_n <= 1'd0; + litedramcore_dfi_p3_bank <= array_muxed21; + litedramcore_dfi_p3_address <= array_muxed22; + litedramcore_dfi_p3_cas_n <= (~array_muxed23); + litedramcore_dfi_p3_ras_n <= (~array_muxed24); + litedramcore_dfi_p3_we_n <= (~array_muxed25); + litedramcore_dfi_p3_rddata_en <= array_muxed26; + litedramcore_dfi_p3_wrdata_en <= array_muxed27; + if (litedramcore_trrdcon_valid) begin + litedramcore_trrdcon_count <= 1'd1; + if (1'd0) begin + litedramcore_trrdcon_ready <= 1'd1; + end else begin + litedramcore_trrdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_trrdcon_ready)) begin + litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1); + if ((litedramcore_trrdcon_count == 1'd1)) begin + litedramcore_trrdcon_ready <= 1'd1; + end + end + end + litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid}; + if ((litedramcore_tfawcon_count < 3'd4)) begin + if ((litedramcore_tfawcon_count == 2'd3)) begin + litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid); + end else begin + litedramcore_tfawcon_ready <= 1'd1; + end + end + if (litedramcore_tccdcon_valid) begin + litedramcore_tccdcon_count <= 1'd0; + if (1'd1) begin + litedramcore_tccdcon_ready <= 1'd1; + end else begin + litedramcore_tccdcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_tccdcon_ready)) begin + litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1); + if ((litedramcore_tccdcon_count == 1'd1)) begin + litedramcore_tccdcon_ready <= 1'd1; + end + end + end + if (litedramcore_twtrcon_valid) begin + litedramcore_twtrcon_count <= 3'd4; + if (1'd0) begin + litedramcore_twtrcon_ready <= 1'd1; + end else begin + litedramcore_twtrcon_ready <= 1'd0; + end + end else begin + if ((~litedramcore_twtrcon_ready)) begin + litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1); + if ((litedramcore_twtrcon_count == 1'd1)) begin + litedramcore_twtrcon_ready <= 1'd1; + end + end + end + multiplexer_state <= multiplexer_next_state; + new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready)); + new_master_wdata_ready1 <= new_master_wdata_ready0; + new_master_wdata_ready2 <= new_master_wdata_ready1; + new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid)); + new_master_rdata_valid1 <= new_master_rdata_valid0; + new_master_rdata_valid2 <= new_master_rdata_valid1; + new_master_rdata_valid3 <= new_master_rdata_valid2; + new_master_rdata_valid4 <= new_master_rdata_valid3; + new_master_rdata_valid5 <= new_master_rdata_valid4; + new_master_rdata_valid6 <= new_master_rdata_valid5; + new_master_rdata_valid7 <= new_master_rdata_valid6; + new_master_rdata_valid8 <= new_master_rdata_valid7; + new_master_rdata_valid9 <= new_master_rdata_valid8; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_init_done0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_init_error0_w; + end + endcase + end + if (csrbank0_init_done0_re) begin + init_done_storage <= csrbank0_init_done0_r; + end + init_done_re <= csrbank0_init_done0_re; + if (csrbank0_init_error0_re) begin + init_error_storage <= csrbank0_init_error0_r; + end + init_error_re <= csrbank0_init_error0_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[4:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w; + end + 3'd7: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w; + end + 4'd8: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w; + end + 4'd9: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w; + end + 4'd10: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w; + end + 4'd11: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w; + end + 4'd12: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w; + end + 4'd13: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w; + end + 4'd14: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w; + end + 4'd15: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w; + end + 5'd16: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w; + end + 5'd17: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w; + end + 5'd18: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w; + end + 5'd19: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w; + end + 5'd20: begin + interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w; + end + 5'd21: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w; + end + 5'd22: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w; + end + 5'd23: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w; + end + 5'd24: begin + interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w; + end + endcase + end + if (csrbank1_dfii_control0_re) begin + litedramcore_storage[3:0] <= csrbank1_dfii_control0_r; + end + litedramcore_re <= csrbank1_dfii_control0_re; + if (csrbank1_dfii_pi0_command0_re) begin + litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r; + end + litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re; + if (csrbank1_dfii_pi0_address0_re) begin + litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r; + end + litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re; + if (csrbank1_dfii_pi0_baddress0_re) begin + litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r; + end + litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re; + if (csrbank1_dfii_pi0_wrdata0_re) begin + litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r; + end + litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re; + if (csrbank1_dfii_pi1_command0_re) begin + litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r; + end + litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re; + if (csrbank1_dfii_pi1_address0_re) begin + litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r; + end + litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re; + if (csrbank1_dfii_pi1_baddress0_re) begin + litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r; + end + litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re; + if (csrbank1_dfii_pi1_wrdata0_re) begin + litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r; + end + litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re; + if (csrbank1_dfii_pi2_command0_re) begin + litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r; + end + litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re; + if (csrbank1_dfii_pi2_address0_re) begin + litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r; + end + litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re; + if (csrbank1_dfii_pi2_baddress0_re) begin + litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r; + end + litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re; + if (csrbank1_dfii_pi2_wrdata0_re) begin + litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r; + end + litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re; + if (csrbank1_dfii_pi3_command0_re) begin + litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r; + end + litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re; + if (csrbank1_dfii_pi3_address0_re) begin + litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r; + end + litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re; + if (csrbank1_dfii_pi3_baddress0_re) begin + litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r; + end + litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re; + if (csrbank1_dfii_pi3_wrdata0_re) begin + litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r; + end + litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re; + if (sys_rst) begin + ddrphy_bankmodel0_active <= 1'd0; + ddrphy_bankmodel0_row <= 14'd0; + ddrphy_bankmodel1_active <= 1'd0; + ddrphy_bankmodel1_row <= 14'd0; + ddrphy_bankmodel2_active <= 1'd0; + ddrphy_bankmodel2_row <= 14'd0; + ddrphy_bankmodel3_active <= 1'd0; + ddrphy_bankmodel3_row <= 14'd0; + ddrphy_bankmodel4_active <= 1'd0; + ddrphy_bankmodel4_row <= 14'd0; + ddrphy_bankmodel5_active <= 1'd0; + ddrphy_bankmodel5_row <= 14'd0; + ddrphy_bankmodel6_active <= 1'd0; + ddrphy_bankmodel6_row <= 14'd0; + ddrphy_bankmodel7_active <= 1'd0; + ddrphy_bankmodel7_row <= 14'd0; + ddrphy_new_bank_write0 <= 1'd0; + ddrphy_new_bank_write_col0 <= 10'd0; + ddrphy_new_bank_write1 <= 1'd0; + ddrphy_new_bank_write_col1 <= 10'd0; + ddrphy_new_bank_write2 <= 1'd0; + ddrphy_new_bank_write_col2 <= 10'd0; + ddrphy_new_bank_write3 <= 1'd0; + ddrphy_new_bank_write_col3 <= 10'd0; + ddrphy_new_bank_write4 <= 1'd0; + ddrphy_new_bank_write_col4 <= 10'd0; + ddrphy_new_bank_write5 <= 1'd0; + ddrphy_new_bank_write_col5 <= 10'd0; + ddrphy_new_bank_write6 <= 1'd0; + ddrphy_new_bank_write_col6 <= 10'd0; + ddrphy_new_bank_write7 <= 1'd0; + ddrphy_new_bank_write_col7 <= 10'd0; + ddrphy_new_bank_write8 <= 1'd0; + ddrphy_new_bank_write_col8 <= 10'd0; + ddrphy_new_bank_write9 <= 1'd0; + ddrphy_new_bank_write_col9 <= 10'd0; + ddrphy_new_bank_write10 <= 1'd0; + ddrphy_new_bank_write_col10 <= 10'd0; + ddrphy_new_bank_write11 <= 1'd0; + ddrphy_new_bank_write_col11 <= 10'd0; + ddrphy_new_bank_write12 <= 1'd0; + ddrphy_new_bank_write_col12 <= 10'd0; + ddrphy_new_bank_write13 <= 1'd0; + ddrphy_new_bank_write_col13 <= 10'd0; + ddrphy_new_bank_write14 <= 1'd0; + ddrphy_new_bank_write_col14 <= 10'd0; + ddrphy_new_bank_write15 <= 1'd0; + ddrphy_new_bank_write_col15 <= 10'd0; + ddrphy_new_banks_read0 <= 1'd0; + ddrphy_new_banks_read_data0 <= 128'd0; + ddrphy_new_banks_read1 <= 1'd0; + ddrphy_new_banks_read_data1 <= 128'd0; + ddrphy_new_banks_read2 <= 1'd0; + ddrphy_new_banks_read_data2 <= 128'd0; + ddrphy_new_banks_read3 <= 1'd0; + ddrphy_new_banks_read_data3 <= 128'd0; + ddrphy_new_banks_read4 <= 1'd0; + ddrphy_new_banks_read_data4 <= 128'd0; + ddrphy_new_banks_read5 <= 1'd0; + ddrphy_new_banks_read_data5 <= 128'd0; + ddrphy_new_banks_read6 <= 1'd0; + ddrphy_new_banks_read_data6 <= 128'd0; + ddrphy_new_banks_read7 <= 1'd0; + ddrphy_new_banks_read_data7 <= 128'd0; + ddrphy_new_banks_read8 <= 1'd0; + ddrphy_new_banks_read_data8 <= 128'd0; + litedramcore_storage <= 4'd1; + litedramcore_re <= 1'd0; + litedramcore_phaseinjector0_command_storage <= 6'd0; + litedramcore_phaseinjector0_command_re <= 1'd0; + litedramcore_phaseinjector0_address_re <= 1'd0; + litedramcore_phaseinjector0_baddress_re <= 1'd0; + litedramcore_phaseinjector0_wrdata_re <= 1'd0; + litedramcore_phaseinjector0_status <= 32'd0; + litedramcore_phaseinjector1_command_storage <= 6'd0; + litedramcore_phaseinjector1_command_re <= 1'd0; + litedramcore_phaseinjector1_address_re <= 1'd0; + litedramcore_phaseinjector1_baddress_re <= 1'd0; + litedramcore_phaseinjector1_wrdata_re <= 1'd0; + litedramcore_phaseinjector1_status <= 32'd0; + litedramcore_phaseinjector2_command_storage <= 6'd0; + litedramcore_phaseinjector2_command_re <= 1'd0; + litedramcore_phaseinjector2_address_re <= 1'd0; + litedramcore_phaseinjector2_baddress_re <= 1'd0; + litedramcore_phaseinjector2_wrdata_re <= 1'd0; + litedramcore_phaseinjector2_status <= 32'd0; + litedramcore_phaseinjector3_command_storage <= 6'd0; + litedramcore_phaseinjector3_command_re <= 1'd0; + litedramcore_phaseinjector3_address_re <= 1'd0; + litedramcore_phaseinjector3_baddress_re <= 1'd0; + litedramcore_phaseinjector3_wrdata_re <= 1'd0; + litedramcore_phaseinjector3_status <= 32'd0; + litedramcore_dfi_p0_address <= 14'd0; + litedramcore_dfi_p0_bank <= 3'd0; + litedramcore_dfi_p0_cas_n <= 1'd1; + litedramcore_dfi_p0_cs_n <= 1'd1; + litedramcore_dfi_p0_ras_n <= 1'd1; + litedramcore_dfi_p0_we_n <= 1'd1; + litedramcore_dfi_p0_wrdata_en <= 1'd0; + litedramcore_dfi_p0_rddata_en <= 1'd0; + litedramcore_dfi_p1_address <= 14'd0; + litedramcore_dfi_p1_bank <= 3'd0; + litedramcore_dfi_p1_cas_n <= 1'd1; + litedramcore_dfi_p1_cs_n <= 1'd1; + litedramcore_dfi_p1_ras_n <= 1'd1; + litedramcore_dfi_p1_we_n <= 1'd1; + litedramcore_dfi_p1_wrdata_en <= 1'd0; + litedramcore_dfi_p1_rddata_en <= 1'd0; + litedramcore_dfi_p2_address <= 14'd0; + litedramcore_dfi_p2_bank <= 3'd0; + litedramcore_dfi_p2_cas_n <= 1'd1; + litedramcore_dfi_p2_cs_n <= 1'd1; + litedramcore_dfi_p2_ras_n <= 1'd1; + litedramcore_dfi_p2_we_n <= 1'd1; + litedramcore_dfi_p2_wrdata_en <= 1'd0; + litedramcore_dfi_p2_rddata_en <= 1'd0; + litedramcore_dfi_p3_address <= 14'd0; + litedramcore_dfi_p3_bank <= 3'd0; + litedramcore_dfi_p3_cas_n <= 1'd1; + litedramcore_dfi_p3_cs_n <= 1'd1; + litedramcore_dfi_p3_ras_n <= 1'd1; + litedramcore_dfi_p3_we_n <= 1'd1; + litedramcore_dfi_p3_wrdata_en <= 1'd0; + litedramcore_dfi_p3_rddata_en <= 1'd0; + litedramcore_timer_count1 <= 10'd781; + litedramcore_postponer_req_o <= 1'd0; + litedramcore_postponer_count <= 1'd0; + litedramcore_sequencer_done1 <= 1'd0; + litedramcore_sequencer_counter <= 6'd0; + litedramcore_sequencer_count <= 1'd0; + litedramcore_zqcs_timer_count1 <= 27'd99999999; + litedramcore_zqcs_executer_done <= 1'd0; + litedramcore_zqcs_executer_counter <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine0_row <= 14'd0; + litedramcore_bankmachine0_row_opened <= 1'd0; + litedramcore_bankmachine0_twtpcon_ready <= 1'd0; + litedramcore_bankmachine0_twtpcon_count <= 3'd0; + litedramcore_bankmachine0_trccon_ready <= 1'd0; + litedramcore_bankmachine0_trccon_count <= 3'd0; + litedramcore_bankmachine0_trascon_ready <= 1'd0; + litedramcore_bankmachine0_trascon_count <= 3'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine1_row <= 14'd0; + litedramcore_bankmachine1_row_opened <= 1'd0; + litedramcore_bankmachine1_twtpcon_ready <= 1'd0; + litedramcore_bankmachine1_twtpcon_count <= 3'd0; + litedramcore_bankmachine1_trccon_ready <= 1'd0; + litedramcore_bankmachine1_trccon_count <= 3'd0; + litedramcore_bankmachine1_trascon_ready <= 1'd0; + litedramcore_bankmachine1_trascon_count <= 3'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine2_row <= 14'd0; + litedramcore_bankmachine2_row_opened <= 1'd0; + litedramcore_bankmachine2_twtpcon_ready <= 1'd0; + litedramcore_bankmachine2_twtpcon_count <= 3'd0; + litedramcore_bankmachine2_trccon_ready <= 1'd0; + litedramcore_bankmachine2_trccon_count <= 3'd0; + litedramcore_bankmachine2_trascon_ready <= 1'd0; + litedramcore_bankmachine2_trascon_count <= 3'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine3_row <= 14'd0; + litedramcore_bankmachine3_row_opened <= 1'd0; + litedramcore_bankmachine3_twtpcon_ready <= 1'd0; + litedramcore_bankmachine3_twtpcon_count <= 3'd0; + litedramcore_bankmachine3_trccon_ready <= 1'd0; + litedramcore_bankmachine3_trccon_count <= 3'd0; + litedramcore_bankmachine3_trascon_ready <= 1'd0; + litedramcore_bankmachine3_trascon_count <= 3'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine4_row <= 14'd0; + litedramcore_bankmachine4_row_opened <= 1'd0; + litedramcore_bankmachine4_twtpcon_ready <= 1'd0; + litedramcore_bankmachine4_twtpcon_count <= 3'd0; + litedramcore_bankmachine4_trccon_ready <= 1'd0; + litedramcore_bankmachine4_trccon_count <= 3'd0; + litedramcore_bankmachine4_trascon_ready <= 1'd0; + litedramcore_bankmachine4_trascon_count <= 3'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine5_row <= 14'd0; + litedramcore_bankmachine5_row_opened <= 1'd0; + litedramcore_bankmachine5_twtpcon_ready <= 1'd0; + litedramcore_bankmachine5_twtpcon_count <= 3'd0; + litedramcore_bankmachine5_trccon_ready <= 1'd0; + litedramcore_bankmachine5_trccon_count <= 3'd0; + litedramcore_bankmachine5_trascon_ready <= 1'd0; + litedramcore_bankmachine5_trascon_count <= 3'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine6_row <= 14'd0; + litedramcore_bankmachine6_row_opened <= 1'd0; + litedramcore_bankmachine6_twtpcon_ready <= 1'd0; + litedramcore_bankmachine6_twtpcon_count <= 3'd0; + litedramcore_bankmachine6_trccon_ready <= 1'd0; + litedramcore_bankmachine6_trccon_count <= 3'd0; + litedramcore_bankmachine6_trascon_ready <= 1'd0; + litedramcore_bankmachine6_trascon_count <= 3'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0; + litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0; + litedramcore_bankmachine7_row <= 14'd0; + litedramcore_bankmachine7_row_opened <= 1'd0; + litedramcore_bankmachine7_twtpcon_ready <= 1'd0; + litedramcore_bankmachine7_twtpcon_count <= 3'd0; + litedramcore_bankmachine7_trccon_ready <= 1'd0; + litedramcore_bankmachine7_trccon_count <= 3'd0; + litedramcore_bankmachine7_trascon_ready <= 1'd0; + litedramcore_bankmachine7_trascon_count <= 3'd0; + litedramcore_choose_cmd_grant <= 3'd0; + litedramcore_choose_req_grant <= 3'd0; + litedramcore_trrdcon_ready <= 1'd0; + litedramcore_trrdcon_count <= 1'd0; + litedramcore_tfawcon_ready <= 1'd1; + litedramcore_tfawcon_window <= 5'd0; + litedramcore_tccdcon_ready <= 1'd0; + litedramcore_tccdcon_count <= 1'd0; + litedramcore_twtrcon_ready <= 1'd0; + litedramcore_twtrcon_count <= 3'd0; + litedramcore_time0 <= 5'd0; + litedramcore_time1 <= 4'd0; + init_done_storage <= 1'd0; + init_done_re <= 1'd0; + init_error_storage <= 1'd0; + init_error_re <= 1'd0; + state <= 1'd0; + refresher_state <= 2'd0; + bankmachine0_state <= 4'd0; + bankmachine1_state <= 4'd0; + bankmachine2_state <= 4'd0; + bankmachine3_state <= 4'd0; + bankmachine4_state <= 4'd0; + bankmachine5_state <= 4'd0; + bankmachine6_state <= 4'd0; + bankmachine7_state <= 4'd0; + multiplexer_state <= 4'd0; + new_master_wdata_ready0 <= 1'd0; + new_master_wdata_ready1 <= 1'd0; + new_master_wdata_ready2 <= 1'd0; + new_master_rdata_valid0 <= 1'd0; + new_master_rdata_valid1 <= 1'd0; + new_master_rdata_valid2 <= 1'd0; + new_master_rdata_valid3 <= 1'd0; + new_master_rdata_valid4 <= 1'd0; + new_master_rdata_valid5 <= 1'd0; + new_master_rdata_valid6 <= 1'd0; + new_master_rdata_valid7 <= 1'd0; + new_master_rdata_valid8 <= 1'd0; + new_master_rdata_valid9 <= 1'd0; + end +end + +reg [127:0] mem[0:2097151]; +reg [20:0] memadr; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel0_write_port_we[0]) + mem[ddrphy_bankmodel0_write_port_adr][7:0] <= ddrphy_bankmodel0_write_port_dat_w[7:0]; + if (ddrphy_bankmodel0_write_port_we[1]) + mem[ddrphy_bankmodel0_write_port_adr][15:8] <= ddrphy_bankmodel0_write_port_dat_w[15:8]; + if (ddrphy_bankmodel0_write_port_we[2]) + mem[ddrphy_bankmodel0_write_port_adr][23:16] <= ddrphy_bankmodel0_write_port_dat_w[23:16]; + if (ddrphy_bankmodel0_write_port_we[3]) + mem[ddrphy_bankmodel0_write_port_adr][31:24] <= ddrphy_bankmodel0_write_port_dat_w[31:24]; + if (ddrphy_bankmodel0_write_port_we[4]) + mem[ddrphy_bankmodel0_write_port_adr][39:32] <= ddrphy_bankmodel0_write_port_dat_w[39:32]; + if (ddrphy_bankmodel0_write_port_we[5]) + mem[ddrphy_bankmodel0_write_port_adr][47:40] <= ddrphy_bankmodel0_write_port_dat_w[47:40]; + if (ddrphy_bankmodel0_write_port_we[6]) + mem[ddrphy_bankmodel0_write_port_adr][55:48] <= ddrphy_bankmodel0_write_port_dat_w[55:48]; + if (ddrphy_bankmodel0_write_port_we[7]) + mem[ddrphy_bankmodel0_write_port_adr][63:56] <= ddrphy_bankmodel0_write_port_dat_w[63:56]; + if (ddrphy_bankmodel0_write_port_we[8]) + mem[ddrphy_bankmodel0_write_port_adr][71:64] <= ddrphy_bankmodel0_write_port_dat_w[71:64]; + if (ddrphy_bankmodel0_write_port_we[9]) + mem[ddrphy_bankmodel0_write_port_adr][79:72] <= ddrphy_bankmodel0_write_port_dat_w[79:72]; + if (ddrphy_bankmodel0_write_port_we[10]) + mem[ddrphy_bankmodel0_write_port_adr][87:80] <= ddrphy_bankmodel0_write_port_dat_w[87:80]; + if (ddrphy_bankmodel0_write_port_we[11]) + mem[ddrphy_bankmodel0_write_port_adr][95:88] <= ddrphy_bankmodel0_write_port_dat_w[95:88]; + if (ddrphy_bankmodel0_write_port_we[12]) + mem[ddrphy_bankmodel0_write_port_adr][103:96] <= ddrphy_bankmodel0_write_port_dat_w[103:96]; + if (ddrphy_bankmodel0_write_port_we[13]) + mem[ddrphy_bankmodel0_write_port_adr][111:104] <= ddrphy_bankmodel0_write_port_dat_w[111:104]; + if (ddrphy_bankmodel0_write_port_we[14]) + mem[ddrphy_bankmodel0_write_port_adr][119:112] <= ddrphy_bankmodel0_write_port_dat_w[119:112]; + if (ddrphy_bankmodel0_write_port_we[15]) + mem[ddrphy_bankmodel0_write_port_adr][127:120] <= ddrphy_bankmodel0_write_port_dat_w[127:120]; + memadr <= ddrphy_bankmodel0_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel0_write_port_dat_r = mem[memadr]; +assign ddrphy_bankmodel0_read_port_dat_r = mem[ddrphy_bankmodel0_read_port_adr]; + +reg [127:0] mem_1[0:2097151]; +reg [20:0] memadr_1; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel1_write_port_we[0]) + mem_1[ddrphy_bankmodel1_write_port_adr][7:0] <= ddrphy_bankmodel1_write_port_dat_w[7:0]; + if (ddrphy_bankmodel1_write_port_we[1]) + mem_1[ddrphy_bankmodel1_write_port_adr][15:8] <= ddrphy_bankmodel1_write_port_dat_w[15:8]; + if (ddrphy_bankmodel1_write_port_we[2]) + mem_1[ddrphy_bankmodel1_write_port_adr][23:16] <= ddrphy_bankmodel1_write_port_dat_w[23:16]; + if (ddrphy_bankmodel1_write_port_we[3]) + mem_1[ddrphy_bankmodel1_write_port_adr][31:24] <= ddrphy_bankmodel1_write_port_dat_w[31:24]; + if (ddrphy_bankmodel1_write_port_we[4]) + mem_1[ddrphy_bankmodel1_write_port_adr][39:32] <= ddrphy_bankmodel1_write_port_dat_w[39:32]; + if (ddrphy_bankmodel1_write_port_we[5]) + mem_1[ddrphy_bankmodel1_write_port_adr][47:40] <= ddrphy_bankmodel1_write_port_dat_w[47:40]; + if (ddrphy_bankmodel1_write_port_we[6]) + mem_1[ddrphy_bankmodel1_write_port_adr][55:48] <= ddrphy_bankmodel1_write_port_dat_w[55:48]; + if (ddrphy_bankmodel1_write_port_we[7]) + mem_1[ddrphy_bankmodel1_write_port_adr][63:56] <= ddrphy_bankmodel1_write_port_dat_w[63:56]; + if (ddrphy_bankmodel1_write_port_we[8]) + mem_1[ddrphy_bankmodel1_write_port_adr][71:64] <= ddrphy_bankmodel1_write_port_dat_w[71:64]; + if (ddrphy_bankmodel1_write_port_we[9]) + mem_1[ddrphy_bankmodel1_write_port_adr][79:72] <= ddrphy_bankmodel1_write_port_dat_w[79:72]; + if (ddrphy_bankmodel1_write_port_we[10]) + mem_1[ddrphy_bankmodel1_write_port_adr][87:80] <= ddrphy_bankmodel1_write_port_dat_w[87:80]; + if (ddrphy_bankmodel1_write_port_we[11]) + mem_1[ddrphy_bankmodel1_write_port_adr][95:88] <= ddrphy_bankmodel1_write_port_dat_w[95:88]; + if (ddrphy_bankmodel1_write_port_we[12]) + mem_1[ddrphy_bankmodel1_write_port_adr][103:96] <= ddrphy_bankmodel1_write_port_dat_w[103:96]; + if (ddrphy_bankmodel1_write_port_we[13]) + mem_1[ddrphy_bankmodel1_write_port_adr][111:104] <= ddrphy_bankmodel1_write_port_dat_w[111:104]; + if (ddrphy_bankmodel1_write_port_we[14]) + mem_1[ddrphy_bankmodel1_write_port_adr][119:112] <= ddrphy_bankmodel1_write_port_dat_w[119:112]; + if (ddrphy_bankmodel1_write_port_we[15]) + mem_1[ddrphy_bankmodel1_write_port_adr][127:120] <= ddrphy_bankmodel1_write_port_dat_w[127:120]; + memadr_1 <= ddrphy_bankmodel1_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel1_write_port_dat_r = mem_1[memadr_1]; +assign ddrphy_bankmodel1_read_port_dat_r = mem_1[ddrphy_bankmodel1_read_port_adr]; + +reg [127:0] mem_2[0:2097151]; +reg [20:0] memadr_2; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel2_write_port_we[0]) + mem_2[ddrphy_bankmodel2_write_port_adr][7:0] <= ddrphy_bankmodel2_write_port_dat_w[7:0]; + if (ddrphy_bankmodel2_write_port_we[1]) + mem_2[ddrphy_bankmodel2_write_port_adr][15:8] <= ddrphy_bankmodel2_write_port_dat_w[15:8]; + if (ddrphy_bankmodel2_write_port_we[2]) + mem_2[ddrphy_bankmodel2_write_port_adr][23:16] <= ddrphy_bankmodel2_write_port_dat_w[23:16]; + if (ddrphy_bankmodel2_write_port_we[3]) + mem_2[ddrphy_bankmodel2_write_port_adr][31:24] <= ddrphy_bankmodel2_write_port_dat_w[31:24]; + if (ddrphy_bankmodel2_write_port_we[4]) + mem_2[ddrphy_bankmodel2_write_port_adr][39:32] <= ddrphy_bankmodel2_write_port_dat_w[39:32]; + if (ddrphy_bankmodel2_write_port_we[5]) + mem_2[ddrphy_bankmodel2_write_port_adr][47:40] <= ddrphy_bankmodel2_write_port_dat_w[47:40]; + if (ddrphy_bankmodel2_write_port_we[6]) + mem_2[ddrphy_bankmodel2_write_port_adr][55:48] <= ddrphy_bankmodel2_write_port_dat_w[55:48]; + if (ddrphy_bankmodel2_write_port_we[7]) + mem_2[ddrphy_bankmodel2_write_port_adr][63:56] <= ddrphy_bankmodel2_write_port_dat_w[63:56]; + if (ddrphy_bankmodel2_write_port_we[8]) + mem_2[ddrphy_bankmodel2_write_port_adr][71:64] <= ddrphy_bankmodel2_write_port_dat_w[71:64]; + if (ddrphy_bankmodel2_write_port_we[9]) + mem_2[ddrphy_bankmodel2_write_port_adr][79:72] <= ddrphy_bankmodel2_write_port_dat_w[79:72]; + if (ddrphy_bankmodel2_write_port_we[10]) + mem_2[ddrphy_bankmodel2_write_port_adr][87:80] <= ddrphy_bankmodel2_write_port_dat_w[87:80]; + if (ddrphy_bankmodel2_write_port_we[11]) + mem_2[ddrphy_bankmodel2_write_port_adr][95:88] <= ddrphy_bankmodel2_write_port_dat_w[95:88]; + if (ddrphy_bankmodel2_write_port_we[12]) + mem_2[ddrphy_bankmodel2_write_port_adr][103:96] <= ddrphy_bankmodel2_write_port_dat_w[103:96]; + if (ddrphy_bankmodel2_write_port_we[13]) + mem_2[ddrphy_bankmodel2_write_port_adr][111:104] <= ddrphy_bankmodel2_write_port_dat_w[111:104]; + if (ddrphy_bankmodel2_write_port_we[14]) + mem_2[ddrphy_bankmodel2_write_port_adr][119:112] <= ddrphy_bankmodel2_write_port_dat_w[119:112]; + if (ddrphy_bankmodel2_write_port_we[15]) + mem_2[ddrphy_bankmodel2_write_port_adr][127:120] <= ddrphy_bankmodel2_write_port_dat_w[127:120]; + memadr_2 <= ddrphy_bankmodel2_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel2_write_port_dat_r = mem_2[memadr_2]; +assign ddrphy_bankmodel2_read_port_dat_r = mem_2[ddrphy_bankmodel2_read_port_adr]; + +reg [127:0] mem_3[0:2097151]; +reg [20:0] memadr_3; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel3_write_port_we[0]) + mem_3[ddrphy_bankmodel3_write_port_adr][7:0] <= ddrphy_bankmodel3_write_port_dat_w[7:0]; + if (ddrphy_bankmodel3_write_port_we[1]) + mem_3[ddrphy_bankmodel3_write_port_adr][15:8] <= ddrphy_bankmodel3_write_port_dat_w[15:8]; + if (ddrphy_bankmodel3_write_port_we[2]) + mem_3[ddrphy_bankmodel3_write_port_adr][23:16] <= ddrphy_bankmodel3_write_port_dat_w[23:16]; + if (ddrphy_bankmodel3_write_port_we[3]) + mem_3[ddrphy_bankmodel3_write_port_adr][31:24] <= ddrphy_bankmodel3_write_port_dat_w[31:24]; + if (ddrphy_bankmodel3_write_port_we[4]) + mem_3[ddrphy_bankmodel3_write_port_adr][39:32] <= ddrphy_bankmodel3_write_port_dat_w[39:32]; + if (ddrphy_bankmodel3_write_port_we[5]) + mem_3[ddrphy_bankmodel3_write_port_adr][47:40] <= ddrphy_bankmodel3_write_port_dat_w[47:40]; + if (ddrphy_bankmodel3_write_port_we[6]) + mem_3[ddrphy_bankmodel3_write_port_adr][55:48] <= ddrphy_bankmodel3_write_port_dat_w[55:48]; + if (ddrphy_bankmodel3_write_port_we[7]) + mem_3[ddrphy_bankmodel3_write_port_adr][63:56] <= ddrphy_bankmodel3_write_port_dat_w[63:56]; + if (ddrphy_bankmodel3_write_port_we[8]) + mem_3[ddrphy_bankmodel3_write_port_adr][71:64] <= ddrphy_bankmodel3_write_port_dat_w[71:64]; + if (ddrphy_bankmodel3_write_port_we[9]) + mem_3[ddrphy_bankmodel3_write_port_adr][79:72] <= ddrphy_bankmodel3_write_port_dat_w[79:72]; + if (ddrphy_bankmodel3_write_port_we[10]) + mem_3[ddrphy_bankmodel3_write_port_adr][87:80] <= ddrphy_bankmodel3_write_port_dat_w[87:80]; + if (ddrphy_bankmodel3_write_port_we[11]) + mem_3[ddrphy_bankmodel3_write_port_adr][95:88] <= ddrphy_bankmodel3_write_port_dat_w[95:88]; + if (ddrphy_bankmodel3_write_port_we[12]) + mem_3[ddrphy_bankmodel3_write_port_adr][103:96] <= ddrphy_bankmodel3_write_port_dat_w[103:96]; + if (ddrphy_bankmodel3_write_port_we[13]) + mem_3[ddrphy_bankmodel3_write_port_adr][111:104] <= ddrphy_bankmodel3_write_port_dat_w[111:104]; + if (ddrphy_bankmodel3_write_port_we[14]) + mem_3[ddrphy_bankmodel3_write_port_adr][119:112] <= ddrphy_bankmodel3_write_port_dat_w[119:112]; + if (ddrphy_bankmodel3_write_port_we[15]) + mem_3[ddrphy_bankmodel3_write_port_adr][127:120] <= ddrphy_bankmodel3_write_port_dat_w[127:120]; + memadr_3 <= ddrphy_bankmodel3_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel3_write_port_dat_r = mem_3[memadr_3]; +assign ddrphy_bankmodel3_read_port_dat_r = mem_3[ddrphy_bankmodel3_read_port_adr]; + +reg [127:0] mem_4[0:2097151]; +reg [20:0] memadr_4; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel4_write_port_we[0]) + mem_4[ddrphy_bankmodel4_write_port_adr][7:0] <= ddrphy_bankmodel4_write_port_dat_w[7:0]; + if (ddrphy_bankmodel4_write_port_we[1]) + mem_4[ddrphy_bankmodel4_write_port_adr][15:8] <= ddrphy_bankmodel4_write_port_dat_w[15:8]; + if (ddrphy_bankmodel4_write_port_we[2]) + mem_4[ddrphy_bankmodel4_write_port_adr][23:16] <= ddrphy_bankmodel4_write_port_dat_w[23:16]; + if (ddrphy_bankmodel4_write_port_we[3]) + mem_4[ddrphy_bankmodel4_write_port_adr][31:24] <= ddrphy_bankmodel4_write_port_dat_w[31:24]; + if (ddrphy_bankmodel4_write_port_we[4]) + mem_4[ddrphy_bankmodel4_write_port_adr][39:32] <= ddrphy_bankmodel4_write_port_dat_w[39:32]; + if (ddrphy_bankmodel4_write_port_we[5]) + mem_4[ddrphy_bankmodel4_write_port_adr][47:40] <= ddrphy_bankmodel4_write_port_dat_w[47:40]; + if (ddrphy_bankmodel4_write_port_we[6]) + mem_4[ddrphy_bankmodel4_write_port_adr][55:48] <= ddrphy_bankmodel4_write_port_dat_w[55:48]; + if (ddrphy_bankmodel4_write_port_we[7]) + mem_4[ddrphy_bankmodel4_write_port_adr][63:56] <= ddrphy_bankmodel4_write_port_dat_w[63:56]; + if (ddrphy_bankmodel4_write_port_we[8]) + mem_4[ddrphy_bankmodel4_write_port_adr][71:64] <= ddrphy_bankmodel4_write_port_dat_w[71:64]; + if (ddrphy_bankmodel4_write_port_we[9]) + mem_4[ddrphy_bankmodel4_write_port_adr][79:72] <= ddrphy_bankmodel4_write_port_dat_w[79:72]; + if (ddrphy_bankmodel4_write_port_we[10]) + mem_4[ddrphy_bankmodel4_write_port_adr][87:80] <= ddrphy_bankmodel4_write_port_dat_w[87:80]; + if (ddrphy_bankmodel4_write_port_we[11]) + mem_4[ddrphy_bankmodel4_write_port_adr][95:88] <= ddrphy_bankmodel4_write_port_dat_w[95:88]; + if (ddrphy_bankmodel4_write_port_we[12]) + mem_4[ddrphy_bankmodel4_write_port_adr][103:96] <= ddrphy_bankmodel4_write_port_dat_w[103:96]; + if (ddrphy_bankmodel4_write_port_we[13]) + mem_4[ddrphy_bankmodel4_write_port_adr][111:104] <= ddrphy_bankmodel4_write_port_dat_w[111:104]; + if (ddrphy_bankmodel4_write_port_we[14]) + mem_4[ddrphy_bankmodel4_write_port_adr][119:112] <= ddrphy_bankmodel4_write_port_dat_w[119:112]; + if (ddrphy_bankmodel4_write_port_we[15]) + mem_4[ddrphy_bankmodel4_write_port_adr][127:120] <= ddrphy_bankmodel4_write_port_dat_w[127:120]; + memadr_4 <= ddrphy_bankmodel4_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel4_write_port_dat_r = mem_4[memadr_4]; +assign ddrphy_bankmodel4_read_port_dat_r = mem_4[ddrphy_bankmodel4_read_port_adr]; + +reg [127:0] mem_5[0:2097151]; +reg [20:0] memadr_5; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel5_write_port_we[0]) + mem_5[ddrphy_bankmodel5_write_port_adr][7:0] <= ddrphy_bankmodel5_write_port_dat_w[7:0]; + if (ddrphy_bankmodel5_write_port_we[1]) + mem_5[ddrphy_bankmodel5_write_port_adr][15:8] <= ddrphy_bankmodel5_write_port_dat_w[15:8]; + if (ddrphy_bankmodel5_write_port_we[2]) + mem_5[ddrphy_bankmodel5_write_port_adr][23:16] <= ddrphy_bankmodel5_write_port_dat_w[23:16]; + if (ddrphy_bankmodel5_write_port_we[3]) + mem_5[ddrphy_bankmodel5_write_port_adr][31:24] <= ddrphy_bankmodel5_write_port_dat_w[31:24]; + if (ddrphy_bankmodel5_write_port_we[4]) + mem_5[ddrphy_bankmodel5_write_port_adr][39:32] <= ddrphy_bankmodel5_write_port_dat_w[39:32]; + if (ddrphy_bankmodel5_write_port_we[5]) + mem_5[ddrphy_bankmodel5_write_port_adr][47:40] <= ddrphy_bankmodel5_write_port_dat_w[47:40]; + if (ddrphy_bankmodel5_write_port_we[6]) + mem_5[ddrphy_bankmodel5_write_port_adr][55:48] <= ddrphy_bankmodel5_write_port_dat_w[55:48]; + if (ddrphy_bankmodel5_write_port_we[7]) + mem_5[ddrphy_bankmodel5_write_port_adr][63:56] <= ddrphy_bankmodel5_write_port_dat_w[63:56]; + if (ddrphy_bankmodel5_write_port_we[8]) + mem_5[ddrphy_bankmodel5_write_port_adr][71:64] <= ddrphy_bankmodel5_write_port_dat_w[71:64]; + if (ddrphy_bankmodel5_write_port_we[9]) + mem_5[ddrphy_bankmodel5_write_port_adr][79:72] <= ddrphy_bankmodel5_write_port_dat_w[79:72]; + if (ddrphy_bankmodel5_write_port_we[10]) + mem_5[ddrphy_bankmodel5_write_port_adr][87:80] <= ddrphy_bankmodel5_write_port_dat_w[87:80]; + if (ddrphy_bankmodel5_write_port_we[11]) + mem_5[ddrphy_bankmodel5_write_port_adr][95:88] <= ddrphy_bankmodel5_write_port_dat_w[95:88]; + if (ddrphy_bankmodel5_write_port_we[12]) + mem_5[ddrphy_bankmodel5_write_port_adr][103:96] <= ddrphy_bankmodel5_write_port_dat_w[103:96]; + if (ddrphy_bankmodel5_write_port_we[13]) + mem_5[ddrphy_bankmodel5_write_port_adr][111:104] <= ddrphy_bankmodel5_write_port_dat_w[111:104]; + if (ddrphy_bankmodel5_write_port_we[14]) + mem_5[ddrphy_bankmodel5_write_port_adr][119:112] <= ddrphy_bankmodel5_write_port_dat_w[119:112]; + if (ddrphy_bankmodel5_write_port_we[15]) + mem_5[ddrphy_bankmodel5_write_port_adr][127:120] <= ddrphy_bankmodel5_write_port_dat_w[127:120]; + memadr_5 <= ddrphy_bankmodel5_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel5_write_port_dat_r = mem_5[memadr_5]; +assign ddrphy_bankmodel5_read_port_dat_r = mem_5[ddrphy_bankmodel5_read_port_adr]; + +reg [127:0] mem_6[0:2097151]; +reg [20:0] memadr_6; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel6_write_port_we[0]) + mem_6[ddrphy_bankmodel6_write_port_adr][7:0] <= ddrphy_bankmodel6_write_port_dat_w[7:0]; + if (ddrphy_bankmodel6_write_port_we[1]) + mem_6[ddrphy_bankmodel6_write_port_adr][15:8] <= ddrphy_bankmodel6_write_port_dat_w[15:8]; + if (ddrphy_bankmodel6_write_port_we[2]) + mem_6[ddrphy_bankmodel6_write_port_adr][23:16] <= ddrphy_bankmodel6_write_port_dat_w[23:16]; + if (ddrphy_bankmodel6_write_port_we[3]) + mem_6[ddrphy_bankmodel6_write_port_adr][31:24] <= ddrphy_bankmodel6_write_port_dat_w[31:24]; + if (ddrphy_bankmodel6_write_port_we[4]) + mem_6[ddrphy_bankmodel6_write_port_adr][39:32] <= ddrphy_bankmodel6_write_port_dat_w[39:32]; + if (ddrphy_bankmodel6_write_port_we[5]) + mem_6[ddrphy_bankmodel6_write_port_adr][47:40] <= ddrphy_bankmodel6_write_port_dat_w[47:40]; + if (ddrphy_bankmodel6_write_port_we[6]) + mem_6[ddrphy_bankmodel6_write_port_adr][55:48] <= ddrphy_bankmodel6_write_port_dat_w[55:48]; + if (ddrphy_bankmodel6_write_port_we[7]) + mem_6[ddrphy_bankmodel6_write_port_adr][63:56] <= ddrphy_bankmodel6_write_port_dat_w[63:56]; + if (ddrphy_bankmodel6_write_port_we[8]) + mem_6[ddrphy_bankmodel6_write_port_adr][71:64] <= ddrphy_bankmodel6_write_port_dat_w[71:64]; + if (ddrphy_bankmodel6_write_port_we[9]) + mem_6[ddrphy_bankmodel6_write_port_adr][79:72] <= ddrphy_bankmodel6_write_port_dat_w[79:72]; + if (ddrphy_bankmodel6_write_port_we[10]) + mem_6[ddrphy_bankmodel6_write_port_adr][87:80] <= ddrphy_bankmodel6_write_port_dat_w[87:80]; + if (ddrphy_bankmodel6_write_port_we[11]) + mem_6[ddrphy_bankmodel6_write_port_adr][95:88] <= ddrphy_bankmodel6_write_port_dat_w[95:88]; + if (ddrphy_bankmodel6_write_port_we[12]) + mem_6[ddrphy_bankmodel6_write_port_adr][103:96] <= ddrphy_bankmodel6_write_port_dat_w[103:96]; + if (ddrphy_bankmodel6_write_port_we[13]) + mem_6[ddrphy_bankmodel6_write_port_adr][111:104] <= ddrphy_bankmodel6_write_port_dat_w[111:104]; + if (ddrphy_bankmodel6_write_port_we[14]) + mem_6[ddrphy_bankmodel6_write_port_adr][119:112] <= ddrphy_bankmodel6_write_port_dat_w[119:112]; + if (ddrphy_bankmodel6_write_port_we[15]) + mem_6[ddrphy_bankmodel6_write_port_adr][127:120] <= ddrphy_bankmodel6_write_port_dat_w[127:120]; + memadr_6 <= ddrphy_bankmodel6_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel6_write_port_dat_r = mem_6[memadr_6]; +assign ddrphy_bankmodel6_read_port_dat_r = mem_6[ddrphy_bankmodel6_read_port_adr]; + +reg [127:0] mem_7[0:2097151]; +reg [20:0] memadr_7; +always @(posedge sys_clk) begin + if (ddrphy_bankmodel7_write_port_we[0]) + mem_7[ddrphy_bankmodel7_write_port_adr][7:0] <= ddrphy_bankmodel7_write_port_dat_w[7:0]; + if (ddrphy_bankmodel7_write_port_we[1]) + mem_7[ddrphy_bankmodel7_write_port_adr][15:8] <= ddrphy_bankmodel7_write_port_dat_w[15:8]; + if (ddrphy_bankmodel7_write_port_we[2]) + mem_7[ddrphy_bankmodel7_write_port_adr][23:16] <= ddrphy_bankmodel7_write_port_dat_w[23:16]; + if (ddrphy_bankmodel7_write_port_we[3]) + mem_7[ddrphy_bankmodel7_write_port_adr][31:24] <= ddrphy_bankmodel7_write_port_dat_w[31:24]; + if (ddrphy_bankmodel7_write_port_we[4]) + mem_7[ddrphy_bankmodel7_write_port_adr][39:32] <= ddrphy_bankmodel7_write_port_dat_w[39:32]; + if (ddrphy_bankmodel7_write_port_we[5]) + mem_7[ddrphy_bankmodel7_write_port_adr][47:40] <= ddrphy_bankmodel7_write_port_dat_w[47:40]; + if (ddrphy_bankmodel7_write_port_we[6]) + mem_7[ddrphy_bankmodel7_write_port_adr][55:48] <= ddrphy_bankmodel7_write_port_dat_w[55:48]; + if (ddrphy_bankmodel7_write_port_we[7]) + mem_7[ddrphy_bankmodel7_write_port_adr][63:56] <= ddrphy_bankmodel7_write_port_dat_w[63:56]; + if (ddrphy_bankmodel7_write_port_we[8]) + mem_7[ddrphy_bankmodel7_write_port_adr][71:64] <= ddrphy_bankmodel7_write_port_dat_w[71:64]; + if (ddrphy_bankmodel7_write_port_we[9]) + mem_7[ddrphy_bankmodel7_write_port_adr][79:72] <= ddrphy_bankmodel7_write_port_dat_w[79:72]; + if (ddrphy_bankmodel7_write_port_we[10]) + mem_7[ddrphy_bankmodel7_write_port_adr][87:80] <= ddrphy_bankmodel7_write_port_dat_w[87:80]; + if (ddrphy_bankmodel7_write_port_we[11]) + mem_7[ddrphy_bankmodel7_write_port_adr][95:88] <= ddrphy_bankmodel7_write_port_dat_w[95:88]; + if (ddrphy_bankmodel7_write_port_we[12]) + mem_7[ddrphy_bankmodel7_write_port_adr][103:96] <= ddrphy_bankmodel7_write_port_dat_w[103:96]; + if (ddrphy_bankmodel7_write_port_we[13]) + mem_7[ddrphy_bankmodel7_write_port_adr][111:104] <= ddrphy_bankmodel7_write_port_dat_w[111:104]; + if (ddrphy_bankmodel7_write_port_we[14]) + mem_7[ddrphy_bankmodel7_write_port_adr][119:112] <= ddrphy_bankmodel7_write_port_dat_w[119:112]; + if (ddrphy_bankmodel7_write_port_we[15]) + mem_7[ddrphy_bankmodel7_write_port_adr][127:120] <= ddrphy_bankmodel7_write_port_dat_w[127:120]; + memadr_7 <= ddrphy_bankmodel7_write_port_adr; +end + +always @(posedge sys_clk) begin +end + +assign ddrphy_bankmodel7_write_port_dat_r = mem_7[memadr_7]; +assign ddrphy_bankmodel7_read_port_dat_r = mem_7[ddrphy_bankmodel7_read_port_adr]; + +reg [23:0] storage[0:15]; +reg [23:0] memdat; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; +assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_1[0:15]; +reg [23:0] memdat_1; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; +assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_2[0:15]; +reg [23:0] memdat_2; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; +assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_3[0:15]; +reg [23:0] memdat_3; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; +assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_4[0:15]; +reg [23:0] memdat_4; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4; +assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_5[0:15]; +reg [23:0] memdat_5; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_6[0:15]; +reg [23:0] memdat_6; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_7[0:15]; +reg [23:0] memdat_7; +always @(posedge sys_clk) begin + if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +endmodule diff --git a/microwatt.core b/microwatt.core index 9cc51ee..fb26f63 100644 --- a/microwatt.core +++ b/microwatt.core @@ -48,6 +48,7 @@ filesets: - soc.vhdl - xics.vhdl - syscon.vhdl + - sync_fifo.vhdl file_type : vhdlSource-2008 fpga: @@ -130,6 +131,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_nexys_video] tools: vivado: {part : xc7a200tsbg484-1} @@ -156,6 +158,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_arty] tools: vivado: {part : xc7a35ticsg324-1L} @@ -182,6 +185,7 @@ targets: - ram_init_file - use_litedram=true - disable_flatten_core + - no_bram generate: [dram_arty] tools: vivado: {part : xc7a100ticsg324-1L} @@ -219,7 +223,7 @@ generate: parameters: memory_size: datatype : int - description : On-chip memory size (bytes) + description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload paramtype : generic default : 16384 @@ -256,3 +260,9 @@ parameters: description : Use liteDRAM paramtype : generic default : false + + no_bram: + datatype : bool + description : No internal block RAM (only DRAM and init code carrying payload) + paramtype : generic + default : false diff --git a/soc.vhdl b/soc.vhdl index 7aef68a..62d6ac4 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -26,14 +26,15 @@ use work.wishbone_types.all; entity soc is generic ( - MEMORY_SIZE : positive; - RAM_INIT_FILE : string; - RESET_LOW : boolean; - CLK_FREQ : positive; - SIM : boolean; + MEMORY_SIZE : natural; + RAM_INIT_FILE : string; + RESET_LOW : boolean; + CLK_FREQ : positive; + SIM : boolean; DISABLE_FLATTEN_CORE : boolean := false; - HAS_DRAM : boolean := false; - DRAM_SIZE : integer := 0 + HAS_DRAM : boolean := false; + DRAM_SIZE : integer := 0; + DRAM_INIT_SIZE : integer := 0 ); port( rst : in std_ulogic; @@ -105,7 +106,6 @@ architecture behaviour of soc is -- Main memory signals: signal wb_bram_in : wishbone_master_out; signal wb_bram_out : wishbone_slave_out; - constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE)))); -- DMI debug bus signals signal dmi_addr : std_ulogic_vector(7 downto 0); @@ -466,6 +466,7 @@ begin HAS_DRAM => HAS_DRAM, BRAM_SIZE => MEMORY_SIZE, DRAM_SIZE => DRAM_SIZE, + DRAM_INIT_SIZE => DRAM_INIT_SIZE, CLK_FREQ => CLK_FREQ ) port map( @@ -516,17 +517,25 @@ begin ); -- BRAM Memory slave - bram0: entity work.wishbone_bram_wrapper - generic map( - MEMORY_SIZE => MEMORY_SIZE, - RAM_INIT_FILE => RAM_INIT_FILE - ) - port map( - clk => system_clk, - rst => rst_bram, - wishbone_in => wb_bram_in, - wishbone_out => wb_bram_out - ); + bram: if MEMORY_SIZE /= 0 generate + bram0: entity work.wishbone_bram_wrapper + generic map( + MEMORY_SIZE => MEMORY_SIZE, + RAM_INIT_FILE => RAM_INIT_FILE + ) + port map( + clk => system_clk, + rst => rst_bram, + wishbone_in => wb_bram_in, + wishbone_out => wb_bram_out + ); + end generate; + + no_bram: if MEMORY_SIZE = 0 generate + wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb; + wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF"; + wb_bram_out.stall <= wb_bram_in.cyc and not wb_bram_out.ack; + end generate; -- DMI(debug bus) <-> JTAG bridge dtm: entity work.dmi_dtm diff --git a/sync_fifo.vhdl b/sync_fifo.vhdl new file mode 100644 index 0000000..79a4deb --- /dev/null +++ b/sync_fifo.vhdl @@ -0,0 +1,163 @@ +-- Synchronous FIFO with a protocol similar to AXI +-- +-- The outputs are generated combinationally from the inputs +-- in order to allow for back-to-back transfers with the type +-- of flow control used by busses lite AXI, pipelined WB or +-- LiteDRAM native port when the FIFO is full. +-- +-- That means that care needs to be taken by the user not to +-- generate the inputs combinationally from the outputs otherwise +-- it would create a logic loop. +-- +-- If breaking that loop is required, a stash buffer could be +-- added to break the flow control "loop" between the read and +-- the write port. +-- +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.utils.all; + +entity sync_fifo is + generic( + -- Fifo depth in entries + DEPTH : natural := 64; + + -- Fifo width in bits + WIDTH : natural := 32; + + -- When INIT_ZERO is set, the memory is pre-initialized to 0's + INIT_ZERO : boolean := false + ); + port( + -- Control lines: + clk : in std_ulogic; + reset : in std_ulogic; + + -- Write port + wr_ready : out std_ulogic; + wr_valid : in std_ulogic; + wr_data : in std_ulogic_vector(WIDTH - 1 downto 0); + + -- Read port + rd_ready : in std_ulogic; + rd_valid : out std_ulogic; + rd_data : out std_ulogic_vector(WIDTH - 1 downto 0) + ); +end entity sync_fifo; + +architecture behaviour of sync_fifo is + + subtype data_t is std_ulogic_vector(WIDTH - 1 downto 0); + type memory_t is array(0 to DEPTH - 1) of data_t; + + function init_mem return memory_t is + variable m : memory_t; + begin + if INIT_ZERO then + for i in 0 to DEPTH - 1 loop + m(i) := (others => '0'); + end loop; + end if; + return m; + end function; + + signal memory : memory_t := init_mem; + + subtype index_t is integer range 0 to DEPTH - 1; + signal rd_idx : index_t; + signal rd_next : index_t; + signal wr_idx : index_t; + signal wr_next : index_t; + + function next_index(idx : index_t) return index_t is + variable r : index_t; + begin + if ispow2(DEPTH) then + r := (idx + 1) mod DEPTH; + else + r := idx + 1; + if r = DEPTH then + r := 0; + end if; + end if; + return r; + end function; + + type op_t is (OP_POP, OP_PUSH); + signal op_prev : op_t := OP_POP; + signal op_next : op_t; + + signal full, empty : std_ulogic; + signal push, pop : std_ulogic; +begin + + -- Current state at last clock edge + empty <= '1' when rd_idx = wr_idx and op_prev = OP_POP else '0'; + full <= '1' when rd_idx = wr_idx and op_prev = OP_PUSH else '0'; + + -- We can accept new data if we aren't full or we are but + -- the read port is going to accept data this cycle + wr_ready <= rd_ready or not full; + + -- We can provide data if we aren't empty or we are but + -- the write port is going to provide data this cycle + rd_valid <= wr_valid or not empty; + + -- Internal control signals + push <= wr_ready and wr_valid; + pop <= rd_ready and rd_valid; + + -- Next state + rd_next <= next_index(rd_idx) when pop = '1' else rd_idx; + wr_next <= next_index(wr_idx) when push = '1' else wr_idx; + with push & pop select op_next <= + OP_PUSH when "10", + OP_POP when "01", + op_prev when others; + + -- Read port output + rd_data <= memory(rd_idx) when empty = '0' else wr_data; + + -- Read counter + reader: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + rd_idx <= 0; + else + rd_idx <= rd_next; + end if; + end if; + end process; + + -- Write counter and memory write + producer: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + wr_idx <= 0; + else + wr_idx <= wr_next; + + if push = '1' then + memory(wr_idx) <= wr_data; + end if; + end if; + end if; + end process; + + -- Previous op latch used for generating empty/full + op: process(clk) + begin + if rising_edge(clk) then + if reset = '1' then + op_prev <= OP_POP; + else + op_prev <= op_next; + end if; + end if; + end process; + +end architecture behaviour; diff --git a/syscon.vhdl b/syscon.vhdl index a9dd1cc..79d9531 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -8,12 +8,13 @@ use work.wishbone_types.all; entity syscon is generic ( - SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001"; - CLK_FREQ : integer; - HAS_UART : boolean; - HAS_DRAM : boolean; - BRAM_SIZE : integer; - DRAM_SIZE : integer + SIG_VALUE : std_ulogic_vector(63 downto 0) := x"f00daa5500010001"; + CLK_FREQ : integer; + HAS_UART : boolean; + HAS_DRAM : boolean; + BRAM_SIZE : integer; + DRAM_SIZE : integer; + DRAM_INIT_SIZE : integer ); port ( clk : in std_ulogic; @@ -36,12 +37,13 @@ architecture behaviour of syscon is constant SYS_REG_BITS : positive := 3; -- Register addresses (matches wishbone addr downto 3, ie, 8 bytes per reg) - constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000"; - constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001"; - constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010"; - constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011"; - constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100"; - constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101"; + constant SYS_REG_SIG : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000"; + constant SYS_REG_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001"; + constant SYS_REG_BRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "010"; + constant SYS_REG_DRAMINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "011"; + constant SYS_REG_CLKINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "100"; + constant SYS_REG_CTRL : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "101"; + constant SYS_REG_DRAMINITINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "110"; -- Muxed reg read signal signal reg_out : std_ulogic_vector(63 downto 0); @@ -49,6 +51,7 @@ architecture behaviour of syscon is -- INFO register bits constant SYS_REG_INFO_HAS_UART : integer := 0; constant SYS_REG_INFO_HAS_DRAM : integer := 1; + constant SYS_REG_INFO_HAS_BRAM : integer := 2; -- BRAMINFO contains the BRAM size in the bottom 52 bits -- DRAMINFO contains the DRAM size if any in the bottom 52 bits @@ -69,14 +72,16 @@ architecture behaviour of syscon is signal reg_info : std_ulogic_vector(63 downto 0); signal reg_braminfo : std_ulogic_vector(63 downto 0); signal reg_draminfo : std_ulogic_vector(63 downto 0); + signal reg_dramiinfo : std_ulogic_vector(63 downto 0); signal reg_clkinfo : std_ulogic_vector(63 downto 0); signal info_has_dram : std_ulogic; + signal info_has_bram : std_ulogic; signal info_has_uart : std_ulogic; signal info_clk : std_ulogic_vector(39 downto 0); begin -- Generated output signals - dram_at_0 <= reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); + dram_at_0 <= '1' when BRAM_SIZE = 0 else reg_ctrl(SYS_REG_CTRL_DRAM_AT_0); soc_reset <= reg_ctrl(SYS_REG_CTRL_SOC_RESET); core_reset <= reg_ctrl(SYS_REG_CTRL_CORE_RESET); @@ -87,13 +92,17 @@ begin -- Info register is hard wired info_has_uart <= '1' when HAS_UART else '0'; info_has_dram <= '1' when HAS_DRAM else '0'; + info_has_bram <= '1' when BRAM_SIZE /= 0 else '0'; info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); reg_info <= (0 => info_has_uart, 1 => info_has_dram, + 2 => info_has_bram, others => '0'); reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM else (others => '0'); + reg_dramiinfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_INIT_SIZE, 52)) when HAS_DRAM + else (others => '0'); reg_clkinfo <= (39 downto 0 => info_clk, others => '0'); @@ -107,6 +116,7 @@ begin reg_info when SYS_REG_INFO, reg_braminfo when SYS_REG_BRAMINFO, reg_draminfo when SYS_REG_DRAMINFO, + reg_dramiinfo when SYS_REG_DRAMINITINFO, reg_clkinfo when SYS_REG_CLKINFO, reg_ctrl_out when SYS_REG_CTRL, (others => '0') when others; @@ -136,6 +146,11 @@ begin if reg_ctrl(SYS_REG_CTRL_CORE_RESET) = '1' then reg_ctrl(SYS_REG_CTRL_CORE_RESET) <= '0'; end if; + + -- If BRAM doesn't exist, force DRAM at 0 + if BRAM_SIZE = 0 then + reg_ctrl(SYS_REG_CTRL_DRAM_AT_0) <= '1'; + end if; end if; end if; end process; diff --git a/utils.vhdl b/utils.vhdl index 4ccc3b5..14a6838 100644 --- a/utils.vhdl +++ b/utils.vhdl @@ -7,7 +7,7 @@ package utils is function log2(i : natural) return integer; function log2ceil(i : natural) return integer; function ispow2(i : integer) return boolean; - + function round_up(i : integer; s : integer) return integer; end utils; package body utils is @@ -43,5 +43,9 @@ package body utils is end if; end function; + function round_up(i : integer; s : integer) return integer is + begin + return ((i + (s - 1)) / s) * s; + end function; end utils;