From 965b1cbcfef197c03f82f8f83d3bbe0207983e16 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Fri, 5 Apr 2024 19:59:41 +1100 Subject: [PATCH] liteeth: Regenerate from current upstream litex Some signals have changed names: "eth_" has been dropped from the names of the MII/GMII/RGMII signals. Signed-off-by: Paul Mackerras --- fpga/top-arty.vhdl | 48 +- fpga/top-nexys-video.vhdl | 40 +- fpga/top-wukong-v2.vhdl | 56 +- liteeth/generated/arty/liteeth_core.v | 6959 ++++++++------- liteeth/generated/nexys-video/liteeth_core.v | 7424 +++++++++------- liteeth/generated/wukong-v2/liteeth_core.v | 8075 ++++++++++-------- 6 files changed, 12419 insertions(+), 10183 deletions(-) diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index dc5a0fe..7e3269a 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -484,18 +484,18 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - mii_eth_clocks_tx : in std_ulogic; - mii_eth_clocks_rx : in std_ulogic; - mii_eth_rst_n : out std_ulogic; - mii_eth_mdio : in std_ulogic; - mii_eth_mdc : out std_ulogic; - mii_eth_rx_dv : in std_ulogic; - mii_eth_rx_er : in std_ulogic; - mii_eth_rx_data : in std_ulogic_vector(3 downto 0); - mii_eth_tx_en : out std_ulogic; - mii_eth_tx_data : out std_ulogic_vector(3 downto 0); - mii_eth_col : in std_ulogic; - mii_eth_crs : in std_ulogic; + mii_clocks_tx : in std_ulogic; + mii_clocks_rx : in std_ulogic; + mii_rst_n : out std_ulogic; + mii_mdio : in std_ulogic; + mii_mdc : out std_ulogic; + mii_rx_dv : in std_ulogic; + mii_rx_er : in std_ulogic; + mii_rx_data : in std_ulogic_vector(3 downto 0); + mii_tx_en : out std_ulogic; + mii_tx_data : out std_ulogic_vector(3 downto 0); + mii_col : in std_ulogic; + mii_crs : in std_ulogic; wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -569,18 +569,18 @@ begin port map( sys_clock => system_clk, sys_reset => periph_rst, - mii_eth_clocks_tx => eth_clocks_tx, - mii_eth_clocks_rx => eth_clocks_rx, - mii_eth_rst_n => eth_rst_n, - mii_eth_mdio => eth_mdio, - mii_eth_mdc => eth_mdc, - mii_eth_rx_dv => eth_rx_dv, - mii_eth_rx_er => eth_rx_er, - mii_eth_rx_data => eth_rx_data, - mii_eth_tx_en => eth_tx_en, - mii_eth_tx_data => eth_tx_data, - mii_eth_col => eth_col, - mii_eth_crs => eth_crs, + mii_clocks_tx => eth_clocks_tx, + mii_clocks_rx => eth_clocks_rx, + mii_rst_n => eth_rst_n, + mii_mdio => eth_mdio, + mii_mdc => eth_mdc, + mii_rx_dv => eth_rx_dv, + mii_rx_er => eth_rx_er, + mii_rx_data => eth_rx_data, + mii_tx_en => eth_tx_en, + mii_tx_data => eth_tx_data, + mii_col => eth_col, + mii_crs => eth_crs, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index f18f80e..156fc97 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -384,16 +384,16 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - rgmii_eth_clocks_tx : out std_ulogic; - rgmii_eth_clocks_rx : in std_ulogic; - rgmii_eth_rst_n : out std_ulogic; - rgmii_eth_int_n : in std_ulogic; - rgmii_eth_mdio : inout std_ulogic; - rgmii_eth_mdc : out std_ulogic; - rgmii_eth_rx_ctl : in std_ulogic; - rgmii_eth_rx_data : in std_ulogic_vector(3 downto 0); - rgmii_eth_tx_ctl : out std_ulogic; - rgmii_eth_tx_data : out std_ulogic_vector(3 downto 0); + rgmii_clocks_tx : out std_ulogic; + rgmii_clocks_rx : in std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -417,16 +417,16 @@ begin port map( sys_clock => system_clk, sys_reset => soc_rst, - rgmii_eth_clocks_tx => eth_clocks_tx, - rgmii_eth_clocks_rx => eth_clocks_rx, - rgmii_eth_rst_n => eth_rst_n, - rgmii_eth_int_n => eth_int_n, - rgmii_eth_mdio => eth_mdio, - rgmii_eth_mdc => eth_mdc, - rgmii_eth_rx_ctl => eth_rx_ctl, - rgmii_eth_rx_data => eth_rx_data, - rgmii_eth_tx_ctl => eth_tx_ctl, - rgmii_eth_tx_data => eth_tx_data, + rgmii_clocks_tx => eth_clocks_tx, + rgmii_clocks_rx => eth_clocks_rx, + rgmii_rst_n => eth_rst_n, + rgmii_int_n => eth_int_n, + rgmii_mdio => eth_mdio, + rgmii_mdc => eth_mdc, + rgmii_rx_ctl => eth_rx_ctl, + rgmii_rx_data => eth_rx_data, + rgmii_tx_ctl => eth_tx_ctl, + rgmii_tx_data => eth_tx_data, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/fpga/top-wukong-v2.vhdl b/fpga/top-wukong-v2.vhdl index 2b6d4e1..b6c7262 100644 --- a/fpga/top-wukong-v2.vhdl +++ b/fpga/top-wukong-v2.vhdl @@ -380,20 +380,20 @@ begin component liteeth_core port ( sys_clock : in std_ulogic; sys_reset : in std_ulogic; - gmii_eth_clocks_tx : in std_ulogic; - gmii_eth_clocks_gtx : out std_ulogic; - gmii_eth_clocks_rx : in std_ulogic; - gmii_eth_rst_n : out std_ulogic; - gmii_eth_mdio : inout std_ulogic; - gmii_eth_mdc : out std_ulogic; - gmii_eth_rx_dv : in std_ulogic; - gmii_eth_rx_er : in std_ulogic; - gmii_eth_rx_data : in std_ulogic_vector(7 downto 0); - gmii_eth_tx_en : out std_ulogic; - gmii_eth_tx_er : out std_ulogic; - gmii_eth_tx_data : out std_ulogic_vector(7 downto 0); - gmii_eth_col : in std_ulogic; - gmii_eth_crs : in std_ulogic; + gmii_clocks_tx : in std_ulogic; + gmii_clocks_gtx : out std_ulogic; + gmii_clocks_rx : in std_ulogic; + gmii_rst_n : out std_ulogic; + gmii_mdio : inout std_ulogic; + gmii_mdc : out std_ulogic; + gmii_rx_dv : in std_ulogic; + gmii_rx_er : in std_ulogic; + gmii_rx_data : in std_ulogic_vector(7 downto 0); + gmii_tx_en : out std_ulogic; + gmii_tx_er : out std_ulogic; + gmii_tx_data : out std_ulogic_vector(7 downto 0); + gmii_col : in std_ulogic; + gmii_crs : in std_ulogic; wishbone_adr : in std_ulogic_vector(29 downto 0); wishbone_dat_w : in std_ulogic_vector(31 downto 0); wishbone_dat_r : out std_ulogic_vector(31 downto 0); @@ -420,20 +420,20 @@ begin port map( sys_clock => system_clk, sys_reset => soc_rst, - gmii_eth_clocks_tx => eth_clocks_tx, - gmii_eth_clocks_gtx => eth_clocks_gtx, - gmii_eth_clocks_rx => eth_clocks_rx, - gmii_eth_rst_n => eth_rst_n, - gmii_eth_mdio => eth_mdio, - gmii_eth_mdc => eth_mdc, - gmii_eth_rx_dv => eth_rx_dv, - gmii_eth_rx_er => eth_rx_er, - gmii_eth_rx_data => eth_rx_data, - gmii_eth_tx_en => eth_tx_en, - gmii_eth_tx_er => eth_tx_er, - gmii_eth_tx_data => eth_tx_data, - gmii_eth_col => eth_col, - gmii_eth_crs => eth_crs, + gmii_clocks_tx => eth_clocks_tx, + gmii_clocks_gtx => eth_clocks_gtx, + gmii_clocks_rx => eth_clocks_rx, + gmii_rst_n => eth_rst_n, + gmii_mdio => eth_mdio, + gmii_mdc => eth_mdc, + gmii_rx_dv => eth_rx_dv, + gmii_rx_er => eth_rx_er, + gmii_rx_data => eth_rx_data, + gmii_tx_en => eth_tx_en, + gmii_tx_er => eth_tx_er, + gmii_tx_data => eth_tx_data, + gmii_col => eth_col, + gmii_crs => eth_crs, wishbone_adr => wb_eth_adr, wishbone_dat_w => wb_ext_io_in.dat, wishbone_dat_r => wb_eth_out.dat, diff --git a/liteeth/generated/arty/liteeth_core.v b/liteeth/generated/arty/liteeth_core.v index 3f5ac6c..f363a2f 100644 --- a/liteeth/generated/arty/liteeth_core.v +++ b/liteeth/generated/arty/liteeth_core.v @@ -1,1041 +1,1334 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:00 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - input wire mii_eth_clocks_tx, - input wire mii_eth_clocks_rx, - output wire mii_eth_rst_n, - inout wire mii_eth_mdio, - output wire mii_eth_mdc, - input wire mii_eth_rx_dv, - input wire mii_eth_rx_er, - input wire [3:0] mii_eth_rx_data, - output reg mii_eth_tx_en, - output reg [3:0] mii_eth_tx_data, - input wire mii_eth_col, - input wire mii_eth_crs, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:49 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire mii_clocks_rx, + input wire mii_clocks_tx, + input wire mii_col, + input wire mii_crs, + output wire mii_mdc, + inout wire mii_mdio, + output wire mii_rst_n, + input wire [3:0] mii_rx_data, + input wire mii_rx_dv, + input wire mii_rx_er, + output reg [3:0] mii_tx_data, + output reg mii_tx_en, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg main_maccore_maccore_soc_rst = 1'd0; -wire main_maccore_maccore_cpu_rst; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_reset_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_scratch_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg main_maccore_int_rst = 1'd1; -reg main_maccore_ethphy_reset_storage = 1'd0; -reg main_maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -wire main_maccore_ethphy_reset0; -wire main_maccore_ethphy_reset1; -reg [8:0] main_maccore_ethphy_counter = 9'd0; -wire main_maccore_ethphy_counter_done; -wire main_maccore_ethphy_counter_ce; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_ready; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_first; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_last; -wire [7:0] main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be; -wire main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error; -wire main_maccore_ethphy_liteethphymiitx_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_sink_ready; -reg main_maccore_ethphy_liteethphymiitx_converter_sink_first = 1'd0; -reg main_maccore_ethphy_liteethphymiitx_converter_sink_last = 1'd0; -wire [7:0] main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data; -wire main_maccore_ethphy_liteethphymiitx_converter_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_source_last; -wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last; -reg [7:0] main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data = 8'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; -reg [3:0] main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data = 4'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count; -reg main_maccore_ethphy_liteethphymiitx_converter_converter_mux = 1'd0; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_first; -wire main_maccore_ethphy_liteethphymiitx_converter_converter_last; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_first; -wire main_maccore_ethphy_liteethphymiitx_converter_source_source_last; -wire [3:0] main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; -wire main_maccore_ethphy_liteethphymiirx_source_source_valid; -wire main_maccore_ethphy_liteethphymiirx_source_source_ready; -wire main_maccore_ethphy_liteethphymiirx_source_source_first; -wire main_maccore_ethphy_liteethphymiirx_source_source_last; -wire [7:0] main_maccore_ethphy_liteethphymiirx_source_source_payload_data; -reg main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_source_source_payload_error = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_sink_valid = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_sink_ready; -reg main_maccore_ethphy_liteethphymiirx_converter_sink_first = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_sink_last; -reg [3:0] main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data = 4'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_source_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_source_first; -wire main_maccore_ethphy_liteethphymiirx_converter_source_last; -reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_payload_data = 8'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; -wire [3:0] main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_first = 1'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_source_last = 1'd0; -reg [7:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data = 8'd0; -reg [1:0] main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count = 2'd0; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_demux = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_converter_load_part; -reg main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all = 1'd0; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_first; -wire main_maccore_ethphy_liteethphymiirx_converter_source_source_last; -wire [7:0] main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data; -reg main_maccore_ethphy_liteethphymiirx_converter_reset = 1'd0; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -wire main_maccore_ethphy_w; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg main_maccore_ethphy__w_re = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__r_re = 1'd0; -wire main_maccore_ethphy_data_w; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_tx_gap_inserter_sink_valid; -reg main_tx_gap_inserter_sink_ready = 1'd0; -wire main_tx_gap_inserter_sink_first; -wire main_tx_gap_inserter_sink_last; -wire [7:0] main_tx_gap_inserter_sink_payload_data; -wire main_tx_gap_inserter_sink_payload_last_be; -wire main_tx_gap_inserter_sink_payload_error; -reg main_tx_gap_inserter_source_valid = 1'd0; -wire main_tx_gap_inserter_source_ready; -reg main_tx_gap_inserter_source_first = 1'd0; -reg main_tx_gap_inserter_source_last = 1'd0; -reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; -reg main_tx_gap_inserter_source_payload_last_be = 1'd0; -reg main_tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] main_tx_gap_inserter_counter = 4'd0; -reg main_preamble_crc_status = 1'd1; -wire main_preamble_crc_we; -reg main_preamble_crc_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_crc_errors_re = 1'd0; -wire main_preamble_inserter_sink_valid; -reg main_preamble_inserter_sink_ready = 1'd0; -wire main_preamble_inserter_sink_first; -wire main_preamble_inserter_sink_last; -wire [7:0] main_preamble_inserter_sink_payload_data; -wire main_preamble_inserter_sink_payload_last_be; -wire main_preamble_inserter_sink_payload_error; -reg main_preamble_inserter_source_valid = 1'd0; -wire main_preamble_inserter_source_ready; -reg main_preamble_inserter_source_first = 1'd0; -reg main_preamble_inserter_source_last = 1'd0; -reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; -wire main_preamble_inserter_source_payload_last_be; -reg main_preamble_inserter_source_payload_error = 1'd0; -reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] main_preamble_inserter_count = 3'd0; -wire main_preamble_checker_sink_valid; -reg main_preamble_checker_sink_ready = 1'd0; -wire main_preamble_checker_sink_first; -wire main_preamble_checker_sink_last; -wire [7:0] main_preamble_checker_sink_payload_data; -wire main_preamble_checker_sink_payload_last_be; -wire main_preamble_checker_sink_payload_error; -reg main_preamble_checker_source_valid = 1'd0; -wire main_preamble_checker_source_ready; -reg main_preamble_checker_source_first = 1'd0; -reg main_preamble_checker_source_last = 1'd0; -wire [7:0] main_preamble_checker_source_payload_data; -wire main_preamble_checker_source_payload_last_be; -reg main_preamble_checker_source_payload_error = 1'd0; -reg main_preamble_checker_error = 1'd0; -wire main_liteethmaccrc32inserter_sink_valid; -reg main_liteethmaccrc32inserter_sink_ready = 1'd0; -wire main_liteethmaccrc32inserter_sink_first; -wire main_liteethmaccrc32inserter_sink_last; -wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; -wire main_liteethmaccrc32inserter_sink_payload_last_be; -wire main_liteethmaccrc32inserter_sink_payload_error; -reg main_liteethmaccrc32inserter_source_valid = 1'd0; -wire main_liteethmaccrc32inserter_source_ready; -reg main_liteethmaccrc32inserter_source_first = 1'd0; -reg main_liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; -reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] main_liteethmaccrc32inserter_value; -wire main_liteethmaccrc32inserter_error; -wire [7:0] main_liteethmaccrc32inserter_data1; -wire [31:0] main_liteethmaccrc32inserter_last; -reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; -reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; -reg main_liteethmaccrc32inserter_ce = 1'd0; -reg main_liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; -wire main_liteethmaccrc32inserter_cnt_done; -reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire main_crc32_inserter_sink_valid; -wire main_crc32_inserter_sink_ready; -wire main_crc32_inserter_sink_first; -wire main_crc32_inserter_sink_last; -wire [7:0] main_crc32_inserter_sink_payload_data; -wire main_crc32_inserter_sink_payload_last_be; -wire main_crc32_inserter_sink_payload_error; -reg main_crc32_inserter_source_valid = 1'd0; -wire main_crc32_inserter_source_ready; -reg main_crc32_inserter_source_first = 1'd0; -reg main_crc32_inserter_source_last = 1'd0; -reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; -reg main_crc32_inserter_source_payload_last_be = 1'd0; -reg main_crc32_inserter_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_source_source_valid; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_first = 1'd0; -wire main_liteethmaccrc32checker_source_source_last; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -wire main_liteethmaccrc32checker_source_source_payload_last_be; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_error; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [31:0] main_liteethmaccrc32checker_crc_value; -wire main_liteethmaccrc32checker_crc_error; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -wire [31:0] main_liteethmaccrc32checker_crc_last; -reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire main_liteethmaccrc32checker_syncfifo_source_ready; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -wire main_liteethmaccrc32checker_fifo_full; -wire main_crc32_checker_sink_valid; -wire main_crc32_checker_sink_ready; -wire main_crc32_checker_sink_first; -wire main_crc32_checker_sink_last; -wire [7:0] main_crc32_checker_sink_payload_data; -wire main_crc32_checker_sink_payload_last_be; -wire main_crc32_checker_sink_payload_error; -reg main_crc32_checker_source_valid = 1'd0; -wire main_crc32_checker_source_ready; -reg main_crc32_checker_source_first = 1'd0; -reg main_crc32_checker_source_last = 1'd0; -reg [7:0] main_crc32_checker_source_payload_data = 8'd0; -reg main_crc32_checker_source_payload_last_be = 1'd0; -reg main_crc32_checker_source_payload_error = 1'd0; -wire main_ps_preamble_error_i; -wire main_ps_preamble_error_o; -reg main_ps_preamble_error_toggle_i = 1'd0; -wire main_ps_preamble_error_toggle_o; -reg main_ps_preamble_error_toggle_o_r = 1'd0; -wire main_ps_crc_error_i; -wire main_ps_crc_error_o; -reg main_ps_crc_error_toggle_i = 1'd0; -wire main_ps_crc_error_toggle_o; -reg main_ps_crc_error_toggle_o_r = 1'd0; -wire main_padding_inserter_sink_valid; -reg main_padding_inserter_sink_ready = 1'd0; -wire main_padding_inserter_sink_first; -wire main_padding_inserter_sink_last; -wire [7:0] main_padding_inserter_sink_payload_data; -wire main_padding_inserter_sink_payload_last_be; -wire main_padding_inserter_sink_payload_error; -reg main_padding_inserter_source_valid = 1'd0; -wire main_padding_inserter_source_ready; -reg main_padding_inserter_source_first = 1'd0; -reg main_padding_inserter_source_last = 1'd0; -reg [7:0] main_padding_inserter_source_payload_data = 8'd0; -reg main_padding_inserter_source_payload_last_be = 1'd0; -reg main_padding_inserter_source_payload_error = 1'd0; -reg [15:0] main_padding_inserter_counter = 16'd0; -wire main_padding_inserter_counter_done; -wire main_padding_checker_sink_valid; -wire main_padding_checker_sink_ready; -wire main_padding_checker_sink_first; -wire main_padding_checker_sink_last; -wire [7:0] main_padding_checker_sink_payload_data; -wire main_padding_checker_sink_payload_last_be; -wire main_padding_checker_sink_payload_error; -wire main_padding_checker_source_valid; -wire main_padding_checker_source_ready; -wire main_padding_checker_source_first; -wire main_padding_checker_source_last; -wire [7:0] main_padding_checker_source_payload_data; -wire main_padding_checker_source_payload_last_be; -wire main_padding_checker_source_payload_error; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_last_be; -wire main_tx_last_be_sink_payload_error; -reg main_tx_last_be_source_valid = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_source_valid; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_payload_error; -wire main_tx_converter_sink_valid; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire [3:0] main_tx_converter_sink_payload_error; -wire main_tx_converter_source_valid; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_rx_converter_sink_valid; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_source_valid; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -wire main_rx_converter_converter_sink_valid; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_source_valid; -wire main_rx_converter_converter_source_ready; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire main_tx_cdc_source_source_valid; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire main_tx_cdc_cdc_source_valid; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire main_tx_cdc_cdc_wrport_we; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire main_rx_cdc_source_source_valid; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire main_rx_cdc_cdc_source_valid; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire main_rx_cdc_cdc_wrport_we; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire main_sink_valid; -wire main_sink_ready; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_last_be; -wire [3:0] main_sink_payload_error; -wire main_source_valid; -wire main_source_ready; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_last_be; -wire [3:0] main_source_payload_error; -wire [29:0] main_bus_adr; -wire [31:0] main_bus_dat_w; -wire [31:0] main_bus_dat_r; -wire [3:0] main_bus_sel; -wire main_bus_cyc; -wire main_bus_stb; -wire main_bus_ack; -wire main_bus_we; -wire [2:0] main_bus_cti; -wire [1:0] main_bus_bte; -wire main_bus_err; -wire main_writer_sink_sink_valid; -reg main_writer_sink_sink_ready = 1'd1; -wire main_writer_sink_sink_first; -wire main_writer_sink_sink_last; -wire [31:0] main_writer_sink_sink_payload_data; -wire [3:0] main_writer_sink_sink_payload_last_be; -wire [3:0] main_writer_sink_sink_payload_error; -wire main_writer_slot_status; -wire main_writer_slot_we; -reg main_writer_slot_re = 1'd0; -wire [31:0] main_writer_length_status; -wire main_writer_length_we; -reg main_writer_length_re = 1'd0; -reg [31:0] main_writer_errors_status = 32'd0; -wire main_writer_errors_we; -reg main_writer_errors_re = 1'd0; -wire main_writer_irq; -wire main_writer_available_status; -wire main_writer_available_pending; -wire main_writer_available_trigger; -reg main_writer_available_clear = 1'd0; -wire main_writer_available0; -wire main_writer_status_status; -wire main_writer_status_we; -reg main_writer_status_re = 1'd0; -wire main_writer_available1; -wire main_writer_pending_status; -wire main_writer_pending_we; -reg main_writer_pending_re = 1'd0; -reg main_writer_pending_r = 1'd0; -wire main_writer_available2; -reg main_writer_enable_storage = 1'd0; -reg main_writer_enable_re = 1'd0; -reg [2:0] main_writer_inc = 3'd0; -reg [31:0] main_writer_counter = 32'd0; -reg main_writer_slot = 1'd0; -reg main_writer_slot_ce = 1'd0; -reg main_writer_start = 1'd0; -reg main_writer_ongoing = 1'd0; -reg main_writer_stat_fifo_sink_valid = 1'd0; -wire main_writer_stat_fifo_sink_ready; -reg main_writer_stat_fifo_sink_first = 1'd0; -reg main_writer_stat_fifo_sink_last = 1'd0; -wire main_writer_stat_fifo_sink_payload_slot; -wire [31:0] main_writer_stat_fifo_sink_payload_length; -wire main_writer_stat_fifo_source_valid; -wire main_writer_stat_fifo_source_ready; -wire main_writer_stat_fifo_source_first; -wire main_writer_stat_fifo_source_last; -wire main_writer_stat_fifo_source_payload_slot; -wire [31:0] main_writer_stat_fifo_source_payload_length; -wire main_writer_stat_fifo_syncfifo_we; -wire main_writer_stat_fifo_syncfifo_writable; -wire main_writer_stat_fifo_syncfifo_re; -wire main_writer_stat_fifo_syncfifo_readable; -wire [34:0] main_writer_stat_fifo_syncfifo_din; -wire [34:0] main_writer_stat_fifo_syncfifo_dout; -reg [1:0] main_writer_stat_fifo_level = 2'd0; -reg main_writer_stat_fifo_replace = 1'd0; -reg main_writer_stat_fifo_produce = 1'd0; -reg main_writer_stat_fifo_consume = 1'd0; -reg main_writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] main_writer_stat_fifo_wrport_dat_r; -wire main_writer_stat_fifo_wrport_we; -wire [34:0] main_writer_stat_fifo_wrport_dat_w; -wire main_writer_stat_fifo_do_read; -wire main_writer_stat_fifo_rdport_adr; -wire [34:0] main_writer_stat_fifo_rdport_dat_r; -wire main_writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_in_payload_length; -wire main_writer_stat_fifo_fifo_in_first; -wire main_writer_stat_fifo_fifo_in_last; -wire main_writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_out_payload_length; -wire main_writer_stat_fifo_fifo_out_first; -wire main_writer_stat_fifo_fifo_out_last; -reg [8:0] main_writer_memory0_adr = 9'd0; -wire [31:0] main_writer_memory0_dat_r; -reg main_writer_memory0_we = 1'd0; -reg [31:0] main_writer_memory0_dat_w = 32'd0; -reg [8:0] main_writer_memory1_adr = 9'd0; -wire [31:0] main_writer_memory1_dat_r; -reg main_writer_memory1_we = 1'd0; -reg [31:0] main_writer_memory1_dat_w = 32'd0; -reg main_reader_source_source_valid = 1'd0; -wire main_reader_source_source_ready; -reg main_reader_source_source_first = 1'd0; -reg main_reader_source_source_last = 1'd0; -reg [31:0] main_reader_source_source_payload_data = 32'd0; -reg [3:0] main_reader_source_source_payload_last_be = 4'd0; -reg [3:0] main_reader_source_source_payload_error = 4'd0; -reg main_reader_start_start_re = 1'd0; -wire main_reader_start_start_r; -reg main_reader_start_start_we = 1'd0; -reg main_reader_start_start_w = 1'd0; -wire main_reader_ready_status; -wire main_reader_ready_we; -reg main_reader_ready_re = 1'd0; -wire [1:0] main_reader_level_status; -wire main_reader_level_we; -reg main_reader_level_re = 1'd0; -reg main_reader_slot_storage = 1'd0; -reg main_reader_slot_re = 1'd0; -reg [10:0] main_reader_length_storage = 11'd0; -reg main_reader_length_re = 1'd0; -wire main_reader_irq; -wire main_reader_eventsourcepulse_status; -reg main_reader_eventsourcepulse_pending = 1'd0; -reg main_reader_eventsourcepulse_trigger = 1'd0; -reg main_reader_eventsourcepulse_clear = 1'd0; -wire main_reader_event00; -wire main_reader_status_status; -wire main_reader_status_we; -reg main_reader_status_re = 1'd0; -wire main_reader_event01; -wire main_reader_pending_status; -wire main_reader_pending_we; -reg main_reader_pending_re = 1'd0; -reg main_reader_pending_r = 1'd0; -wire main_reader_event02; -reg main_reader_enable_storage = 1'd0; -reg main_reader_enable_re = 1'd0; -reg main_reader_start = 1'd0; -wire main_reader_cmd_fifo_sink_valid; -wire main_reader_cmd_fifo_sink_ready; -reg main_reader_cmd_fifo_sink_first = 1'd0; -reg main_reader_cmd_fifo_sink_last = 1'd0; -wire main_reader_cmd_fifo_sink_payload_slot; -wire [10:0] main_reader_cmd_fifo_sink_payload_length; -wire main_reader_cmd_fifo_source_valid; -reg main_reader_cmd_fifo_source_ready = 1'd0; -wire main_reader_cmd_fifo_source_first; -wire main_reader_cmd_fifo_source_last; -wire main_reader_cmd_fifo_source_payload_slot; -wire [10:0] main_reader_cmd_fifo_source_payload_length; -wire main_reader_cmd_fifo_syncfifo_we; -wire main_reader_cmd_fifo_syncfifo_writable; -wire main_reader_cmd_fifo_syncfifo_re; -wire main_reader_cmd_fifo_syncfifo_readable; -wire [13:0] main_reader_cmd_fifo_syncfifo_din; -wire [13:0] main_reader_cmd_fifo_syncfifo_dout; -reg [1:0] main_reader_cmd_fifo_level = 2'd0; -reg main_reader_cmd_fifo_replace = 1'd0; -reg main_reader_cmd_fifo_produce = 1'd0; -reg main_reader_cmd_fifo_consume = 1'd0; -reg main_reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] main_reader_cmd_fifo_wrport_dat_r; -wire main_reader_cmd_fifo_wrport_we; -wire [13:0] main_reader_cmd_fifo_wrport_dat_w; -wire main_reader_cmd_fifo_do_read; -wire main_reader_cmd_fifo_rdport_adr; -wire [13:0] main_reader_cmd_fifo_rdport_dat_r; -wire main_reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length; -wire main_reader_cmd_fifo_fifo_in_first; -wire main_reader_cmd_fifo_fifo_in_last; -wire main_reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length; -wire main_reader_cmd_fifo_fifo_out_first; -wire main_reader_cmd_fifo_fifo_out_last; -reg [10:0] main_reader_read_address = 11'd0; -reg [10:0] main_reader_counter = 11'd0; -wire [8:0] main_reader_memory0_adr; -wire [31:0] main_reader_memory0_dat_r; -wire [8:0] main_reader_memory1_adr; -wire [31:0] main_reader_memory1_dat_r; -wire main_ev_irq; -wire [29:0] main_sram0_bus_adr0; -wire [31:0] main_sram0_bus_dat_w0; -wire [31:0] main_sram0_bus_dat_r0; -wire [3:0] main_sram0_bus_sel0; -wire main_sram0_bus_cyc0; -wire main_sram0_bus_stb0; -reg main_sram0_bus_ack0 = 1'd0; -wire main_sram0_bus_we0; -wire [2:0] main_sram0_bus_cti0; -wire [1:0] main_sram0_bus_bte0; -reg main_sram0_bus_err0 = 1'd0; -wire [8:0] main_sram0_adr0; -wire [31:0] main_sram0_dat_r0; -wire [29:0] main_sram1_bus_adr0; -wire [31:0] main_sram1_bus_dat_w0; -wire [31:0] main_sram1_bus_dat_r0; -wire [3:0] main_sram1_bus_sel0; -wire main_sram1_bus_cyc0; -wire main_sram1_bus_stb0; -reg main_sram1_bus_ack0 = 1'd0; -wire main_sram1_bus_we0; -wire [2:0] main_sram1_bus_cti0; -wire [1:0] main_sram1_bus_bte0; -reg main_sram1_bus_err0 = 1'd0; -wire [8:0] main_sram1_adr0; -wire [31:0] main_sram1_dat_r0; -wire [29:0] main_sram0_bus_adr1; -wire [31:0] main_sram0_bus_dat_w1; -wire [31:0] main_sram0_bus_dat_r1; -wire [3:0] main_sram0_bus_sel1; -wire main_sram0_bus_cyc1; -wire main_sram0_bus_stb1; -reg main_sram0_bus_ack1 = 1'd0; -wire main_sram0_bus_we1; -wire [2:0] main_sram0_bus_cti1; -wire [1:0] main_sram0_bus_bte1; -reg main_sram0_bus_err1 = 1'd0; -wire [8:0] main_sram0_adr1; -wire [31:0] main_sram0_dat_r1; -reg [3:0] main_sram0_we = 4'd0; -wire [31:0] main_sram0_dat_w; -wire [29:0] main_sram1_bus_adr1; -wire [31:0] main_sram1_bus_dat_w1; -wire [31:0] main_sram1_bus_dat_r1; -wire [3:0] main_sram1_bus_sel1; -wire main_sram1_bus_cyc1; -wire main_sram1_bus_stb1; -reg main_sram1_bus_ack1 = 1'd0; -wire main_sram1_bus_we1; -wire [2:0] main_sram1_bus_cti1; -wire [1:0] main_sram1_bus_bte1; -reg main_sram1_bus_err1 = 1'd0; -wire [8:0] main_sram1_adr1; -wire [31:0] main_sram1_dat_r1; -reg [3:0] main_sram1_we = 4'd0; -wire [31:0] main_sram1_dat_w; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -wire [29:0] main_wb_bus_adr; -wire [31:0] main_wb_bus_dat_w; -wire [31:0] main_wb_bus_dat_r; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_cyc; -wire main_wb_bus_stb; -wire main_wb_bus_ack; -wire main_wb_bus_we; -wire [2:0] main_wb_bus_cti; -wire [1:0] main_wb_bus_bte; -wire main_wb_bus_err; -reg builder_liteethmacgap_state = 1'd0; -reg builder_liteethmacgap_next_state = 1'd0; -reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg builder_liteethmacpreamblechecker_state = 1'd0; -reg builder_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; -reg builder_liteethmacpaddinginserter_state = 1'd0; -reg builder_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg builder_liteethmactxlastbe_state = 1'd0; -reg builder_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] main_writer_counter_t_next_value = 32'd0; -reg main_writer_counter_t_next_value_ce = 1'd0; -reg [31:0] main_writer_errors_status_f_next_value = 32'd0; -reg main_writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [10:0] main_reader_counter_next_value = 11'd0; -reg main_reader_counter_next_value_ce = 1'd0; -reg [13:0] builder_maccore_adr = 14'd0; -reg builder_maccore_we = 1'd0; -reg [31:0] builder_maccore_dat_w = 32'd0; -wire [31:0] builder_maccore_dat_r; -wire [29:0] builder_maccore_wishbone_adr; -wire [31:0] builder_maccore_wishbone_dat_w; -reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; -wire [3:0] builder_maccore_wishbone_sel; -wire builder_maccore_wishbone_cyc; -wire builder_maccore_wishbone_stb; -reg builder_maccore_wishbone_ack = 1'd0; -wire builder_maccore_wishbone_we; -wire [2:0] builder_maccore_wishbone_cti; -wire [1:0] builder_maccore_wishbone_bte; -reg builder_maccore_wishbone_err = 1'd0; -wire [29:0] builder_shared_adr; -wire [31:0] builder_shared_dat_w; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [3:0] builder_shared_sel; -wire builder_shared_cyc; -wire builder_shared_stb; -reg builder_shared_ack = 1'd0; -wire builder_shared_we; -wire [2:0] builder_shared_cti; -wire [1:0] builder_shared_bte; -wire builder_shared_err; -wire builder_request; -wire builder_grant; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_error = 1'd0; -wire builder_wait; -wire builder_done; -reg [19:0] builder_count = 20'd1000000; -wire [13:0] builder_interface0_bank_bus_adr; -wire builder_interface0_bank_bus_we; -wire [31:0] builder_interface0_bank_bus_dat_w; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -wire builder_csrbank0_sel; -wire [13:0] builder_interface1_bank_bus_adr; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_bank_bus_dat_w; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_r; -reg builder_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_w; -reg builder_csrbank1_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_r; -reg builder_csrbank1_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_w; -wire builder_csrbank1_sel; -wire [13:0] builder_interface2_bank_bus_adr; -wire builder_interface2_bank_bus_we; -wire [31:0] builder_interface2_bank_bus_dat_w; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire builder_csrbank2_mdio_r_w; -wire builder_csrbank2_sel; -wire [13:0] builder_csr_interconnect_adr; -wire builder_csr_interconnect_we; -wire [31:0] builder_csr_interconnect_dat_w; -wire [31:0] builder_csr_interconnect_dat_r; -reg builder_state = 1'd0; -reg builder_next_state = 1'd0; -reg [29:0] builder_array_muxed0 = 30'd0; -reg [31:0] builder_array_muxed1 = 32'd0; -reg [3:0] builder_array_muxed2 = 4'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg [2:0] builder_array_muxed6 = 3'd0; -reg [1:0] builder_array_muxed7 = 2'd0; -wire builder_rst_meta0; -wire builder_rst_meta1; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0; + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYMII) +│ └─── crg (LiteEthPHYMIICRG) +│ │ └─── hw_reset (LiteEthPHYHWReset) +│ └─── tx (LiteEthPHYMIITX) +│ │ └─── converter (Converter) +│ │ │ └─── _downconverter_0* (_DownConverter) +│ └─── rx (LiteEthPHYMIIRX) +│ │ └─── converter_0* (Converter) +│ │ │ └─── _upconverter_0* (_UpConverter) +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg builder_next_state = 1'd0; +wire builder_request; +wire builder_rst_meta0; +wire builder_rst_meta1; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl30 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl31 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore__r_re = 1'd0; +reg main_maccore__r_status = 1'd0; +wire main_maccore__r_we; +reg main_maccore__w_re = 1'd0; +reg [2:0] main_maccore__w_storage = 3'd0; +wire main_maccore_bus_error; +reg [31:0] main_maccore_bus_errors = 32'd0; +reg main_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_bus_errors_status; +wire main_maccore_bus_errors_we; +wire main_maccore_cpu_rst; +reg [8:0] main_maccore_crg_counter = 9'd0; +wire main_maccore_crg_counter_ce; +wire main_maccore_crg_counter_done; +wire main_maccore_crg_reset0; +wire main_maccore_crg_reset1; +reg main_maccore_crg_reset_re = 1'd0; +reg main_maccore_crg_reset_storage = 1'd0; +wire main_maccore_data_oe; +wire main_maccore_data_r; +wire main_maccore_data_w; +reg main_maccore_int_rst = 1'd1; +reg main_maccore_liteethphymiirx_converter_demux = 1'd0; +wire main_maccore_liteethphymiirx_converter_load_part; +reg main_maccore_liteethphymiirx_converter_sink_first = 1'd0; +wire main_maccore_liteethphymiirx_converter_sink_last; +reg [3:0] main_maccore_liteethphymiirx_converter_sink_payload_data = 4'd0; +wire main_maccore_liteethphymiirx_converter_sink_ready; +reg main_maccore_liteethphymiirx_converter_sink_valid = 1'd0; +reg main_maccore_liteethphymiirx_converter_source_first = 1'd0; +reg main_maccore_liteethphymiirx_converter_source_last = 1'd0; +reg [7:0] main_maccore_liteethphymiirx_converter_source_payload_data = 8'd0; +reg [1:0] main_maccore_liteethphymiirx_converter_source_payload_valid_token_count = 2'd0; +wire main_maccore_liteethphymiirx_converter_source_ready; +wire main_maccore_liteethphymiirx_converter_source_valid; +reg main_maccore_liteethphymiirx_converter_strobe_all = 1'd0; +reg main_maccore_liteethphymiirx_reset = 1'd0; +wire main_maccore_liteethphymiirx_source_first; +wire main_maccore_liteethphymiirx_source_last; +wire [7:0] main_maccore_liteethphymiirx_source_payload_data; +reg main_maccore_liteethphymiirx_source_payload_error = 1'd0; +reg main_maccore_liteethphymiirx_source_payload_last_be = 1'd0; +wire main_maccore_liteethphymiirx_source_ready; +wire main_maccore_liteethphymiirx_source_source_first; +wire main_maccore_liteethphymiirx_source_source_last; +wire [7:0] main_maccore_liteethphymiirx_source_source_payload_data; +wire main_maccore_liteethphymiirx_source_source_ready; +wire main_maccore_liteethphymiirx_source_source_valid; +wire main_maccore_liteethphymiirx_source_valid; +wire main_maccore_liteethphymiitx_converter_first; +wire main_maccore_liteethphymiitx_converter_last; +reg main_maccore_liteethphymiitx_converter_mux = 1'd0; +reg main_maccore_liteethphymiitx_converter_sink_first = 1'd0; +reg main_maccore_liteethphymiitx_converter_sink_last = 1'd0; +wire [7:0] main_maccore_liteethphymiitx_converter_sink_payload_data; +wire main_maccore_liteethphymiitx_converter_sink_ready; +wire main_maccore_liteethphymiitx_converter_sink_valid; +wire main_maccore_liteethphymiitx_converter_source_first; +wire main_maccore_liteethphymiitx_converter_source_last; +reg [3:0] main_maccore_liteethphymiitx_converter_source_payload_data = 4'd0; +wire main_maccore_liteethphymiitx_converter_source_payload_valid_token_count; +wire main_maccore_liteethphymiitx_converter_source_ready; +wire main_maccore_liteethphymiitx_converter_source_valid; +wire main_maccore_liteethphymiitx_sink_first; +wire main_maccore_liteethphymiitx_sink_last; +wire [7:0] main_maccore_liteethphymiitx_sink_payload_data; +wire main_maccore_liteethphymiitx_sink_payload_error; +wire main_maccore_liteethphymiitx_sink_payload_last_be; +wire main_maccore_liteethphymiitx_sink_ready; +wire main_maccore_liteethphymiitx_sink_valid; +wire main_maccore_liteethphymiitx_source_source_first; +wire main_maccore_liteethphymiitx_source_source_last; +wire [3:0] main_maccore_liteethphymiitx_source_source_payload_data; +wire main_maccore_liteethphymiitx_source_source_ready; +wire main_maccore_liteethphymiitx_source_source_valid; +wire main_maccore_mdc; +wire main_maccore_oe; +reg main_maccore_r = 1'd0; +reg main_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_reset_storage = 2'd0; +reg main_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_scratch_storage = 32'd305419896; +reg main_maccore_soc_rst = 1'd0; +wire main_maccore_w; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ assign main_wb_bus_adr = wishbone_adr; assign main_wb_bus_dat_w = wishbone_dat_w; @@ -1048,362 +1341,693 @@ assign main_wb_bus_we = wishbone_we; assign main_wb_bus_cti = wishbone_cti; assign main_wb_bus_bte = wishbone_bte; assign wishbone_err = main_wb_bus_err; -assign interrupt = main_ev_irq; -assign main_maccore_maccore_bus_error = builder_error; -assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign interrupt = main_sram167_irq; +assign main_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_bus_errors_status = main_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = main_maccore_int_rst; -assign eth_rx_clk = mii_eth_clocks_rx; -assign eth_tx_clk = mii_eth_clocks_tx; -assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); -assign mii_eth_rst_n = (~main_maccore_ethphy_reset0); -assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); -assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); -assign main_maccore_ethphy_liteethphymiitx_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_sink_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data = main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_sink_ready; -assign main_maccore_ethphy_liteethphymiitx_converter_source_ready = 1'd1; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiitx_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiitx_converter_sink_first; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiitx_converter_sink_last; -assign main_maccore_ethphy_liteethphymiitx_converter_sink_ready = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready; -always @(*) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[3:0]; - main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4] <= main_maccore_ethphy_liteethphymiitx_converter_sink_payload_data[7:4]; -end -assign main_maccore_ethphy_liteethphymiitx_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_source_source_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_source_first = main_maccore_ethphy_liteethphymiitx_converter_source_source_first; -assign main_maccore_ethphy_liteethphymiitx_converter_source_last = main_maccore_ethphy_liteethphymiitx_converter_source_source_last; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_ready; -assign {main_maccore_ethphy_liteethphymiitx_converter_source_payload_data} = main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiitx_converter_source_source_ready; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_first = main_maccore_ethphy_liteethphymiitx_converter_converter_source_first; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_last = main_maccore_ethphy_liteethphymiitx_converter_converter_source_last; -assign main_maccore_ethphy_liteethphymiitx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd0); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_mux == 1'd1); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiitx_converter_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_first = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_first & main_maccore_ethphy_liteethphymiitx_converter_converter_first); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_last = (main_maccore_ethphy_liteethphymiitx_converter_converter_sink_last & main_maccore_ethphy_liteethphymiitx_converter_converter_last); -assign main_maccore_ethphy_liteethphymiitx_converter_converter_sink_ready = (main_maccore_ethphy_liteethphymiitx_converter_converter_last & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready); -always @(*) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= 4'd0; - case (main_maccore_ethphy_liteethphymiitx_converter_converter_mux) - 1'd0: begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[3:0]; - end - default: begin - main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_data <= main_maccore_ethphy_liteethphymiitx_converter_converter_sink_payload_data[7:4]; - end - endcase -end -assign main_maccore_ethphy_liteethphymiitx_converter_converter_source_payload_valid_token_count = main_maccore_ethphy_liteethphymiitx_converter_converter_last; -assign main_maccore_ethphy_liteethphymiirx_converter_sink_last = (~mii_eth_rx_dv); -assign main_maccore_ethphy_liteethphymiirx_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_source_ready = main_maccore_ethphy_liteethphymiirx_source_source_ready; -assign main_maccore_ethphy_liteethphymiirx_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_first; -assign main_maccore_ethphy_liteethphymiirx_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_last; -assign main_maccore_ethphy_liteethphymiirx_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid = main_maccore_ethphy_liteethphymiirx_converter_sink_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first = main_maccore_ethphy_liteethphymiirx_converter_sink_first; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last = main_maccore_ethphy_liteethphymiirx_converter_sink_last; -assign main_maccore_ethphy_liteethphymiirx_converter_sink_ready = main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data = {main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data}; -assign main_maccore_ethphy_liteethphymiirx_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_source_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_source_first = main_maccore_ethphy_liteethphymiirx_converter_source_source_first; -assign main_maccore_ethphy_liteethphymiirx_converter_source_last = main_maccore_ethphy_liteethphymiirx_converter_source_source_last; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_ready; -always @(*) begin - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[3:0]; - main_maccore_ethphy_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data[7:4]; -end -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready = main_maccore_ethphy_liteethphymiirx_converter_source_source_ready; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_first = main_maccore_ethphy_liteethphymiirx_converter_converter_source_first; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_last = main_maccore_ethphy_liteethphymiirx_converter_converter_source_last; -assign main_maccore_ethphy_liteethphymiirx_converter_source_source_payload_data = main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready = ((~main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all) | main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready); -assign main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid = main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all; -assign main_maccore_ethphy_liteethphymiirx_converter_converter_load_part = (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready); -assign mii_eth_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_tx_cdc_sink_sink_valid = main_source_valid; -assign main_source_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_source_first; -assign main_tx_cdc_sink_sink_last = main_source_last; -assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error; -assign main_sink_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_sink_ready; -assign main_sink_first = main_rx_cdc_source_source_first; -assign main_sink_last = main_rx_cdc_source_source_last; -assign main_sink_payload_data = main_rx_cdc_source_source_payload_data; -assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_sink_payload_error = main_rx_cdc_source_source_payload_error; -assign main_ps_preamble_error_i = main_preamble_checker_error; -assign main_ps_crc_error_i = main_liteethmaccrc32checker_error; -always @(*) begin - main_tx_gap_inserter_source_valid <= 1'd0; - builder_liteethmacgap_next_state <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - main_tx_gap_inserter_source_first <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - main_tx_gap_inserter_source_last <= 1'd0; - main_tx_gap_inserter_source_payload_data <= 8'd0; - main_tx_gap_inserter_source_payload_last_be <= 1'd0; - main_tx_gap_inserter_source_payload_error <= 1'd0; - main_tx_gap_inserter_sink_ready <= 1'd0; - builder_liteethmacgap_next_state <= builder_liteethmacgap_state; - case (builder_liteethmacgap_state) - 1'd1: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1); - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((main_tx_gap_inserter_counter == 4'd11)) begin - builder_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; - main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; - main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; - main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; - main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; - main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; - main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; - if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin - builder_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; -always @(*) begin - builder_liteethmacpreambleinserter_next_state <= 2'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - main_preamble_inserter_source_valid <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - main_preamble_inserter_source_first <= 1'd0; - main_preamble_inserter_source_last <= 1'd0; - main_preamble_inserter_source_payload_data <= 8'd0; - main_preamble_inserter_source_payload_error <= 1'd0; - main_preamble_inserter_sink_ready <= 1'd0; - main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; - builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; - case (builder_liteethmacpreambleinserter_state) - 1'd1: begin - main_preamble_inserter_source_valid <= 1'd1; - case (main_preamble_inserter_count) - 1'd0: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; - end - 1'd1: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; - end - 2'd2: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; - end - 2'd3: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; - end - 3'd4: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; - end - 3'd5: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; - end - 3'd6: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; - end - default: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; - end - endcase - if (main_preamble_inserter_source_ready) begin - if ((main_preamble_inserter_count == 3'd7)) begin - builder_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1); - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; - main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; - main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; - main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; - main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; - if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin - builder_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - main_preamble_inserter_sink_ready <= 1'd1; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (main_preamble_inserter_sink_valid) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; -assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; -always @(*) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - main_preamble_checker_source_first <= 1'd0; - main_preamble_checker_sink_ready <= 1'd0; - main_preamble_checker_source_last <= 1'd0; - main_preamble_checker_source_payload_error <= 1'd0; - main_preamble_checker_error <= 1'd0; - main_preamble_checker_source_valid <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; - case (builder_liteethmacpreamblechecker_state) - 1'd1: begin - main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; - main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; - main_preamble_checker_source_first <= main_preamble_checker_sink_first; - main_preamble_checker_source_last <= main_preamble_checker_sink_last; - main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; - if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - main_preamble_checker_sink_ready <= 1'd1; - if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin - builder_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin - main_preamble_checker_error <= 1'd1; - end - end - endcase -end -assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); -assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid; -assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready; -assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first; -assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last; -assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data; -assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; -assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error; -assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0; -assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; -assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]}); -assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32inserter_next <= 32'd0; - main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); - main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - main_liteethmaccrc32inserter_source_valid <= 1'd0; - main_liteethmaccrc32inserter_source_first <= 1'd0; - main_liteethmaccrc32inserter_source_last <= 1'd0; - main_liteethmaccrc32inserter_source_payload_data <= 8'd0; - main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - main_liteethmaccrc32inserter_source_payload_error <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 2'd0; - main_liteethmaccrc32inserter_data0 <= 8'd0; - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - main_liteethmaccrc32inserter_ce <= 1'd0; - main_liteethmaccrc32inserter_reset <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; - case (builder_liteethmaccrc32inserter_state) - 1'd1: begin - main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); - main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; - main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; - main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; - main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; - main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; - main_liteethmaccrc32inserter_source_last <= 1'd0; - if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin - builder_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - main_liteethmaccrc32inserter_source_valid <= 1'd1; - case (main_liteethmaccrc32inserter_cnt) - 1'd0: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8]; - end - default: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0]; - end - endcase - if (main_liteethmaccrc32inserter_cnt_done) begin - main_liteethmaccrc32inserter_source_last <= 1'd1; - if (main_liteethmaccrc32inserter_source_ready) begin - builder_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - main_liteethmaccrc32inserter_reset <= 1'd1; - main_liteethmaccrc32inserter_sink_ready <= 1'd1; - if (main_liteethmaccrc32inserter_sink_valid) begin - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 1'd1; - end - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready); +assign eth_rx_clk = mii_clocks_rx; +assign eth_tx_clk = mii_clocks_tx; +assign main_maccore_crg_reset0 = (main_maccore_crg_reset_storage | main_maccore_crg_reset1); +assign mii_rst_n = (~main_maccore_crg_reset0); +assign main_maccore_crg_counter_done = (main_maccore_crg_counter == 9'd256); +assign main_maccore_crg_counter_ce = (~main_maccore_crg_counter_done); +assign main_maccore_crg_reset1 = (~main_maccore_crg_counter_done); +assign main_maccore_liteethphymiitx_converter_sink_valid = main_maccore_liteethphymiitx_sink_valid; +assign main_maccore_liteethphymiitx_converter_sink_payload_data = main_maccore_liteethphymiitx_sink_payload_data; +assign main_maccore_liteethphymiitx_sink_ready = main_maccore_liteethphymiitx_converter_sink_ready; +assign main_maccore_liteethphymiitx_source_source_ready = 1'd1; +assign main_maccore_liteethphymiitx_source_source_valid = main_maccore_liteethphymiitx_converter_source_valid; +assign main_maccore_liteethphymiitx_converter_source_ready = main_maccore_liteethphymiitx_source_source_ready; +assign main_maccore_liteethphymiitx_source_source_first = main_maccore_liteethphymiitx_converter_source_first; +assign main_maccore_liteethphymiitx_source_source_last = main_maccore_liteethphymiitx_converter_source_last; +assign main_maccore_liteethphymiitx_source_source_payload_data = main_maccore_liteethphymiitx_converter_source_payload_data; +assign main_maccore_liteethphymiitx_converter_first = (main_maccore_liteethphymiitx_converter_mux == 1'd0); +assign main_maccore_liteethphymiitx_converter_last = (main_maccore_liteethphymiitx_converter_mux == 1'd1); +assign main_maccore_liteethphymiitx_converter_source_valid = main_maccore_liteethphymiitx_converter_sink_valid; +assign main_maccore_liteethphymiitx_converter_source_first = (main_maccore_liteethphymiitx_converter_sink_first & main_maccore_liteethphymiitx_converter_first); +assign main_maccore_liteethphymiitx_converter_source_last = (main_maccore_liteethphymiitx_converter_sink_last & main_maccore_liteethphymiitx_converter_last); +assign main_maccore_liteethphymiitx_converter_sink_ready = (main_maccore_liteethphymiitx_converter_last & main_maccore_liteethphymiitx_converter_source_ready); +always @(*) begin + main_maccore_liteethphymiitx_converter_source_payload_data <= 4'd0; + case (main_maccore_liteethphymiitx_converter_mux) + 1'd0: begin + main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[3:0]; + end + default: begin + main_maccore_liteethphymiitx_converter_source_payload_data <= main_maccore_liteethphymiitx_converter_sink_payload_data[7:4]; + end + endcase +end +assign main_maccore_liteethphymiitx_converter_source_payload_valid_token_count = main_maccore_liteethphymiitx_converter_last; +assign main_maccore_liteethphymiirx_converter_sink_last = (~mii_rx_dv); +assign main_maccore_liteethphymiirx_source_valid = main_maccore_liteethphymiirx_source_source_valid; +assign main_maccore_liteethphymiirx_source_source_ready = main_maccore_liteethphymiirx_source_ready; +assign main_maccore_liteethphymiirx_source_first = main_maccore_liteethphymiirx_source_source_first; +assign main_maccore_liteethphymiirx_source_last = main_maccore_liteethphymiirx_source_source_last; +assign main_maccore_liteethphymiirx_source_payload_data = main_maccore_liteethphymiirx_source_source_payload_data; +assign main_maccore_liteethphymiirx_source_source_valid = main_maccore_liteethphymiirx_converter_source_valid; +assign main_maccore_liteethphymiirx_converter_source_ready = main_maccore_liteethphymiirx_source_source_ready; +assign main_maccore_liteethphymiirx_source_source_first = main_maccore_liteethphymiirx_converter_source_first; +assign main_maccore_liteethphymiirx_source_source_last = main_maccore_liteethphymiirx_converter_source_last; +assign main_maccore_liteethphymiirx_source_source_payload_data = main_maccore_liteethphymiirx_converter_source_payload_data; +assign main_maccore_liteethphymiirx_converter_sink_ready = ((~main_maccore_liteethphymiirx_converter_strobe_all) | main_maccore_liteethphymiirx_converter_source_ready); +assign main_maccore_liteethphymiirx_converter_source_valid = main_maccore_liteethphymiirx_converter_strobe_all; +assign main_maccore_liteethphymiirx_converter_load_part = (main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready); +assign mii_mdc = main_maccore__w_storage[0]; +assign main_maccore_data_oe = main_maccore__w_storage[1]; +assign main_maccore_data_w = main_maccore__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_liteethphymiitx_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_liteethphymiitx_sink_ready; +assign main_maccore_liteethphymiitx_sink_first = main_tx_gap_source_first; +assign main_maccore_liteethphymiitx_sink_last = main_tx_gap_source_last; +assign main_maccore_liteethphymiitx_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_liteethphymiitx_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_liteethphymiitx_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); @@ -1413,72 +2037,70 @@ assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmacc assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; -end -always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); -assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out; -assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be; always @(*) begin - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error); + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error); assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid; -assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0; -assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg; -assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]}); -assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32checker_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); end assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; @@ -1497,12 +2119,12 @@ assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteet assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; - end + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); @@ -1512,126 +2134,99 @@ assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32 assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; - case (builder_liteethmaccrc32checker_state) - 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready); -assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); -assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); -assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); -always @(*) begin - main_padding_inserter_source_valid <= 1'd0; - main_padding_inserter_source_first <= 1'd0; - main_padding_inserter_source_last <= 1'd0; - main_padding_inserter_source_payload_data <= 8'd0; - main_padding_inserter_source_payload_last_be <= 1'd0; - main_padding_inserter_source_payload_error <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - main_padding_inserter_sink_ready <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; - case (builder_liteethmacpaddinginserter_state) - 1'd1: begin - main_padding_inserter_source_valid <= 1'd1; - main_padding_inserter_source_last <= main_padding_inserter_counter_done; - main_padding_inserter_source_payload_data <= 1'd0; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_counter_done) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; - main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; - main_padding_inserter_source_first <= main_padding_inserter_sink_first; - main_padding_inserter_source_last <= main_padding_inserter_sink_last; - main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; - main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; - main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_sink_last) begin - if ((~main_padding_inserter_counter_done)) begin - main_padding_inserter_source_last <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign main_padding_checker_source_valid = main_padding_checker_sink_valid; -assign main_padding_checker_sink_ready = main_padding_checker_source_ready; -assign main_padding_checker_source_first = main_padding_checker_sink_first; -assign main_padding_checker_source_last = main_padding_checker_sink_last; -assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; -assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; -assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; -always @(*) begin - main_tx_last_be_source_valid <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - builder_liteethmactxlastbe_next_state <= 1'd0; - builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state; - case (builder_liteethmactxlastbe_state) - 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin - builder_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase -end + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; assign main_rx_last_be_source_first = main_rx_last_be_sink_first; @@ -1639,63 +2234,12 @@ assign main_rx_last_be_source_last = main_rx_last_be_sink_last; assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end end -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; -always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; -end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); -always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) - 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; @@ -1706,25 +2250,25 @@ assign main_rx_converter_source_first = main_rx_converter_source_source_first; assign main_rx_converter_source_last = main_rx_converter_source_source_last; assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; end assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; @@ -1734,63 +2278,6 @@ assign main_rx_converter_source_source_payload_data = main_rx_converter_converte assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; @@ -1831,100 +2318,51 @@ assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; - end + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end end assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; - end + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end end assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; -assign main_padding_inserter_sink_first = main_tx_last_be_source_first; -assign main_padding_inserter_sink_last = main_tx_last_be_source_last; -assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; -assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; -assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; -assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; -assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; -assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; -assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; -assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid; -assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready; -assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first; -assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last; -assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; -assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; -assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; -assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; -assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; -assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; -assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; -assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; -assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; -assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_valid = main_tx_gap_inserter_source_valid; -assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_liteethphymiitx_sink_sink_ready; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_first = main_tx_gap_inserter_source_first; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_last = main_tx_gap_inserter_source_last; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_data = main_tx_gap_inserter_source_payload_data; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; -assign main_maccore_ethphy_liteethphymiitx_sink_sink_payload_error = main_tx_gap_inserter_source_payload_error; -assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphymiirx_source_source_valid; -assign main_maccore_ethphy_liteethphymiirx_source_source_ready = main_preamble_checker_sink_ready; -assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphymiirx_source_source_first; -assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphymiirx_source_source_last; -assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphymiirx_source_source_payload_data; -assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphymiirx_source_source_payload_last_be; -assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphymiirx_source_source_payload_error; -assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid; -assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready; -assign main_crc32_checker_sink_first = main_preamble_checker_source_first; -assign main_crc32_checker_sink_last = main_preamble_checker_source_last; -assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data; -assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be; -assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error; -assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready; -assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; -assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_padding_checker_source_first; -assign main_rx_last_be_sink_last = main_padding_checker_source_last; -assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; +assign main_rx_preamble_sink_valid = main_maccore_liteethphymiirx_source_valid; +assign main_maccore_liteethphymiirx_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_liteethphymiirx_source_first; +assign main_rx_preamble_sink_last = main_maccore_liteethphymiirx_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_liteethphymiirx_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_liteethphymiirx_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_liteethphymiirx_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; assign main_rx_converter_sink_first = main_rx_last_be_source_first; @@ -1939,1529 +2377,1700 @@ assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_writer_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_writer_sink_sink_ready; -assign main_writer_sink_sink_first = main_sink_first; -assign main_writer_sink_sink_last = main_sink_last; -assign main_writer_sink_sink_payload_data = main_sink_payload_data; -assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_writer_sink_sink_payload_error = main_sink_payload_error; -assign main_source_valid = main_reader_source_source_valid; -assign main_reader_source_source_ready = main_source_ready; -assign main_source_first = main_reader_source_source_first; -assign main_source_last = main_reader_source_source_last; -assign main_source_payload_data = main_reader_source_source_payload_data; -assign main_source_payload_last_be = main_reader_source_source_payload_last_be; -assign main_source_payload_error = main_reader_source_source_payload_error; -always @(*) begin - main_writer_inc <= 3'd0; - case (main_writer_sink_sink_payload_last_be) - 1'd1: begin - main_writer_inc <= 1'd1; - end - 2'd2: begin - main_writer_inc <= 2'd2; - end - 3'd4: begin - main_writer_inc <= 2'd3; - end - default: begin - main_writer_inc <= 3'd4; - end - endcase -end -assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot; -assign main_writer_stat_fifo_sink_payload_length = main_writer_counter; -assign main_writer_stat_fifo_source_ready = main_writer_available_clear; -assign main_writer_available_trigger = main_writer_stat_fifo_source_valid; -assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot; -assign main_writer_length_status = main_writer_stat_fifo_source_payload_length; -always @(*) begin - main_writer_memory0_we <= 1'd0; - main_writer_memory0_dat_w <= 32'd0; - main_writer_memory1_adr <= 9'd0; - main_writer_memory1_we <= 1'd0; - main_writer_memory0_adr <= 9'd0; - main_writer_memory1_dat_w <= 32'd0; - case (main_writer_slot) - 1'd0: begin - main_writer_memory0_adr <= main_writer_counter[31:2]; - main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - main_writer_memory1_adr <= main_writer_counter[31:2]; - main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory1_we <= 4'd15; - end - end - endcase -end -assign main_writer_available0 = main_writer_available_status; -assign main_writer_available1 = main_writer_available_pending; -always @(*) begin - main_writer_available_clear <= 1'd0; - if ((main_writer_pending_re & main_writer_pending_r)) begin - main_writer_available_clear <= 1'd1; - end -end -assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage); -assign main_writer_available_status = main_writer_available_trigger; -assign main_writer_available_pending = main_writer_available_trigger; -assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot}; -assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout; -assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable; -assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid; -assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first; -assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last; -assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot; -assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length; -assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable; -assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first; -assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last; -assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot; -assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length; -assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready; -always @(*) begin - main_writer_stat_fifo_wrport_adr <= 1'd0; - if (main_writer_stat_fifo_replace) begin - main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1); - end else begin - main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce; - end -end -assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din; -assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace)); -assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re); -assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume; -assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r; -assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2); -assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0); -always @(*) begin - main_writer_start <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd0; - main_writer_ongoing <= 1'd0; - main_writer_slot_ce <= 1'd0; - main_writer_errors_status_f_next_value <= 32'd0; - main_writer_stat_fifo_sink_valid <= 1'd0; - main_writer_errors_status_f_next_value_ce <= 1'd0; - builder_liteethmacsramwriter_next_state <= 3'd0; - main_writer_counter_t_next_value <= 32'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) - 1'd1: begin - if (main_writer_sink_sink_valid) begin - if ((main_writer_counter == 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; - end else begin - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_ongoing <= 1'd1; - end - if (main_writer_sink_sink_last) begin - if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd2; - end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_slot_ce <= 1'd1; - main_writer_stat_fifo_sink_valid <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (main_writer_sink_sink_valid) begin - if (main_writer_stat_fifo_sink_ready) begin - main_writer_start <= 1'd1; - main_writer_ongoing <= 1'd1; - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd1; - end else begin - main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); - main_writer_errors_status_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re; -assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage; -assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage; -assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready; -assign main_reader_level_status = main_reader_cmd_fifo_level; -always @(*) begin - main_reader_source_source_payload_last_be <= 4'd0; - if (main_reader_source_source_last) begin - case (main_reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - main_reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - main_reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - main_reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - main_reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign main_reader_memory0_adr = main_reader_read_address[10:2]; -assign main_reader_memory1_adr = main_reader_read_address[10:2]; -always @(*) begin - main_reader_source_source_payload_data <= 32'd0; - case (main_reader_cmd_fifo_source_payload_slot) - 1'd0: begin - main_reader_source_source_payload_data <= main_reader_memory0_dat_r; - end - 1'd1: begin - main_reader_source_source_payload_data <= main_reader_memory1_dat_r; - end - endcase -end -assign main_reader_event00 = main_reader_eventsourcepulse_status; -assign main_reader_event01 = main_reader_eventsourcepulse_pending; -always @(*) begin - main_reader_eventsourcepulse_clear <= 1'd0; - if ((main_reader_pending_re & main_reader_pending_r)) begin - main_reader_eventsourcepulse_clear <= 1'd1; - end -end -assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage); -assign main_reader_eventsourcepulse_status = 1'd0; -assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot}; -assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout; -assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable; -assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid; -assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first; -assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last; -assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot; -assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length; -assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable; -assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first; -assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last; -assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot; -assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length; -assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready; -always @(*) begin - main_reader_cmd_fifo_wrport_adr <= 1'd0; - if (main_reader_cmd_fifo_replace) begin - main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1); - end else begin - main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce; - end -end -assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din; -assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace)); -assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re); -assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume; -assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r; -assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2); -assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0); -always @(*) begin - main_reader_source_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= 2'd0; - main_reader_counter_next_value <= 11'd0; - main_reader_read_address <= 11'd0; - main_reader_counter_next_value_ce <= 1'd0; - main_reader_cmd_fifo_source_ready <= 1'd0; - main_reader_eventsourcepulse_trigger <= 1'd0; - main_reader_source_source_valid <= 1'd0; - main_reader_start <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) - 1'd1: begin - main_reader_source_source_valid <= 1'd1; - main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4)); - main_reader_read_address <= main_reader_counter; - if (main_reader_source_source_ready) begin - main_reader_read_address <= (main_reader_counter + 3'd4); - main_reader_counter_next_value <= (main_reader_counter + 3'd4); - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_source_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - main_reader_eventsourcepulse_trigger <= 1'd1; - main_reader_cmd_fifo_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - main_reader_counter_next_value <= 1'd0; - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_cmd_fifo_source_valid) begin - main_reader_start <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign main_ev_irq = (main_writer_irq | main_reader_irq); -assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; -assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; -assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; -assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; -always @(*) begin - main_sram0_we <= 4'd0; - main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); - main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); - main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); - main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); -end -assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; -assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; -assign main_sram0_dat_w = main_sram0_bus_dat_w1; -always @(*) begin - main_sram1_we <= 4'd0; - main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); - main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); - main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); - main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); -end -assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; -assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; -assign main_sram1_dat_w = main_sram1_bus_dat_w1; -always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); -end -assign main_sram0_bus_adr0 = main_bus_adr; -assign main_sram0_bus_dat_w0 = main_bus_dat_w; -assign main_sram0_bus_sel0 = main_bus_sel; -assign main_sram0_bus_stb0 = main_bus_stb; -assign main_sram0_bus_we0 = main_bus_we; -assign main_sram0_bus_cti0 = main_bus_cti; -assign main_sram0_bus_bte0 = main_bus_bte; -assign main_sram1_bus_adr0 = main_bus_adr; -assign main_sram1_bus_dat_w0 = main_bus_dat_w; -assign main_sram1_bus_sel0 = main_bus_sel; -assign main_sram1_bus_stb0 = main_bus_stb; -assign main_sram1_bus_we0 = main_bus_we; -assign main_sram1_bus_cti0 = main_bus_cti; -assign main_sram1_bus_bte0 = main_bus_bte; -assign main_sram0_bus_adr1 = main_bus_adr; -assign main_sram0_bus_dat_w1 = main_bus_dat_w; -assign main_sram0_bus_sel1 = main_bus_sel; -assign main_sram0_bus_stb1 = main_bus_stb; -assign main_sram0_bus_we1 = main_bus_we; -assign main_sram0_bus_cti1 = main_bus_cti; -assign main_sram0_bus_bte1 = main_bus_bte; -assign main_sram1_bus_adr1 = main_bus_adr; -assign main_sram1_bus_dat_w1 = main_bus_dat_w; -assign main_sram1_bus_sel1 = main_bus_sel; -assign main_sram1_bus_stb1 = main_bus_stb; -assign main_sram1_bus_we1 = main_bus_we; -assign main_sram1_bus_cti1 = main_bus_cti; -assign main_sram1_bus_bte1 = main_bus_bte; -assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); -assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); -assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); -assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); -assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); -always @(*) begin - builder_next_state <= 1'd0; - builder_maccore_wishbone_dat_r <= 32'd0; - builder_maccore_adr <= 14'd0; - builder_maccore_we <= 1'd0; - builder_maccore_wishbone_ack <= 1'd0; - builder_maccore_dat_w <= 32'd0; - builder_next_state <= builder_state; - case (builder_state) - 1'd1: begin - builder_maccore_wishbone_ack <= 1'd1; - builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; - builder_next_state <= 1'd0; - end - default: begin - builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; - if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin - builder_maccore_adr <= builder_maccore_wishbone_adr; - builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); - builder_next_state <= 1'd1; - end - end - endcase -end -assign builder_shared_adr = builder_array_muxed0; -assign builder_shared_dat_w = builder_array_muxed1; -assign builder_shared_sel = builder_array_muxed2; -assign builder_shared_cyc = builder_array_muxed3; -assign builder_shared_stb = builder_array_muxed4; -assign builder_shared_we = builder_array_muxed5; -assign builder_shared_cti = builder_array_muxed6; -assign builder_shared_bte = builder_array_muxed7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; -always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); -end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_maccore_wishbone_adr = builder_shared_adr; -assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; -assign builder_maccore_wishbone_sel = builder_shared_sel; -assign builder_maccore_wishbone_stb = builder_shared_stb; -assign builder_maccore_wishbone_we = builder_shared_we; -assign builder_maccore_wishbone_cti = builder_shared_cti; -assign builder_maccore_wishbone_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); -always @(*) begin - builder_shared_ack <= 1'd0; - builder_error <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; - end +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase end -assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_re <= 1'd0; - builder_csrbank0_reset0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_scratch0_we <= 1'd0; - builder_csrbank0_scratch0_re <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; - end + main_maccore_soc_rst <= 1'd0; + if (main_maccore_reset_re) begin + main_maccore_soc_rst <= main_maccore_reset_storage[0]; + end end -assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; -assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; -assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; -assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; -assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign main_maccore_cpu_rst = main_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_bus_errors_status[31:0]; +assign main_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_we <= 1'd0; - builder_csrbank1_sram_writer_slot_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank1_sram_writer_errors_re <= 1'd0; - builder_csrbank1_sram_writer_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end -assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0]; +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_reader_start_start_re <= 1'd0; - main_reader_start_start_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_reader_start_start_re <= builder_interface1_bank_bus_we; - main_reader_start_start_we <= (~builder_interface1_bank_bus_we); - end + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_we <= 1'd0; - builder_csrbank1_sram_reader_ready_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_we <= 1'd0; - builder_csrbank1_sram_reader_level_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_re <= 1'd0; - builder_csrbank1_sram_reader_length0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_we <= 1'd0; - builder_csrbank1_preamble_crc_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_preamble_errors_re <= 1'd0; - builder_csrbank1_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_crc_errors_re <= 1'd0; - builder_csrbank1_crc_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; -assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; -assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; -assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; -assign main_writer_status_status = main_writer_available0; -assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status; -assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we; -assign main_writer_pending_status = main_writer_available1; -assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status; -assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_writer_available2 = main_writer_enable_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage; -assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; -assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; -assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; -assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; -assign main_reader_status_status = main_reader_event00; -assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status; -assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we; -assign main_reader_pending_status = main_reader_event01; -assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status; -assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_reader_event02 = main_reader_enable_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage; -assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; -assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; -assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_crc_errors_we; + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_re <= 1'd0; - builder_csrbank2_crg_reset0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_we <= 1'd0; - builder_csrbank2_mdio_w0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); - end -end -assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; -assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; -assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; -assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; -assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; -assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; -assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_csr_interconnect_adr = builder_maccore_adr; -assign builder_csr_interconnect_we = builder_maccore_we; -assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; -assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; -assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -always @(*) begin - builder_array_muxed0 <= 30'd0; - case (builder_grant) - default: begin - builder_array_muxed0 <= main_wb_bus_adr; - end - endcase -end -always @(*) begin - builder_array_muxed1 <= 32'd0; - case (builder_grant) - default: begin - builder_array_muxed1 <= main_wb_bus_dat_w; - end - endcase -end -always @(*) begin - builder_array_muxed2 <= 4'd0; - case (builder_grant) - default: begin - builder_array_muxed2 <= main_wb_bus_sel; - end - endcase -end -always @(*) begin - builder_array_muxed3 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed3 <= main_wb_bus_cyc; - end - endcase -end -always @(*) begin - builder_array_muxed4 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed4 <= main_wb_bus_stb; - end - endcase -end -always @(*) begin - builder_array_muxed5 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed5 <= main_wb_bus_we; - end - endcase -end -always @(*) begin - builder_array_muxed6 <= 3'd0; - case (builder_grant) - default: begin - builder_array_muxed6 <= main_wb_bus_cti; - end - endcase -end -always @(*) begin - builder_array_muxed7 <= 2'd0; - case (builder_grant) - default: begin - builder_array_muxed7 <= main_wb_bus_bte; - end - endcase -end -always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl0_regs1; -end -assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; -assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_w = main_maccore_crg_reset_storage; +assign main_maccore_mdc = main_maccore__w_storage[0]; +assign main_maccore_oe = main_maccore__w_storage[1]; +assign main_maccore_w = main_maccore__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore__r_status; +assign main_maccore__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +always @(*) begin + main_maccore__r_status <= 1'd0; + main_maccore__r_status <= main_maccore_r; + main_maccore__r_status <= builder_xilinxmultiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_liteethphymiirx_converter_reset <= (~mii_eth_rx_dv); - main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd1; - main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data <= mii_eth_rx_data; - if (main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - if (((main_maccore_ethphy_liteethphymiirx_converter_converter_demux == 1'd1) | main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd1; - end else begin - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); - end - end - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_source_ready)) begin - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last; - end else begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_maccore_ethphy_liteethphymiirx_converter_converter_sink_valid & main_maccore_ethphy_liteethphymiirx_converter_converter_sink_ready)) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_first <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_first | main_maccore_ethphy_liteethphymiirx_converter_converter_source_first); - main_maccore_ethphy_liteethphymiirx_converter_converter_source_last <= (main_maccore_ethphy_liteethphymiirx_converter_converter_sink_last | main_maccore_ethphy_liteethphymiirx_converter_converter_source_last); - end - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - case (main_maccore_ethphy_liteethphymiirx_converter_converter_demux) - 1'd0: begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[3:0] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data[7:4] <= main_maccore_ethphy_liteethphymiirx_converter_converter_sink_payload_data; - end - endcase - end - if (main_maccore_ethphy_liteethphymiirx_converter_converter_load_part) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= (main_maccore_ethphy_liteethphymiirx_converter_converter_demux + 1'd1); - end - if (main_maccore_ethphy_liteethphymiirx_converter_reset) begin - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - end - builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next; - end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; - if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin - main_crc32_checker_source_valid <= main_crc32_checker_sink_valid; - main_crc32_checker_source_first <= main_crc32_checker_sink_first; - main_crc32_checker_source_last <= main_crc32_checker_sink_last; - main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data; - main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be; - main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error; - end - if (main_ps_preamble_error_i) begin - main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); - end - if (main_ps_crc_error_i) begin - main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); - end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; - end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; - end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); - end - end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; - end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); - end - end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) - 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; - end - 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; - end - 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; - end - endcase - end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); - end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - main_maccore_ethphy_liteethphymiirx_converter_sink_valid <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_sink_payload_data <= 4'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_demux <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_converter_strobe_all <= 1'd0; - main_maccore_ethphy_liteethphymiirx_converter_reset <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_crc32_checker_source_valid <= 1'd0; - main_crc32_checker_source_payload_data <= 8'd0; - main_crc32_checker_source_payload_last_be <= 1'd0; - main_crc32_checker_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_liteethmacpreamblechecker_state <= 1'd0; - builder_liteethmaccrc32checker_state <= 2'd0; - end - builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; + main_maccore_liteethphymiirx_reset <= (~mii_rx_dv); + main_maccore_liteethphymiirx_converter_sink_valid <= 1'd1; + main_maccore_liteethphymiirx_converter_sink_payload_data <= mii_rx_data; + if (main_maccore_liteethphymiirx_converter_source_ready) begin + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + if (((main_maccore_liteethphymiirx_converter_demux == 1'd1) | main_maccore_liteethphymiirx_converter_sink_last)) begin + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd1; + end else begin + main_maccore_liteethphymiirx_converter_demux <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + end + end + if ((main_maccore_liteethphymiirx_converter_source_valid & main_maccore_liteethphymiirx_converter_source_ready)) begin + if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin + main_maccore_liteethphymiirx_converter_source_first <= main_maccore_liteethphymiirx_converter_sink_first; + main_maccore_liteethphymiirx_converter_source_last <= main_maccore_liteethphymiirx_converter_sink_last; + end else begin + main_maccore_liteethphymiirx_converter_source_first <= 1'd0; + main_maccore_liteethphymiirx_converter_source_last <= 1'd0; + end + end else begin + if ((main_maccore_liteethphymiirx_converter_sink_valid & main_maccore_liteethphymiirx_converter_sink_ready)) begin + main_maccore_liteethphymiirx_converter_source_first <= (main_maccore_liteethphymiirx_converter_sink_first | main_maccore_liteethphymiirx_converter_source_first); + main_maccore_liteethphymiirx_converter_source_last <= (main_maccore_liteethphymiirx_converter_sink_last | main_maccore_liteethphymiirx_converter_source_last); + end + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + case (main_maccore_liteethphymiirx_converter_demux) + 1'd0: begin + main_maccore_liteethphymiirx_converter_source_payload_data[3:0] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + end + 1'd1: begin + main_maccore_liteethphymiirx_converter_source_payload_data[7:4] <= main_maccore_liteethphymiirx_converter_sink_payload_data; + end + endcase + end + if (main_maccore_liteethphymiirx_converter_load_part) begin + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= (main_maccore_liteethphymiirx_converter_demux + 1'd1); + end + if (main_maccore_liteethphymiirx_reset) begin + main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_liteethphymiirx_converter_sink_valid <= 1'd0; + main_maccore_liteethphymiirx_converter_sink_payload_data <= 4'd0; + main_maccore_liteethphymiirx_converter_source_payload_data <= 8'd0; + main_maccore_liteethphymiirx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_liteethphymiirx_converter_demux <= 1'd0; + main_maccore_liteethphymiirx_converter_strobe_all <= 1'd0; + main_maccore_liteethphymiirx_reset <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - mii_eth_tx_en <= main_maccore_ethphy_liteethphymiitx_converter_source_valid; - mii_eth_tx_data <= main_maccore_ethphy_liteethphymiitx_converter_source_payload_data; - if ((main_maccore_ethphy_liteethphymiitx_converter_converter_source_valid & main_maccore_ethphy_liteethphymiitx_converter_converter_source_ready)) begin - if (main_maccore_ethphy_liteethphymiitx_converter_converter_last) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; - end else begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= (main_maccore_ethphy_liteethphymiitx_converter_converter_mux + 1'd1); - end - end - builder_liteethmacgap_state <= builder_liteethmacgap_next_state; - if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value; - end - builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; - if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (main_liteethmaccrc32inserter_is_ongoing0) begin - main_liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin - main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); - end - end - if (main_liteethmaccrc32inserter_ce) begin - main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; - end - if (main_liteethmaccrc32inserter_reset) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - end - builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; - if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin - main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; - main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; - main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; - main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; - main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; - main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; - end - builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; - if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; - end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); - end - end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - main_maccore_ethphy_liteethphymiitx_converter_converter_mux <= 1'd0; - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - main_liteethmaccrc32inserter_cnt <= 2'd3; - main_crc32_inserter_source_valid <= 1'd0; - main_crc32_inserter_source_payload_data <= 8'd0; - main_crc32_inserter_source_payload_last_be <= 1'd0; - main_crc32_inserter_source_payload_error <= 1'd0; - main_padding_inserter_counter <= 16'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - builder_liteethmacgap_state <= 1'd0; - builder_liteethmacpreambleinserter_state <= 2'd0; - builder_liteethmaccrc32inserter_state <= 2'd0; - builder_liteethmacpaddinginserter_state <= 1'd0; - builder_liteethmactxlastbe_state <= 1'd0; - end - builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; + mii_tx_en <= main_maccore_liteethphymiitx_source_source_valid; + mii_tx_data <= main_maccore_liteethphymiitx_source_source_payload_data; + if ((main_maccore_liteethphymiitx_converter_source_valid & main_maccore_liteethphymiitx_converter_source_ready)) begin + if (main_maccore_liteethphymiitx_converter_last) begin + main_maccore_liteethphymiitx_converter_mux <= 1'd0; + end else begin + main_maccore_liteethphymiitx_converter_mux <= (main_maccore_liteethphymiitx_converter_mux + 1'd1); + end + end + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_maccore_liteethphymiitx_converter_mux <= 1'd0; + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); - end - end - if (main_maccore_ethphy_counter_ce) begin - main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); - end - if (main_ps_preamble_error_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); - end - if (main_ps_crc_error_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); - end - main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; - main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (main_writer_slot_ce) begin - main_writer_slot <= (main_writer_slot + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1); - end - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - if ((~main_writer_stat_fifo_do_read)) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1); - end - end else begin - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1); - end - end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_writer_counter_t_next_value_ce) begin - main_writer_counter <= main_writer_counter_t_next_value; - end - if (main_writer_errors_status_f_next_value_ce) begin - main_writer_errors_status <= main_writer_errors_status_f_next_value; - end - if (main_reader_eventsourcepulse_clear) begin - main_reader_eventsourcepulse_pending <= 1'd0; - end - if (main_reader_eventsourcepulse_trigger) begin - main_reader_eventsourcepulse_pending <= 1'd1; - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1); - end - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1); - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - if ((~main_reader_cmd_fifo_do_read)) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1); - end - end else begin - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1); - end - end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_reader_counter_next_value_ce) begin - main_reader_counter <= main_reader_counter_next_value; - end - main_sram0_bus_ack0 <= 1'd0; - if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin - main_sram0_bus_ack0 <= 1'd1; - end - main_sram1_bus_ack0 <= 1'd0; - if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin - main_sram1_bus_ack0 <= 1'd1; - end - main_sram0_bus_ack1 <= 1'd0; - if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin - main_sram0_bus_ack1 <= 1'd1; - end - main_sram1_bus_ack1 <= 1'd0; - if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin - main_sram1_bus_ack1 <= 1'd1; - end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); - end - end else begin - builder_count <= 20'd1000000; - end - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; - end - 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; - end - 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; - end - endcase - end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; - end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; - end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; - end - 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_reader_start_start_w; - end - 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; - end - 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; - end - 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; - end - 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; - end - endcase - end - main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re; - main_writer_length_re <= builder_csrbank1_sram_writer_length_re; - main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re; - main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r; - end - main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r; - end - main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re; - main_reader_level_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; - end - main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; - end - main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; - main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r; - end - main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r; - end - main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_preamble_crc_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; - end - 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; - end - 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; - end - endcase - end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; - end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; - end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; - if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy_counter <= 9'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_preamble_crc_re <= 1'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_writer_slot_re <= 1'd0; - main_writer_length_re <= 1'd0; - main_writer_errors_status <= 32'd0; - main_writer_errors_re <= 1'd0; - main_writer_status_re <= 1'd0; - main_writer_pending_re <= 1'd0; - main_writer_pending_r <= 1'd0; - main_writer_enable_storage <= 1'd0; - main_writer_enable_re <= 1'd0; - main_writer_counter <= 32'd0; - main_writer_slot <= 1'd0; - main_writer_stat_fifo_level <= 2'd0; - main_writer_stat_fifo_produce <= 1'd0; - main_writer_stat_fifo_consume <= 1'd0; - main_reader_ready_re <= 1'd0; - main_reader_level_re <= 1'd0; - main_reader_slot_re <= 1'd0; - main_reader_length_re <= 1'd0; - main_reader_eventsourcepulse_pending <= 1'd0; - main_reader_status_re <= 1'd0; - main_reader_pending_re <= 1'd0; - main_reader_pending_r <= 1'd0; - main_reader_enable_storage <= 1'd0; - main_reader_enable_re <= 1'd0; - main_reader_cmd_fifo_level <= 2'd0; - main_reader_cmd_fifo_produce <= 1'd0; - main_reader_cmd_fifo_consume <= 1'd0; - main_reader_counter <= 11'd0; - main_sram0_bus_ack0 <= 1'd0; - main_sram1_bus_ack0 <= 1'd0; - main_sram0_bus_ack1 <= 1'd0; - main_sram1_bus_ack1 <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_state <= 1'd0; - end - builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; - builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; - builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; - builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; - builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; - builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; - builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_bus_error) begin + main_maccore_bus_errors <= (main_maccore_bus_errors + 1'd1); + end + end + if (main_maccore_crg_counter_ce) begin + main_maccore_crg_counter <= (main_maccore_crg_counter + 1'd1); + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_crg_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_crg_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_reset_storage <= 2'd0; + main_maccore_reset_re <= 1'd0; + main_maccore_scratch_storage <= 32'd305419896; + main_maccore_scratch_re <= 1'd0; + main_maccore_bus_errors_re <= 1'd0; + main_maccore_bus_errors <= 32'd0; + main_maccore_crg_reset_storage <= 1'd0; + main_maccore_crg_reset_re <= 1'd0; + main_maccore_crg_counter <= 9'd0; + main_maccore__w_storage <= 3'd0; + main_maccore__w_re <= 1'd0; + main_maccore__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_data_r; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; + builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; end -assign mii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = mii_eth_mdio; - -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr]; -end -always @(posedge eth_rx_clk) begin -end +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr]; +assign mii_mdio = main_maccore_data_oe ? main_maccore_data_w : 1'bz; +assign main_maccore_data_r = mii_mdio; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; always @(posedge sys_clk) begin if (main_tx_cdc_cdc_wrport_we) - storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - memadr <= main_tx_cdc_cdc_wrport_adr; + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - always @(posedge eth_tx_clk) begin - memadr_1 <= main_tx_cdc_cdc_rdport_adr; + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign main_tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign main_tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +end +always @(posedge eth_rx_clk) begin +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin if (main_rx_cdc_cdc_wrport_we) storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - memadr_2 <= main_rx_cdc_cdc_wrport_adr; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= main_rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign main_rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_writer_stat_fifo_wrport_we) - storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[main_writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign main_writer_stat_fifo_wrport_dat_r = memdat_1; -assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_writer_memory0_we) - mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; - memadr_4 <= main_writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[main_sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign main_writer_memory0_dat_r = mem[memadr_4]; -assign main_sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_writer_memory1_we) - mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; - memadr_5 <= main_writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[main_sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign main_writer_memory1_dat_r = mem_1[memadr_5]; -assign main_sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_reader_cmd_fifo_wrport_we) - storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign main_reader_cmd_fifo_wrport_dat_r = memdat_4; -assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= main_reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end - always @(posedge sys_clk) begin - if (main_sram0_we[0]) - mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; - if (main_sram0_we[1]) - mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; - if (main_sram0_we[2]) - mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; - if (main_sram0_we[3]) - mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; - memadr_7 <= main_sram0_adr1; -end + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; -assign main_reader_memory0_dat_r = mem_2[memadr_6]; -assign main_sram0_dat_r1 = mem_2[memadr_7]; -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - memadr_8 <= main_reader_memory1_adr; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; end - always @(posedge sys_clk) begin - if (main_sram1_we[0]) - mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; - if (main_sram1_we[1]) - mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; - if (main_sram1_we[2]) - mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; - if (main_sram1_we[3]) - mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; - memadr_9 <= main_sram1_adr1; -end + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; +end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -assign main_reader_memory1_dat_r = mem_3[memadr_8]; -assign main_sram1_dat_r1 = mem_3[memadr_9]; -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset0), - .Q(builder_rst_meta0) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (builder_rst_meta0) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(builder_rst_meta0), - .PRE(main_maccore_ethphy_reset0), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_rst_meta0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset0), - .Q(builder_rst_meta1) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (builder_rst_meta1) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(builder_rst_meta1), - .PRE(main_maccore_ethphy_reset0), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_rst_meta1), + .PRE (main_maccore_crg_reset0), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:49. +//------------------------------------------------------------------------------ diff --git a/liteeth/generated/nexys-video/liteeth_core.v b/liteeth/generated/nexys-video/liteeth_core.v index 6fd6fb3..1d780a9 100644 --- a/liteeth/generated/nexys-video/liteeth_core.v +++ b/liteeth/generated/nexys-video/liteeth_core.v @@ -1,1010 +1,1361 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - output wire rgmii_eth_clocks_tx, - input wire rgmii_eth_clocks_rx, - output wire rgmii_eth_rst_n, - input wire rgmii_eth_int_n, - inout wire rgmii_eth_mdio, - output wire rgmii_eth_mdc, - input wire rgmii_eth_rx_ctl, - input wire [3:0] rgmii_eth_rx_data, - output wire rgmii_eth_tx_ctl, - output wire [3:0] rgmii_eth_tx_data, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:49 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire rgmii_clocks_rx, + output wire rgmii_clocks_tx, + input wire rgmii_int_n, + output wire rgmii_mdc, + inout wire rgmii_mdio, + output wire rgmii_rst_n, + input wire rgmii_rx_ctl, + input wire [3:0] rgmii_rx_data, + output wire rgmii_tx_ctl, + output wire [3:0] rgmii_tx_data, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg main_maccore_maccore_soc_rst = 1'd0; -wire main_maccore_maccore_cpu_rst; -reg [1:0] main_maccore_maccore_reset_storage = 2'd0; -reg main_maccore_maccore_reset_re = 1'd0; -reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; -reg main_maccore_maccore_scratch_re = 1'd0; -wire [31:0] main_maccore_maccore_bus_errors_status; -wire main_maccore_maccore_bus_errors_we; -reg main_maccore_maccore_bus_errors_re = 1'd0; -wire main_maccore_maccore_bus_error; -reg [31:0] main_maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg main_maccore_int_rst = 1'd1; -reg main_maccore_ethphy_reset_storage = 1'd0; -reg main_maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -wire main_maccore_ethphy_eth_rx_clk_ibuf; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -wire eth_tx_delayed_clk; -reg main_maccore_ethphy_reset0 = 1'd0; -reg main_maccore_ethphy_power_down = 1'd0; -wire main_maccore_ethphy_locked; -wire main_maccore_ethphy_clkin; -wire main_maccore_ethphy_clkout0; -wire main_maccore_ethphy_clkout_buf0; -wire main_maccore_ethphy_clkout1; -wire main_maccore_ethphy_clkout_buf1; -wire main_maccore_ethphy_eth_tx_clk_obuf; -wire main_maccore_ethphy_reset1; -wire main_maccore_ethphy_sink_valid; -wire main_maccore_ethphy_sink_ready; -wire main_maccore_ethphy_sink_first; -wire main_maccore_ethphy_sink_last; -wire [7:0] main_maccore_ethphy_sink_payload_data; -wire main_maccore_ethphy_sink_payload_last_be; -wire main_maccore_ethphy_sink_payload_error; -wire main_maccore_ethphy_tx_ctl_obuf; -wire [3:0] main_maccore_ethphy_tx_data_obuf; -reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; -reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_source_last; -reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; -reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; -wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; -wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; -wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; -wire main_maccore_ethphy_liteethphyrgmiirx; -reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; -wire main_maccore_ethphy_liteethphyrgmiirx_last; -wire main_maccore_ethphy_mdc; -wire main_maccore_ethphy_oe; -wire main_maccore_ethphy_w; -reg [2:0] main_maccore_ethphy__w_storage = 3'd0; -reg main_maccore_ethphy__w_re = 1'd0; -reg main_maccore_ethphy_r = 1'd0; -reg main_maccore_ethphy__r_status = 1'd0; -wire main_maccore_ethphy__r_we; -reg main_maccore_ethphy__r_re = 1'd0; -wire main_maccore_ethphy_data_w; -wire main_maccore_ethphy_data_oe; -wire main_maccore_ethphy_data_r; -wire main_tx_gap_inserter_sink_valid; -reg main_tx_gap_inserter_sink_ready = 1'd0; -wire main_tx_gap_inserter_sink_first; -wire main_tx_gap_inserter_sink_last; -wire [7:0] main_tx_gap_inserter_sink_payload_data; -wire main_tx_gap_inserter_sink_payload_last_be; -wire main_tx_gap_inserter_sink_payload_error; -reg main_tx_gap_inserter_source_valid = 1'd0; -wire main_tx_gap_inserter_source_ready; -reg main_tx_gap_inserter_source_first = 1'd0; -reg main_tx_gap_inserter_source_last = 1'd0; -reg [7:0] main_tx_gap_inserter_source_payload_data = 8'd0; -reg main_tx_gap_inserter_source_payload_last_be = 1'd0; -reg main_tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] main_tx_gap_inserter_counter = 4'd0; -reg main_preamble_crc_status = 1'd1; -wire main_preamble_crc_we; -reg main_preamble_crc_re = 1'd0; -reg [31:0] main_preamble_errors_status = 32'd0; -wire main_preamble_errors_we; -reg main_preamble_errors_re = 1'd0; -reg [31:0] main_crc_errors_status = 32'd0; -wire main_crc_errors_we; -reg main_crc_errors_re = 1'd0; -wire main_preamble_inserter_sink_valid; -reg main_preamble_inserter_sink_ready = 1'd0; -wire main_preamble_inserter_sink_first; -wire main_preamble_inserter_sink_last; -wire [7:0] main_preamble_inserter_sink_payload_data; -wire main_preamble_inserter_sink_payload_last_be; -wire main_preamble_inserter_sink_payload_error; -reg main_preamble_inserter_source_valid = 1'd0; -wire main_preamble_inserter_source_ready; -reg main_preamble_inserter_source_first = 1'd0; -reg main_preamble_inserter_source_last = 1'd0; -reg [7:0] main_preamble_inserter_source_payload_data = 8'd0; -wire main_preamble_inserter_source_payload_last_be; -reg main_preamble_inserter_source_payload_error = 1'd0; -reg [63:0] main_preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] main_preamble_inserter_count = 3'd0; -wire main_preamble_checker_sink_valid; -reg main_preamble_checker_sink_ready = 1'd0; -wire main_preamble_checker_sink_first; -wire main_preamble_checker_sink_last; -wire [7:0] main_preamble_checker_sink_payload_data; -wire main_preamble_checker_sink_payload_last_be; -wire main_preamble_checker_sink_payload_error; -reg main_preamble_checker_source_valid = 1'd0; -wire main_preamble_checker_source_ready; -reg main_preamble_checker_source_first = 1'd0; -reg main_preamble_checker_source_last = 1'd0; -wire [7:0] main_preamble_checker_source_payload_data; -wire main_preamble_checker_source_payload_last_be; -reg main_preamble_checker_source_payload_error = 1'd0; -reg main_preamble_checker_error = 1'd0; -wire main_liteethmaccrc32inserter_sink_valid; -reg main_liteethmaccrc32inserter_sink_ready = 1'd0; -wire main_liteethmaccrc32inserter_sink_first; -wire main_liteethmaccrc32inserter_sink_last; -wire [7:0] main_liteethmaccrc32inserter_sink_payload_data; -wire main_liteethmaccrc32inserter_sink_payload_last_be; -wire main_liteethmaccrc32inserter_sink_payload_error; -reg main_liteethmaccrc32inserter_source_valid = 1'd0; -wire main_liteethmaccrc32inserter_source_ready; -reg main_liteethmaccrc32inserter_source_first = 1'd0; -reg main_liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_source_payload_data = 8'd0; -reg main_liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg main_liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] main_liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] main_liteethmaccrc32inserter_value; -wire main_liteethmaccrc32inserter_error; -wire [7:0] main_liteethmaccrc32inserter_data1; -wire [31:0] main_liteethmaccrc32inserter_last; -reg [31:0] main_liteethmaccrc32inserter_next = 32'd0; -reg [31:0] main_liteethmaccrc32inserter_reg = 32'd4294967295; -reg main_liteethmaccrc32inserter_ce = 1'd0; -reg main_liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] main_liteethmaccrc32inserter_cnt = 2'd3; -wire main_liteethmaccrc32inserter_cnt_done; -reg main_liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg main_liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire main_crc32_inserter_sink_valid; -wire main_crc32_inserter_sink_ready; -wire main_crc32_inserter_sink_first; -wire main_crc32_inserter_sink_last; -wire [7:0] main_crc32_inserter_sink_payload_data; -wire main_crc32_inserter_sink_payload_last_be; -wire main_crc32_inserter_sink_payload_error; -reg main_crc32_inserter_source_valid = 1'd0; -wire main_crc32_inserter_source_ready; -reg main_crc32_inserter_source_first = 1'd0; -reg main_crc32_inserter_source_last = 1'd0; -reg [7:0] main_crc32_inserter_source_payload_data = 8'd0; -reg main_crc32_inserter_source_payload_last_be = 1'd0; -reg main_crc32_inserter_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_valid; -reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire main_liteethmaccrc32checker_sink_sink_first; -wire main_liteethmaccrc32checker_sink_sink_last; -wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; -wire main_liteethmaccrc32checker_sink_sink_payload_last_be; -wire main_liteethmaccrc32checker_sink_sink_payload_error; -wire main_liteethmaccrc32checker_source_source_valid; -wire main_liteethmaccrc32checker_source_source_ready; -reg main_liteethmaccrc32checker_source_source_first = 1'd0; -wire main_liteethmaccrc32checker_source_source_last; -wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; -wire main_liteethmaccrc32checker_source_source_payload_last_be; -reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire main_liteethmaccrc32checker_error; -wire [7:0] main_liteethmaccrc32checker_crc_data0; -wire [31:0] main_liteethmaccrc32checker_crc_value; -wire main_liteethmaccrc32checker_crc_error; -wire [7:0] main_liteethmaccrc32checker_crc_data1; -wire [31:0] main_liteethmaccrc32checker_crc_last; -reg [31:0] main_liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg main_liteethmaccrc32checker_crc_ce = 1'd0; -reg main_liteethmaccrc32checker_crc_reset = 1'd0; -reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire main_liteethmaccrc32checker_syncfifo_sink_ready; -wire main_liteethmaccrc32checker_syncfifo_sink_first; -wire main_liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; -wire main_liteethmaccrc32checker_syncfifo_source_valid; -wire main_liteethmaccrc32checker_syncfifo_source_ready; -wire main_liteethmaccrc32checker_syncfifo_source_first; -wire main_liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; -wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_source_payload_error; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; -wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; -reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire main_liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire main_liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; -wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; -reg main_liteethmaccrc32checker_fifo_reset = 1'd0; -wire main_liteethmaccrc32checker_fifo_in; -wire main_liteethmaccrc32checker_fifo_out; -wire main_liteethmaccrc32checker_fifo_full; -wire main_crc32_checker_sink_valid; -wire main_crc32_checker_sink_ready; -wire main_crc32_checker_sink_first; -wire main_crc32_checker_sink_last; -wire [7:0] main_crc32_checker_sink_payload_data; -wire main_crc32_checker_sink_payload_last_be; -wire main_crc32_checker_sink_payload_error; -reg main_crc32_checker_source_valid = 1'd0; -wire main_crc32_checker_source_ready; -reg main_crc32_checker_source_first = 1'd0; -reg main_crc32_checker_source_last = 1'd0; -reg [7:0] main_crc32_checker_source_payload_data = 8'd0; -reg main_crc32_checker_source_payload_last_be = 1'd0; -reg main_crc32_checker_source_payload_error = 1'd0; -wire main_ps_preamble_error_i; -wire main_ps_preamble_error_o; -reg main_ps_preamble_error_toggle_i = 1'd0; -wire main_ps_preamble_error_toggle_o; -reg main_ps_preamble_error_toggle_o_r = 1'd0; -wire main_ps_crc_error_i; -wire main_ps_crc_error_o; -reg main_ps_crc_error_toggle_i = 1'd0; -wire main_ps_crc_error_toggle_o; -reg main_ps_crc_error_toggle_o_r = 1'd0; -wire main_padding_inserter_sink_valid; -reg main_padding_inserter_sink_ready = 1'd0; -wire main_padding_inserter_sink_first; -wire main_padding_inserter_sink_last; -wire [7:0] main_padding_inserter_sink_payload_data; -wire main_padding_inserter_sink_payload_last_be; -wire main_padding_inserter_sink_payload_error; -reg main_padding_inserter_source_valid = 1'd0; -wire main_padding_inserter_source_ready; -reg main_padding_inserter_source_first = 1'd0; -reg main_padding_inserter_source_last = 1'd0; -reg [7:0] main_padding_inserter_source_payload_data = 8'd0; -reg main_padding_inserter_source_payload_last_be = 1'd0; -reg main_padding_inserter_source_payload_error = 1'd0; -reg [15:0] main_padding_inserter_counter = 16'd0; -wire main_padding_inserter_counter_done; -wire main_padding_checker_sink_valid; -wire main_padding_checker_sink_ready; -wire main_padding_checker_sink_first; -wire main_padding_checker_sink_last; -wire [7:0] main_padding_checker_sink_payload_data; -wire main_padding_checker_sink_payload_last_be; -wire main_padding_checker_sink_payload_error; -wire main_padding_checker_source_valid; -wire main_padding_checker_source_ready; -wire main_padding_checker_source_first; -wire main_padding_checker_source_last; -wire [7:0] main_padding_checker_source_payload_data; -wire main_padding_checker_source_payload_last_be; -wire main_padding_checker_source_payload_error; -wire main_tx_last_be_sink_valid; -reg main_tx_last_be_sink_ready = 1'd0; -wire main_tx_last_be_sink_first; -wire main_tx_last_be_sink_last; -wire [7:0] main_tx_last_be_sink_payload_data; -wire main_tx_last_be_sink_payload_last_be; -wire main_tx_last_be_sink_payload_error; -reg main_tx_last_be_source_valid = 1'd0; -wire main_tx_last_be_source_ready; -reg main_tx_last_be_source_first = 1'd0; -reg main_tx_last_be_source_last = 1'd0; -reg [7:0] main_tx_last_be_source_payload_data = 8'd0; -reg main_tx_last_be_source_payload_last_be = 1'd0; -reg main_tx_last_be_source_payload_error = 1'd0; -wire main_rx_last_be_sink_valid; -wire main_rx_last_be_sink_ready; -wire main_rx_last_be_sink_first; -wire main_rx_last_be_sink_last; -wire [7:0] main_rx_last_be_sink_payload_data; -wire main_rx_last_be_sink_payload_last_be; -wire main_rx_last_be_sink_payload_error; -wire main_rx_last_be_source_valid; -wire main_rx_last_be_source_ready; -wire main_rx_last_be_source_first; -wire main_rx_last_be_source_last; -wire [7:0] main_rx_last_be_source_payload_data; -reg main_rx_last_be_source_payload_last_be = 1'd0; -wire main_rx_last_be_source_payload_error; -wire main_tx_converter_sink_valid; -wire main_tx_converter_sink_ready; -wire main_tx_converter_sink_first; -wire main_tx_converter_sink_last; -wire [31:0] main_tx_converter_sink_payload_data; -wire [3:0] main_tx_converter_sink_payload_last_be; -wire [3:0] main_tx_converter_sink_payload_error; -wire main_tx_converter_source_valid; -wire main_tx_converter_source_ready; -wire main_tx_converter_source_first; -wire main_tx_converter_source_last; -wire [7:0] main_tx_converter_source_payload_data; -wire main_tx_converter_source_payload_last_be; -wire main_tx_converter_source_payload_error; -wire main_tx_converter_converter_sink_valid; -wire main_tx_converter_converter_sink_ready; -wire main_tx_converter_converter_sink_first; -wire main_tx_converter_converter_sink_last; -reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; -wire main_tx_converter_converter_source_valid; -wire main_tx_converter_converter_source_ready; -wire main_tx_converter_converter_source_first; -wire main_tx_converter_converter_source_last; -reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; -wire main_tx_converter_converter_source_payload_valid_token_count; -reg [1:0] main_tx_converter_converter_mux = 2'd0; -wire main_tx_converter_converter_first; -wire main_tx_converter_converter_last; -wire main_tx_converter_source_source_valid; -wire main_tx_converter_source_source_ready; -wire main_tx_converter_source_source_first; -wire main_tx_converter_source_source_last; -wire [9:0] main_tx_converter_source_source_payload_data; -wire main_rx_converter_sink_valid; -wire main_rx_converter_sink_ready; -wire main_rx_converter_sink_first; -wire main_rx_converter_sink_last; -wire [7:0] main_rx_converter_sink_payload_data; -wire main_rx_converter_sink_payload_last_be; -wire main_rx_converter_sink_payload_error; -wire main_rx_converter_source_valid; -wire main_rx_converter_source_ready; -wire main_rx_converter_source_first; -wire main_rx_converter_source_last; -reg [31:0] main_rx_converter_source_payload_data = 32'd0; -reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; -reg [3:0] main_rx_converter_source_payload_error = 4'd0; -wire main_rx_converter_converter_sink_valid; -wire main_rx_converter_converter_sink_ready; -wire main_rx_converter_converter_sink_first; -wire main_rx_converter_converter_sink_last; -wire [9:0] main_rx_converter_converter_sink_payload_data; -wire main_rx_converter_converter_source_valid; -wire main_rx_converter_converter_source_ready; -reg main_rx_converter_converter_source_first = 1'd0; -reg main_rx_converter_converter_source_last = 1'd0; -reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] main_rx_converter_converter_demux = 2'd0; -wire main_rx_converter_converter_load_part; -reg main_rx_converter_converter_strobe_all = 1'd0; -wire main_rx_converter_source_source_valid; -wire main_rx_converter_source_source_ready; -wire main_rx_converter_source_source_first; -wire main_rx_converter_source_source_last; -wire [39:0] main_rx_converter_source_source_payload_data; -wire main_tx_cdc_sink_sink_valid; -wire main_tx_cdc_sink_sink_ready; -wire main_tx_cdc_sink_sink_first; -wire main_tx_cdc_sink_sink_last; -wire [31:0] main_tx_cdc_sink_sink_payload_data; -wire [3:0] main_tx_cdc_sink_sink_payload_last_be; -wire [3:0] main_tx_cdc_sink_sink_payload_error; -wire main_tx_cdc_source_source_valid; -wire main_tx_cdc_source_source_ready; -wire main_tx_cdc_source_source_first; -wire main_tx_cdc_source_source_last; -wire [31:0] main_tx_cdc_source_source_payload_data; -wire [3:0] main_tx_cdc_source_source_payload_last_be; -wire [3:0] main_tx_cdc_source_source_payload_error; -wire main_tx_cdc_cdc_sink_valid; -wire main_tx_cdc_cdc_sink_ready; -wire main_tx_cdc_cdc_sink_first; -wire main_tx_cdc_cdc_sink_last; -wire [31:0] main_tx_cdc_cdc_sink_payload_data; -wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_tx_cdc_cdc_sink_payload_error; -wire main_tx_cdc_cdc_source_valid; -wire main_tx_cdc_cdc_source_ready; -wire main_tx_cdc_cdc_source_first; -wire main_tx_cdc_cdc_source_last; -wire [31:0] main_tx_cdc_cdc_source_payload_data; -wire [3:0] main_tx_cdc_cdc_source_payload_last_be; -wire [3:0] main_tx_cdc_cdc_source_payload_error; -wire main_tx_cdc_cdc_asyncfifo_we; -wire main_tx_cdc_cdc_asyncfifo_writable; -wire main_tx_cdc_cdc_asyncfifo_re; -wire main_tx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_tx_cdc_cdc_asyncfifo_din; -wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; -wire main_tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_tx_cdc_cdc_produce_rdomain; -wire [5:0] main_tx_cdc_cdc_consume_wdomain; -wire [4:0] main_tx_cdc_cdc_wrport_adr; -wire [41:0] main_tx_cdc_cdc_wrport_dat_r; -wire main_tx_cdc_cdc_wrport_we; -wire [41:0] main_tx_cdc_cdc_wrport_dat_w; -wire [4:0] main_tx_cdc_cdc_rdport_adr; -wire [41:0] main_tx_cdc_cdc_rdport_dat_r; -wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; -wire main_tx_cdc_cdc_fifo_in_first; -wire main_tx_cdc_cdc_fifo_in_last; -wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; -wire main_tx_cdc_cdc_fifo_out_first; -wire main_tx_cdc_cdc_fifo_out_last; -wire main_rx_cdc_sink_sink_valid; -wire main_rx_cdc_sink_sink_ready; -wire main_rx_cdc_sink_sink_first; -wire main_rx_cdc_sink_sink_last; -wire [31:0] main_rx_cdc_sink_sink_payload_data; -wire [3:0] main_rx_cdc_sink_sink_payload_last_be; -wire [3:0] main_rx_cdc_sink_sink_payload_error; -wire main_rx_cdc_source_source_valid; -wire main_rx_cdc_source_source_ready; -wire main_rx_cdc_source_source_first; -wire main_rx_cdc_source_source_last; -wire [31:0] main_rx_cdc_source_source_payload_data; -wire [3:0] main_rx_cdc_source_source_payload_last_be; -wire [3:0] main_rx_cdc_source_source_payload_error; -wire main_rx_cdc_cdc_sink_valid; -wire main_rx_cdc_cdc_sink_ready; -wire main_rx_cdc_cdc_sink_first; -wire main_rx_cdc_cdc_sink_last; -wire [31:0] main_rx_cdc_cdc_sink_payload_data; -wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; -wire [3:0] main_rx_cdc_cdc_sink_payload_error; -wire main_rx_cdc_cdc_source_valid; -wire main_rx_cdc_cdc_source_ready; -wire main_rx_cdc_cdc_source_first; -wire main_rx_cdc_cdc_source_last; -wire [31:0] main_rx_cdc_cdc_source_payload_data; -wire [3:0] main_rx_cdc_cdc_source_payload_last_be; -wire [3:0] main_rx_cdc_cdc_source_payload_error; -wire main_rx_cdc_cdc_asyncfifo_we; -wire main_rx_cdc_cdc_asyncfifo_writable; -wire main_rx_cdc_cdc_asyncfifo_re; -wire main_rx_cdc_cdc_asyncfifo_readable; -wire [41:0] main_rx_cdc_cdc_asyncfifo_din; -wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; -wire main_rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire main_rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] main_rx_cdc_cdc_produce_rdomain; -wire [5:0] main_rx_cdc_cdc_consume_wdomain; -wire [4:0] main_rx_cdc_cdc_wrport_adr; -wire [41:0] main_rx_cdc_cdc_wrport_dat_r; -wire main_rx_cdc_cdc_wrport_we; -wire [41:0] main_rx_cdc_cdc_wrport_dat_w; -wire [4:0] main_rx_cdc_cdc_rdport_adr; -wire [41:0] main_rx_cdc_cdc_rdport_dat_r; -wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; -wire main_rx_cdc_cdc_fifo_in_first; -wire main_rx_cdc_cdc_fifo_in_last; -wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; -wire main_rx_cdc_cdc_fifo_out_first; -wire main_rx_cdc_cdc_fifo_out_last; -wire main_sink_valid; -wire main_sink_ready; -wire main_sink_first; -wire main_sink_last; -wire [31:0] main_sink_payload_data; -wire [3:0] main_sink_payload_last_be; -wire [3:0] main_sink_payload_error; -wire main_source_valid; -wire main_source_ready; -wire main_source_first; -wire main_source_last; -wire [31:0] main_source_payload_data; -wire [3:0] main_source_payload_last_be; -wire [3:0] main_source_payload_error; -wire [29:0] main_bus_adr; -wire [31:0] main_bus_dat_w; -wire [31:0] main_bus_dat_r; -wire [3:0] main_bus_sel; -wire main_bus_cyc; -wire main_bus_stb; -wire main_bus_ack; -wire main_bus_we; -wire [2:0] main_bus_cti; -wire [1:0] main_bus_bte; -wire main_bus_err; -wire main_writer_sink_sink_valid; -reg main_writer_sink_sink_ready = 1'd1; -wire main_writer_sink_sink_first; -wire main_writer_sink_sink_last; -wire [31:0] main_writer_sink_sink_payload_data; -wire [3:0] main_writer_sink_sink_payload_last_be; -wire [3:0] main_writer_sink_sink_payload_error; -wire main_writer_slot_status; -wire main_writer_slot_we; -reg main_writer_slot_re = 1'd0; -wire [31:0] main_writer_length_status; -wire main_writer_length_we; -reg main_writer_length_re = 1'd0; -reg [31:0] main_writer_errors_status = 32'd0; -wire main_writer_errors_we; -reg main_writer_errors_re = 1'd0; -wire main_writer_irq; -wire main_writer_available_status; -wire main_writer_available_pending; -wire main_writer_available_trigger; -reg main_writer_available_clear = 1'd0; -wire main_writer_available0; -wire main_writer_status_status; -wire main_writer_status_we; -reg main_writer_status_re = 1'd0; -wire main_writer_available1; -wire main_writer_pending_status; -wire main_writer_pending_we; -reg main_writer_pending_re = 1'd0; -reg main_writer_pending_r = 1'd0; -wire main_writer_available2; -reg main_writer_enable_storage = 1'd0; -reg main_writer_enable_re = 1'd0; -reg [2:0] main_writer_inc = 3'd0; -reg [31:0] main_writer_counter = 32'd0; -reg main_writer_slot = 1'd0; -reg main_writer_slot_ce = 1'd0; -reg main_writer_start = 1'd0; -reg main_writer_ongoing = 1'd0; -reg main_writer_stat_fifo_sink_valid = 1'd0; -wire main_writer_stat_fifo_sink_ready; -reg main_writer_stat_fifo_sink_first = 1'd0; -reg main_writer_stat_fifo_sink_last = 1'd0; -wire main_writer_stat_fifo_sink_payload_slot; -wire [31:0] main_writer_stat_fifo_sink_payload_length; -wire main_writer_stat_fifo_source_valid; -wire main_writer_stat_fifo_source_ready; -wire main_writer_stat_fifo_source_first; -wire main_writer_stat_fifo_source_last; -wire main_writer_stat_fifo_source_payload_slot; -wire [31:0] main_writer_stat_fifo_source_payload_length; -wire main_writer_stat_fifo_syncfifo_we; -wire main_writer_stat_fifo_syncfifo_writable; -wire main_writer_stat_fifo_syncfifo_re; -wire main_writer_stat_fifo_syncfifo_readable; -wire [34:0] main_writer_stat_fifo_syncfifo_din; -wire [34:0] main_writer_stat_fifo_syncfifo_dout; -reg [1:0] main_writer_stat_fifo_level = 2'd0; -reg main_writer_stat_fifo_replace = 1'd0; -reg main_writer_stat_fifo_produce = 1'd0; -reg main_writer_stat_fifo_consume = 1'd0; -reg main_writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] main_writer_stat_fifo_wrport_dat_r; -wire main_writer_stat_fifo_wrport_we; -wire [34:0] main_writer_stat_fifo_wrport_dat_w; -wire main_writer_stat_fifo_do_read; -wire main_writer_stat_fifo_rdport_adr; -wire [34:0] main_writer_stat_fifo_rdport_dat_r; -wire main_writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_in_payload_length; -wire main_writer_stat_fifo_fifo_in_first; -wire main_writer_stat_fifo_fifo_in_last; -wire main_writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] main_writer_stat_fifo_fifo_out_payload_length; -wire main_writer_stat_fifo_fifo_out_first; -wire main_writer_stat_fifo_fifo_out_last; -reg [8:0] main_writer_memory0_adr = 9'd0; -wire [31:0] main_writer_memory0_dat_r; -reg main_writer_memory0_we = 1'd0; -reg [31:0] main_writer_memory0_dat_w = 32'd0; -reg [8:0] main_writer_memory1_adr = 9'd0; -wire [31:0] main_writer_memory1_dat_r; -reg main_writer_memory1_we = 1'd0; -reg [31:0] main_writer_memory1_dat_w = 32'd0; -reg main_reader_source_source_valid = 1'd0; -wire main_reader_source_source_ready; -reg main_reader_source_source_first = 1'd0; -reg main_reader_source_source_last = 1'd0; -reg [31:0] main_reader_source_source_payload_data = 32'd0; -reg [3:0] main_reader_source_source_payload_last_be = 4'd0; -reg [3:0] main_reader_source_source_payload_error = 4'd0; -reg main_reader_start_start_re = 1'd0; -wire main_reader_start_start_r; -reg main_reader_start_start_we = 1'd0; -reg main_reader_start_start_w = 1'd0; -wire main_reader_ready_status; -wire main_reader_ready_we; -reg main_reader_ready_re = 1'd0; -wire [1:0] main_reader_level_status; -wire main_reader_level_we; -reg main_reader_level_re = 1'd0; -reg main_reader_slot_storage = 1'd0; -reg main_reader_slot_re = 1'd0; -reg [10:0] main_reader_length_storage = 11'd0; -reg main_reader_length_re = 1'd0; -wire main_reader_irq; -wire main_reader_eventsourcepulse_status; -reg main_reader_eventsourcepulse_pending = 1'd0; -reg main_reader_eventsourcepulse_trigger = 1'd0; -reg main_reader_eventsourcepulse_clear = 1'd0; -wire main_reader_event00; -wire main_reader_status_status; -wire main_reader_status_we; -reg main_reader_status_re = 1'd0; -wire main_reader_event01; -wire main_reader_pending_status; -wire main_reader_pending_we; -reg main_reader_pending_re = 1'd0; -reg main_reader_pending_r = 1'd0; -wire main_reader_event02; -reg main_reader_enable_storage = 1'd0; -reg main_reader_enable_re = 1'd0; -reg main_reader_start = 1'd0; -wire main_reader_cmd_fifo_sink_valid; -wire main_reader_cmd_fifo_sink_ready; -reg main_reader_cmd_fifo_sink_first = 1'd0; -reg main_reader_cmd_fifo_sink_last = 1'd0; -wire main_reader_cmd_fifo_sink_payload_slot; -wire [10:0] main_reader_cmd_fifo_sink_payload_length; -wire main_reader_cmd_fifo_source_valid; -reg main_reader_cmd_fifo_source_ready = 1'd0; -wire main_reader_cmd_fifo_source_first; -wire main_reader_cmd_fifo_source_last; -wire main_reader_cmd_fifo_source_payload_slot; -wire [10:0] main_reader_cmd_fifo_source_payload_length; -wire main_reader_cmd_fifo_syncfifo_we; -wire main_reader_cmd_fifo_syncfifo_writable; -wire main_reader_cmd_fifo_syncfifo_re; -wire main_reader_cmd_fifo_syncfifo_readable; -wire [13:0] main_reader_cmd_fifo_syncfifo_din; -wire [13:0] main_reader_cmd_fifo_syncfifo_dout; -reg [1:0] main_reader_cmd_fifo_level = 2'd0; -reg main_reader_cmd_fifo_replace = 1'd0; -reg main_reader_cmd_fifo_produce = 1'd0; -reg main_reader_cmd_fifo_consume = 1'd0; -reg main_reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] main_reader_cmd_fifo_wrport_dat_r; -wire main_reader_cmd_fifo_wrport_we; -wire [13:0] main_reader_cmd_fifo_wrport_dat_w; -wire main_reader_cmd_fifo_do_read; -wire main_reader_cmd_fifo_rdport_adr; -wire [13:0] main_reader_cmd_fifo_rdport_dat_r; -wire main_reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_in_payload_length; -wire main_reader_cmd_fifo_fifo_in_first; -wire main_reader_cmd_fifo_fifo_in_last; -wire main_reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] main_reader_cmd_fifo_fifo_out_payload_length; -wire main_reader_cmd_fifo_fifo_out_first; -wire main_reader_cmd_fifo_fifo_out_last; -reg [10:0] main_reader_read_address = 11'd0; -reg [10:0] main_reader_counter = 11'd0; -wire [8:0] main_reader_memory0_adr; -wire [31:0] main_reader_memory0_dat_r; -wire [8:0] main_reader_memory1_adr; -wire [31:0] main_reader_memory1_dat_r; -wire main_ev_irq; -wire [29:0] main_sram0_bus_adr0; -wire [31:0] main_sram0_bus_dat_w0; -wire [31:0] main_sram0_bus_dat_r0; -wire [3:0] main_sram0_bus_sel0; -wire main_sram0_bus_cyc0; -wire main_sram0_bus_stb0; -reg main_sram0_bus_ack0 = 1'd0; -wire main_sram0_bus_we0; -wire [2:0] main_sram0_bus_cti0; -wire [1:0] main_sram0_bus_bte0; -reg main_sram0_bus_err0 = 1'd0; -wire [8:0] main_sram0_adr0; -wire [31:0] main_sram0_dat_r0; -wire [29:0] main_sram1_bus_adr0; -wire [31:0] main_sram1_bus_dat_w0; -wire [31:0] main_sram1_bus_dat_r0; -wire [3:0] main_sram1_bus_sel0; -wire main_sram1_bus_cyc0; -wire main_sram1_bus_stb0; -reg main_sram1_bus_ack0 = 1'd0; -wire main_sram1_bus_we0; -wire [2:0] main_sram1_bus_cti0; -wire [1:0] main_sram1_bus_bte0; -reg main_sram1_bus_err0 = 1'd0; -wire [8:0] main_sram1_adr0; -wire [31:0] main_sram1_dat_r0; -wire [29:0] main_sram0_bus_adr1; -wire [31:0] main_sram0_bus_dat_w1; -wire [31:0] main_sram0_bus_dat_r1; -wire [3:0] main_sram0_bus_sel1; -wire main_sram0_bus_cyc1; -wire main_sram0_bus_stb1; -reg main_sram0_bus_ack1 = 1'd0; -wire main_sram0_bus_we1; -wire [2:0] main_sram0_bus_cti1; -wire [1:0] main_sram0_bus_bte1; -reg main_sram0_bus_err1 = 1'd0; -wire [8:0] main_sram0_adr1; -wire [31:0] main_sram0_dat_r1; -reg [3:0] main_sram0_we = 4'd0; -wire [31:0] main_sram0_dat_w; -wire [29:0] main_sram1_bus_adr1; -wire [31:0] main_sram1_bus_dat_w1; -wire [31:0] main_sram1_bus_dat_r1; -wire [3:0] main_sram1_bus_sel1; -wire main_sram1_bus_cyc1; -wire main_sram1_bus_stb1; -reg main_sram1_bus_ack1 = 1'd0; -wire main_sram1_bus_we1; -wire [2:0] main_sram1_bus_cti1; -wire [1:0] main_sram1_bus_bte1; -reg main_sram1_bus_err1 = 1'd0; -wire [8:0] main_sram1_adr1; -wire [31:0] main_sram1_dat_r1; -reg [3:0] main_sram1_we = 4'd0; -wire [31:0] main_sram1_dat_w; -reg [3:0] main_slave_sel = 4'd0; -reg [3:0] main_slave_sel_r = 4'd0; -wire [29:0] main_wb_bus_adr; -wire [31:0] main_wb_bus_dat_w; -wire [31:0] main_wb_bus_dat_r; -wire [3:0] main_wb_bus_sel; -wire main_wb_bus_cyc; -wire main_wb_bus_stb; -wire main_wb_bus_ack; -wire main_wb_bus_we; -wire [2:0] main_wb_bus_cti; -wire [1:0] main_wb_bus_bte; -wire main_wb_bus_err; -wire builder_reset0; -wire builder_reset1; -wire builder_reset2; -wire builder_reset3; -wire builder_reset4; -wire builder_reset5; -wire builder_reset6; -wire builder_reset7; -wire builder_pll_fb; -reg builder_liteethmacgap_state = 1'd0; -reg builder_liteethmacgap_next_state = 1'd0; -reg [3:0] main_tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg main_tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] builder_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] main_preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg builder_liteethmacpreamblechecker_state = 1'd0; -reg builder_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] builder_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] builder_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_state = 2'd0; -reg [1:0] builder_liteethmaccrc32checker_next_state = 2'd0; -reg builder_liteethmacpaddinginserter_state = 1'd0; -reg builder_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] main_padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg builder_liteethmactxlastbe_state = 1'd0; -reg builder_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] builder_liteethmacsramwriter_state = 3'd0; -reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] main_writer_counter_t_next_value = 32'd0; -reg main_writer_counter_t_next_value_ce = 1'd0; -reg [31:0] main_writer_errors_status_f_next_value = 32'd0; -reg main_writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] builder_liteethmacsramreader_state = 2'd0; -reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; -reg [10:0] main_reader_counter_next_value = 11'd0; -reg main_reader_counter_next_value_ce = 1'd0; -reg [13:0] builder_maccore_adr = 14'd0; -reg builder_maccore_we = 1'd0; -reg [31:0] builder_maccore_dat_w = 32'd0; -wire [31:0] builder_maccore_dat_r; -wire [29:0] builder_maccore_wishbone_adr; -wire [31:0] builder_maccore_wishbone_dat_w; -reg [31:0] builder_maccore_wishbone_dat_r = 32'd0; -wire [3:0] builder_maccore_wishbone_sel; -wire builder_maccore_wishbone_cyc; -wire builder_maccore_wishbone_stb; -reg builder_maccore_wishbone_ack = 1'd0; -wire builder_maccore_wishbone_we; -wire [2:0] builder_maccore_wishbone_cti; -wire [1:0] builder_maccore_wishbone_bte; -reg builder_maccore_wishbone_err = 1'd0; -wire [29:0] builder_shared_adr; -wire [31:0] builder_shared_dat_w; -reg [31:0] builder_shared_dat_r = 32'd0; -wire [3:0] builder_shared_sel; -wire builder_shared_cyc; -wire builder_shared_stb; -reg builder_shared_ack = 1'd0; -wire builder_shared_we; -wire [2:0] builder_shared_cti; -wire [1:0] builder_shared_bte; -wire builder_shared_err; -wire builder_request; -wire builder_grant; -reg [1:0] builder_slave_sel = 2'd0; -reg [1:0] builder_slave_sel_r = 2'd0; -reg builder_error = 1'd0; -wire builder_wait; -wire builder_done; -reg [19:0] builder_count = 20'd1000000; -wire [13:0] builder_interface0_bank_bus_adr; -wire builder_interface0_bank_bus_we; -wire [31:0] builder_interface0_bank_bus_dat_w; -reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; -reg builder_csrbank0_reset0_re = 1'd0; -wire [1:0] builder_csrbank0_reset0_r; -reg builder_csrbank0_reset0_we = 1'd0; -wire [1:0] builder_csrbank0_reset0_w; -reg builder_csrbank0_scratch0_re = 1'd0; -wire [31:0] builder_csrbank0_scratch0_r; -reg builder_csrbank0_scratch0_we = 1'd0; -wire [31:0] builder_csrbank0_scratch0_w; -reg builder_csrbank0_bus_errors_re = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_r; -reg builder_csrbank0_bus_errors_we = 1'd0; -wire [31:0] builder_csrbank0_bus_errors_w; -wire builder_csrbank0_sel; -wire [13:0] builder_interface1_bank_bus_adr; -wire builder_interface1_bank_bus_we; -wire [31:0] builder_interface1_bank_bus_dat_w; -reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; -reg builder_csrbank1_sram_writer_slot_re = 1'd0; -wire builder_csrbank1_sram_writer_slot_r; -reg builder_csrbank1_sram_writer_slot_we = 1'd0; -wire builder_csrbank1_sram_writer_slot_w; -reg builder_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_r; -reg builder_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_length_w; -reg builder_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_r; -reg builder_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] builder_csrbank1_sram_writer_errors_w; -reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_r; -reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_status_w; -reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_r; -reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_pending_w; -reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_r; -reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_writer_ev_enable0_w; -reg builder_csrbank1_sram_reader_ready_re = 1'd0; -wire builder_csrbank1_sram_reader_ready_r; -reg builder_csrbank1_sram_reader_ready_we = 1'd0; -wire builder_csrbank1_sram_reader_ready_w; -reg builder_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_r; -reg builder_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] builder_csrbank1_sram_reader_level_w; -reg builder_csrbank1_sram_reader_slot0_re = 1'd0; -wire builder_csrbank1_sram_reader_slot0_r; -reg builder_csrbank1_sram_reader_slot0_we = 1'd0; -wire builder_csrbank1_sram_reader_slot0_w; -reg builder_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_r; -reg builder_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] builder_csrbank1_sram_reader_length0_w; -reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_r; -reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_status_w; -reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_r; -reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_pending_w; -reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_r; -reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire builder_csrbank1_sram_reader_ev_enable0_w; -reg builder_csrbank1_preamble_crc_re = 1'd0; -wire builder_csrbank1_preamble_crc_r; -reg builder_csrbank1_preamble_crc_we = 1'd0; -wire builder_csrbank1_preamble_crc_w; -reg builder_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_r; -reg builder_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] builder_csrbank1_preamble_errors_w; -reg builder_csrbank1_crc_errors_re = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_r; -reg builder_csrbank1_crc_errors_we = 1'd0; -wire [31:0] builder_csrbank1_crc_errors_w; -wire builder_csrbank1_sel; -wire [13:0] builder_interface2_bank_bus_adr; -wire builder_interface2_bank_bus_we; -wire [31:0] builder_interface2_bank_bus_dat_w; -reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; -reg builder_csrbank2_crg_reset0_re = 1'd0; -wire builder_csrbank2_crg_reset0_r; -reg builder_csrbank2_crg_reset0_we = 1'd0; -wire builder_csrbank2_crg_reset0_w; -reg builder_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_r; -reg builder_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] builder_csrbank2_mdio_w0_w; -reg builder_csrbank2_mdio_r_re = 1'd0; -wire builder_csrbank2_mdio_r_r; -reg builder_csrbank2_mdio_r_we = 1'd0; -wire builder_csrbank2_mdio_r_w; -wire builder_csrbank2_sel; -wire [13:0] builder_csr_interconnect_adr; -wire builder_csr_interconnect_we; -wire [31:0] builder_csr_interconnect_dat_w; -wire [31:0] builder_csr_interconnect_dat_r; -reg builder_state = 1'd0; -reg builder_next_state = 1'd0; -reg [29:0] builder_array_muxed0 = 30'd0; -reg [31:0] builder_array_muxed1 = 32'd0; -reg [3:0] builder_array_muxed2 = 4'd0; -reg builder_array_muxed3 = 1'd0; -reg builder_array_muxed4 = 1'd0; -reg builder_array_muxed5 = 1'd0; -reg [2:0] builder_array_muxed6 = 3'd0; -reg [1:0] builder_array_muxed7 = 2'd0; -wire builder_xilinxasyncresetsynchronizerimpl0; -wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl0_expr; -wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; -wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl3_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] builder_xilinxmultiregimpl6_regs1 = 6'd0; + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYRGMII) +│ └─── crg (LiteEthPHYRGMIICRG) +│ │ └─── pll (S7PLL) +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [BUFG] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [FDCE] +│ │ │ └─── [PLLE2_ADV] +│ │ │ └─── [BUFG] +│ │ └─── [BUFG] +│ │ └─── [ODDR] +│ │ └─── [IBUF] +│ │ └─── [OBUF] +│ └─── tx (LiteEthPHYRGMIITX) +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ │ └─── [OBUF] +│ │ └─── [OBUF] +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ │ └─── [ODDR] +│ │ └─── [ODDR] +│ │ └─── [OBUF] +│ │ └─── [ODDR] +│ └─── rx (LiteEthPHYRGMIIRX) +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IBUF] +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IDELAYE2] +│ │ └─── [IDDR] +│ │ └─── [IDDR] +│ │ └─── [IBUF] +│ │ └─── [IDELAYE2] +│ │ └─── [IDELAYE2] +│ │ └─── [IDELAYE2] +│ │ └─── [IBUF] +│ │ └─── [IDDR] +│ │ └─── [IDELAYE2] +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg builder_next_state = 1'd0; +wire builder_pll_fb; +wire builder_request; +wire builder_reset0; +wire builder_reset1; +wire builder_reset2; +wire builder_reset3; +wire builder_reset4; +wire builder_reset5; +wire builder_reset6; +wire builder_reset7; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +wire builder_xilinxasyncresetsynchronizerimpl0_async_reset; +wire builder_xilinxasyncresetsynchronizerimpl0_expr; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl10 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl11 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl30 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl31 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl50 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl51 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_delayed_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +wire main_maccore_ethphy_clkin; +wire main_maccore_ethphy_clkout0; +wire main_maccore_ethphy_clkout1; +wire main_maccore_ethphy_clkout_buf0; +wire main_maccore_ethphy_clkout_buf1; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +wire main_maccore_ethphy_eth_rx_clk_ibuf; +wire main_maccore_ethphy_eth_tx_clk_obuf; +wire main_maccore_ethphy_liteethphyrgmiirx; +wire main_maccore_ethphy_liteethphyrgmiirx_last; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; +reg main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf; +wire main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay; +wire [7:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data; +wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf; +wire [3:0] main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay; +reg main_maccore_ethphy_liteethphyrgmiirx_source_first = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_source_last; +reg [7:0] main_maccore_ethphy_liteethphyrgmiirx_source_payload_data = 8'd0; +reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_error = 1'd0; +reg main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_liteethphyrgmiirx_source_ready; +reg main_maccore_ethphy_liteethphyrgmiirx_source_valid = 1'd0; +wire main_maccore_ethphy_locked; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +reg main_maccore_ethphy_power_down = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy_reset0 = 1'd0; +wire main_maccore_ethphy_reset1; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire main_maccore_ethphy_sink_first; +wire main_maccore_ethphy_sink_last; +wire [7:0] main_maccore_ethphy_sink_payload_data; +wire main_maccore_ethphy_sink_payload_error; +wire main_maccore_ethphy_sink_payload_last_be; +wire main_maccore_ethphy_sink_ready; +wire main_maccore_ethphy_sink_valid; +wire main_maccore_ethphy_tx_ctl_obuf; +wire [3:0] main_maccore_ethphy_tx_data_obuf; +wire main_maccore_ethphy_w; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ assign main_wb_bus_adr = wishbone_adr; assign main_wb_bus_dat_w = wishbone_dat_w; @@ -1017,294 +1368,653 @@ assign main_wb_bus_we = wishbone_we; assign main_wb_bus_cti = wishbone_cti; assign main_wb_bus_bte = wishbone_bte; assign wishbone_err = main_wb_bus_err; -assign interrupt = main_ev_irq; +assign interrupt = main_sram167_irq; assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; assign sys_rst = main_maccore_int_rst; assign main_maccore_ethphy_reset1 = main_maccore_ethphy_reset_storage; -assign rgmii_eth_rst_n = (~main_maccore_ethphy_reset1); +assign rgmii_rst_n = (~main_maccore_ethphy_reset1); assign main_maccore_ethphy_clkin = eth_rx_clk; assign eth_tx_clk = main_maccore_ethphy_clkout_buf0; assign eth_tx_delayed_clk = main_maccore_ethphy_clkout_buf1; assign main_maccore_ethphy_sink_ready = 1'd1; assign main_maccore_ethphy_liteethphyrgmiirx_last = ((~main_maccore_ethphy_liteethphyrgmiirx_rx_ctl) & main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d); assign main_maccore_ethphy_liteethphyrgmiirx_source_last = main_maccore_ethphy_liteethphyrgmiirx_last; -assign rgmii_eth_mdc = main_maccore_ethphy__w_storage[0]; +assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; -assign main_tx_cdc_sink_sink_valid = main_source_valid; -assign main_source_ready = main_tx_cdc_sink_sink_ready; -assign main_tx_cdc_sink_sink_first = main_source_first; -assign main_tx_cdc_sink_sink_last = main_source_last; -assign main_tx_cdc_sink_sink_payload_data = main_source_payload_data; -assign main_tx_cdc_sink_sink_payload_last_be = main_source_payload_last_be; -assign main_tx_cdc_sink_sink_payload_error = main_source_payload_error; -assign main_sink_valid = main_rx_cdc_source_source_valid; -assign main_rx_cdc_source_source_ready = main_sink_ready; -assign main_sink_first = main_rx_cdc_source_source_first; -assign main_sink_last = main_rx_cdc_source_source_last; -assign main_sink_payload_data = main_rx_cdc_source_source_payload_data; -assign main_sink_payload_last_be = main_rx_cdc_source_source_payload_last_be; -assign main_sink_payload_error = main_rx_cdc_source_source_payload_error; -assign main_ps_preamble_error_i = main_preamble_checker_error; -assign main_ps_crc_error_i = main_liteethmaccrc32checker_error; -always @(*) begin - main_tx_gap_inserter_source_payload_last_be <= 1'd0; - main_tx_gap_inserter_source_payload_error <= 1'd0; - main_tx_gap_inserter_sink_ready <= 1'd0; - main_tx_gap_inserter_source_valid <= 1'd0; - builder_liteethmacgap_next_state <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - main_tx_gap_inserter_source_first <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - main_tx_gap_inserter_source_last <= 1'd0; - main_tx_gap_inserter_source_payload_data <= 8'd0; - builder_liteethmacgap_next_state <= builder_liteethmacgap_state; - case (builder_liteethmacgap_state) - 1'd1: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= (main_tx_gap_inserter_counter + 1'd1); - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((main_tx_gap_inserter_counter == 4'd11)) begin - builder_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - main_tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - main_tx_gap_inserter_source_valid <= main_tx_gap_inserter_sink_valid; - main_tx_gap_inserter_sink_ready <= main_tx_gap_inserter_source_ready; - main_tx_gap_inserter_source_first <= main_tx_gap_inserter_sink_first; - main_tx_gap_inserter_source_last <= main_tx_gap_inserter_sink_last; - main_tx_gap_inserter_source_payload_data <= main_tx_gap_inserter_sink_payload_data; - main_tx_gap_inserter_source_payload_last_be <= main_tx_gap_inserter_sink_payload_last_be; - main_tx_gap_inserter_source_payload_error <= main_tx_gap_inserter_sink_payload_error; - if (((main_tx_gap_inserter_sink_valid & main_tx_gap_inserter_sink_last) & main_tx_gap_inserter_sink_ready)) begin - builder_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_inserter_source_payload_last_be = main_preamble_inserter_sink_payload_last_be; -always @(*) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 2'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - main_preamble_inserter_source_valid <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - main_preamble_inserter_source_first <= 1'd0; - main_preamble_inserter_source_last <= 1'd0; - main_preamble_inserter_source_payload_data <= 8'd0; - main_preamble_inserter_source_payload_error <= 1'd0; - main_preamble_inserter_source_payload_data <= main_preamble_inserter_sink_payload_data; - builder_liteethmacpreambleinserter_next_state <= builder_liteethmacpreambleinserter_state; - case (builder_liteethmacpreambleinserter_state) - 1'd1: begin - main_preamble_inserter_source_valid <= 1'd1; - case (main_preamble_inserter_count) - 1'd0: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[7:0]; - end - 1'd1: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[15:8]; - end - 2'd2: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[23:16]; - end - 2'd3: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[31:24]; - end - 3'd4: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[39:32]; - end - 3'd5: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[47:40]; - end - 3'd6: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[55:48]; - end - default: begin - main_preamble_inserter_source_payload_data <= main_preamble_inserter_preamble[63:56]; - end - endcase - if (main_preamble_inserter_source_ready) begin - if ((main_preamble_inserter_count == 3'd7)) begin - builder_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= (main_preamble_inserter_count + 1'd1); - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - main_preamble_inserter_source_valid <= main_preamble_inserter_sink_valid; - main_preamble_inserter_sink_ready <= main_preamble_inserter_source_ready; - main_preamble_inserter_source_first <= main_preamble_inserter_sink_first; - main_preamble_inserter_source_last <= main_preamble_inserter_sink_last; - main_preamble_inserter_source_payload_error <= main_preamble_inserter_sink_payload_error; - if (((main_preamble_inserter_sink_valid & main_preamble_inserter_sink_last) & main_preamble_inserter_source_ready)) begin - builder_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - main_preamble_inserter_sink_ready <= 1'd1; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (main_preamble_inserter_sink_valid) begin - main_preamble_inserter_sink_ready <= 1'd0; - builder_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data; -assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be; -always @(*) begin - main_preamble_checker_source_payload_error <= 1'd0; - main_preamble_checker_error <= 1'd0; - main_preamble_checker_source_valid <= 1'd0; - main_preamble_checker_sink_ready <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= 1'd0; - main_preamble_checker_source_first <= 1'd0; - main_preamble_checker_source_last <= 1'd0; - builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state; - case (builder_liteethmacpreamblechecker_state) - 1'd1: begin - main_preamble_checker_source_valid <= main_preamble_checker_sink_valid; - main_preamble_checker_sink_ready <= main_preamble_checker_source_ready; - main_preamble_checker_source_first <= main_preamble_checker_sink_first; - main_preamble_checker_source_last <= main_preamble_checker_sink_last; - main_preamble_checker_source_payload_error <= main_preamble_checker_sink_payload_error; - if (((main_preamble_checker_source_valid & main_preamble_checker_source_last) & main_preamble_checker_source_ready)) begin - builder_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - main_preamble_checker_sink_ready <= 1'd1; - if (((main_preamble_checker_sink_valid & (~main_preamble_checker_sink_last)) & (main_preamble_checker_sink_payload_data == 8'd213))) begin - builder_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((main_preamble_checker_sink_valid & main_preamble_checker_sink_last)) begin - main_preamble_checker_error <= 1'd1; - end - end - endcase -end -assign main_liteethmaccrc32inserter_cnt_done = (main_liteethmaccrc32inserter_cnt == 1'd0); -assign main_liteethmaccrc32inserter_sink_valid = main_crc32_inserter_source_valid; -assign main_crc32_inserter_source_ready = main_liteethmaccrc32inserter_sink_ready; -assign main_liteethmaccrc32inserter_sink_first = main_crc32_inserter_source_first; -assign main_liteethmaccrc32inserter_sink_last = main_crc32_inserter_source_last; -assign main_liteethmaccrc32inserter_sink_payload_data = main_crc32_inserter_source_payload_data; -assign main_liteethmaccrc32inserter_sink_payload_last_be = main_crc32_inserter_source_payload_last_be; -assign main_liteethmaccrc32inserter_sink_payload_error = main_crc32_inserter_source_payload_error; -assign main_liteethmaccrc32inserter_data1 = main_liteethmaccrc32inserter_data0; -assign main_liteethmaccrc32inserter_last = main_liteethmaccrc32inserter_reg; -assign main_liteethmaccrc32inserter_value = (~{main_liteethmaccrc32inserter_reg[0], main_liteethmaccrc32inserter_reg[1], main_liteethmaccrc32inserter_reg[2], main_liteethmaccrc32inserter_reg[3], main_liteethmaccrc32inserter_reg[4], main_liteethmaccrc32inserter_reg[5], main_liteethmaccrc32inserter_reg[6], main_liteethmaccrc32inserter_reg[7], main_liteethmaccrc32inserter_reg[8], main_liteethmaccrc32inserter_reg[9], main_liteethmaccrc32inserter_reg[10], main_liteethmaccrc32inserter_reg[11], main_liteethmaccrc32inserter_reg[12], main_liteethmaccrc32inserter_reg[13], main_liteethmaccrc32inserter_reg[14], main_liteethmaccrc32inserter_reg[15], main_liteethmaccrc32inserter_reg[16], main_liteethmaccrc32inserter_reg[17], main_liteethmaccrc32inserter_reg[18], main_liteethmaccrc32inserter_reg[19], main_liteethmaccrc32inserter_reg[20], main_liteethmaccrc32inserter_reg[21], main_liteethmaccrc32inserter_reg[22], main_liteethmaccrc32inserter_reg[23], main_liteethmaccrc32inserter_reg[24], main_liteethmaccrc32inserter_reg[25], main_liteethmaccrc32inserter_reg[26], main_liteethmaccrc32inserter_reg[27], main_liteethmaccrc32inserter_reg[28], main_liteethmaccrc32inserter_reg[29], main_liteethmaccrc32inserter_reg[30], main_liteethmaccrc32inserter_reg[31]}); -assign main_liteethmaccrc32inserter_error = (main_liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32inserter_next <= 32'd0; - main_liteethmaccrc32inserter_next[0] <= (((main_liteethmaccrc32inserter_last[24] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[1] <= (((((((main_liteethmaccrc32inserter_last[25] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[2] <= (((((((((main_liteethmaccrc32inserter_last[26] ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[3] <= (((((((main_liteethmaccrc32inserter_last[27] ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[4] <= (((((((((main_liteethmaccrc32inserter_last[28] ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[5] <= (((((((((((((main_liteethmaccrc32inserter_last[29] ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[6] <= (((((((((((main_liteethmaccrc32inserter_last[30] ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[7] <= (((((((((main_liteethmaccrc32inserter_last[31] ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[8] <= ((((((((main_liteethmaccrc32inserter_last[0] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[9] <= ((((((((main_liteethmaccrc32inserter_last[1] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[10] <= ((((((((main_liteethmaccrc32inserter_last[2] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[11] <= ((((((((main_liteethmaccrc32inserter_last[3] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[12] <= ((((((((((((main_liteethmaccrc32inserter_last[4] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[13] <= ((((((((((((main_liteethmaccrc32inserter_last[5] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[14] <= ((((((((((main_liteethmaccrc32inserter_last[6] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[15] <= ((((((((main_liteethmaccrc32inserter_last[7] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[16] <= ((((((main_liteethmaccrc32inserter_last[8] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[17] <= ((((((main_liteethmaccrc32inserter_last[9] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[18] <= ((((((main_liteethmaccrc32inserter_last[10] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[19] <= ((((main_liteethmaccrc32inserter_last[11] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[20] <= ((main_liteethmaccrc32inserter_last[12] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[21] <= ((main_liteethmaccrc32inserter_last[13] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); - main_liteethmaccrc32inserter_next[22] <= ((main_liteethmaccrc32inserter_last[14] ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[23] <= ((((((main_liteethmaccrc32inserter_last[15] ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_data1[6]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[24] <= ((((((main_liteethmaccrc32inserter_last[16] ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[25] <= ((((main_liteethmaccrc32inserter_last[17] ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[26] <= ((((((((main_liteethmaccrc32inserter_last[18] ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]) ^ main_liteethmaccrc32inserter_last[24]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_data1[7]); - main_liteethmaccrc32inserter_next[27] <= ((((((((main_liteethmaccrc32inserter_last[19] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]) ^ main_liteethmaccrc32inserter_last[25]) ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_data1[6]); - main_liteethmaccrc32inserter_next[28] <= ((((((main_liteethmaccrc32inserter_last[20] ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]) ^ main_liteethmaccrc32inserter_last[26]) ^ main_liteethmaccrc32inserter_data1[5]); - main_liteethmaccrc32inserter_next[29] <= ((((((main_liteethmaccrc32inserter_last[21] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[30]) ^ main_liteethmaccrc32inserter_data1[1]) ^ main_liteethmaccrc32inserter_last[27]) ^ main_liteethmaccrc32inserter_data1[4]); - main_liteethmaccrc32inserter_next[30] <= ((((main_liteethmaccrc32inserter_last[22] ^ main_liteethmaccrc32inserter_last[31]) ^ main_liteethmaccrc32inserter_data1[0]) ^ main_liteethmaccrc32inserter_last[28]) ^ main_liteethmaccrc32inserter_data1[3]); - main_liteethmaccrc32inserter_next[31] <= ((main_liteethmaccrc32inserter_last[23] ^ main_liteethmaccrc32inserter_last[29]) ^ main_liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - main_liteethmaccrc32inserter_ce <= 1'd0; - main_liteethmaccrc32inserter_reset <= 1'd0; - main_liteethmaccrc32inserter_source_valid <= 1'd0; - main_liteethmaccrc32inserter_source_first <= 1'd0; - main_liteethmaccrc32inserter_source_last <= 1'd0; - main_liteethmaccrc32inserter_source_payload_data <= 8'd0; - main_liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - main_liteethmaccrc32inserter_source_payload_error <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 2'd0; - main_liteethmaccrc32inserter_data0 <= 8'd0; - builder_liteethmaccrc32inserter_next_state <= builder_liteethmaccrc32inserter_state; - case (builder_liteethmaccrc32inserter_state) - 1'd1: begin - main_liteethmaccrc32inserter_ce <= (main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_source_ready); - main_liteethmaccrc32inserter_data0 <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_valid <= main_liteethmaccrc32inserter_sink_valid; - main_liteethmaccrc32inserter_sink_ready <= main_liteethmaccrc32inserter_source_ready; - main_liteethmaccrc32inserter_source_first <= main_liteethmaccrc32inserter_sink_first; - main_liteethmaccrc32inserter_source_last <= main_liteethmaccrc32inserter_sink_last; - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_sink_payload_data; - main_liteethmaccrc32inserter_source_payload_last_be <= main_liteethmaccrc32inserter_sink_payload_last_be; - main_liteethmaccrc32inserter_source_payload_error <= main_liteethmaccrc32inserter_sink_payload_error; - main_liteethmaccrc32inserter_source_last <= 1'd0; - if (((main_liteethmaccrc32inserter_sink_valid & main_liteethmaccrc32inserter_sink_last) & main_liteethmaccrc32inserter_source_ready)) begin - builder_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - main_liteethmaccrc32inserter_source_valid <= 1'd1; - case (main_liteethmaccrc32inserter_cnt) - 1'd0: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[15:8]; - end - default: begin - main_liteethmaccrc32inserter_source_payload_data <= main_liteethmaccrc32inserter_value[7:0]; - end - endcase - if (main_liteethmaccrc32inserter_cnt_done) begin - main_liteethmaccrc32inserter_source_last <= 1'd1; - if (main_liteethmaccrc32inserter_source_ready) begin - builder_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - main_liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - main_liteethmaccrc32inserter_reset <= 1'd1; - main_liteethmaccrc32inserter_sink_ready <= 1'd1; - if (main_liteethmaccrc32inserter_sink_valid) begin - main_liteethmaccrc32inserter_sink_ready <= 1'd0; - builder_liteethmaccrc32inserter_next_state <= 1'd1; - end - main_liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign main_crc32_inserter_sink_ready = ((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready); +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; +assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); @@ -1314,72 +2024,70 @@ assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmacc assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; always @(*) begin - main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; - main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; end always @(*) begin - main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; - main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; end -assign main_liteethmaccrc32checker_source_source_valid = (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); -assign main_liteethmaccrc32checker_source_source_last = main_liteethmaccrc32checker_sink_sink_last; -assign main_liteethmaccrc32checker_syncfifo_source_ready = main_liteethmaccrc32checker_fifo_out; +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; -assign main_liteethmaccrc32checker_source_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; always @(*) begin - main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; - main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; - main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | main_liteethmaccrc32checker_crc_error); + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end end -assign main_liteethmaccrc32checker_error = ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_last) & main_liteethmaccrc32checker_crc_error); -assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; -assign main_liteethmaccrc32checker_sink_sink_valid = main_crc32_checker_source_valid; -assign main_crc32_checker_source_ready = main_liteethmaccrc32checker_sink_sink_ready; -assign main_liteethmaccrc32checker_sink_sink_first = main_crc32_checker_source_first; -assign main_liteethmaccrc32checker_sink_sink_last = main_crc32_checker_source_last; -assign main_liteethmaccrc32checker_sink_sink_payload_data = main_crc32_checker_source_payload_data; -assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_crc32_checker_source_payload_last_be; -assign main_liteethmaccrc32checker_sink_sink_payload_error = main_crc32_checker_source_payload_error; -assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0; -assign main_liteethmaccrc32checker_crc_last = main_liteethmaccrc32checker_crc_reg; -assign main_liteethmaccrc32checker_crc_value = (~{main_liteethmaccrc32checker_crc_reg[0], main_liteethmaccrc32checker_crc_reg[1], main_liteethmaccrc32checker_crc_reg[2], main_liteethmaccrc32checker_crc_reg[3], main_liteethmaccrc32checker_crc_reg[4], main_liteethmaccrc32checker_crc_reg[5], main_liteethmaccrc32checker_crc_reg[6], main_liteethmaccrc32checker_crc_reg[7], main_liteethmaccrc32checker_crc_reg[8], main_liteethmaccrc32checker_crc_reg[9], main_liteethmaccrc32checker_crc_reg[10], main_liteethmaccrc32checker_crc_reg[11], main_liteethmaccrc32checker_crc_reg[12], main_liteethmaccrc32checker_crc_reg[13], main_liteethmaccrc32checker_crc_reg[14], main_liteethmaccrc32checker_crc_reg[15], main_liteethmaccrc32checker_crc_reg[16], main_liteethmaccrc32checker_crc_reg[17], main_liteethmaccrc32checker_crc_reg[18], main_liteethmaccrc32checker_crc_reg[19], main_liteethmaccrc32checker_crc_reg[20], main_liteethmaccrc32checker_crc_reg[21], main_liteethmaccrc32checker_crc_reg[22], main_liteethmaccrc32checker_crc_reg[23], main_liteethmaccrc32checker_crc_reg[24], main_liteethmaccrc32checker_crc_reg[25], main_liteethmaccrc32checker_crc_reg[26], main_liteethmaccrc32checker_crc_reg[27], main_liteethmaccrc32checker_crc_reg[28], main_liteethmaccrc32checker_crc_reg[29], main_liteethmaccrc32checker_crc_reg[30], main_liteethmaccrc32checker_crc_reg[31]}); -assign main_liteethmaccrc32checker_crc_error = (main_liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - main_liteethmaccrc32checker_crc_next <= 32'd0; - main_liteethmaccrc32checker_crc_next[0] <= (((main_liteethmaccrc32checker_crc_last[24] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_last[25] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_last[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_last[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_last[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_last[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_last[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_last[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_last[0] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_last[1] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_last[2] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_last[3] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_last[4] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_last[5] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_last[6] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_last[7] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_last[8] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_last[9] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_last[10] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_last[11] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[20] <= ((main_liteethmaccrc32checker_crc_last[12] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[21] <= ((main_liteethmaccrc32checker_crc_last[13] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); - main_liteethmaccrc32checker_crc_next[22] <= ((main_liteethmaccrc32checker_crc_last[14] ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_last[15] ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_last[16] ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_last[17] ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_last[18] ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_last[24]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); - main_liteethmaccrc32checker_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_last[19] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_last[25]) ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); - main_liteethmaccrc32checker_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_last[20] ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_last[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); - main_liteethmaccrc32checker_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_last[21] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_last[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); - main_liteethmaccrc32checker_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_last[22] ^ main_liteethmaccrc32checker_crc_last[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_last[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); - main_liteethmaccrc32checker_crc_next[31] <= ((main_liteethmaccrc32checker_crc_last[23] ^ main_liteethmaccrc32checker_crc_last[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); end assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; @@ -1398,12 +2106,12 @@ assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteet assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; always @(*) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (main_liteethmaccrc32checker_syncfifo_replace) begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; - end + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end end assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); @@ -1413,126 +2121,99 @@ assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32 assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); always @(*) begin - builder_liteethmaccrc32checker_next_state <= 2'd0; - main_liteethmaccrc32checker_crc_ce <= 1'd0; - main_liteethmaccrc32checker_crc_reset <= 1'd0; - main_liteethmaccrc32checker_fifo_reset <= 1'd0; - builder_liteethmaccrc32checker_next_state <= builder_liteethmaccrc32checker_state; - case (builder_liteethmaccrc32checker_state) - 1'd1: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin - main_liteethmaccrc32checker_crc_ce <= 1'd1; - if (main_liteethmaccrc32checker_sink_sink_last) begin - builder_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - main_liteethmaccrc32checker_crc_reset <= 1'd1; - main_liteethmaccrc32checker_fifo_reset <= 1'd1; - builder_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign main_crc32_checker_sink_ready = ((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready); -assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_preamble_error_toggle_o_r); -assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r); -assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59); -always @(*) begin - builder_liteethmacpaddinginserter_next_state <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - main_padding_inserter_sink_ready <= 1'd0; - main_padding_inserter_source_valid <= 1'd0; - main_padding_inserter_source_first <= 1'd0; - main_padding_inserter_source_last <= 1'd0; - main_padding_inserter_source_payload_data <= 8'd0; - main_padding_inserter_source_payload_last_be <= 1'd0; - main_padding_inserter_source_payload_error <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state; - case (builder_liteethmacpaddinginserter_state) - 1'd1: begin - main_padding_inserter_source_valid <= 1'd1; - main_padding_inserter_source_last <= main_padding_inserter_counter_done; - main_padding_inserter_source_payload_data <= 1'd0; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_counter_done) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - builder_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - main_padding_inserter_source_valid <= main_padding_inserter_sink_valid; - main_padding_inserter_sink_ready <= main_padding_inserter_source_ready; - main_padding_inserter_source_first <= main_padding_inserter_sink_first; - main_padding_inserter_source_last <= main_padding_inserter_sink_last; - main_padding_inserter_source_payload_data <= main_padding_inserter_sink_payload_data; - main_padding_inserter_source_payload_last_be <= main_padding_inserter_sink_payload_last_be; - main_padding_inserter_source_payload_error <= main_padding_inserter_sink_payload_error; - if ((main_padding_inserter_source_valid & main_padding_inserter_source_ready)) begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= (main_padding_inserter_counter + 1'd1); - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (main_padding_inserter_sink_last) begin - if ((~main_padding_inserter_counter_done)) begin - main_padding_inserter_source_last <= 1'd0; - builder_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign main_padding_checker_source_valid = main_padding_checker_sink_valid; -assign main_padding_checker_sink_ready = main_padding_checker_source_ready; -assign main_padding_checker_source_first = main_padding_checker_sink_first; -assign main_padding_checker_source_last = main_padding_checker_sink_last; -assign main_padding_checker_source_payload_data = main_padding_checker_sink_payload_data; -assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be; -assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error; -always @(*) begin - main_tx_last_be_source_last <= 1'd0; - main_tx_last_be_source_payload_data <= 8'd0; - main_tx_last_be_source_payload_error <= 1'd0; - builder_liteethmactxlastbe_next_state <= 1'd0; - main_tx_last_be_source_first <= 1'd0; - main_tx_last_be_source_valid <= 1'd0; - main_tx_last_be_sink_ready <= 1'd0; - builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state; - case (builder_liteethmactxlastbe_state) - 1'd1: begin - main_tx_last_be_sink_ready <= 1'd1; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin - builder_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; - main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; - main_tx_last_be_source_first <= main_tx_last_be_sink_first; - main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; - main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; - main_tx_last_be_source_last <= main_tx_last_be_sink_payload_last_be; - if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin - if ((main_tx_last_be_sink_payload_last_be & (~main_tx_last_be_sink_last))) begin - builder_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; assign main_rx_last_be_source_first = main_rx_last_be_sink_first; @@ -1540,63 +2221,12 @@ assign main_rx_last_be_source_last = main_rx_last_be_sink_last; assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; always @(*) begin - main_rx_last_be_source_payload_last_be <= 1'd0; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; - main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; -end -assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; -assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; -assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; -assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; -always @(*) begin - main_tx_converter_converter_sink_payload_data <= 40'd0; - main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; - main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; - main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; - main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; - main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; - main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; - main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; - main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; - main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; - main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; - main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; - main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end end -assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; -assign main_tx_converter_source_first = main_tx_converter_source_source_first; -assign main_tx_converter_source_last = main_tx_converter_source_source_last; -assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; -assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; -assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; -assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; -assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; -assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; -assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; -assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); -assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); -assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; -assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); -assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); -assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); -always @(*) begin - main_tx_converter_converter_source_payload_data <= 10'd0; - case (main_tx_converter_converter_mux) - 1'd0: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; @@ -1607,25 +2237,25 @@ assign main_rx_converter_source_first = main_rx_converter_source_source_first; assign main_rx_converter_source_last = main_rx_converter_source_source_last; assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; always @(*) begin - main_rx_converter_source_payload_data <= 32'd0; - main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; - main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; - main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; - main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; end always @(*) begin - main_rx_converter_source_payload_last_be <= 4'd0; - main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; - main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; - main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; - main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; end always @(*) begin - main_rx_converter_source_payload_error <= 4'd0; - main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; - main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; - main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; - main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; end assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; @@ -1635,63 +2265,6 @@ assign main_rx_converter_source_source_payload_data = main_rx_converter_converte assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); -assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; -assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; -assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; -assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; -assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; -assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; -assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; -assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; -assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; -assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; -assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; -assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; -assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; -assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; -assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; -assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; -assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; -assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; -assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; -assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; -assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; -assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; -assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; -assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; -assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; -assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; -assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; -assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; -assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; -assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; -assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); -assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); -assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); -assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); -assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; -assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; -assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; -always @(*) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter0_ce) begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_tx_cdc_cdc_graycounter1_ce) begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; - end -end -assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; @@ -1732,100 +2305,51 @@ assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; always @(*) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter0_ce) begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; - end + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end end assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); always @(*) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (main_rx_cdc_cdc_graycounter1_ce) begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; - end + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end end assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; -assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; -assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; -assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; -assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; -assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; -assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; -assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; -assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; -assign main_tx_last_be_sink_first = main_tx_converter_source_first; -assign main_tx_last_be_sink_last = main_tx_converter_source_last; -assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; -assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; -assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; -assign main_padding_inserter_sink_valid = main_tx_last_be_source_valid; -assign main_tx_last_be_source_ready = main_padding_inserter_sink_ready; -assign main_padding_inserter_sink_first = main_tx_last_be_source_first; -assign main_padding_inserter_sink_last = main_tx_last_be_source_last; -assign main_padding_inserter_sink_payload_data = main_tx_last_be_source_payload_data; -assign main_padding_inserter_sink_payload_last_be = main_tx_last_be_source_payload_last_be; -assign main_padding_inserter_sink_payload_error = main_tx_last_be_source_payload_error; -assign main_crc32_inserter_sink_valid = main_padding_inserter_source_valid; -assign main_padding_inserter_source_ready = main_crc32_inserter_sink_ready; -assign main_crc32_inserter_sink_first = main_padding_inserter_source_first; -assign main_crc32_inserter_sink_last = main_padding_inserter_source_last; -assign main_crc32_inserter_sink_payload_data = main_padding_inserter_source_payload_data; -assign main_crc32_inserter_sink_payload_last_be = main_padding_inserter_source_payload_last_be; -assign main_crc32_inserter_sink_payload_error = main_padding_inserter_source_payload_error; -assign main_preamble_inserter_sink_valid = main_liteethmaccrc32inserter_source_valid; -assign main_liteethmaccrc32inserter_source_ready = main_preamble_inserter_sink_ready; -assign main_preamble_inserter_sink_first = main_liteethmaccrc32inserter_source_first; -assign main_preamble_inserter_sink_last = main_liteethmaccrc32inserter_source_last; -assign main_preamble_inserter_sink_payload_data = main_liteethmaccrc32inserter_source_payload_data; -assign main_preamble_inserter_sink_payload_last_be = main_liteethmaccrc32inserter_source_payload_last_be; -assign main_preamble_inserter_sink_payload_error = main_liteethmaccrc32inserter_source_payload_error; -assign main_tx_gap_inserter_sink_valid = main_preamble_inserter_source_valid; -assign main_preamble_inserter_source_ready = main_tx_gap_inserter_sink_ready; -assign main_tx_gap_inserter_sink_first = main_preamble_inserter_source_first; -assign main_tx_gap_inserter_sink_last = main_preamble_inserter_source_last; -assign main_tx_gap_inserter_sink_payload_data = main_preamble_inserter_source_payload_data; -assign main_tx_gap_inserter_sink_payload_last_be = main_preamble_inserter_source_payload_last_be; -assign main_tx_gap_inserter_sink_payload_error = main_preamble_inserter_source_payload_error; -assign main_maccore_ethphy_sink_valid = main_tx_gap_inserter_source_valid; -assign main_tx_gap_inserter_source_ready = main_maccore_ethphy_sink_ready; -assign main_maccore_ethphy_sink_first = main_tx_gap_inserter_source_first; -assign main_maccore_ethphy_sink_last = main_tx_gap_inserter_source_last; -assign main_maccore_ethphy_sink_payload_data = main_tx_gap_inserter_source_payload_data; -assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_inserter_source_payload_last_be; -assign main_maccore_ethphy_sink_payload_error = main_tx_gap_inserter_source_payload_error; -assign main_preamble_checker_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; -assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_preamble_checker_sink_ready; -assign main_preamble_checker_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; -assign main_preamble_checker_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; -assign main_preamble_checker_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; -assign main_preamble_checker_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; -assign main_preamble_checker_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; -assign main_crc32_checker_sink_valid = main_preamble_checker_source_valid; -assign main_preamble_checker_source_ready = main_crc32_checker_sink_ready; -assign main_crc32_checker_sink_first = main_preamble_checker_source_first; -assign main_crc32_checker_sink_last = main_preamble_checker_source_last; -assign main_crc32_checker_sink_payload_data = main_preamble_checker_source_payload_data; -assign main_crc32_checker_sink_payload_last_be = main_preamble_checker_source_payload_last_be; -assign main_crc32_checker_sink_payload_error = main_preamble_checker_source_payload_error; -assign main_padding_checker_sink_valid = main_liteethmaccrc32checker_source_source_valid; -assign main_liteethmaccrc32checker_source_source_ready = main_padding_checker_sink_ready; -assign main_padding_checker_sink_first = main_liteethmaccrc32checker_source_source_first; -assign main_padding_checker_sink_last = main_liteethmaccrc32checker_source_source_last; -assign main_padding_checker_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; -assign main_padding_checker_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; -assign main_padding_checker_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; -assign main_rx_last_be_sink_valid = main_padding_checker_source_valid; -assign main_padding_checker_source_ready = main_rx_last_be_sink_ready; -assign main_rx_last_be_sink_first = main_padding_checker_source_first; -assign main_rx_last_be_sink_last = main_padding_checker_source_last; -assign main_rx_last_be_sink_payload_data = main_padding_checker_source_payload_data; -assign main_rx_last_be_sink_payload_last_be = main_padding_checker_source_payload_last_be; -assign main_rx_last_be_sink_payload_error = main_padding_checker_source_payload_error; +assign main_rx_preamble_sink_valid = main_maccore_ethphy_liteethphyrgmiirx_source_valid; +assign main_maccore_ethphy_liteethphyrgmiirx_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_liteethphyrgmiirx_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_liteethphyrgmiirx_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_liteethphyrgmiirx_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_liteethphyrgmiirx_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_liteethphyrgmiirx_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; assign main_rx_converter_sink_first = main_rx_last_be_source_first; @@ -1840,460 +2364,454 @@ assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; -assign main_writer_sink_sink_valid = main_sink_valid; -assign main_sink_ready = main_writer_sink_sink_ready; -assign main_writer_sink_sink_first = main_sink_first; -assign main_writer_sink_sink_last = main_sink_last; -assign main_writer_sink_sink_payload_data = main_sink_payload_data; -assign main_writer_sink_sink_payload_last_be = main_sink_payload_last_be; -assign main_writer_sink_sink_payload_error = main_sink_payload_error; -assign main_source_valid = main_reader_source_source_valid; -assign main_reader_source_source_ready = main_source_ready; -assign main_source_first = main_reader_source_source_first; -assign main_source_last = main_reader_source_source_last; -assign main_source_payload_data = main_reader_source_source_payload_data; -assign main_source_payload_last_be = main_reader_source_source_payload_last_be; -assign main_source_payload_error = main_reader_source_source_payload_error; -always @(*) begin - main_writer_inc <= 3'd0; - case (main_writer_sink_sink_payload_last_be) - 1'd1: begin - main_writer_inc <= 1'd1; - end - 2'd2: begin - main_writer_inc <= 2'd2; - end - 3'd4: begin - main_writer_inc <= 2'd3; - end - default: begin - main_writer_inc <= 3'd4; - end - endcase -end -assign main_writer_stat_fifo_sink_payload_slot = main_writer_slot; -assign main_writer_stat_fifo_sink_payload_length = main_writer_counter; -assign main_writer_stat_fifo_source_ready = main_writer_available_clear; -assign main_writer_available_trigger = main_writer_stat_fifo_source_valid; -assign main_writer_slot_status = main_writer_stat_fifo_source_payload_slot; -assign main_writer_length_status = main_writer_stat_fifo_source_payload_length; -always @(*) begin - main_writer_memory1_adr <= 9'd0; - main_writer_memory1_we <= 1'd0; - main_writer_memory0_adr <= 9'd0; - main_writer_memory1_dat_w <= 32'd0; - main_writer_memory0_we <= 1'd0; - main_writer_memory0_dat_w <= 32'd0; - case (main_writer_slot) - 1'd0: begin - main_writer_memory0_adr <= main_writer_counter[31:2]; - main_writer_memory0_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - main_writer_memory1_adr <= main_writer_counter[31:2]; - main_writer_memory1_dat_w <= main_writer_sink_sink_payload_data; - if ((main_writer_sink_sink_valid & main_writer_ongoing)) begin - main_writer_memory1_we <= 4'd15; - end - end - endcase -end -assign main_writer_available0 = main_writer_available_status; -assign main_writer_available1 = main_writer_available_pending; -always @(*) begin - main_writer_available_clear <= 1'd0; - if ((main_writer_pending_re & main_writer_pending_r)) begin - main_writer_available_clear <= 1'd1; - end -end -assign main_writer_irq = (main_writer_pending_status & main_writer_enable_storage); -assign main_writer_available_status = main_writer_available_trigger; -assign main_writer_available_pending = main_writer_available_trigger; -assign main_writer_stat_fifo_syncfifo_din = {main_writer_stat_fifo_fifo_in_last, main_writer_stat_fifo_fifo_in_first, main_writer_stat_fifo_fifo_in_payload_length, main_writer_stat_fifo_fifo_in_payload_slot}; -assign {main_writer_stat_fifo_fifo_out_last, main_writer_stat_fifo_fifo_out_first, main_writer_stat_fifo_fifo_out_payload_length, main_writer_stat_fifo_fifo_out_payload_slot} = main_writer_stat_fifo_syncfifo_dout; -assign main_writer_stat_fifo_sink_ready = main_writer_stat_fifo_syncfifo_writable; -assign main_writer_stat_fifo_syncfifo_we = main_writer_stat_fifo_sink_valid; -assign main_writer_stat_fifo_fifo_in_first = main_writer_stat_fifo_sink_first; -assign main_writer_stat_fifo_fifo_in_last = main_writer_stat_fifo_sink_last; -assign main_writer_stat_fifo_fifo_in_payload_slot = main_writer_stat_fifo_sink_payload_slot; -assign main_writer_stat_fifo_fifo_in_payload_length = main_writer_stat_fifo_sink_payload_length; -assign main_writer_stat_fifo_source_valid = main_writer_stat_fifo_syncfifo_readable; -assign main_writer_stat_fifo_source_first = main_writer_stat_fifo_fifo_out_first; -assign main_writer_stat_fifo_source_last = main_writer_stat_fifo_fifo_out_last; -assign main_writer_stat_fifo_source_payload_slot = main_writer_stat_fifo_fifo_out_payload_slot; -assign main_writer_stat_fifo_source_payload_length = main_writer_stat_fifo_fifo_out_payload_length; -assign main_writer_stat_fifo_syncfifo_re = main_writer_stat_fifo_source_ready; -always @(*) begin - main_writer_stat_fifo_wrport_adr <= 1'd0; - if (main_writer_stat_fifo_replace) begin - main_writer_stat_fifo_wrport_adr <= (main_writer_stat_fifo_produce - 1'd1); - end else begin - main_writer_stat_fifo_wrport_adr <= main_writer_stat_fifo_produce; - end -end -assign main_writer_stat_fifo_wrport_dat_w = main_writer_stat_fifo_syncfifo_din; -assign main_writer_stat_fifo_wrport_we = (main_writer_stat_fifo_syncfifo_we & (main_writer_stat_fifo_syncfifo_writable | main_writer_stat_fifo_replace)); -assign main_writer_stat_fifo_do_read = (main_writer_stat_fifo_syncfifo_readable & main_writer_stat_fifo_syncfifo_re); -assign main_writer_stat_fifo_rdport_adr = main_writer_stat_fifo_consume; -assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r; -assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2); -assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0); -always @(*) begin - builder_liteethmacsramwriter_next_state <= 3'd0; - main_writer_slot_ce <= 1'd0; - main_writer_counter_t_next_value <= 32'd0; - main_writer_counter_t_next_value_ce <= 1'd0; - main_writer_start <= 1'd0; - main_writer_ongoing <= 1'd0; - main_writer_errors_status_f_next_value <= 32'd0; - main_writer_stat_fifo_sink_valid <= 1'd0; - main_writer_errors_status_f_next_value_ce <= 1'd0; - builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; - case (builder_liteethmacsramwriter_state) - 1'd1: begin - if (main_writer_sink_sink_valid) begin - if ((main_writer_counter == 11'd1530)) begin - builder_liteethmacsramwriter_next_state <= 2'd3; - end else begin - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_ongoing <= 1'd1; - end - if (main_writer_sink_sink_last) begin - if (((main_writer_sink_sink_payload_error & main_writer_sink_sink_payload_last_be) != 1'd0)) begin - builder_liteethmacsramwriter_next_state <= 2'd2; - end else begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((main_writer_sink_sink_valid & main_writer_sink_sink_last)) begin - builder_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - main_writer_counter_t_next_value <= 1'd0; - main_writer_counter_t_next_value_ce <= 1'd1; - main_writer_slot_ce <= 1'd1; - main_writer_stat_fifo_sink_valid <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (main_writer_sink_sink_valid) begin - if (main_writer_stat_fifo_sink_ready) begin - main_writer_start <= 1'd1; - main_writer_ongoing <= 1'd1; - main_writer_counter_t_next_value <= (main_writer_counter + main_writer_inc); - main_writer_counter_t_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 1'd1; - end else begin - main_writer_errors_status_f_next_value <= (main_writer_errors_status + 1'd1); - main_writer_errors_status_f_next_value_ce <= 1'd1; - builder_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign main_reader_cmd_fifo_sink_valid = main_reader_start_start_re; -assign main_reader_cmd_fifo_sink_payload_slot = main_reader_slot_storage; -assign main_reader_cmd_fifo_sink_payload_length = main_reader_length_storage; -assign main_reader_ready_status = main_reader_cmd_fifo_sink_ready; -assign main_reader_level_status = main_reader_cmd_fifo_level; -always @(*) begin - main_reader_source_source_payload_last_be <= 4'd0; - if (main_reader_source_source_last) begin - case (main_reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - main_reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - main_reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - main_reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - main_reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign main_reader_memory0_adr = main_reader_read_address[10:2]; -assign main_reader_memory1_adr = main_reader_read_address[10:2]; -always @(*) begin - main_reader_source_source_payload_data <= 32'd0; - case (main_reader_cmd_fifo_source_payload_slot) - 1'd0: begin - main_reader_source_source_payload_data <= main_reader_memory0_dat_r; - end - 1'd1: begin - main_reader_source_source_payload_data <= main_reader_memory1_dat_r; - end - endcase -end -assign main_reader_event00 = main_reader_eventsourcepulse_status; -assign main_reader_event01 = main_reader_eventsourcepulse_pending; -always @(*) begin - main_reader_eventsourcepulse_clear <= 1'd0; - if ((main_reader_pending_re & main_reader_pending_r)) begin - main_reader_eventsourcepulse_clear <= 1'd1; - end -end -assign main_reader_irq = (main_reader_pending_status & main_reader_enable_storage); -assign main_reader_eventsourcepulse_status = 1'd0; -assign main_reader_cmd_fifo_syncfifo_din = {main_reader_cmd_fifo_fifo_in_last, main_reader_cmd_fifo_fifo_in_first, main_reader_cmd_fifo_fifo_in_payload_length, main_reader_cmd_fifo_fifo_in_payload_slot}; -assign {main_reader_cmd_fifo_fifo_out_last, main_reader_cmd_fifo_fifo_out_first, main_reader_cmd_fifo_fifo_out_payload_length, main_reader_cmd_fifo_fifo_out_payload_slot} = main_reader_cmd_fifo_syncfifo_dout; -assign main_reader_cmd_fifo_sink_ready = main_reader_cmd_fifo_syncfifo_writable; -assign main_reader_cmd_fifo_syncfifo_we = main_reader_cmd_fifo_sink_valid; -assign main_reader_cmd_fifo_fifo_in_first = main_reader_cmd_fifo_sink_first; -assign main_reader_cmd_fifo_fifo_in_last = main_reader_cmd_fifo_sink_last; -assign main_reader_cmd_fifo_fifo_in_payload_slot = main_reader_cmd_fifo_sink_payload_slot; -assign main_reader_cmd_fifo_fifo_in_payload_length = main_reader_cmd_fifo_sink_payload_length; -assign main_reader_cmd_fifo_source_valid = main_reader_cmd_fifo_syncfifo_readable; -assign main_reader_cmd_fifo_source_first = main_reader_cmd_fifo_fifo_out_first; -assign main_reader_cmd_fifo_source_last = main_reader_cmd_fifo_fifo_out_last; -assign main_reader_cmd_fifo_source_payload_slot = main_reader_cmd_fifo_fifo_out_payload_slot; -assign main_reader_cmd_fifo_source_payload_length = main_reader_cmd_fifo_fifo_out_payload_length; -assign main_reader_cmd_fifo_syncfifo_re = main_reader_cmd_fifo_source_ready; -always @(*) begin - main_reader_cmd_fifo_wrport_adr <= 1'd0; - if (main_reader_cmd_fifo_replace) begin - main_reader_cmd_fifo_wrport_adr <= (main_reader_cmd_fifo_produce - 1'd1); - end else begin - main_reader_cmd_fifo_wrport_adr <= main_reader_cmd_fifo_produce; - end -end -assign main_reader_cmd_fifo_wrport_dat_w = main_reader_cmd_fifo_syncfifo_din; -assign main_reader_cmd_fifo_wrport_we = (main_reader_cmd_fifo_syncfifo_we & (main_reader_cmd_fifo_syncfifo_writable | main_reader_cmd_fifo_replace)); -assign main_reader_cmd_fifo_do_read = (main_reader_cmd_fifo_syncfifo_readable & main_reader_cmd_fifo_syncfifo_re); -assign main_reader_cmd_fifo_rdport_adr = main_reader_cmd_fifo_consume; -assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r; -assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2); -assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0); -always @(*) begin - main_reader_source_source_valid <= 1'd0; - main_reader_start <= 1'd0; - main_reader_source_source_last <= 1'd0; - builder_liteethmacsramreader_next_state <= 2'd0; - main_reader_counter_next_value <= 11'd0; - main_reader_read_address <= 11'd0; - main_reader_counter_next_value_ce <= 1'd0; - main_reader_cmd_fifo_source_ready <= 1'd0; - main_reader_eventsourcepulse_trigger <= 1'd0; - builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; - case (builder_liteethmacsramreader_state) - 1'd1: begin - main_reader_source_source_valid <= 1'd1; - main_reader_source_source_last <= (main_reader_counter >= (main_reader_cmd_fifo_source_payload_length - 3'd4)); - main_reader_read_address <= main_reader_counter; - if (main_reader_source_source_ready) begin - main_reader_read_address <= (main_reader_counter + 3'd4); - main_reader_counter_next_value <= (main_reader_counter + 3'd4); - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_source_source_last) begin - builder_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - main_reader_eventsourcepulse_trigger <= 1'd1; - main_reader_cmd_fifo_source_ready <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - main_reader_counter_next_value <= 1'd0; - main_reader_counter_next_value_ce <= 1'd1; - if (main_reader_cmd_fifo_source_valid) begin - main_reader_start <= 1'd1; - builder_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign main_ev_irq = (main_writer_irq | main_reader_irq); -assign main_sram0_adr0 = main_sram0_bus_adr0[8:0]; -assign main_sram0_bus_dat_r0 = main_sram0_dat_r0; -assign main_sram1_adr0 = main_sram1_bus_adr0[8:0]; -assign main_sram1_bus_dat_r0 = main_sram1_dat_r0; -always @(*) begin - main_sram0_we <= 4'd0; - main_sram0_we[0] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[0]); - main_sram0_we[1] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[1]); - main_sram0_we[2] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[2]); - main_sram0_we[3] <= (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & main_sram0_bus_we1) & main_sram0_bus_sel1[3]); -end -assign main_sram0_adr1 = main_sram0_bus_adr1[8:0]; -assign main_sram0_bus_dat_r1 = main_sram0_dat_r1; -assign main_sram0_dat_w = main_sram0_bus_dat_w1; -always @(*) begin - main_sram1_we <= 4'd0; - main_sram1_we[0] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[0]); - main_sram1_we[1] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[1]); - main_sram1_we[2] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[2]); - main_sram1_we[3] <= (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & main_sram1_bus_we1) & main_sram1_bus_sel1[3]); -end -assign main_sram1_adr1 = main_sram1_bus_adr1[8:0]; -assign main_sram1_bus_dat_r1 = main_sram1_dat_r1; -assign main_sram1_dat_w = main_sram1_bus_dat_w1; -always @(*) begin - main_slave_sel <= 4'd0; - main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); - main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); - main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); - main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); -end -assign main_sram0_bus_adr0 = main_bus_adr; -assign main_sram0_bus_dat_w0 = main_bus_dat_w; -assign main_sram0_bus_sel0 = main_bus_sel; -assign main_sram0_bus_stb0 = main_bus_stb; -assign main_sram0_bus_we0 = main_bus_we; -assign main_sram0_bus_cti0 = main_bus_cti; -assign main_sram0_bus_bte0 = main_bus_bte; -assign main_sram1_bus_adr0 = main_bus_adr; -assign main_sram1_bus_dat_w0 = main_bus_dat_w; -assign main_sram1_bus_sel0 = main_bus_sel; -assign main_sram1_bus_stb0 = main_bus_stb; -assign main_sram1_bus_we0 = main_bus_we; -assign main_sram1_bus_cti0 = main_bus_cti; -assign main_sram1_bus_bte0 = main_bus_bte; -assign main_sram0_bus_adr1 = main_bus_adr; -assign main_sram0_bus_dat_w1 = main_bus_dat_w; -assign main_sram0_bus_sel1 = main_bus_sel; -assign main_sram0_bus_stb1 = main_bus_stb; -assign main_sram0_bus_we1 = main_bus_we; -assign main_sram0_bus_cti1 = main_bus_cti; -assign main_sram0_bus_bte1 = main_bus_bte; -assign main_sram1_bus_adr1 = main_bus_adr; -assign main_sram1_bus_dat_w1 = main_bus_dat_w; -assign main_sram1_bus_sel1 = main_bus_sel; -assign main_sram1_bus_stb1 = main_bus_stb; -assign main_sram1_bus_we1 = main_bus_we; -assign main_sram1_bus_cti1 = main_bus_cti; -assign main_sram1_bus_bte1 = main_bus_bte; -assign main_sram0_bus_cyc0 = (main_bus_cyc & main_slave_sel[0]); -assign main_sram1_bus_cyc0 = (main_bus_cyc & main_slave_sel[1]); -assign main_sram0_bus_cyc1 = (main_bus_cyc & main_slave_sel[2]); -assign main_sram1_bus_cyc1 = (main_bus_cyc & main_slave_sel[3]); -assign main_bus_ack = (((main_sram0_bus_ack0 | main_sram1_bus_ack0) | main_sram0_bus_ack1) | main_sram1_bus_ack1); -assign main_bus_err = (((main_sram0_bus_err0 | main_sram1_bus_err0) | main_sram0_bus_err1) | main_sram1_bus_err1); -assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) | ({32{main_slave_sel_r[1]}} & main_sram1_bus_dat_r0)) | ({32{main_slave_sel_r[2]}} & main_sram0_bus_dat_r1)) | ({32{main_slave_sel_r[3]}} & main_sram1_bus_dat_r1)); -always @(*) begin - builder_maccore_adr <= 14'd0; - builder_maccore_we <= 1'd0; - builder_maccore_dat_w <= 32'd0; - builder_maccore_wishbone_ack <= 1'd0; - builder_next_state <= 1'd0; - builder_maccore_wishbone_dat_r <= 32'd0; - builder_next_state <= builder_state; - case (builder_state) - 1'd1: begin - builder_maccore_wishbone_ack <= 1'd1; - builder_maccore_wishbone_dat_r <= builder_maccore_dat_r; - builder_next_state <= 1'd0; - end - default: begin - builder_maccore_dat_w <= builder_maccore_wishbone_dat_w; - if ((builder_maccore_wishbone_cyc & builder_maccore_wishbone_stb)) begin - builder_maccore_adr <= builder_maccore_wishbone_adr; - builder_maccore_we <= (builder_maccore_wishbone_we & (builder_maccore_wishbone_sel != 1'd0)); - builder_next_state <= 1'd1; - end - end - endcase -end -assign builder_shared_adr = builder_array_muxed0; -assign builder_shared_dat_w = builder_array_muxed1; -assign builder_shared_sel = builder_array_muxed2; -assign builder_shared_cyc = builder_array_muxed3; -assign builder_shared_stb = builder_array_muxed4; -assign builder_shared_we = builder_array_muxed5; -assign builder_shared_cti = builder_array_muxed6; -assign builder_shared_bte = builder_array_muxed7; -assign main_wb_bus_dat_r = builder_shared_dat_r; -assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); -assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); -assign builder_request = {main_wb_bus_cyc}; -assign builder_grant = 1'd0; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; always @(*) begin - builder_slave_sel <= 2'd0; - builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); - builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase end -assign main_bus_adr = builder_shared_adr; -assign main_bus_dat_w = builder_shared_dat_w; -assign main_bus_sel = builder_shared_sel; -assign main_bus_stb = builder_shared_stb; -assign main_bus_we = builder_shared_we; -assign main_bus_cti = builder_shared_cti; -assign main_bus_bte = builder_shared_bte; -assign builder_maccore_wishbone_adr = builder_shared_adr; -assign builder_maccore_wishbone_dat_w = builder_shared_dat_w; -assign builder_maccore_wishbone_sel = builder_shared_sel; -assign builder_maccore_wishbone_stb = builder_shared_stb; -assign builder_maccore_wishbone_we = builder_shared_we; -assign builder_maccore_wishbone_cti = builder_shared_cti; -assign builder_maccore_wishbone_bte = builder_shared_bte; -assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); -assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]); -assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err); -assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; always @(*) begin - builder_shared_ack <= 1'd0; - builder_error <= 1'd0; - builder_shared_dat_r <= 32'd0; - builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack); - builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r)); - if (builder_done) begin - builder_shared_dat_r <= 32'd4294967295; - builder_shared_ack <= 1'd1; - builder_error <= 1'd1; - end + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase end -assign builder_done = (builder_count == 1'd0); assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank0_reset0_we <= 1'd0; - builder_csrbank0_reset0_re <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_scratch0_re <= 1'd0; - builder_csrbank0_scratch0_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; - builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end end assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank0_bus_errors_re <= 1'd0; - builder_csrbank0_bus_errors_we <= 1'd0; - if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; - builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); - end + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end end always @(*) begin - main_maccore_maccore_soc_rst <= 1'd0; - if (main_maccore_maccore_reset_re) begin - main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; - end + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end end assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; @@ -2303,218 +2821,230 @@ assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_slot_re <= 1'd0; - builder_csrbank1_sram_writer_slot_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end end -assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0]; +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_writer_length_re <= 1'd0; - builder_csrbank1_sram_writer_length_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; always @(*) begin - builder_csrbank1_sram_writer_errors_we <= 1'd0; - builder_csrbank1_sram_writer_errors_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_status_we <= 1'd0; - builder_csrbank1_sram_writer_ev_status_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin - builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; - builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin - builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin - builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end -assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0]; +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - main_reader_start_start_we <= 1'd0; - main_reader_start_start_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin - main_reader_start_start_re <= builder_interface1_bank_bus_we; - main_reader_start_start_we <= (~builder_interface1_bank_bus_we); - end + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ready_we <= 1'd0; - builder_csrbank1_sram_reader_ready_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin - builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; always @(*) begin - builder_csrbank1_sram_reader_level_re <= 1'd0; - builder_csrbank1_sram_reader_level_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin - builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_slot0_re <= 1'd0; - builder_csrbank1_sram_reader_slot0_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin - builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; always @(*) begin - builder_csrbank1_sram_reader_length0_we <= 1'd0; - builder_csrbank1_sram_reader_length0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin - builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_status_re <= 1'd0; - builder_csrbank1_sram_reader_ev_status_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin - builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; - builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin - builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin - builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; - builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); - end + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end end assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank1_preamble_crc_re <= 1'd0; - builder_csrbank1_preamble_crc_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin - builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_preamble_errors_re <= 1'd0; - builder_csrbank1_preamble_errors_we <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin - builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - builder_csrbank1_crc_errors_we <= 1'd0; - builder_csrbank1_crc_errors_re <= 1'd0; - if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin - builder_csrbank1_crc_errors_re <= builder_interface1_bank_bus_we; - builder_csrbank1_crc_errors_we <= (~builder_interface1_bank_bus_we); - end -end -assign builder_csrbank1_sram_writer_slot_w = main_writer_slot_status; -assign main_writer_slot_we = builder_csrbank1_sram_writer_slot_we; -assign builder_csrbank1_sram_writer_length_w = main_writer_length_status[31:0]; -assign main_writer_length_we = builder_csrbank1_sram_writer_length_we; -assign builder_csrbank1_sram_writer_errors_w = main_writer_errors_status[31:0]; -assign main_writer_errors_we = builder_csrbank1_sram_writer_errors_we; -assign main_writer_status_status = main_writer_available0; -assign builder_csrbank1_sram_writer_ev_status_w = main_writer_status_status; -assign main_writer_status_we = builder_csrbank1_sram_writer_ev_status_we; -assign main_writer_pending_status = main_writer_available1; -assign builder_csrbank1_sram_writer_ev_pending_w = main_writer_pending_status; -assign main_writer_pending_we = builder_csrbank1_sram_writer_ev_pending_we; -assign main_writer_available2 = main_writer_enable_storage; -assign builder_csrbank1_sram_writer_ev_enable0_w = main_writer_enable_storage; -assign builder_csrbank1_sram_reader_ready_w = main_reader_ready_status; -assign main_reader_ready_we = builder_csrbank1_sram_reader_ready_we; -assign builder_csrbank1_sram_reader_level_w = main_reader_level_status[1:0]; -assign main_reader_level_we = builder_csrbank1_sram_reader_level_we; -assign builder_csrbank1_sram_reader_slot0_w = main_reader_slot_storage; -assign builder_csrbank1_sram_reader_length0_w = main_reader_length_storage[10:0]; -assign main_reader_status_status = main_reader_event00; -assign builder_csrbank1_sram_reader_ev_status_w = main_reader_status_status; -assign main_reader_status_we = builder_csrbank1_sram_reader_ev_status_we; -assign main_reader_pending_status = main_reader_event01; -assign builder_csrbank1_sram_reader_ev_pending_w = main_reader_pending_status; -assign main_reader_pending_we = builder_csrbank1_sram_reader_ev_pending_we; -assign main_reader_event02 = main_reader_enable_storage; -assign builder_csrbank1_sram_reader_ev_enable0_w = main_reader_enable_storage; -assign builder_csrbank1_preamble_crc_w = main_preamble_crc_status; -assign main_preamble_crc_we = builder_csrbank1_preamble_crc_we; -assign builder_csrbank1_preamble_errors_w = main_preamble_errors_status[31:0]; -assign main_preamble_errors_we = builder_csrbank1_preamble_errors_we; -assign builder_csrbank1_crc_errors_w = main_crc_errors_status[31:0]; -assign main_crc_errors_we = builder_csrbank1_crc_errors_we; + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_crg_reset0_we <= 1'd0; - builder_csrbank2_crg_reset0_re <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin - builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; always @(*) begin - builder_csrbank2_mdio_w0_re <= 1'd0; - builder_csrbank2_mdio_w0_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin - builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; always @(*) begin - builder_csrbank2_mdio_r_re <= 1'd0; - builder_csrbank2_mdio_r_we <= 1'd0; - if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin - builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; - builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); - end + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end end assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; @@ -2523,1151 +3053,1605 @@ assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; -assign builder_csr_interconnect_adr = builder_maccore_adr; -assign builder_csr_interconnect_we = builder_maccore_we; -assign builder_csr_interconnect_dat_w = builder_maccore_dat_w; -assign builder_maccore_dat_r = builder_csr_interconnect_dat_r; -assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr; -assign builder_interface0_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface1_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface2_bank_bus_we = builder_csr_interconnect_we; -assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; -assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); -always @(*) begin - builder_array_muxed0 <= 30'd0; - case (builder_grant) - default: begin - builder_array_muxed0 <= main_wb_bus_adr; - end - endcase -end -always @(*) begin - builder_array_muxed1 <= 32'd0; - case (builder_grant) - default: begin - builder_array_muxed1 <= main_wb_bus_dat_w; - end - endcase -end -always @(*) begin - builder_array_muxed2 <= 4'd0; - case (builder_grant) - default: begin - builder_array_muxed2 <= main_wb_bus_sel; - end - endcase -end -always @(*) begin - builder_array_muxed3 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed3 <= main_wb_bus_cyc; - end - endcase -end -always @(*) begin - builder_array_muxed4 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed4 <= main_wb_bus_stb; - end - endcase -end -always @(*) begin - builder_array_muxed5 <= 1'd0; - case (builder_grant) - default: begin - builder_array_muxed5 <= main_wb_bus_we; - end - endcase -end -always @(*) begin - builder_array_muxed6 <= 3'd0; - case (builder_grant) - default: begin - builder_array_muxed6 <= main_wb_bus_cti; - end - endcase -end -always @(*) begin - builder_array_muxed7 <= 2'd0; - case (builder_grant) - default: begin - builder_array_muxed7 <= main_wb_bus_bte; - end - endcase -end -assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_maccore_ethphy_locked); -always @(*) begin - main_maccore_ethphy__r_status <= 1'd0; - main_maccore_ethphy__r_status <= main_maccore_ethphy_r; - main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl0_regs1; -end -assign main_ps_preamble_error_toggle_o = builder_xilinxmultiregimpl1_regs1; -assign main_ps_crc_error_toggle_o = builder_xilinxmultiregimpl2_regs1; -assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl3_regs1; -assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl4_regs1; -assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl5_regs1; -assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl6_regs1; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +assign builder_xilinxasyncresetsynchronizerimpl0_async_reset = (~main_maccore_ethphy_locked); +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; - builder_liteethmacpreamblechecker_state <= builder_liteethmacpreamblechecker_next_state; - if (main_liteethmaccrc32checker_crc_ce) begin - main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_next; - end - if (main_liteethmaccrc32checker_crc_reset) begin - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin - if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (main_liteethmaccrc32checker_syncfifo_do_read) begin - main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (main_liteethmaccrc32checker_fifo_reset) begin - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - builder_liteethmaccrc32checker_state <= builder_liteethmaccrc32checker_next_state; - if (((~main_crc32_checker_source_valid) | main_crc32_checker_source_ready)) begin - main_crc32_checker_source_valid <= main_crc32_checker_sink_valid; - main_crc32_checker_source_first <= main_crc32_checker_sink_first; - main_crc32_checker_source_last <= main_crc32_checker_sink_last; - main_crc32_checker_source_payload_data <= main_crc32_checker_sink_payload_data; - main_crc32_checker_source_payload_last_be <= main_crc32_checker_sink_payload_last_be; - main_crc32_checker_source_payload_error <= main_crc32_checker_sink_payload_error; - end - if (main_ps_preamble_error_i) begin - main_ps_preamble_error_toggle_i <= (~main_ps_preamble_error_toggle_i); - end - if (main_ps_crc_error_i) begin - main_ps_crc_error_toggle_i <= (~main_ps_crc_error_toggle_i); - end - if (main_rx_converter_converter_source_ready) begin - main_rx_converter_converter_strobe_all <= 1'd0; - end - if (main_rx_converter_converter_load_part) begin - if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin - main_rx_converter_converter_demux <= 1'd0; - main_rx_converter_converter_strobe_all <= 1'd1; - end else begin - main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); - end - end - if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; - main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; - end else begin - main_rx_converter_converter_source_first <= 1'd0; - main_rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin - main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); - main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); - end - end - if (main_rx_converter_converter_load_part) begin - case (main_rx_converter_converter_demux) - 1'd0: begin - main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; - end - 1'd1: begin - main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; - end - 2'd2: begin - main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; - end - 2'd3: begin - main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; - end - endcase - end - if (main_rx_converter_converter_load_part) begin - main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); - end - main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; - main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; - main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; - main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; - main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; - main_liteethmaccrc32checker_syncfifo_level <= 3'd0; - main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; - main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; - main_crc32_checker_source_valid <= 1'd0; - main_crc32_checker_source_payload_data <= 8'd0; - main_crc32_checker_source_payload_last_be <= 1'd0; - main_crc32_checker_source_payload_error <= 1'd0; - main_rx_converter_converter_source_payload_data <= 40'd0; - main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; - main_rx_converter_converter_demux <= 2'd0; - main_rx_converter_converter_strobe_all <= 1'd0; - main_rx_cdc_cdc_graycounter0_q <= 6'd0; - main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - builder_liteethmacpreamblechecker_state <= 1'd0; - builder_liteethmaccrc32checker_state <= 2'd0; - end - builder_xilinxmultiregimpl6_regs0 <= main_rx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl6_regs1 <= builder_xilinxmultiregimpl6_regs0; + main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; + main_maccore_ethphy_liteethphyrgmiirx_source_valid <= main_maccore_ethphy_liteethphyrgmiirx_rx_ctl; + main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= main_maccore_ethphy_liteethphyrgmiirx_rx_data; + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_liteethphyrgmiirx_source_valid <= 1'd0; + main_maccore_ethphy_liteethphyrgmiirx_source_payload_data <= 8'd0; + main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_d <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end always @(posedge eth_tx_clk) begin - builder_liteethmacgap_state <= builder_liteethmacgap_next_state; - if (main_tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - main_tx_gap_inserter_counter <= main_tx_gap_inserter_counter_liteethmacgap_next_value; - end - builder_liteethmacpreambleinserter_state <= builder_liteethmacpreambleinserter_next_state; - if (main_preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - main_preamble_inserter_count <= main_preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (main_liteethmaccrc32inserter_is_ongoing0) begin - main_liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((main_liteethmaccrc32inserter_is_ongoing1 & (~main_liteethmaccrc32inserter_cnt_done))) begin - main_liteethmaccrc32inserter_cnt <= (main_liteethmaccrc32inserter_cnt - main_liteethmaccrc32inserter_source_ready); - end - end - if (main_liteethmaccrc32inserter_ce) begin - main_liteethmaccrc32inserter_reg <= main_liteethmaccrc32inserter_next; - end - if (main_liteethmaccrc32inserter_reset) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - end - builder_liteethmaccrc32inserter_state <= builder_liteethmaccrc32inserter_next_state; - if (((~main_crc32_inserter_source_valid) | main_crc32_inserter_source_ready)) begin - main_crc32_inserter_source_valid <= main_crc32_inserter_sink_valid; - main_crc32_inserter_source_first <= main_crc32_inserter_sink_first; - main_crc32_inserter_source_last <= main_crc32_inserter_sink_last; - main_crc32_inserter_source_payload_data <= main_crc32_inserter_sink_payload_data; - main_crc32_inserter_source_payload_last_be <= main_crc32_inserter_sink_payload_last_be; - main_crc32_inserter_source_payload_error <= main_crc32_inserter_sink_payload_error; - end - builder_liteethmacpaddinginserter_state <= builder_liteethmacpaddinginserter_next_state; - if (main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - main_padding_inserter_counter <= main_padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - builder_liteethmactxlastbe_state <= builder_liteethmactxlastbe_next_state; - if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin - if (main_tx_converter_converter_last) begin - main_tx_converter_converter_mux <= 1'd0; - end else begin - main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); - end - end - main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; - main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - main_liteethmaccrc32inserter_reg <= 32'd4294967295; - main_liteethmaccrc32inserter_cnt <= 2'd3; - main_crc32_inserter_source_valid <= 1'd0; - main_crc32_inserter_source_payload_data <= 8'd0; - main_crc32_inserter_source_payload_last_be <= 1'd0; - main_crc32_inserter_source_payload_error <= 1'd0; - main_padding_inserter_counter <= 16'd0; - main_tx_converter_converter_mux <= 2'd0; - main_tx_cdc_cdc_graycounter1_q <= 6'd0; - main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - builder_liteethmacgap_state <= 1'd0; - builder_liteethmacpreambleinserter_state <= 2'd0; - builder_liteethmaccrc32inserter_state <= 2'd0; - builder_liteethmacpaddinginserter_state <= 1'd0; - builder_liteethmactxlastbe_state <= 1'd0; - end - builder_xilinxmultiregimpl3_regs0 <= main_tx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl3_regs1 <= builder_xilinxmultiregimpl3_regs0; + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; end always @(posedge por_clk) begin - main_maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin - if (main_maccore_maccore_bus_error) begin - main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); - end - end - if (main_ps_preamble_error_o) begin - main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); - end - if (main_ps_crc_error_o) begin - main_crc_errors_status <= (main_crc_errors_status + 1'd1); - end - main_ps_preamble_error_toggle_o_r <= main_ps_preamble_error_toggle_o; - main_ps_crc_error_toggle_o_r <= main_ps_crc_error_toggle_o; - main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; - main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; - main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; - main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; - if (main_writer_slot_ce) begin - main_writer_slot <= (main_writer_slot + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - main_writer_stat_fifo_produce <= (main_writer_stat_fifo_produce + 1'd1); - end - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_consume <= (main_writer_stat_fifo_consume + 1'd1); - end - if (((main_writer_stat_fifo_syncfifo_we & main_writer_stat_fifo_syncfifo_writable) & (~main_writer_stat_fifo_replace))) begin - if ((~main_writer_stat_fifo_do_read)) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level + 1'd1); - end - end else begin - if (main_writer_stat_fifo_do_read) begin - main_writer_stat_fifo_level <= (main_writer_stat_fifo_level - 1'd1); - end - end - builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; - if (main_writer_counter_t_next_value_ce) begin - main_writer_counter <= main_writer_counter_t_next_value; - end - if (main_writer_errors_status_f_next_value_ce) begin - main_writer_errors_status <= main_writer_errors_status_f_next_value; - end - if (main_reader_eventsourcepulse_clear) begin - main_reader_eventsourcepulse_pending <= 1'd0; - end - if (main_reader_eventsourcepulse_trigger) begin - main_reader_eventsourcepulse_pending <= 1'd1; - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - main_reader_cmd_fifo_produce <= (main_reader_cmd_fifo_produce + 1'd1); - end - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_consume <= (main_reader_cmd_fifo_consume + 1'd1); - end - if (((main_reader_cmd_fifo_syncfifo_we & main_reader_cmd_fifo_syncfifo_writable) & (~main_reader_cmd_fifo_replace))) begin - if ((~main_reader_cmd_fifo_do_read)) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level + 1'd1); - end - end else begin - if (main_reader_cmd_fifo_do_read) begin - main_reader_cmd_fifo_level <= (main_reader_cmd_fifo_level - 1'd1); - end - end - builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; - if (main_reader_counter_next_value_ce) begin - main_reader_counter <= main_reader_counter_next_value; - end - main_sram0_bus_ack0 <= 1'd0; - if (((main_sram0_bus_cyc0 & main_sram0_bus_stb0) & (~main_sram0_bus_ack0))) begin - main_sram0_bus_ack0 <= 1'd1; - end - main_sram1_bus_ack0 <= 1'd0; - if (((main_sram1_bus_cyc0 & main_sram1_bus_stb0) & (~main_sram1_bus_ack0))) begin - main_sram1_bus_ack0 <= 1'd1; - end - main_sram0_bus_ack1 <= 1'd0; - if (((main_sram0_bus_cyc1 & main_sram0_bus_stb1) & (~main_sram0_bus_ack1))) begin - main_sram0_bus_ack1 <= 1'd1; - end - main_sram1_bus_ack1 <= 1'd0; - if (((main_sram1_bus_cyc1 & main_sram1_bus_stb1) & (~main_sram1_bus_ack1))) begin - main_sram1_bus_ack1 <= 1'd1; - end - main_slave_sel_r <= main_slave_sel; - builder_state <= builder_next_state; - builder_slave_sel_r <= builder_slave_sel; - if (builder_wait) begin - if ((~builder_done)) begin - builder_count <= (builder_count - 1'd1); - end - end else begin - builder_count <= 20'd1000000; - end - builder_interface0_bank_bus_dat_r <= 1'd0; - if (builder_csrbank0_sel) begin - case (builder_interface0_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; - end - 1'd1: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; - end - 2'd2: begin - builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; - end - endcase - end - if (builder_csrbank0_reset0_re) begin - main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; - end - main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; - if (builder_csrbank0_scratch0_re) begin - main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; - end - main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; - main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; - builder_interface1_bank_bus_dat_r <= 1'd0; - if (builder_csrbank1_sel) begin - case (builder_interface1_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; - end - 2'd2: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - builder_interface1_bank_bus_dat_r <= main_reader_start_start_w; - end - 3'd7: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; - end - 4'd9: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; - end - 4'd15: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_errors_w; - end - 5'd16: begin - builder_interface1_bank_bus_dat_r <= builder_csrbank1_crc_errors_w; - end - endcase - end - main_writer_slot_re <= builder_csrbank1_sram_writer_slot_re; - main_writer_length_re <= builder_csrbank1_sram_writer_length_re; - main_writer_errors_re <= builder_csrbank1_sram_writer_errors_re; - main_writer_status_re <= builder_csrbank1_sram_writer_ev_status_re; - if (builder_csrbank1_sram_writer_ev_pending_re) begin - main_writer_pending_r <= builder_csrbank1_sram_writer_ev_pending_r; - end - main_writer_pending_re <= builder_csrbank1_sram_writer_ev_pending_re; - if (builder_csrbank1_sram_writer_ev_enable0_re) begin - main_writer_enable_storage <= builder_csrbank1_sram_writer_ev_enable0_r; - end - main_writer_enable_re <= builder_csrbank1_sram_writer_ev_enable0_re; - main_reader_ready_re <= builder_csrbank1_sram_reader_ready_re; - main_reader_level_re <= builder_csrbank1_sram_reader_level_re; - if (builder_csrbank1_sram_reader_slot0_re) begin - main_reader_slot_storage <= builder_csrbank1_sram_reader_slot0_r; - end - main_reader_slot_re <= builder_csrbank1_sram_reader_slot0_re; - if (builder_csrbank1_sram_reader_length0_re) begin - main_reader_length_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; - end - main_reader_length_re <= builder_csrbank1_sram_reader_length0_re; - main_reader_status_re <= builder_csrbank1_sram_reader_ev_status_re; - if (builder_csrbank1_sram_reader_ev_pending_re) begin - main_reader_pending_r <= builder_csrbank1_sram_reader_ev_pending_r; - end - main_reader_pending_re <= builder_csrbank1_sram_reader_ev_pending_re; - if (builder_csrbank1_sram_reader_ev_enable0_re) begin - main_reader_enable_storage <= builder_csrbank1_sram_reader_ev_enable0_r; - end - main_reader_enable_re <= builder_csrbank1_sram_reader_ev_enable0_re; - main_preamble_crc_re <= builder_csrbank1_preamble_crc_re; - main_preamble_errors_re <= builder_csrbank1_preamble_errors_re; - main_crc_errors_re <= builder_csrbank1_crc_errors_re; - builder_interface2_bank_bus_dat_r <= 1'd0; - if (builder_csrbank2_sel) begin - case (builder_interface2_bank_bus_adr[8:0]) - 1'd0: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; - end - 1'd1: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; - end - 2'd2: begin - builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; - end - endcase - end - if (builder_csrbank2_crg_reset0_re) begin - main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; - end - main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; - if (builder_csrbank2_mdio_w0_re) begin - main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; - end - main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; - main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; - if (sys_rst) begin - main_maccore_maccore_reset_storage <= 2'd0; - main_maccore_maccore_reset_re <= 1'd0; - main_maccore_maccore_scratch_storage <= 32'd305419896; - main_maccore_maccore_scratch_re <= 1'd0; - main_maccore_maccore_bus_errors_re <= 1'd0; - main_maccore_maccore_bus_errors <= 32'd0; - main_maccore_ethphy_reset_storage <= 1'd0; - main_maccore_ethphy_reset_re <= 1'd0; - main_maccore_ethphy__w_storage <= 3'd0; - main_maccore_ethphy__w_re <= 1'd0; - main_maccore_ethphy__r_re <= 1'd0; - main_preamble_crc_re <= 1'd0; - main_preamble_errors_status <= 32'd0; - main_preamble_errors_re <= 1'd0; - main_crc_errors_status <= 32'd0; - main_crc_errors_re <= 1'd0; - main_tx_cdc_cdc_graycounter0_q <= 6'd0; - main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - main_rx_cdc_cdc_graycounter1_q <= 6'd0; - main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - main_writer_slot_re <= 1'd0; - main_writer_length_re <= 1'd0; - main_writer_errors_status <= 32'd0; - main_writer_errors_re <= 1'd0; - main_writer_status_re <= 1'd0; - main_writer_pending_re <= 1'd0; - main_writer_pending_r <= 1'd0; - main_writer_enable_storage <= 1'd0; - main_writer_enable_re <= 1'd0; - main_writer_counter <= 32'd0; - main_writer_slot <= 1'd0; - main_writer_stat_fifo_level <= 2'd0; - main_writer_stat_fifo_produce <= 1'd0; - main_writer_stat_fifo_consume <= 1'd0; - main_reader_ready_re <= 1'd0; - main_reader_level_re <= 1'd0; - main_reader_slot_re <= 1'd0; - main_reader_length_re <= 1'd0; - main_reader_eventsourcepulse_pending <= 1'd0; - main_reader_status_re <= 1'd0; - main_reader_pending_re <= 1'd0; - main_reader_pending_r <= 1'd0; - main_reader_enable_storage <= 1'd0; - main_reader_enable_re <= 1'd0; - main_reader_cmd_fifo_level <= 2'd0; - main_reader_cmd_fifo_produce <= 1'd0; - main_reader_cmd_fifo_consume <= 1'd0; - main_reader_counter <= 11'd0; - main_sram0_bus_ack0 <= 1'd0; - main_sram1_bus_ack0 <= 1'd0; - main_sram0_bus_ack1 <= 1'd0; - main_sram1_bus_ack1 <= 1'd0; - main_slave_sel_r <= 4'd0; - builder_liteethmacsramwriter_state <= 3'd0; - builder_liteethmacsramreader_state <= 2'd0; - builder_slave_sel_r <= 2'd0; - builder_count <= 20'd1000000; - builder_state <= 1'd0; - end - builder_xilinxmultiregimpl0_regs0 <= main_maccore_ethphy_data_r; - builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; - builder_xilinxmultiregimpl1_regs0 <= main_ps_preamble_error_toggle_i; - builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; - builder_xilinxmultiregimpl2_regs0 <= main_ps_crc_error_toggle_i; - builder_xilinxmultiregimpl2_regs1 <= builder_xilinxmultiregimpl2_regs0; - builder_xilinxmultiregimpl4_regs0 <= main_tx_cdc_cdc_graycounter1_q; - builder_xilinxmultiregimpl4_regs1 <= builder_xilinxmultiregimpl4_regs0; - builder_xilinxmultiregimpl5_regs0 <= main_rx_cdc_cdc_graycounter0_q; - builder_xilinxmultiregimpl5_regs1 <= builder_xilinxmultiregimpl5_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_ethphy_data_r; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; + builder_xilinxmultiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance IBUF of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF( - .I(rgmii_eth_clocks_rx), - .O(main_maccore_ethphy_eth_rx_clk_ibuf) + // Inputs. + .I (rgmii_clocks_rx), + + // Outputs. + .O (main_maccore_ethphy_eth_rx_clk_ibuf) ); +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(main_maccore_ethphy_eth_rx_clk_ibuf), - .O(eth_rx_clk) + // Inputs. + .I (main_maccore_ethphy_eth_rx_clk_ibuf), + + // Outputs. + .O (eth_rx_clk) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(main_maccore_ethphy_clkout0), - .O(main_maccore_ethphy_clkout_buf0) + // Inputs. + .I (main_maccore_ethphy_clkout0), + + // Outputs. + .O (main_maccore_ethphy_clkout_buf0) ); +//------------------------------------------------------------------------------ +// Instance BUFG_2 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_2( - .I(main_maccore_ethphy_clkout1), - .O(main_maccore_ethphy_clkout_buf1) + // Inputs. + .I (main_maccore_ethphy_clkout1), + + // Outputs. + .O (main_maccore_ethphy_clkout_buf1) ); +//------------------------------------------------------------------------------ +// Instance ODDR of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D1(1'd1), - .D2(1'd0), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_eth_tx_clk_obuf) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D1 (1'd1), + .D2 (1'd0), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_eth_tx_clk_obuf) ); +//------------------------------------------------------------------------------ +// Instance OBUF of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF( - .I(main_maccore_ethphy_eth_tx_clk_obuf), - .O(rgmii_eth_clocks_tx) + // Inputs. + .I (main_maccore_ethphy_eth_tx_clk_obuf), + + // Outputs. + .O (rgmii_clocks_tx) ); +//------------------------------------------------------------------------------ +// Instance ODDR_1 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_valid), - .D2(main_maccore_ethphy_sink_valid), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_ctl_obuf) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_valid), + .D2 (main_maccore_ethphy_sink_valid), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_ctl_obuf) ); +//------------------------------------------------------------------------------ +// Instance OBUF_1 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_1( - .I(main_maccore_ethphy_tx_ctl_obuf), - .O(rgmii_eth_tx_ctl) + // Inputs. + .I (main_maccore_ethphy_tx_ctl_obuf), + + // Outputs. + .O (rgmii_tx_ctl) ); +//------------------------------------------------------------------------------ +// Instance ODDR_2 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_2 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[0]), - .D2(main_maccore_ethphy_sink_payload_data[4]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[0]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[0]), + .D2 (main_maccore_ethphy_sink_payload_data[4]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[0]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_2 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_2( - .I(main_maccore_ethphy_tx_data_obuf[0]), - .O(rgmii_eth_tx_data[0]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[0]), + + // Outputs. + .O (rgmii_tx_data[0]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_3 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_3 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[1]), - .D2(main_maccore_ethphy_sink_payload_data[5]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[1]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[1]), + .D2 (main_maccore_ethphy_sink_payload_data[5]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[1]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_3 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_3( - .I(main_maccore_ethphy_tx_data_obuf[1]), - .O(rgmii_eth_tx_data[1]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[1]), + + // Outputs. + .O (rgmii_tx_data[1]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_4 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_4 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[2]), - .D2(main_maccore_ethphy_sink_payload_data[6]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[2]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[2]), + .D2 (main_maccore_ethphy_sink_payload_data[6]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[2]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_4 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_4( - .I(main_maccore_ethphy_tx_data_obuf[2]), - .O(rgmii_eth_tx_data[2]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[2]), + + // Outputs. + .O (rgmii_tx_data[2]) ); +//------------------------------------------------------------------------------ +// Instance ODDR_5 of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR_5 ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(main_maccore_ethphy_sink_payload_data[3]), - .D2(main_maccore_ethphy_sink_payload_data[7]), - .R(1'd0), - .S(1'd0), - .Q(main_maccore_ethphy_tx_data_obuf[3]) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (main_maccore_ethphy_sink_payload_data[3]), + .D2 (main_maccore_ethphy_sink_payload_data[7]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_obuf[3]) ); +//------------------------------------------------------------------------------ +// Instance OBUF_5 of OBUF Module. +//------------------------------------------------------------------------------ OBUF OBUF_5( - .I(main_maccore_ethphy_tx_data_obuf[3]), - .O(rgmii_eth_tx_data[3]) + // Inputs. + .I (main_maccore_ethphy_tx_data_obuf[3]), + + // Outputs. + .O (rgmii_tx_data[3]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_1 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_1( - .I(rgmii_eth_rx_ctl), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) + // Inputs. + .I (rgmii_rx_ctl), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_ibuf), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay) ); +//------------------------------------------------------------------------------ +// Instance IDDR of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), - .Q2(main_maccore_ethphy_liteethphyrgmiirx) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl_idelay), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_ctl), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx) ); +//------------------------------------------------------------------------------ +// Instance IBUF_2 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_2( - .I(rgmii_eth_rx_data[0]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) + // Inputs. + .I (rgmii_rx_data[0]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_1 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_1 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[0]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_1 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_1 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[0]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[0]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[4]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_3 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_3( - .I(rgmii_eth_rx_data[1]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) + // Inputs. + .I (rgmii_rx_data[1]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_2 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_2 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[1]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_2 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[1]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[1]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[5]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_4 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_4( - .I(rgmii_eth_rx_data[2]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) + // Inputs. + .I (rgmii_rx_data[2]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_3 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_3 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[2]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_3 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[2]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[2]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[6]) ); +//------------------------------------------------------------------------------ +// Instance IBUF_5 of IBUF Module. +//------------------------------------------------------------------------------ IBUF IBUF_5( - .I(rgmii_eth_rx_data[3]), - .O(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) + // Inputs. + .I (rgmii_rx_data[3]), + + // Outputs. + .O (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]) ); +//------------------------------------------------------------------------------ +// Instance IDELAYE2_4 of IDELAYE2 Module. +//------------------------------------------------------------------------------ IDELAYE2 #( - .IDELAY_TYPE("FIXED"), - .IDELAY_VALUE(5'd26), - .REFCLK_FREQUENCY(200.0) + // Parameters. + .IDELAY_TYPE ("FIXED"), + .IDELAY_VALUE (5'd26), + .REFCLK_FREQUENCY (200.0) ) IDELAYE2_4 ( - .C(1'd0), - .CE(1'd0), - .IDATAIN(main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), - .INC(1'd0), - .LD(1'd0), - .LDPIPEEN(1'd0), - .DATAOUT(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) + // Inputs. + .C (1'd0), + .CE (1'd0), + .IDATAIN (main_maccore_ethphy_liteethphyrgmiirx_rx_data_ibuf[3]), + .INC (1'd0), + .LD (1'd0), + .LDPIPEEN (1'd0), + + // Outputs. + .DATAOUT (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]) ); +//------------------------------------------------------------------------------ +// Instance IDDR_4 of IDDR Module. +//------------------------------------------------------------------------------ IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED") ) IDDR_4 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), - .R(1'd0), - .S(1'd0), - .Q1(main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), - .Q2(main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (main_maccore_ethphy_liteethphyrgmiirx_rx_data_idelay[3]), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q1 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[3]), + .Q2 (main_maccore_ethphy_liteethphyrgmiirx_rx_data[7]) ); -assign rgmii_eth_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; -assign main_maccore_ethphy_data_r = rgmii_eth_mdio; +assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = rgmii_mdio; -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (main_liteethmaccrc32checker_syncfifo_wrport_we) - storage[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - -always @(posedge eth_rx_clk) begin +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; -always @(posedge sys_clk) begin - if (main_tx_cdc_cdc_wrport_we) - storage_1[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; - memadr <= main_tx_cdc_cdc_wrport_adr; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; end - -always @(posedge eth_tx_clk) begin - memadr_1 <= main_tx_cdc_cdc_rdport_adr; +always @(posedge eth_rx_clk) begin end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -assign main_tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign main_tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin if (main_rx_cdc_cdc_wrport_we) storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; - memadr_2 <= main_rx_cdc_cdc_wrport_adr; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= main_rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign main_rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign main_rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (main_writer_stat_fifo_wrport_we) - storage_3[main_writer_stat_fifo_wrport_adr] <= main_writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[main_writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign main_writer_stat_fifo_wrport_dat_r = memdat_1; -assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (main_writer_memory0_we) - mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w; - memadr_4 <= main_writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[main_sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign main_writer_memory0_dat_r = mem[memadr_4]; -assign main_sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (main_writer_memory1_we) - mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w; - memadr_5 <= main_writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[main_sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign main_writer_memory1_dat_r = mem_1[memadr_5]; -assign main_sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (main_reader_cmd_fifo_wrport_we) - storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign main_reader_cmd_fifo_wrport_dat_r = memdat_4; -assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= main_reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end +always @(posedge sys_clk) begin + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; + +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - if (main_sram0_we[0]) - mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0]; - if (main_sram0_we[1]) - mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8]; - if (main_sram0_we[2]) - mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16]; - if (main_sram0_we[3]) - mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24]; - memadr_7 <= main_sram0_adr1; -end - -assign main_reader_memory0_dat_r = mem_2[memadr_6]; -assign main_sram0_dat_r1 = mem_2[memadr_7]; - -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; +end always @(posedge sys_clk) begin - memadr_8 <= main_reader_memory1_adr; + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -always @(posedge sys_clk) begin - if (main_sram1_we[0]) - mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0]; - if (main_sram1_we[1]) - mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8]; - if (main_sram1_we[2]) - mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16]; - if (main_sram1_we[3]) - mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24]; - memadr_9 <= main_sram1_adr1; -end - -assign main_reader_memory1_dat_r = mem_3[memadr_8]; -assign main_sram1_dat_r1 = mem_3[memadr_9]; - -FD FD( - .C(main_maccore_ethphy_clkin), - .D(main_maccore_ethphy_reset0), - .Q(builder_reset0) + +//------------------------------------------------------------------------------ +// Instance FDCE of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_reset0) ); -FD FD_1( - .C(main_maccore_ethphy_clkin), - .D(builder_reset0), - .Q(builder_reset1) +//------------------------------------------------------------------------------ +// Instance FDCE_1 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_1( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset0), + + // Outputs. + .Q (builder_reset1) ); -FD FD_2( - .C(main_maccore_ethphy_clkin), - .D(builder_reset1), - .Q(builder_reset2) +//------------------------------------------------------------------------------ +// Instance FDCE_2 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_2( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset1), + + // Outputs. + .Q (builder_reset2) ); -FD FD_3( - .C(main_maccore_ethphy_clkin), - .D(builder_reset2), - .Q(builder_reset3) +//------------------------------------------------------------------------------ +// Instance FDCE_3 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_3( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset2), + + // Outputs. + .Q (builder_reset3) ); -FD FD_4( - .C(main_maccore_ethphy_clkin), - .D(builder_reset3), - .Q(builder_reset4) +//------------------------------------------------------------------------------ +// Instance FDCE_4 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_4( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset3), + + // Outputs. + .Q (builder_reset4) ); -FD FD_5( - .C(main_maccore_ethphy_clkin), - .D(builder_reset4), - .Q(builder_reset5) +//------------------------------------------------------------------------------ +// Instance FDCE_5 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_5( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset4), + + // Outputs. + .Q (builder_reset5) ); -FD FD_6( - .C(main_maccore_ethphy_clkin), - .D(builder_reset5), - .Q(builder_reset6) +//------------------------------------------------------------------------------ +// Instance FDCE_6 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_6( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset5), + + // Outputs. + .Q (builder_reset6) ); -FD FD_7( - .C(main_maccore_ethphy_clkin), - .D(builder_reset6), - .Q(builder_reset7) +//------------------------------------------------------------------------------ +// Instance FDCE_7 of FDCE Module. +//------------------------------------------------------------------------------ +FDCE FDCE_7( + // Inputs. + .C (main_maccore_ethphy_clkin), + .CE (1'd1), + .CLR (1'd0), + .D (builder_reset6), + + // Outputs. + .Q (builder_reset7) ); +//------------------------------------------------------------------------------ +// Instance PLLE2_ADV of PLLE2_ADV Module. +//------------------------------------------------------------------------------ PLLE2_ADV #( - .CLKFBOUT_MULT(4'd12), - .CLKIN1_PERIOD(8.0), - .CLKOUT0_DIVIDE(4'd12), - .CLKOUT0_PHASE(1'd0), - .CLKOUT1_DIVIDE(4'd12), - .CLKOUT1_PHASE(90.0), - .DIVCLK_DIVIDE(1'd1), - .REF_JITTER1(0.01), - .STARTUP_WAIT("FALSE") + // Parameters. + .CLKFBOUT_MULT (4'd12), + .CLKIN1_PERIOD (8.0), + .CLKOUT0_DIVIDE (4'd12), + .CLKOUT0_PHASE (1'd0), + .CLKOUT1_DIVIDE (4'd12), + .CLKOUT1_PHASE (90.0), + .DIVCLK_DIVIDE (1'd1), + .REF_JITTER1 (0.01), + .STARTUP_WAIT ("FALSE") ) PLLE2_ADV ( - .CLKFBIN(builder_pll_fb), - .CLKIN1(main_maccore_ethphy_clkin), - .PWRDWN(main_maccore_ethphy_power_down), - .RST(builder_reset7), - .CLKFBOUT(builder_pll_fb), - .CLKOUT0(main_maccore_ethphy_clkout0), - .CLKOUT1(main_maccore_ethphy_clkout1), - .LOCKED(main_maccore_ethphy_locked) + // Inputs. + .CLKFBIN (builder_pll_fb), + .CLKIN1 (main_maccore_ethphy_clkin), + .PWRDWN (main_maccore_ethphy_power_down), + .RST (builder_reset7), + + // Outputs. + .CLKFBOUT (builder_pll_fb), + .CLKOUT0 (main_maccore_ethphy_clkout0), + .CLKOUT1 (main_maccore_ethphy_clkout1), + .LOCKED (main_maccore_ethphy_locked) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D(1'd0), - .PRE(builder_xilinxasyncresetsynchronizerimpl0), - .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D (1'd0), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_delayed_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), - .PRE(builder_xilinxasyncresetsynchronizerimpl0), - .Q(builder_xilinxasyncresetsynchronizerimpl0_expr) + // Inputs. + .C (eth_tx_delayed_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE (builder_xilinxasyncresetsynchronizerimpl0_async_reset), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl0_expr) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset1), - .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl1_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), - .PRE(main_maccore_ethphy_reset1), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_4 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_4 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(main_maccore_ethphy_reset1), - .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (builder_xilinxasyncresetsynchronizerimpl2_rst_meta) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_5 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_5 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), - .PRE(main_maccore_ethphy_reset1), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE (main_maccore_ethphy_reset1), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:49. +//------------------------------------------------------------------------------ diff --git a/liteeth/generated/wukong-v2/liteeth_core.v b/liteeth/generated/wukong-v2/liteeth_core.v index ba65299..9a2da5a 100644 --- a/liteeth/generated/wukong-v2/liteeth_core.v +++ b/liteeth/generated/wukong-v2/liteeth_core.v @@ -1,3810 +1,4453 @@ -//-------------------------------------------------------------------------------- -// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01 -//-------------------------------------------------------------------------------- -module liteeth_core( - input wire sys_clock, - input wire sys_reset, - input wire gmii_eth_clocks_tx, - output wire gmii_eth_clocks_gtx, - input wire gmii_eth_clocks_rx, - output wire gmii_eth_rst_n, - input wire gmii_eth_int_n, - inout wire gmii_eth_mdio, - output wire gmii_eth_mdc, - input wire gmii_eth_rx_dv, - input wire gmii_eth_rx_er, - input wire [7:0] gmii_eth_rx_data, - output reg gmii_eth_tx_en, - output wire gmii_eth_tx_er, - output reg [7:0] gmii_eth_tx_data, - input wire gmii_eth_col, - input wire gmii_eth_crs, - input wire [29:0] wishbone_adr, - input wire [31:0] wishbone_dat_w, - output wire [31:0] wishbone_dat_r, - input wire [3:0] wishbone_sel, - input wire wishbone_cyc, - input wire wishbone_stb, - output wire wishbone_ack, - input wire wishbone_we, - input wire [2:0] wishbone_cti, - input wire [1:0] wishbone_bte, - output wire wishbone_err, - output wire interrupt +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : xc7 +// LiteX sha1 : 87137c30 +// Date : 2024-04-05 17:38:50 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire gmii_clocks_gtx, + input wire gmii_clocks_rx, + input wire gmii_clocks_tx, + input wire gmii_col, + input wire gmii_crs, + input wire gmii_int_n, + output wire gmii_mdc, + inout wire gmii_mdio, + output wire gmii_rst_n, + input wire [7:0] gmii_rx_data, + input wire gmii_rx_dv, + input wire gmii_rx_er, + output reg [7:0] gmii_tx_data, + output reg gmii_tx_en, + output wire gmii_tx_er, + output wire interrupt, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we ); -reg maccore_maccore_soc_rst = 1'd0; -wire maccore_maccore_cpu_rst; -reg [1:0] maccore_maccore_reset_storage = 2'd0; -reg maccore_maccore_reset_re = 1'd0; -reg [31:0] maccore_maccore_scratch_storage = 32'd305419896; -reg maccore_maccore_scratch_re = 1'd0; -wire [31:0] maccore_maccore_bus_errors_status; -wire maccore_maccore_bus_errors_we; -reg maccore_maccore_bus_errors_re = 1'd0; -wire maccore_maccore_bus_error; -reg [31:0] maccore_maccore_bus_errors = 32'd0; -(* dont_touch = "true" *) wire sys_clk; -wire sys_rst; -wire por_clk; -reg maccore_int_rst = 1'd1; -reg maccore_ethphy_mode0 = 1'd0; -wire maccore_ethphy_mode_status; -wire maccore_ethphy_mode_we; -reg maccore_ethphy_mode_re = 1'd0; -reg maccore_ethphy_mode1 = 1'd0; -reg maccore_ethphy_update_mode = 1'd0; -wire maccore_ethphy_eth_tick; -reg [9:0] maccore_ethphy_eth_counter = 10'd0; -wire maccore_ethphy_sys_tick; -wire maccore_ethphy_i; -wire maccore_ethphy_o; -reg maccore_ethphy_toggle_i = 1'd0; -wire maccore_ethphy_toggle_o; -reg maccore_ethphy_toggle_o_r = 1'd0; -reg [23:0] maccore_ethphy_sys_counter = 24'd0; -reg maccore_ethphy_sys_counter_reset = 1'd0; -reg maccore_ethphy_sys_counter_ce = 1'd0; -reg maccore_ethphy_reset_storage = 1'd0; -reg maccore_ethphy_reset_re = 1'd0; -(* dont_touch = "true" *) wire eth_rx_clk; -wire eth_rx_rst; -(* dont_touch = "true" *) wire eth_tx_clk; -wire eth_tx_rst; -reg maccore_ethphy_eth_tx_clk = 1'd0; -wire maccore_ethphy_reset0; -wire maccore_ethphy_reset1; -reg [8:0] maccore_ethphy_counter = 9'd0; -wire maccore_ethphy_counter_done; -wire maccore_ethphy_counter_ce; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last0; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid; -reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error; -reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last1; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1; -wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1; -wire maccore_ethphy_liteethphygmiimiitx_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_sink_ready; -reg maccore_ethphy_liteethphygmiimiitx_converter_sink_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_converter_sink_last = 1'd0; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_last; -wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last; -reg [3:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data = 4'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count; -reg maccore_ethphy_liteethphygmiimiitx_converter_converter_mux = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_converter_last; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_first; -wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_last; -wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; -reg maccore_ethphy_liteethphygmiimiitx_demux_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_first; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error = 1'd0; -wire maccore_ethphy_liteethphygmiimiitx_demux_sel; -wire maccore_ethphy_liteethphygmiimiirx_source_source_valid0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_ready0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_first0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_last0; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0; -reg maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_source_source_valid1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_ready1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_first1; -wire maccore_ethphy_liteethphygmiimiirx_source_source_last1; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1; -reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1 = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1 = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_sink_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_sink_ready; -reg maccore_ethphy_liteethphygmiimiirx_converter_sink_first = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_sink_last; -reg [3:0] maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data = 4'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_last; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data = 8'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last; -wire [3:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data = 8'd0; -reg [1:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count = 2'd0; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_demux = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part; -reg maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_first; -wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data; -reg maccore_ethphy_liteethphygmiimiirx_converter_reset = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_valid = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_source_ready; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_first = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_last = 1'd0; -reg [7:0] maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data = 8'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be = 1'd0; -reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid; -reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid; -reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready = 1'd0; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last; -wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be; -wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error; -wire maccore_ethphy_liteethphygmiimiirx_mux_sel; -wire maccore_ethphy_mdc; -wire maccore_ethphy_oe; -wire maccore_ethphy_w; -reg [2:0] maccore_ethphy__w_storage = 3'd0; -reg maccore_ethphy__w_re = 1'd0; -reg maccore_ethphy_r = 1'd0; -reg maccore_ethphy__r_status = 1'd0; -wire maccore_ethphy__r_we; -reg maccore_ethphy__r_re = 1'd0; -wire maccore_ethphy_data_w; -wire maccore_ethphy_data_oe; -wire maccore_ethphy_data_r; -wire tx_gap_inserter_sink_valid; -reg tx_gap_inserter_sink_ready = 1'd0; -wire tx_gap_inserter_sink_first; -wire tx_gap_inserter_sink_last; -wire [7:0] tx_gap_inserter_sink_payload_data; -wire tx_gap_inserter_sink_payload_last_be; -wire tx_gap_inserter_sink_payload_error; -reg tx_gap_inserter_source_valid = 1'd0; -wire tx_gap_inserter_source_ready; -reg tx_gap_inserter_source_first = 1'd0; -reg tx_gap_inserter_source_last = 1'd0; -reg [7:0] tx_gap_inserter_source_payload_data = 8'd0; -reg tx_gap_inserter_source_payload_last_be = 1'd0; -reg tx_gap_inserter_source_payload_error = 1'd0; -reg [3:0] tx_gap_inserter_counter = 4'd0; -reg preamble_crc_status = 1'd1; -wire preamble_crc_we; -reg preamble_crc_re = 1'd0; -reg [31:0] preamble_errors_status = 32'd0; -wire preamble_errors_we; -reg preamble_errors_re = 1'd0; -reg [31:0] crc_errors_status = 32'd0; -wire crc_errors_we; -reg crc_errors_re = 1'd0; -wire preamble_inserter_sink_valid; -reg preamble_inserter_sink_ready = 1'd0; -wire preamble_inserter_sink_first; -wire preamble_inserter_sink_last; -wire [7:0] preamble_inserter_sink_payload_data; -wire preamble_inserter_sink_payload_last_be; -wire preamble_inserter_sink_payload_error; -reg preamble_inserter_source_valid = 1'd0; -wire preamble_inserter_source_ready; -reg preamble_inserter_source_first = 1'd0; -reg preamble_inserter_source_last = 1'd0; -reg [7:0] preamble_inserter_source_payload_data = 8'd0; -wire preamble_inserter_source_payload_last_be; -reg preamble_inserter_source_payload_error = 1'd0; -reg [63:0] preamble_inserter_preamble = 64'd15372286728091293013; -reg [2:0] preamble_inserter_count = 3'd0; -wire preamble_checker_sink_valid; -reg preamble_checker_sink_ready = 1'd0; -wire preamble_checker_sink_first; -wire preamble_checker_sink_last; -wire [7:0] preamble_checker_sink_payload_data; -wire preamble_checker_sink_payload_last_be; -wire preamble_checker_sink_payload_error; -reg preamble_checker_source_valid = 1'd0; -wire preamble_checker_source_ready; -reg preamble_checker_source_first = 1'd0; -reg preamble_checker_source_last = 1'd0; -wire [7:0] preamble_checker_source_payload_data; -wire preamble_checker_source_payload_last_be; -reg preamble_checker_source_payload_error = 1'd0; -reg preamble_checker_error = 1'd0; -wire liteethmaccrc32inserter_sink_valid; -reg liteethmaccrc32inserter_sink_ready = 1'd0; -wire liteethmaccrc32inserter_sink_first; -wire liteethmaccrc32inserter_sink_last; -wire [7:0] liteethmaccrc32inserter_sink_payload_data; -wire liteethmaccrc32inserter_sink_payload_last_be; -wire liteethmaccrc32inserter_sink_payload_error; -reg liteethmaccrc32inserter_source_valid = 1'd0; -wire liteethmaccrc32inserter_source_ready; -reg liteethmaccrc32inserter_source_first = 1'd0; -reg liteethmaccrc32inserter_source_last = 1'd0; -reg [7:0] liteethmaccrc32inserter_source_payload_data = 8'd0; -reg liteethmaccrc32inserter_source_payload_last_be = 1'd0; -reg liteethmaccrc32inserter_source_payload_error = 1'd0; -reg [7:0] liteethmaccrc32inserter_data0 = 8'd0; -wire [31:0] liteethmaccrc32inserter_value; -wire liteethmaccrc32inserter_error; -wire [7:0] liteethmaccrc32inserter_data1; -wire [31:0] liteethmaccrc32inserter_last; -reg [31:0] liteethmaccrc32inserter_next = 32'd0; -reg [31:0] liteethmaccrc32inserter_reg = 32'd4294967295; -reg liteethmaccrc32inserter_ce = 1'd0; -reg liteethmaccrc32inserter_reset = 1'd0; -reg [1:0] liteethmaccrc32inserter_cnt = 2'd3; -wire liteethmaccrc32inserter_cnt_done; -reg liteethmaccrc32inserter_is_ongoing0 = 1'd0; -reg liteethmaccrc32inserter_is_ongoing1 = 1'd0; -wire crc32_inserter_sink_valid; -wire crc32_inserter_sink_ready; -wire crc32_inserter_sink_first; -wire crc32_inserter_sink_last; -wire [7:0] crc32_inserter_sink_payload_data; -wire crc32_inserter_sink_payload_last_be; -wire crc32_inserter_sink_payload_error; -reg crc32_inserter_source_valid = 1'd0; -wire crc32_inserter_source_ready; -reg crc32_inserter_source_first = 1'd0; -reg crc32_inserter_source_last = 1'd0; -reg [7:0] crc32_inserter_source_payload_data = 8'd0; -reg crc32_inserter_source_payload_last_be = 1'd0; -reg crc32_inserter_source_payload_error = 1'd0; -wire liteethmaccrc32checker_sink_sink_valid; -reg liteethmaccrc32checker_sink_sink_ready = 1'd0; -wire liteethmaccrc32checker_sink_sink_first; -wire liteethmaccrc32checker_sink_sink_last; -wire [7:0] liteethmaccrc32checker_sink_sink_payload_data; -wire liteethmaccrc32checker_sink_sink_payload_last_be; -wire liteethmaccrc32checker_sink_sink_payload_error; -wire liteethmaccrc32checker_source_source_valid; -wire liteethmaccrc32checker_source_source_ready; -reg liteethmaccrc32checker_source_source_first = 1'd0; -wire liteethmaccrc32checker_source_source_last; -wire [7:0] liteethmaccrc32checker_source_source_payload_data; -wire liteethmaccrc32checker_source_source_payload_last_be; -reg liteethmaccrc32checker_source_source_payload_error = 1'd0; -wire liteethmaccrc32checker_error; -wire [7:0] liteethmaccrc32checker_crc_data0; -wire [31:0] liteethmaccrc32checker_crc_value; -wire liteethmaccrc32checker_crc_error; -wire [7:0] liteethmaccrc32checker_crc_data1; -wire [31:0] liteethmaccrc32checker_crc_last; -reg [31:0] liteethmaccrc32checker_crc_next = 32'd0; -reg [31:0] liteethmaccrc32checker_crc_reg = 32'd4294967295; -reg liteethmaccrc32checker_crc_ce = 1'd0; -reg liteethmaccrc32checker_crc_reset = 1'd0; -reg liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; -wire liteethmaccrc32checker_syncfifo_sink_ready; -wire liteethmaccrc32checker_syncfifo_sink_first; -wire liteethmaccrc32checker_syncfifo_sink_last; -wire [7:0] liteethmaccrc32checker_syncfifo_sink_payload_data; -wire liteethmaccrc32checker_syncfifo_sink_payload_last_be; -wire liteethmaccrc32checker_syncfifo_sink_payload_error; -wire liteethmaccrc32checker_syncfifo_source_valid; -wire liteethmaccrc32checker_syncfifo_source_ready; -wire liteethmaccrc32checker_syncfifo_source_first; -wire liteethmaccrc32checker_syncfifo_source_last; -wire [7:0] liteethmaccrc32checker_syncfifo_source_payload_data; -wire liteethmaccrc32checker_syncfifo_source_payload_last_be; -wire liteethmaccrc32checker_syncfifo_source_payload_error; -wire liteethmaccrc32checker_syncfifo_syncfifo_we; -wire liteethmaccrc32checker_syncfifo_syncfifo_writable; -wire liteethmaccrc32checker_syncfifo_syncfifo_re; -wire liteethmaccrc32checker_syncfifo_syncfifo_readable; -wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_din; -wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_dout; -reg [2:0] liteethmaccrc32checker_syncfifo_level = 3'd0; -reg liteethmaccrc32checker_syncfifo_replace = 1'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_produce = 3'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_consume = 3'd0; -reg [2:0] liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; -wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_r; -wire liteethmaccrc32checker_syncfifo_wrport_we; -wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_w; -wire liteethmaccrc32checker_syncfifo_do_read; -wire [2:0] liteethmaccrc32checker_syncfifo_rdport_adr; -wire [11:0] liteethmaccrc32checker_syncfifo_rdport_dat_r; -wire [7:0] liteethmaccrc32checker_syncfifo_fifo_in_payload_data; -wire liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; -wire liteethmaccrc32checker_syncfifo_fifo_in_payload_error; -wire liteethmaccrc32checker_syncfifo_fifo_in_first; -wire liteethmaccrc32checker_syncfifo_fifo_in_last; -wire [7:0] liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -wire liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -wire liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -wire liteethmaccrc32checker_syncfifo_fifo_out_first; -wire liteethmaccrc32checker_syncfifo_fifo_out_last; -reg liteethmaccrc32checker_fifo_reset = 1'd0; -wire liteethmaccrc32checker_fifo_in; -wire liteethmaccrc32checker_fifo_out; -wire liteethmaccrc32checker_fifo_full; -wire crc32_checker_sink_valid; -wire crc32_checker_sink_ready; -wire crc32_checker_sink_first; -wire crc32_checker_sink_last; -wire [7:0] crc32_checker_sink_payload_data; -wire crc32_checker_sink_payload_last_be; -wire crc32_checker_sink_payload_error; -reg crc32_checker_source_valid = 1'd0; -wire crc32_checker_source_ready; -reg crc32_checker_source_first = 1'd0; -reg crc32_checker_source_last = 1'd0; -reg [7:0] crc32_checker_source_payload_data = 8'd0; -reg crc32_checker_source_payload_last_be = 1'd0; -reg crc32_checker_source_payload_error = 1'd0; -wire ps_preamble_error_i; -wire ps_preamble_error_o; -reg ps_preamble_error_toggle_i = 1'd0; -wire ps_preamble_error_toggle_o; -reg ps_preamble_error_toggle_o_r = 1'd0; -wire ps_crc_error_i; -wire ps_crc_error_o; -reg ps_crc_error_toggle_i = 1'd0; -wire ps_crc_error_toggle_o; -reg ps_crc_error_toggle_o_r = 1'd0; -wire padding_inserter_sink_valid; -reg padding_inserter_sink_ready = 1'd0; -wire padding_inserter_sink_first; -wire padding_inserter_sink_last; -wire [7:0] padding_inserter_sink_payload_data; -wire padding_inserter_sink_payload_last_be; -wire padding_inserter_sink_payload_error; -reg padding_inserter_source_valid = 1'd0; -wire padding_inserter_source_ready; -reg padding_inserter_source_first = 1'd0; -reg padding_inserter_source_last = 1'd0; -reg [7:0] padding_inserter_source_payload_data = 8'd0; -reg padding_inserter_source_payload_last_be = 1'd0; -reg padding_inserter_source_payload_error = 1'd0; -reg [15:0] padding_inserter_counter = 16'd0; -wire padding_inserter_counter_done; -wire padding_checker_sink_valid; -wire padding_checker_sink_ready; -wire padding_checker_sink_first; -wire padding_checker_sink_last; -wire [7:0] padding_checker_sink_payload_data; -wire padding_checker_sink_payload_last_be; -wire padding_checker_sink_payload_error; -wire padding_checker_source_valid; -wire padding_checker_source_ready; -wire padding_checker_source_first; -wire padding_checker_source_last; -wire [7:0] padding_checker_source_payload_data; -wire padding_checker_source_payload_last_be; -wire padding_checker_source_payload_error; -wire tx_last_be_sink_valid; -reg tx_last_be_sink_ready = 1'd0; -wire tx_last_be_sink_first; -wire tx_last_be_sink_last; -wire [7:0] tx_last_be_sink_payload_data; -wire tx_last_be_sink_payload_last_be; -wire tx_last_be_sink_payload_error; -reg tx_last_be_source_valid = 1'd0; -wire tx_last_be_source_ready; -reg tx_last_be_source_first = 1'd0; -reg tx_last_be_source_last = 1'd0; -reg [7:0] tx_last_be_source_payload_data = 8'd0; -reg tx_last_be_source_payload_last_be = 1'd0; -reg tx_last_be_source_payload_error = 1'd0; -wire rx_last_be_sink_valid; -wire rx_last_be_sink_ready; -wire rx_last_be_sink_first; -wire rx_last_be_sink_last; -wire [7:0] rx_last_be_sink_payload_data; -wire rx_last_be_sink_payload_last_be; -wire rx_last_be_sink_payload_error; -wire rx_last_be_source_valid; -wire rx_last_be_source_ready; -wire rx_last_be_source_first; -wire rx_last_be_source_last; -wire [7:0] rx_last_be_source_payload_data; -reg rx_last_be_source_payload_last_be = 1'd0; -wire rx_last_be_source_payload_error; -wire tx_converter_sink_valid; -wire tx_converter_sink_ready; -wire tx_converter_sink_first; -wire tx_converter_sink_last; -wire [31:0] tx_converter_sink_payload_data; -wire [3:0] tx_converter_sink_payload_last_be; -wire [3:0] tx_converter_sink_payload_error; -wire tx_converter_source_valid; -wire tx_converter_source_ready; -wire tx_converter_source_first; -wire tx_converter_source_last; -wire [7:0] tx_converter_source_payload_data; -wire tx_converter_source_payload_last_be; -wire tx_converter_source_payload_error; -wire tx_converter_converter_sink_valid; -wire tx_converter_converter_sink_ready; -wire tx_converter_converter_sink_first; -wire tx_converter_converter_sink_last; -reg [39:0] tx_converter_converter_sink_payload_data = 40'd0; -wire tx_converter_converter_source_valid; -wire tx_converter_converter_source_ready; -wire tx_converter_converter_source_first; -wire tx_converter_converter_source_last; -reg [9:0] tx_converter_converter_source_payload_data = 10'd0; -wire tx_converter_converter_source_payload_valid_token_count; -reg [1:0] tx_converter_converter_mux = 2'd0; -wire tx_converter_converter_first; -wire tx_converter_converter_last; -wire tx_converter_source_source_valid; -wire tx_converter_source_source_ready; -wire tx_converter_source_source_first; -wire tx_converter_source_source_last; -wire [9:0] tx_converter_source_source_payload_data; -wire rx_converter_sink_valid; -wire rx_converter_sink_ready; -wire rx_converter_sink_first; -wire rx_converter_sink_last; -wire [7:0] rx_converter_sink_payload_data; -wire rx_converter_sink_payload_last_be; -wire rx_converter_sink_payload_error; -wire rx_converter_source_valid; -wire rx_converter_source_ready; -wire rx_converter_source_first; -wire rx_converter_source_last; -reg [31:0] rx_converter_source_payload_data = 32'd0; -reg [3:0] rx_converter_source_payload_last_be = 4'd0; -reg [3:0] rx_converter_source_payload_error = 4'd0; -wire rx_converter_converter_sink_valid; -wire rx_converter_converter_sink_ready; -wire rx_converter_converter_sink_first; -wire rx_converter_converter_sink_last; -wire [9:0] rx_converter_converter_sink_payload_data; -wire rx_converter_converter_source_valid; -wire rx_converter_converter_source_ready; -reg rx_converter_converter_source_first = 1'd0; -reg rx_converter_converter_source_last = 1'd0; -reg [39:0] rx_converter_converter_source_payload_data = 40'd0; -reg [2:0] rx_converter_converter_source_payload_valid_token_count = 3'd0; -reg [1:0] rx_converter_converter_demux = 2'd0; -wire rx_converter_converter_load_part; -reg rx_converter_converter_strobe_all = 1'd0; -wire rx_converter_source_source_valid; -wire rx_converter_source_source_ready; -wire rx_converter_source_source_first; -wire rx_converter_source_source_last; -wire [39:0] rx_converter_source_source_payload_data; -wire tx_cdc_sink_sink_valid; -wire tx_cdc_sink_sink_ready; -wire tx_cdc_sink_sink_first; -wire tx_cdc_sink_sink_last; -wire [31:0] tx_cdc_sink_sink_payload_data; -wire [3:0] tx_cdc_sink_sink_payload_last_be; -wire [3:0] tx_cdc_sink_sink_payload_error; -wire tx_cdc_source_source_valid; -wire tx_cdc_source_source_ready; -wire tx_cdc_source_source_first; -wire tx_cdc_source_source_last; -wire [31:0] tx_cdc_source_source_payload_data; -wire [3:0] tx_cdc_source_source_payload_last_be; -wire [3:0] tx_cdc_source_source_payload_error; -wire tx_cdc_cdc_sink_valid; -wire tx_cdc_cdc_sink_ready; -wire tx_cdc_cdc_sink_first; -wire tx_cdc_cdc_sink_last; -wire [31:0] tx_cdc_cdc_sink_payload_data; -wire [3:0] tx_cdc_cdc_sink_payload_last_be; -wire [3:0] tx_cdc_cdc_sink_payload_error; -wire tx_cdc_cdc_source_valid; -wire tx_cdc_cdc_source_ready; -wire tx_cdc_cdc_source_first; -wire tx_cdc_cdc_source_last; -wire [31:0] tx_cdc_cdc_source_payload_data; -wire [3:0] tx_cdc_cdc_source_payload_last_be; -wire [3:0] tx_cdc_cdc_source_payload_error; -wire tx_cdc_cdc_asyncfifo_we; -wire tx_cdc_cdc_asyncfifo_writable; -wire tx_cdc_cdc_asyncfifo_re; -wire tx_cdc_cdc_asyncfifo_readable; -wire [41:0] tx_cdc_cdc_asyncfifo_din; -wire [41:0] tx_cdc_cdc_asyncfifo_dout; -wire tx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] tx_cdc_cdc_graycounter0_q_next; -reg [5:0] tx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire tx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] tx_cdc_cdc_graycounter1_q_next; -reg [5:0] tx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] tx_cdc_cdc_produce_rdomain; -wire [5:0] tx_cdc_cdc_consume_wdomain; -wire [4:0] tx_cdc_cdc_wrport_adr; -wire [41:0] tx_cdc_cdc_wrport_dat_r; -wire tx_cdc_cdc_wrport_we; -wire [41:0] tx_cdc_cdc_wrport_dat_w; -wire [4:0] tx_cdc_cdc_rdport_adr; -wire [41:0] tx_cdc_cdc_rdport_dat_r; -wire [31:0] tx_cdc_cdc_fifo_in_payload_data; -wire [3:0] tx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] tx_cdc_cdc_fifo_in_payload_error; -wire tx_cdc_cdc_fifo_in_first; -wire tx_cdc_cdc_fifo_in_last; -wire [31:0] tx_cdc_cdc_fifo_out_payload_data; -wire [3:0] tx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] tx_cdc_cdc_fifo_out_payload_error; -wire tx_cdc_cdc_fifo_out_first; -wire tx_cdc_cdc_fifo_out_last; -wire rx_cdc_sink_sink_valid; -wire rx_cdc_sink_sink_ready; -wire rx_cdc_sink_sink_first; -wire rx_cdc_sink_sink_last; -wire [31:0] rx_cdc_sink_sink_payload_data; -wire [3:0] rx_cdc_sink_sink_payload_last_be; -wire [3:0] rx_cdc_sink_sink_payload_error; -wire rx_cdc_source_source_valid; -wire rx_cdc_source_source_ready; -wire rx_cdc_source_source_first; -wire rx_cdc_source_source_last; -wire [31:0] rx_cdc_source_source_payload_data; -wire [3:0] rx_cdc_source_source_payload_last_be; -wire [3:0] rx_cdc_source_source_payload_error; -wire rx_cdc_cdc_sink_valid; -wire rx_cdc_cdc_sink_ready; -wire rx_cdc_cdc_sink_first; -wire rx_cdc_cdc_sink_last; -wire [31:0] rx_cdc_cdc_sink_payload_data; -wire [3:0] rx_cdc_cdc_sink_payload_last_be; -wire [3:0] rx_cdc_cdc_sink_payload_error; -wire rx_cdc_cdc_source_valid; -wire rx_cdc_cdc_source_ready; -wire rx_cdc_cdc_source_first; -wire rx_cdc_cdc_source_last; -wire [31:0] rx_cdc_cdc_source_payload_data; -wire [3:0] rx_cdc_cdc_source_payload_last_be; -wire [3:0] rx_cdc_cdc_source_payload_error; -wire rx_cdc_cdc_asyncfifo_we; -wire rx_cdc_cdc_asyncfifo_writable; -wire rx_cdc_cdc_asyncfifo_re; -wire rx_cdc_cdc_asyncfifo_readable; -wire [41:0] rx_cdc_cdc_asyncfifo_din; -wire [41:0] rx_cdc_cdc_asyncfifo_dout; -wire rx_cdc_cdc_graycounter0_ce; -(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter0_q = 6'd0; -wire [5:0] rx_cdc_cdc_graycounter0_q_next; -reg [5:0] rx_cdc_cdc_graycounter0_q_binary = 6'd0; -reg [5:0] rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; -wire rx_cdc_cdc_graycounter1_ce; -(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter1_q = 6'd0; -wire [5:0] rx_cdc_cdc_graycounter1_q_next; -reg [5:0] rx_cdc_cdc_graycounter1_q_binary = 6'd0; -reg [5:0] rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; -wire [5:0] rx_cdc_cdc_produce_rdomain; -wire [5:0] rx_cdc_cdc_consume_wdomain; -wire [4:0] rx_cdc_cdc_wrport_adr; -wire [41:0] rx_cdc_cdc_wrport_dat_r; -wire rx_cdc_cdc_wrport_we; -wire [41:0] rx_cdc_cdc_wrport_dat_w; -wire [4:0] rx_cdc_cdc_rdport_adr; -wire [41:0] rx_cdc_cdc_rdport_dat_r; -wire [31:0] rx_cdc_cdc_fifo_in_payload_data; -wire [3:0] rx_cdc_cdc_fifo_in_payload_last_be; -wire [3:0] rx_cdc_cdc_fifo_in_payload_error; -wire rx_cdc_cdc_fifo_in_first; -wire rx_cdc_cdc_fifo_in_last; -wire [31:0] rx_cdc_cdc_fifo_out_payload_data; -wire [3:0] rx_cdc_cdc_fifo_out_payload_last_be; -wire [3:0] rx_cdc_cdc_fifo_out_payload_error; -wire rx_cdc_cdc_fifo_out_first; -wire rx_cdc_cdc_fifo_out_last; -wire sink_valid; -wire sink_ready; -wire sink_first; -wire sink_last; -wire [31:0] sink_payload_data; -wire [3:0] sink_payload_last_be; -wire [3:0] sink_payload_error; -wire source_valid; -wire source_ready; -wire source_first; -wire source_last; -wire [31:0] source_payload_data; -wire [3:0] source_payload_last_be; -wire [3:0] source_payload_error; -wire [29:0] bus_adr; -wire [31:0] bus_dat_w; -wire [31:0] bus_dat_r; -wire [3:0] bus_sel; -wire bus_cyc; -wire bus_stb; -wire bus_ack; -wire bus_we; -wire [2:0] bus_cti; -wire [1:0] bus_bte; -wire bus_err; -wire writer_sink_sink_valid; -reg writer_sink_sink_ready = 1'd1; -wire writer_sink_sink_first; -wire writer_sink_sink_last; -wire [31:0] writer_sink_sink_payload_data; -wire [3:0] writer_sink_sink_payload_last_be; -wire [3:0] writer_sink_sink_payload_error; -wire writer_slot_status; -wire writer_slot_we; -reg writer_slot_re = 1'd0; -wire [31:0] writer_length_status; -wire writer_length_we; -reg writer_length_re = 1'd0; -reg [31:0] writer_errors_status = 32'd0; -wire writer_errors_we; -reg writer_errors_re = 1'd0; -wire writer_irq; -wire writer_available_status; -wire writer_available_pending; -wire writer_available_trigger; -reg writer_available_clear = 1'd0; -wire writer_available0; -wire writer_status_status; -wire writer_status_we; -reg writer_status_re = 1'd0; -wire writer_available1; -wire writer_pending_status; -wire writer_pending_we; -reg writer_pending_re = 1'd0; -reg writer_pending_r = 1'd0; -wire writer_available2; -reg writer_enable_storage = 1'd0; -reg writer_enable_re = 1'd0; -reg [2:0] writer_inc = 3'd0; -reg [31:0] writer_counter = 32'd0; -reg writer_slot = 1'd0; -reg writer_slot_ce = 1'd0; -reg writer_start = 1'd0; -reg writer_ongoing = 1'd0; -reg writer_stat_fifo_sink_valid = 1'd0; -wire writer_stat_fifo_sink_ready; -reg writer_stat_fifo_sink_first = 1'd0; -reg writer_stat_fifo_sink_last = 1'd0; -wire writer_stat_fifo_sink_payload_slot; -wire [31:0] writer_stat_fifo_sink_payload_length; -wire writer_stat_fifo_source_valid; -wire writer_stat_fifo_source_ready; -wire writer_stat_fifo_source_first; -wire writer_stat_fifo_source_last; -wire writer_stat_fifo_source_payload_slot; -wire [31:0] writer_stat_fifo_source_payload_length; -wire writer_stat_fifo_syncfifo_we; -wire writer_stat_fifo_syncfifo_writable; -wire writer_stat_fifo_syncfifo_re; -wire writer_stat_fifo_syncfifo_readable; -wire [34:0] writer_stat_fifo_syncfifo_din; -wire [34:0] writer_stat_fifo_syncfifo_dout; -reg [1:0] writer_stat_fifo_level = 2'd0; -reg writer_stat_fifo_replace = 1'd0; -reg writer_stat_fifo_produce = 1'd0; -reg writer_stat_fifo_consume = 1'd0; -reg writer_stat_fifo_wrport_adr = 1'd0; -wire [34:0] writer_stat_fifo_wrport_dat_r; -wire writer_stat_fifo_wrport_we; -wire [34:0] writer_stat_fifo_wrport_dat_w; -wire writer_stat_fifo_do_read; -wire writer_stat_fifo_rdport_adr; -wire [34:0] writer_stat_fifo_rdport_dat_r; -wire writer_stat_fifo_fifo_in_payload_slot; -wire [31:0] writer_stat_fifo_fifo_in_payload_length; -wire writer_stat_fifo_fifo_in_first; -wire writer_stat_fifo_fifo_in_last; -wire writer_stat_fifo_fifo_out_payload_slot; -wire [31:0] writer_stat_fifo_fifo_out_payload_length; -wire writer_stat_fifo_fifo_out_first; -wire writer_stat_fifo_fifo_out_last; -reg [8:0] writer_memory0_adr = 9'd0; -wire [31:0] writer_memory0_dat_r; -reg writer_memory0_we = 1'd0; -reg [31:0] writer_memory0_dat_w = 32'd0; -reg [8:0] writer_memory1_adr = 9'd0; -wire [31:0] writer_memory1_dat_r; -reg writer_memory1_we = 1'd0; -reg [31:0] writer_memory1_dat_w = 32'd0; -reg reader_source_source_valid = 1'd0; -wire reader_source_source_ready; -reg reader_source_source_first = 1'd0; -reg reader_source_source_last = 1'd0; -reg [31:0] reader_source_source_payload_data = 32'd0; -reg [3:0] reader_source_source_payload_last_be = 4'd0; -reg [3:0] reader_source_source_payload_error = 4'd0; -reg reader_start_start_re = 1'd0; -wire reader_start_start_r; -reg reader_start_start_we = 1'd0; -reg reader_start_start_w = 1'd0; -wire reader_ready_status; -wire reader_ready_we; -reg reader_ready_re = 1'd0; -wire [1:0] reader_level_status; -wire reader_level_we; -reg reader_level_re = 1'd0; -reg reader_slot_storage = 1'd0; -reg reader_slot_re = 1'd0; -reg [10:0] reader_length_storage = 11'd0; -reg reader_length_re = 1'd0; -wire reader_irq; -wire reader_eventsourcepulse_status; -reg reader_eventsourcepulse_pending = 1'd0; -reg reader_eventsourcepulse_trigger = 1'd0; -reg reader_eventsourcepulse_clear = 1'd0; -wire reader_event00; -wire reader_status_status; -wire reader_status_we; -reg reader_status_re = 1'd0; -wire reader_event01; -wire reader_pending_status; -wire reader_pending_we; -reg reader_pending_re = 1'd0; -reg reader_pending_r = 1'd0; -wire reader_event02; -reg reader_enable_storage = 1'd0; -reg reader_enable_re = 1'd0; -reg reader_start = 1'd0; -wire reader_cmd_fifo_sink_valid; -wire reader_cmd_fifo_sink_ready; -reg reader_cmd_fifo_sink_first = 1'd0; -reg reader_cmd_fifo_sink_last = 1'd0; -wire reader_cmd_fifo_sink_payload_slot; -wire [10:0] reader_cmd_fifo_sink_payload_length; -wire reader_cmd_fifo_source_valid; -reg reader_cmd_fifo_source_ready = 1'd0; -wire reader_cmd_fifo_source_first; -wire reader_cmd_fifo_source_last; -wire reader_cmd_fifo_source_payload_slot; -wire [10:0] reader_cmd_fifo_source_payload_length; -wire reader_cmd_fifo_syncfifo_we; -wire reader_cmd_fifo_syncfifo_writable; -wire reader_cmd_fifo_syncfifo_re; -wire reader_cmd_fifo_syncfifo_readable; -wire [13:0] reader_cmd_fifo_syncfifo_din; -wire [13:0] reader_cmd_fifo_syncfifo_dout; -reg [1:0] reader_cmd_fifo_level = 2'd0; -reg reader_cmd_fifo_replace = 1'd0; -reg reader_cmd_fifo_produce = 1'd0; -reg reader_cmd_fifo_consume = 1'd0; -reg reader_cmd_fifo_wrport_adr = 1'd0; -wire [13:0] reader_cmd_fifo_wrport_dat_r; -wire reader_cmd_fifo_wrport_we; -wire [13:0] reader_cmd_fifo_wrport_dat_w; -wire reader_cmd_fifo_do_read; -wire reader_cmd_fifo_rdport_adr; -wire [13:0] reader_cmd_fifo_rdport_dat_r; -wire reader_cmd_fifo_fifo_in_payload_slot; -wire [10:0] reader_cmd_fifo_fifo_in_payload_length; -wire reader_cmd_fifo_fifo_in_first; -wire reader_cmd_fifo_fifo_in_last; -wire reader_cmd_fifo_fifo_out_payload_slot; -wire [10:0] reader_cmd_fifo_fifo_out_payload_length; -wire reader_cmd_fifo_fifo_out_first; -wire reader_cmd_fifo_fifo_out_last; -reg [10:0] reader_read_address = 11'd0; -reg [10:0] reader_counter = 11'd0; -wire [8:0] reader_memory0_adr; -wire [31:0] reader_memory0_dat_r; -wire [8:0] reader_memory1_adr; -wire [31:0] reader_memory1_dat_r; -wire ev_irq; -wire [29:0] sram0_bus_adr0; -wire [31:0] sram0_bus_dat_w0; -wire [31:0] sram0_bus_dat_r0; -wire [3:0] sram0_bus_sel0; -wire sram0_bus_cyc0; -wire sram0_bus_stb0; -reg sram0_bus_ack0 = 1'd0; -wire sram0_bus_we0; -wire [2:0] sram0_bus_cti0; -wire [1:0] sram0_bus_bte0; -reg sram0_bus_err0 = 1'd0; -wire [8:0] sram0_adr0; -wire [31:0] sram0_dat_r0; -wire [29:0] sram1_bus_adr0; -wire [31:0] sram1_bus_dat_w0; -wire [31:0] sram1_bus_dat_r0; -wire [3:0] sram1_bus_sel0; -wire sram1_bus_cyc0; -wire sram1_bus_stb0; -reg sram1_bus_ack0 = 1'd0; -wire sram1_bus_we0; -wire [2:0] sram1_bus_cti0; -wire [1:0] sram1_bus_bte0; -reg sram1_bus_err0 = 1'd0; -wire [8:0] sram1_adr0; -wire [31:0] sram1_dat_r0; -wire [29:0] sram0_bus_adr1; -wire [31:0] sram0_bus_dat_w1; -wire [31:0] sram0_bus_dat_r1; -wire [3:0] sram0_bus_sel1; -wire sram0_bus_cyc1; -wire sram0_bus_stb1; -reg sram0_bus_ack1 = 1'd0; -wire sram0_bus_we1; -wire [2:0] sram0_bus_cti1; -wire [1:0] sram0_bus_bte1; -reg sram0_bus_err1 = 1'd0; -wire [8:0] sram0_adr1; -wire [31:0] sram0_dat_r1; -reg [3:0] sram0_we = 4'd0; -wire [31:0] sram0_dat_w; -wire [29:0] sram1_bus_adr1; -wire [31:0] sram1_bus_dat_w1; -wire [31:0] sram1_bus_dat_r1; -wire [3:0] sram1_bus_sel1; -wire sram1_bus_cyc1; -wire sram1_bus_stb1; -reg sram1_bus_ack1 = 1'd0; -wire sram1_bus_we1; -wire [2:0] sram1_bus_cti1; -wire [1:0] sram1_bus_bte1; -reg sram1_bus_err1 = 1'd0; -wire [8:0] sram1_adr1; -wire [31:0] sram1_dat_r1; -reg [3:0] sram1_we = 4'd0; -wire [31:0] sram1_dat_w; -reg [3:0] slave_sel = 4'd0; -reg [3:0] slave_sel_r = 4'd0; -wire [29:0] wb_bus_adr; -wire [31:0] wb_bus_dat_w; -wire [31:0] wb_bus_dat_r; -wire [3:0] wb_bus_sel; -wire wb_bus_cyc; -wire wb_bus_stb; -wire wb_bus_ack; -wire wb_bus_we; -wire [2:0] wb_bus_cti; -wire [1:0] wb_bus_bte; -wire wb_bus_err; -reg [1:0] subfragments_state = 2'd0; -reg [1:0] subfragments_next_state = 2'd0; -reg subfragments_liteethmacgap_state = 1'd0; -reg subfragments_liteethmacgap_next_state = 1'd0; -reg [3:0] tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0; -reg tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0; -reg [1:0] subfragments_liteethmacpreambleinserter_state = 2'd0; -reg [1:0] subfragments_liteethmacpreambleinserter_next_state = 2'd0; -reg [2:0] preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0; -reg preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0; -reg subfragments_liteethmacpreamblechecker_state = 1'd0; -reg subfragments_liteethmacpreamblechecker_next_state = 1'd0; -reg [1:0] subfragments_liteethmaccrc32inserter_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32inserter_next_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32checker_state = 2'd0; -reg [1:0] subfragments_liteethmaccrc32checker_next_state = 2'd0; -reg subfragments_liteethmacpaddinginserter_state = 1'd0; -reg subfragments_liteethmacpaddinginserter_next_state = 1'd0; -reg [15:0] padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0; -reg padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0; -reg subfragments_liteethmactxlastbe_state = 1'd0; -reg subfragments_liteethmactxlastbe_next_state = 1'd0; -reg [2:0] subfragments_liteethmacsramwriter_state = 3'd0; -reg [2:0] subfragments_liteethmacsramwriter_next_state = 3'd0; -reg [31:0] writer_counter_t_next_value = 32'd0; -reg writer_counter_t_next_value_ce = 1'd0; -reg [31:0] writer_errors_status_f_next_value = 32'd0; -reg writer_errors_status_f_next_value_ce = 1'd0; -reg [1:0] subfragments_liteethmacsramreader_state = 2'd0; -reg [1:0] subfragments_liteethmacsramreader_next_state = 2'd0; -reg [10:0] reader_counter_next_value = 11'd0; -reg reader_counter_next_value_ce = 1'd0; -reg [13:0] maccore_maccore_adr = 14'd0; -reg maccore_maccore_we = 1'd0; -reg [31:0] maccore_maccore_dat_w = 32'd0; -wire [31:0] maccore_maccore_dat_r; -wire [29:0] maccore_maccore_wishbone_adr; -wire [31:0] maccore_maccore_wishbone_dat_w; -reg [31:0] maccore_maccore_wishbone_dat_r = 32'd0; -wire [3:0] maccore_maccore_wishbone_sel; -wire maccore_maccore_wishbone_cyc; -wire maccore_maccore_wishbone_stb; -reg maccore_maccore_wishbone_ack = 1'd0; -wire maccore_maccore_wishbone_we; -wire [2:0] maccore_maccore_wishbone_cti; -wire [1:0] maccore_maccore_wishbone_bte; -reg maccore_maccore_wishbone_err = 1'd0; -wire [29:0] maccore_shared_adr; -wire [31:0] maccore_shared_dat_w; -reg [31:0] maccore_shared_dat_r = 32'd0; -wire [3:0] maccore_shared_sel; -wire maccore_shared_cyc; -wire maccore_shared_stb; -reg maccore_shared_ack = 1'd0; -wire maccore_shared_we; -wire [2:0] maccore_shared_cti; -wire [1:0] maccore_shared_bte; -wire maccore_shared_err; -wire maccore_request; -wire maccore_grant; -reg [1:0] maccore_slave_sel = 2'd0; -reg [1:0] maccore_slave_sel_r = 2'd0; -reg maccore_error = 1'd0; -wire maccore_wait; -wire maccore_done; -reg [19:0] maccore_count = 20'd1000000; -wire [13:0] maccore_interface0_bank_bus_adr; -wire maccore_interface0_bank_bus_we; -wire [31:0] maccore_interface0_bank_bus_dat_w; -reg [31:0] maccore_interface0_bank_bus_dat_r = 32'd0; -reg maccore_csrbank0_reset0_re = 1'd0; -wire [1:0] maccore_csrbank0_reset0_r; -reg maccore_csrbank0_reset0_we = 1'd0; -wire [1:0] maccore_csrbank0_reset0_w; -reg maccore_csrbank0_scratch0_re = 1'd0; -wire [31:0] maccore_csrbank0_scratch0_r; -reg maccore_csrbank0_scratch0_we = 1'd0; -wire [31:0] maccore_csrbank0_scratch0_w; -reg maccore_csrbank0_bus_errors_re = 1'd0; -wire [31:0] maccore_csrbank0_bus_errors_r; -reg maccore_csrbank0_bus_errors_we = 1'd0; -wire [31:0] maccore_csrbank0_bus_errors_w; -wire maccore_csrbank0_sel; -wire [13:0] maccore_interface1_bank_bus_adr; -wire maccore_interface1_bank_bus_we; -wire [31:0] maccore_interface1_bank_bus_dat_w; -reg [31:0] maccore_interface1_bank_bus_dat_r = 32'd0; -reg maccore_csrbank1_sram_writer_slot_re = 1'd0; -wire maccore_csrbank1_sram_writer_slot_r; -reg maccore_csrbank1_sram_writer_slot_we = 1'd0; -wire maccore_csrbank1_sram_writer_slot_w; -reg maccore_csrbank1_sram_writer_length_re = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_length_r; -reg maccore_csrbank1_sram_writer_length_we = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_length_w; -reg maccore_csrbank1_sram_writer_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_errors_r; -reg maccore_csrbank1_sram_writer_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_sram_writer_errors_w; -reg maccore_csrbank1_sram_writer_ev_status_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_status_r; -reg maccore_csrbank1_sram_writer_ev_status_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_status_w; -reg maccore_csrbank1_sram_writer_ev_pending_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_pending_r; -reg maccore_csrbank1_sram_writer_ev_pending_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_pending_w; -reg maccore_csrbank1_sram_writer_ev_enable0_re = 1'd0; -wire maccore_csrbank1_sram_writer_ev_enable0_r; -reg maccore_csrbank1_sram_writer_ev_enable0_we = 1'd0; -wire maccore_csrbank1_sram_writer_ev_enable0_w; -reg maccore_csrbank1_sram_reader_ready_re = 1'd0; -wire maccore_csrbank1_sram_reader_ready_r; -reg maccore_csrbank1_sram_reader_ready_we = 1'd0; -wire maccore_csrbank1_sram_reader_ready_w; -reg maccore_csrbank1_sram_reader_level_re = 1'd0; -wire [1:0] maccore_csrbank1_sram_reader_level_r; -reg maccore_csrbank1_sram_reader_level_we = 1'd0; -wire [1:0] maccore_csrbank1_sram_reader_level_w; -reg maccore_csrbank1_sram_reader_slot0_re = 1'd0; -wire maccore_csrbank1_sram_reader_slot0_r; -reg maccore_csrbank1_sram_reader_slot0_we = 1'd0; -wire maccore_csrbank1_sram_reader_slot0_w; -reg maccore_csrbank1_sram_reader_length0_re = 1'd0; -wire [10:0] maccore_csrbank1_sram_reader_length0_r; -reg maccore_csrbank1_sram_reader_length0_we = 1'd0; -wire [10:0] maccore_csrbank1_sram_reader_length0_w; -reg maccore_csrbank1_sram_reader_ev_status_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_status_r; -reg maccore_csrbank1_sram_reader_ev_status_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_status_w; -reg maccore_csrbank1_sram_reader_ev_pending_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_pending_r; -reg maccore_csrbank1_sram_reader_ev_pending_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_pending_w; -reg maccore_csrbank1_sram_reader_ev_enable0_re = 1'd0; -wire maccore_csrbank1_sram_reader_ev_enable0_r; -reg maccore_csrbank1_sram_reader_ev_enable0_we = 1'd0; -wire maccore_csrbank1_sram_reader_ev_enable0_w; -reg maccore_csrbank1_preamble_crc_re = 1'd0; -wire maccore_csrbank1_preamble_crc_r; -reg maccore_csrbank1_preamble_crc_we = 1'd0; -wire maccore_csrbank1_preamble_crc_w; -reg maccore_csrbank1_preamble_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_preamble_errors_r; -reg maccore_csrbank1_preamble_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_preamble_errors_w; -reg maccore_csrbank1_crc_errors_re = 1'd0; -wire [31:0] maccore_csrbank1_crc_errors_r; -reg maccore_csrbank1_crc_errors_we = 1'd0; -wire [31:0] maccore_csrbank1_crc_errors_w; -wire maccore_csrbank1_sel; -wire [13:0] maccore_interface2_bank_bus_adr; -wire maccore_interface2_bank_bus_we; -wire [31:0] maccore_interface2_bank_bus_dat_w; -reg [31:0] maccore_interface2_bank_bus_dat_r = 32'd0; -reg maccore_csrbank2_mode_detection_mode_re = 1'd0; -wire maccore_csrbank2_mode_detection_mode_r; -reg maccore_csrbank2_mode_detection_mode_we = 1'd0; -wire maccore_csrbank2_mode_detection_mode_w; -reg maccore_csrbank2_crg_reset0_re = 1'd0; -wire maccore_csrbank2_crg_reset0_r; -reg maccore_csrbank2_crg_reset0_we = 1'd0; -wire maccore_csrbank2_crg_reset0_w; -reg maccore_csrbank2_mdio_w0_re = 1'd0; -wire [2:0] maccore_csrbank2_mdio_w0_r; -reg maccore_csrbank2_mdio_w0_we = 1'd0; -wire [2:0] maccore_csrbank2_mdio_w0_w; -reg maccore_csrbank2_mdio_r_re = 1'd0; -wire maccore_csrbank2_mdio_r_r; -reg maccore_csrbank2_mdio_r_we = 1'd0; -wire maccore_csrbank2_mdio_r_w; -wire maccore_csrbank2_sel; -wire [13:0] maccore_csr_interconnect_adr; -wire maccore_csr_interconnect_we; -wire [31:0] maccore_csr_interconnect_dat_w; -wire [31:0] maccore_csr_interconnect_dat_r; -reg maccore_state = 1'd0; -reg maccore_next_state = 1'd0; -reg [29:0] array_muxed0 = 30'd0; -reg [31:0] array_muxed1 = 32'd0; -reg [3:0] array_muxed2 = 4'd0; -reg array_muxed3 = 1'd0; -reg array_muxed4 = 1'd0; -reg array_muxed5 = 1'd0; -reg [2:0] array_muxed6 = 3'd0; -reg [1:0] array_muxed7 = 2'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0; -wire rst_meta0; -wire rst_meta1; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0; -(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs1 = 6'd0; -(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs0 = 6'd0; -(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs1 = 6'd0; -assign wb_bus_adr = wishbone_adr; -assign wb_bus_dat_w = wishbone_dat_w; -assign wishbone_dat_r = wb_bus_dat_r; -assign wb_bus_sel = wishbone_sel; -assign wb_bus_cyc = wishbone_cyc; -assign wb_bus_stb = wishbone_stb; -assign wishbone_ack = wb_bus_ack; -assign wb_bus_we = wishbone_we; -assign wb_bus_cti = wishbone_cti; -assign wb_bus_bte = wishbone_bte; -assign wishbone_err = wb_bus_err; -assign interrupt = ev_irq; -assign maccore_maccore_bus_error = maccore_error; -assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors; +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYGMIIMII) +│ └─── mode_detection (LiteEthGMIIMIIModeDetection) +│ │ └─── eth_ps (PulseSynchronizer) +│ │ └─── fsm (FSM) +│ └─── crg (LiteEthPHYGMIICRG) +│ │ └─── hw_reset (LiteEthPHYHWReset) +│ │ └─── [BUFG] +│ │ └─── [BUFG] +│ └─── tx (LiteEthPHYGMIIMIITX) +│ │ └─── liteethphygmiitx_0* (LiteEthPHYGMIITX) +│ │ └─── liteethphymiitx_0* (LiteEthPHYMIITX) +│ │ │ └─── converter (Converter) +│ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ └─── demultiplexer_0* (Demultiplexer) +│ └─── rx (LiteEthPHYGMIIMIIRX) +│ │ └─── gmii_rx (LiteEthPHYGMIIRX) +│ │ └─── mii_rx (LiteEthPHYMIIRX) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ └─── mux (Multiplexer) +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [FDPE] +└─── [ODDR] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire builder_csrbank2_mode_detection_mode_r; +reg builder_csrbank2_mode_detection_mode_re = 1'd0; +wire builder_csrbank2_mode_detection_mode_w; +reg builder_csrbank2_mode_detection_mode_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +reg [1:0] builder_liteethphygmiimii_next_state = 2'd0; +reg [1:0] builder_liteethphygmiimii_state = 2'd0; +wire builder_request; +wire builder_rst_meta0; +wire builder_rst_meta1; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +reg builder_wishbone2csr_next_state = 1'd0; +reg builder_wishbone2csr_state = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl00 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl01 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl10 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl11 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl20 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl21 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl30 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl31 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl40 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl41 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl50 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) +reg builder_xilinxmultiregimpl51 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl60 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl61 = 6'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl70 = 6'd0; +(* async_reg = "true", dont_touch = "true" *) +reg [5:0] builder_xilinxmultiregimpl71 = 6'd0; +(* dont_touch = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* dont_touch = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +reg [8:0] main_maccore_ethphy_counter = 9'd0; +wire main_maccore_ethphy_counter_ce; +wire main_maccore_ethphy_counter_done; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +reg main_maccore_ethphy_demux_endpoint0_source_first = 1'd0; +reg main_maccore_ethphy_demux_endpoint0_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_demux_endpoint0_source_payload_data = 8'd0; +reg main_maccore_ethphy_demux_endpoint0_source_payload_error = 1'd0; +reg main_maccore_ethphy_demux_endpoint0_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_demux_endpoint0_source_ready; +reg main_maccore_ethphy_demux_endpoint0_source_valid = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_first = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_demux_endpoint1_source_payload_data = 8'd0; +reg main_maccore_ethphy_demux_endpoint1_source_payload_error = 1'd0; +reg main_maccore_ethphy_demux_endpoint1_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_demux_endpoint1_source_ready; +reg main_maccore_ethphy_demux_endpoint1_source_valid = 1'd0; +wire main_maccore_ethphy_demux_sel; +wire main_maccore_ethphy_demux_sink_first; +wire main_maccore_ethphy_demux_sink_last; +wire [7:0] main_maccore_ethphy_demux_sink_payload_data; +wire main_maccore_ethphy_demux_sink_payload_error; +wire main_maccore_ethphy_demux_sink_payload_last_be; +reg main_maccore_ethphy_demux_sink_ready = 1'd0; +wire main_maccore_ethphy_demux_sink_valid; +reg [9:0] main_maccore_ethphy_eth_counter = 10'd0; +wire main_maccore_ethphy_eth_tick; +reg main_maccore_ethphy_eth_tx_clk = 1'd0; +reg main_maccore_ethphy_gmii_rx_dv_d = 1'd0; +reg main_maccore_ethphy_gmii_rx_source_first = 1'd0; +wire main_maccore_ethphy_gmii_rx_source_last; +reg [7:0] main_maccore_ethphy_gmii_rx_source_payload_data = 8'd0; +reg main_maccore_ethphy_gmii_rx_source_payload_error = 1'd0; +reg main_maccore_ethphy_gmii_rx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_gmii_rx_source_ready; +reg main_maccore_ethphy_gmii_rx_source_valid = 1'd0; +reg [7:0] main_maccore_ethphy_gmii_tx_pads_tx_data = 8'd0; +reg main_maccore_ethphy_gmii_tx_pads_tx_en = 1'd0; +reg main_maccore_ethphy_gmii_tx_pads_tx_er = 1'd0; +wire main_maccore_ethphy_gmii_tx_sink_first; +wire main_maccore_ethphy_gmii_tx_sink_last; +wire [7:0] main_maccore_ethphy_gmii_tx_sink_payload_data; +wire main_maccore_ethphy_gmii_tx_sink_payload_error; +wire main_maccore_ethphy_gmii_tx_sink_payload_last_be; +reg main_maccore_ethphy_gmii_tx_sink_ready = 1'd0; +wire main_maccore_ethphy_gmii_tx_sink_valid; +wire main_maccore_ethphy_i; +wire main_maccore_ethphy_mdc; +reg main_maccore_ethphy_mii_rx_converter_demux = 1'd0; +wire main_maccore_ethphy_mii_rx_converter_load_part; +reg main_maccore_ethphy_mii_rx_converter_sink_first = 1'd0; +wire main_maccore_ethphy_mii_rx_converter_sink_last; +reg [3:0] main_maccore_ethphy_mii_rx_converter_sink_payload_data = 4'd0; +wire main_maccore_ethphy_mii_rx_converter_sink_ready; +reg main_maccore_ethphy_mii_rx_converter_sink_valid = 1'd0; +reg main_maccore_ethphy_mii_rx_converter_source_first = 1'd0; +reg main_maccore_ethphy_mii_rx_converter_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_mii_rx_converter_source_payload_data = 8'd0; +reg [1:0] main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count = 2'd0; +wire main_maccore_ethphy_mii_rx_converter_source_ready; +wire main_maccore_ethphy_mii_rx_converter_source_valid; +reg main_maccore_ethphy_mii_rx_converter_strobe_all = 1'd0; +reg main_maccore_ethphy_mii_rx_reset = 1'd0; +wire main_maccore_ethphy_mii_rx_source_first; +wire main_maccore_ethphy_mii_rx_source_last; +wire [7:0] main_maccore_ethphy_mii_rx_source_payload_data; +reg main_maccore_ethphy_mii_rx_source_payload_error = 1'd0; +reg main_maccore_ethphy_mii_rx_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_mii_rx_source_ready; +wire main_maccore_ethphy_mii_rx_source_source_first; +wire main_maccore_ethphy_mii_rx_source_source_last; +wire [7:0] main_maccore_ethphy_mii_rx_source_source_payload_data; +wire main_maccore_ethphy_mii_rx_source_source_ready; +wire main_maccore_ethphy_mii_rx_source_source_valid; +wire main_maccore_ethphy_mii_rx_source_valid; +wire main_maccore_ethphy_mii_tx_converter_first; +wire main_maccore_ethphy_mii_tx_converter_last; +reg main_maccore_ethphy_mii_tx_converter_mux = 1'd0; +reg main_maccore_ethphy_mii_tx_converter_sink_first = 1'd0; +reg main_maccore_ethphy_mii_tx_converter_sink_last = 1'd0; +wire [7:0] main_maccore_ethphy_mii_tx_converter_sink_payload_data; +wire main_maccore_ethphy_mii_tx_converter_sink_ready; +wire main_maccore_ethphy_mii_tx_converter_sink_valid; +wire main_maccore_ethphy_mii_tx_converter_source_first; +wire main_maccore_ethphy_mii_tx_converter_source_last; +reg [3:0] main_maccore_ethphy_mii_tx_converter_source_payload_data = 4'd0; +wire main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count; +wire main_maccore_ethphy_mii_tx_converter_source_ready; +wire main_maccore_ethphy_mii_tx_converter_source_valid; +reg [7:0] main_maccore_ethphy_mii_tx_pads_tx_data = 8'd0; +reg main_maccore_ethphy_mii_tx_pads_tx_en = 1'd0; +reg main_maccore_ethphy_mii_tx_pads_tx_er = 1'd0; +wire main_maccore_ethphy_mii_tx_sink_first; +wire main_maccore_ethphy_mii_tx_sink_last; +wire [7:0] main_maccore_ethphy_mii_tx_sink_payload_data; +wire main_maccore_ethphy_mii_tx_sink_payload_error; +wire main_maccore_ethphy_mii_tx_sink_payload_last_be; +wire main_maccore_ethphy_mii_tx_sink_ready; +wire main_maccore_ethphy_mii_tx_sink_valid; +wire main_maccore_ethphy_mii_tx_source_source_first; +wire main_maccore_ethphy_mii_tx_source_source_last; +wire [3:0] main_maccore_ethphy_mii_tx_source_source_payload_data; +wire main_maccore_ethphy_mii_tx_source_source_ready; +wire main_maccore_ethphy_mii_tx_source_source_valid; +reg main_maccore_ethphy_mode0 = 1'd0; +reg main_maccore_ethphy_mode1 = 1'd0; +reg main_maccore_ethphy_mode_re = 1'd0; +wire main_maccore_ethphy_mode_status; +wire main_maccore_ethphy_mode_we; +wire main_maccore_ethphy_mux_endpoint0_sink_first; +wire main_maccore_ethphy_mux_endpoint0_sink_last; +wire [7:0] main_maccore_ethphy_mux_endpoint0_sink_payload_data; +wire main_maccore_ethphy_mux_endpoint0_sink_payload_error; +wire main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; +reg main_maccore_ethphy_mux_endpoint0_sink_ready = 1'd0; +wire main_maccore_ethphy_mux_endpoint0_sink_valid; +wire main_maccore_ethphy_mux_endpoint1_sink_first; +wire main_maccore_ethphy_mux_endpoint1_sink_last; +wire [7:0] main_maccore_ethphy_mux_endpoint1_sink_payload_data; +wire main_maccore_ethphy_mux_endpoint1_sink_payload_error; +wire main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; +reg main_maccore_ethphy_mux_endpoint1_sink_ready = 1'd0; +wire main_maccore_ethphy_mux_endpoint1_sink_valid; +wire main_maccore_ethphy_mux_sel; +reg main_maccore_ethphy_mux_source_first = 1'd0; +reg main_maccore_ethphy_mux_source_last = 1'd0; +reg [7:0] main_maccore_ethphy_mux_source_payload_data = 8'd0; +reg main_maccore_ethphy_mux_source_payload_error = 1'd0; +reg main_maccore_ethphy_mux_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_mux_source_ready; +reg main_maccore_ethphy_mux_source_valid = 1'd0; +wire main_maccore_ethphy_o; +wire main_maccore_ethphy_oe; +reg [7:0] main_maccore_ethphy_pads_d_rx_data = 8'd0; +reg main_maccore_ethphy_pads_d_rx_dv = 1'd0; +reg main_maccore_ethphy_r = 1'd0; +wire main_maccore_ethphy_reset0; +wire main_maccore_ethphy_reset1; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire main_maccore_ethphy_sink_sink_first; +wire main_maccore_ethphy_sink_sink_last; +wire [7:0] main_maccore_ethphy_sink_sink_payload_data; +wire main_maccore_ethphy_sink_sink_payload_error; +wire main_maccore_ethphy_sink_sink_payload_last_be; +wire main_maccore_ethphy_sink_sink_ready; +wire main_maccore_ethphy_sink_sink_valid; +wire main_maccore_ethphy_source_source_first; +wire main_maccore_ethphy_source_source_last; +wire [7:0] main_maccore_ethphy_source_source_payload_data; +wire main_maccore_ethphy_source_source_payload_error; +wire main_maccore_ethphy_source_source_payload_last_be; +wire main_maccore_ethphy_source_source_ready; +wire main_maccore_ethphy_source_source_valid; +reg [23:0] main_maccore_ethphy_sys_counter = 24'd0; +reg main_maccore_ethphy_sys_counter_ce = 1'd0; +reg main_maccore_ethphy_sys_counter_reset = 1'd0; +wire main_maccore_ethphy_sys_tick; +reg main_maccore_ethphy_toggle_i = 1'd0; +wire main_maccore_ethphy_toggle_o; +reg main_maccore_ethphy_toggle_o_r = 1'd0; +reg main_maccore_ethphy_update_mode = 1'd0; +wire main_maccore_ethphy_w; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* dont_touch = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* dont_touch = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_wb_bus_adr = wishbone_adr; +assign main_wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wishbone_sel; +assign main_wb_bus_cyc = wishbone_cyc; +assign main_wb_bus_stb = wishbone_stb; +assign wishbone_ack = main_wb_bus_ack; +assign main_wb_bus_we = wishbone_we; +assign main_wb_bus_cti = wishbone_cti; +assign main_wb_bus_bte = wishbone_bte; +assign wishbone_err = main_wb_bus_err; +assign interrupt = main_sram167_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; assign sys_clk = sys_clock; assign por_clk = sys_clock; -assign sys_rst = maccore_int_rst; -assign maccore_ethphy_mode_status = maccore_ethphy_mode0; -assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0); -assign maccore_ethphy_i = maccore_ethphy_eth_tick; -assign maccore_ethphy_sys_tick = maccore_ethphy_o; -assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r); -always @(*) begin - subfragments_next_state <= 2'd0; - maccore_ethphy_sys_counter_reset <= 1'd0; - maccore_ethphy_sys_counter_ce <= 1'd0; - maccore_ethphy_mode1 <= 1'd0; - maccore_ethphy_update_mode <= 1'd0; - subfragments_next_state <= subfragments_state; - case (subfragments_state) - 1'd1: begin - maccore_ethphy_sys_counter_ce <= 1'd1; - if (maccore_ethphy_sys_tick) begin - subfragments_next_state <= 2'd2; - end - end - 2'd2: begin - maccore_ethphy_update_mode <= 1'd1; - if ((maccore_ethphy_sys_counter > 10'd860)) begin - maccore_ethphy_mode1 <= 1'd1; - end else begin - maccore_ethphy_mode1 <= 1'd0; - end - subfragments_next_state <= 1'd0; - end - default: begin - maccore_ethphy_sys_counter_reset <= 1'd1; - if (maccore_ethphy_sys_tick) begin - subfragments_next_state <= 1'd1; - end - end - endcase -end -always @(*) begin - maccore_ethphy_eth_tx_clk <= 1'd0; - if ((maccore_ethphy_mode0 == 1'd1)) begin - maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_tx; - end else begin - maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_rx; - end -end -assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1); -assign gmii_eth_rst_n = (~maccore_ethphy_reset0); -assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256); -assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done); -assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done); -assign maccore_ethphy_liteethphygmiimiitx_demux_sel = (maccore_ethphy_mode0 == 1'd1); -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0 = maccore_ethphy_liteethphygmiimiitx_demux_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_first = maccore_ethphy_liteethphygmiimiitx_sink_sink_first0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_last = maccore_ethphy_liteethphygmiimiitx_sink_sink_last0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0; -assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready = maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error; -assign gmii_eth_tx_er = 1'd0; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1 = maccore_ethphy_liteethphygmiimiitx_converter_sink_ready; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_ready = 1'd1; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiitx_converter_sink_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiitx_converter_sink_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_sink_ready = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready; -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[3:0]; - maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[7:4]; -end -assign maccore_ethphy_liteethphygmiimiitx_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_first = maccore_ethphy_liteethphygmiimiitx_converter_source_source_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_last = maccore_ethphy_liteethphygmiimiitx_converter_source_source_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_ready; -assign {maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data} = maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_first = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_last = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last; -assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd0); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd1); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first & maccore_ethphy_liteethphygmiimiitx_converter_converter_first); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_last); -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready = (maccore_ethphy_liteethphygmiimiitx_converter_converter_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready); -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= 4'd0; - case (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux) - 1'd0: begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0]; - end - default: begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4]; - end - endcase -end -assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count = maccore_ethphy_liteethphygmiimiitx_converter_converter_last; -always @(*) begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= 1'd0; - case (maccore_ethphy_liteethphygmiimiitx_demux_sel) - 1'd0: begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid; - maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error; - end - endcase -end -assign maccore_ethphy_liteethphygmiimiirx_mux_sel = (maccore_ethphy_mode0 == 1'd1); -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready = maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_ready1 = maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1; -assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_valid0 = maccore_ethphy_liteethphygmiimiirx_mux_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_mux_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready0; -assign maccore_ethphy_liteethphygmiimiirx_source_source_first0 = maccore_ethphy_liteethphygmiimiirx_mux_source_first; -assign maccore_ethphy_liteethphygmiimiirx_source_source_last0 = maccore_ethphy_liteethphygmiimiirx_mux_source_last; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error; -assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last = ((~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv) & maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d); -assign maccore_ethphy_liteethphygmiimiirx_converter_sink_last = (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv); -assign maccore_ethphy_liteethphygmiimiirx_source_source_valid1 = maccore_ethphy_liteethphygmiimiirx_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready1; -assign maccore_ethphy_liteethphygmiimiirx_source_source_first1 = maccore_ethphy_liteethphygmiimiirx_converter_source_first; -assign maccore_ethphy_liteethphygmiimiirx_source_source_last1 = maccore_ethphy_liteethphygmiimiirx_converter_source_last; -assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1 = maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiirx_converter_sink_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiirx_converter_sink_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiirx_converter_sink_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_sink_ready = maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data = {maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data}; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_first = maccore_ethphy_liteethphygmiimiirx_converter_source_source_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_last = maccore_ethphy_liteethphygmiimiirx_converter_source_source_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_ready; -always @(*) begin - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[3:0]; - maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[7:4]; -end -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_first = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_last = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last; -assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready = ((~maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all) | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready); -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all; -assign maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part = (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready); -always @(*) begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= 1'd0; - case (maccore_ethphy_liteethphygmiimiirx_mux_sel) - 1'd0: begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid; - maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready; - maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first; - maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be; - maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error; - end - endcase -end -assign gmii_eth_mdc = maccore_ethphy__w_storage[0]; -assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1]; -assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2]; -assign tx_cdc_sink_sink_valid = source_valid; -assign source_ready = tx_cdc_sink_sink_ready; -assign tx_cdc_sink_sink_first = source_first; -assign tx_cdc_sink_sink_last = source_last; -assign tx_cdc_sink_sink_payload_data = source_payload_data; -assign tx_cdc_sink_sink_payload_last_be = source_payload_last_be; -assign tx_cdc_sink_sink_payload_error = source_payload_error; -assign sink_valid = rx_cdc_source_source_valid; -assign rx_cdc_source_source_ready = sink_ready; -assign sink_first = rx_cdc_source_source_first; -assign sink_last = rx_cdc_source_source_last; -assign sink_payload_data = rx_cdc_source_source_payload_data; -assign sink_payload_last_be = rx_cdc_source_source_payload_last_be; -assign sink_payload_error = rx_cdc_source_source_payload_error; -assign ps_preamble_error_i = preamble_checker_error; -assign ps_crc_error_i = liteethmaccrc32checker_error; -always @(*) begin - tx_gap_inserter_source_valid <= 1'd0; - tx_gap_inserter_source_first <= 1'd0; - tx_gap_inserter_source_last <= 1'd0; - tx_gap_inserter_source_payload_data <= 8'd0; - tx_gap_inserter_source_payload_last_be <= 1'd0; - tx_gap_inserter_source_payload_error <= 1'd0; - subfragments_liteethmacgap_next_state <= 1'd0; - tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0; - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0; - tx_gap_inserter_sink_ready <= 1'd0; - subfragments_liteethmacgap_next_state <= subfragments_liteethmacgap_state; - case (subfragments_liteethmacgap_state) - 1'd1: begin - tx_gap_inserter_counter_liteethmacgap_next_value <= (tx_gap_inserter_counter + 1'd1); - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - if ((tx_gap_inserter_counter == 4'd11)) begin - subfragments_liteethmacgap_next_state <= 1'd0; - end - end - default: begin - tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0; - tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1; - tx_gap_inserter_source_valid <= tx_gap_inserter_sink_valid; - tx_gap_inserter_sink_ready <= tx_gap_inserter_source_ready; - tx_gap_inserter_source_first <= tx_gap_inserter_sink_first; - tx_gap_inserter_source_last <= tx_gap_inserter_sink_last; - tx_gap_inserter_source_payload_data <= tx_gap_inserter_sink_payload_data; - tx_gap_inserter_source_payload_last_be <= tx_gap_inserter_sink_payload_last_be; - tx_gap_inserter_source_payload_error <= tx_gap_inserter_sink_payload_error; - if (((tx_gap_inserter_sink_valid & tx_gap_inserter_sink_last) & tx_gap_inserter_sink_ready)) begin - subfragments_liteethmacgap_next_state <= 1'd1; - end - end - endcase -end -assign preamble_inserter_source_payload_last_be = preamble_inserter_sink_payload_last_be; -always @(*) begin - preamble_inserter_source_first <= 1'd0; - preamble_inserter_source_last <= 1'd0; - preamble_inserter_source_payload_data <= 8'd0; - subfragments_liteethmacpreambleinserter_next_state <= 2'd0; - preamble_inserter_source_payload_error <= 1'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0; - preamble_inserter_sink_ready <= 1'd0; - preamble_inserter_source_valid <= 1'd0; - preamble_inserter_source_payload_data <= preamble_inserter_sink_payload_data; - subfragments_liteethmacpreambleinserter_next_state <= subfragments_liteethmacpreambleinserter_state; - case (subfragments_liteethmacpreambleinserter_state) - 1'd1: begin - preamble_inserter_source_valid <= 1'd1; - case (preamble_inserter_count) - 1'd0: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[7:0]; - end - 1'd1: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[15:8]; - end - 2'd2: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[23:16]; - end - 2'd3: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[31:24]; - end - 3'd4: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[39:32]; - end - 3'd5: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[47:40]; - end - 3'd6: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[55:48]; - end - default: begin - preamble_inserter_source_payload_data <= preamble_inserter_preamble[63:56]; - end - endcase - if (preamble_inserter_source_ready) begin - if ((preamble_inserter_count == 3'd7)) begin - subfragments_liteethmacpreambleinserter_next_state <= 2'd2; - end else begin - preamble_inserter_count_liteethmacpreambleinserter_next_value <= (preamble_inserter_count + 1'd1); - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - end - end - end - 2'd2: begin - preamble_inserter_source_valid <= preamble_inserter_sink_valid; - preamble_inserter_sink_ready <= preamble_inserter_source_ready; - preamble_inserter_source_first <= preamble_inserter_sink_first; - preamble_inserter_source_last <= preamble_inserter_sink_last; - preamble_inserter_source_payload_error <= preamble_inserter_sink_payload_error; - if (((preamble_inserter_sink_valid & preamble_inserter_sink_last) & preamble_inserter_source_ready)) begin - subfragments_liteethmacpreambleinserter_next_state <= 1'd0; - end - end - default: begin - preamble_inserter_sink_ready <= 1'd1; - preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0; - preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1; - if (preamble_inserter_sink_valid) begin - preamble_inserter_sink_ready <= 1'd0; - subfragments_liteethmacpreambleinserter_next_state <= 1'd1; - end - end - endcase -end -assign preamble_checker_source_payload_data = preamble_checker_sink_payload_data; -assign preamble_checker_source_payload_last_be = preamble_checker_sink_payload_last_be; -always @(*) begin - preamble_checker_source_payload_error <= 1'd0; - preamble_checker_error <= 1'd0; - preamble_checker_source_first <= 1'd0; - preamble_checker_source_valid <= 1'd0; - subfragments_liteethmacpreamblechecker_next_state <= 1'd0; - preamble_checker_sink_ready <= 1'd0; - preamble_checker_source_last <= 1'd0; - subfragments_liteethmacpreamblechecker_next_state <= subfragments_liteethmacpreamblechecker_state; - case (subfragments_liteethmacpreamblechecker_state) - 1'd1: begin - preamble_checker_source_valid <= preamble_checker_sink_valid; - preamble_checker_sink_ready <= preamble_checker_source_ready; - preamble_checker_source_first <= preamble_checker_sink_first; - preamble_checker_source_last <= preamble_checker_sink_last; - preamble_checker_source_payload_error <= preamble_checker_sink_payload_error; - if (((preamble_checker_source_valid & preamble_checker_source_last) & preamble_checker_source_ready)) begin - subfragments_liteethmacpreamblechecker_next_state <= 1'd0; - end - end - default: begin - preamble_checker_sink_ready <= 1'd1; - if (((preamble_checker_sink_valid & (~preamble_checker_sink_last)) & (preamble_checker_sink_payload_data == 8'd213))) begin - subfragments_liteethmacpreamblechecker_next_state <= 1'd1; - end - if ((preamble_checker_sink_valid & preamble_checker_sink_last)) begin - preamble_checker_error <= 1'd1; - end - end - endcase -end -assign liteethmaccrc32inserter_cnt_done = (liteethmaccrc32inserter_cnt == 1'd0); -assign liteethmaccrc32inserter_sink_valid = crc32_inserter_source_valid; -assign crc32_inserter_source_ready = liteethmaccrc32inserter_sink_ready; -assign liteethmaccrc32inserter_sink_first = crc32_inserter_source_first; -assign liteethmaccrc32inserter_sink_last = crc32_inserter_source_last; -assign liteethmaccrc32inserter_sink_payload_data = crc32_inserter_source_payload_data; -assign liteethmaccrc32inserter_sink_payload_last_be = crc32_inserter_source_payload_last_be; -assign liteethmaccrc32inserter_sink_payload_error = crc32_inserter_source_payload_error; -assign liteethmaccrc32inserter_data1 = liteethmaccrc32inserter_data0; -assign liteethmaccrc32inserter_last = liteethmaccrc32inserter_reg; -assign liteethmaccrc32inserter_value = (~{liteethmaccrc32inserter_reg[0], liteethmaccrc32inserter_reg[1], liteethmaccrc32inserter_reg[2], liteethmaccrc32inserter_reg[3], liteethmaccrc32inserter_reg[4], liteethmaccrc32inserter_reg[5], liteethmaccrc32inserter_reg[6], liteethmaccrc32inserter_reg[7], liteethmaccrc32inserter_reg[8], liteethmaccrc32inserter_reg[9], liteethmaccrc32inserter_reg[10], liteethmaccrc32inserter_reg[11], liteethmaccrc32inserter_reg[12], liteethmaccrc32inserter_reg[13], liteethmaccrc32inserter_reg[14], liteethmaccrc32inserter_reg[15], liteethmaccrc32inserter_reg[16], liteethmaccrc32inserter_reg[17], liteethmaccrc32inserter_reg[18], liteethmaccrc32inserter_reg[19], liteethmaccrc32inserter_reg[20], liteethmaccrc32inserter_reg[21], liteethmaccrc32inserter_reg[22], liteethmaccrc32inserter_reg[23], liteethmaccrc32inserter_reg[24], liteethmaccrc32inserter_reg[25], liteethmaccrc32inserter_reg[26], liteethmaccrc32inserter_reg[27], liteethmaccrc32inserter_reg[28], liteethmaccrc32inserter_reg[29], liteethmaccrc32inserter_reg[30], liteethmaccrc32inserter_reg[31]}); -assign liteethmaccrc32inserter_error = (liteethmaccrc32inserter_next != 32'd3338984827); -always @(*) begin - liteethmaccrc32inserter_next <= 32'd0; - liteethmaccrc32inserter_next[0] <= (((liteethmaccrc32inserter_last[24] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[1] <= (((((((liteethmaccrc32inserter_last[25] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[2] <= (((((((((liteethmaccrc32inserter_last[26] ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[3] <= (((((((liteethmaccrc32inserter_last[27] ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[4] <= (((((((((liteethmaccrc32inserter_last[28] ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[5] <= (((((((((((((liteethmaccrc32inserter_last[29] ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[6] <= (((((((((((liteethmaccrc32inserter_last[30] ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[7] <= (((((((((liteethmaccrc32inserter_last[31] ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[8] <= ((((((((liteethmaccrc32inserter_last[0] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[9] <= ((((((((liteethmaccrc32inserter_last[1] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[10] <= ((((((((liteethmaccrc32inserter_last[2] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[11] <= ((((((((liteethmaccrc32inserter_last[3] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[12] <= ((((((((((((liteethmaccrc32inserter_last[4] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[13] <= ((((((((((((liteethmaccrc32inserter_last[5] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[14] <= ((((((((((liteethmaccrc32inserter_last[6] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[15] <= ((((((((liteethmaccrc32inserter_last[7] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[16] <= ((((((liteethmaccrc32inserter_last[8] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[17] <= ((((((liteethmaccrc32inserter_last[9] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[18] <= ((((((liteethmaccrc32inserter_last[10] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[19] <= ((((liteethmaccrc32inserter_last[11] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[20] <= ((liteethmaccrc32inserter_last[12] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]); - liteethmaccrc32inserter_next[21] <= ((liteethmaccrc32inserter_last[13] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]); - liteethmaccrc32inserter_next[22] <= ((liteethmaccrc32inserter_last[14] ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[23] <= ((((((liteethmaccrc32inserter_last[15] ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[24] <= ((((((liteethmaccrc32inserter_last[16] ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[25] <= ((((liteethmaccrc32inserter_last[17] ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[26] <= ((((((((liteethmaccrc32inserter_last[18] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]); - liteethmaccrc32inserter_next[27] <= ((((((((liteethmaccrc32inserter_last[19] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]); - liteethmaccrc32inserter_next[28] <= ((((((liteethmaccrc32inserter_last[20] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]); - liteethmaccrc32inserter_next[29] <= ((((((liteethmaccrc32inserter_last[21] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]); - liteethmaccrc32inserter_next[30] <= ((((liteethmaccrc32inserter_last[22] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]); - liteethmaccrc32inserter_next[31] <= ((liteethmaccrc32inserter_last[23] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]); -end -always @(*) begin - liteethmaccrc32inserter_source_first <= 1'd0; - liteethmaccrc32inserter_source_last <= 1'd0; - liteethmaccrc32inserter_source_payload_data <= 8'd0; - liteethmaccrc32inserter_source_payload_last_be <= 1'd0; - liteethmaccrc32inserter_source_payload_error <= 1'd0; - liteethmaccrc32inserter_data0 <= 8'd0; - liteethmaccrc32inserter_is_ongoing0 <= 1'd0; - liteethmaccrc32inserter_sink_ready <= 1'd0; - liteethmaccrc32inserter_is_ongoing1 <= 1'd0; - liteethmaccrc32inserter_ce <= 1'd0; - liteethmaccrc32inserter_reset <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= 2'd0; - liteethmaccrc32inserter_source_valid <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= subfragments_liteethmaccrc32inserter_state; - case (subfragments_liteethmaccrc32inserter_state) - 1'd1: begin - liteethmaccrc32inserter_ce <= (liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_source_ready); - liteethmaccrc32inserter_data0 <= liteethmaccrc32inserter_sink_payload_data; - liteethmaccrc32inserter_source_valid <= liteethmaccrc32inserter_sink_valid; - liteethmaccrc32inserter_sink_ready <= liteethmaccrc32inserter_source_ready; - liteethmaccrc32inserter_source_first <= liteethmaccrc32inserter_sink_first; - liteethmaccrc32inserter_source_last <= liteethmaccrc32inserter_sink_last; - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_sink_payload_data; - liteethmaccrc32inserter_source_payload_last_be <= liteethmaccrc32inserter_sink_payload_last_be; - liteethmaccrc32inserter_source_payload_error <= liteethmaccrc32inserter_sink_payload_error; - liteethmaccrc32inserter_source_last <= 1'd0; - if (((liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_sink_last) & liteethmaccrc32inserter_source_ready)) begin - subfragments_liteethmaccrc32inserter_next_state <= 2'd2; - end - end - 2'd2: begin - liteethmaccrc32inserter_source_valid <= 1'd1; - case (liteethmaccrc32inserter_cnt) - 1'd0: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[31:24]; - end - 1'd1: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[23:16]; - end - 2'd2: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[15:8]; - end - default: begin - liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[7:0]; - end - endcase - if (liteethmaccrc32inserter_cnt_done) begin - liteethmaccrc32inserter_source_last <= 1'd1; - if (liteethmaccrc32inserter_source_ready) begin - subfragments_liteethmaccrc32inserter_next_state <= 1'd0; - end - end - liteethmaccrc32inserter_is_ongoing1 <= 1'd1; - end - default: begin - liteethmaccrc32inserter_reset <= 1'd1; - liteethmaccrc32inserter_sink_ready <= 1'd1; - if (liteethmaccrc32inserter_sink_valid) begin - liteethmaccrc32inserter_sink_ready <= 1'd0; - subfragments_liteethmaccrc32inserter_next_state <= 1'd1; - end - liteethmaccrc32inserter_is_ongoing0 <= 1'd1; - end - endcase -end -assign crc32_inserter_sink_ready = ((~crc32_inserter_source_valid) | crc32_inserter_source_ready); -assign liteethmaccrc32checker_fifo_full = (liteethmaccrc32checker_syncfifo_level == 3'd4); -assign liteethmaccrc32checker_fifo_in = (liteethmaccrc32checker_sink_sink_valid & ((~liteethmaccrc32checker_fifo_full) | liteethmaccrc32checker_fifo_out)); -assign liteethmaccrc32checker_fifo_out = (liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_ready); -assign liteethmaccrc32checker_syncfifo_sink_first = liteethmaccrc32checker_sink_sink_first; -assign liteethmaccrc32checker_syncfifo_sink_last = liteethmaccrc32checker_sink_sink_last; -assign liteethmaccrc32checker_syncfifo_sink_payload_data = liteethmaccrc32checker_sink_sink_payload_data; -assign liteethmaccrc32checker_syncfifo_sink_payload_last_be = liteethmaccrc32checker_sink_sink_payload_last_be; -assign liteethmaccrc32checker_syncfifo_sink_payload_error = liteethmaccrc32checker_sink_sink_payload_error; -always @(*) begin - liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; - liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_sink_sink_valid; - liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_fifo_in; -end -always @(*) begin - liteethmaccrc32checker_sink_sink_ready <= 1'd0; - liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_syncfifo_sink_ready; - liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_fifo_in; -end -assign liteethmaccrc32checker_source_source_valid = (liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_fifo_full); -assign liteethmaccrc32checker_source_source_last = liteethmaccrc32checker_sink_sink_last; -assign liteethmaccrc32checker_syncfifo_source_ready = liteethmaccrc32checker_fifo_out; -assign liteethmaccrc32checker_source_source_payload_data = liteethmaccrc32checker_syncfifo_source_payload_data; -assign liteethmaccrc32checker_source_source_payload_last_be = liteethmaccrc32checker_syncfifo_source_payload_last_be; -always @(*) begin - liteethmaccrc32checker_source_source_payload_error <= 1'd0; - liteethmaccrc32checker_source_source_payload_error <= liteethmaccrc32checker_syncfifo_source_payload_error; - liteethmaccrc32checker_source_source_payload_error <= (liteethmaccrc32checker_sink_sink_payload_error | liteethmaccrc32checker_crc_error); -end -assign liteethmaccrc32checker_error = ((liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_last) & liteethmaccrc32checker_crc_error); -assign liteethmaccrc32checker_crc_data0 = liteethmaccrc32checker_sink_sink_payload_data; -assign liteethmaccrc32checker_sink_sink_valid = crc32_checker_source_valid; -assign crc32_checker_source_ready = liteethmaccrc32checker_sink_sink_ready; -assign liteethmaccrc32checker_sink_sink_first = crc32_checker_source_first; -assign liteethmaccrc32checker_sink_sink_last = crc32_checker_source_last; -assign liteethmaccrc32checker_sink_sink_payload_data = crc32_checker_source_payload_data; -assign liteethmaccrc32checker_sink_sink_payload_last_be = crc32_checker_source_payload_last_be; -assign liteethmaccrc32checker_sink_sink_payload_error = crc32_checker_source_payload_error; -assign liteethmaccrc32checker_crc_data1 = liteethmaccrc32checker_crc_data0; -assign liteethmaccrc32checker_crc_last = liteethmaccrc32checker_crc_reg; -assign liteethmaccrc32checker_crc_value = (~{liteethmaccrc32checker_crc_reg[0], liteethmaccrc32checker_crc_reg[1], liteethmaccrc32checker_crc_reg[2], liteethmaccrc32checker_crc_reg[3], liteethmaccrc32checker_crc_reg[4], liteethmaccrc32checker_crc_reg[5], liteethmaccrc32checker_crc_reg[6], liteethmaccrc32checker_crc_reg[7], liteethmaccrc32checker_crc_reg[8], liteethmaccrc32checker_crc_reg[9], liteethmaccrc32checker_crc_reg[10], liteethmaccrc32checker_crc_reg[11], liteethmaccrc32checker_crc_reg[12], liteethmaccrc32checker_crc_reg[13], liteethmaccrc32checker_crc_reg[14], liteethmaccrc32checker_crc_reg[15], liteethmaccrc32checker_crc_reg[16], liteethmaccrc32checker_crc_reg[17], liteethmaccrc32checker_crc_reg[18], liteethmaccrc32checker_crc_reg[19], liteethmaccrc32checker_crc_reg[20], liteethmaccrc32checker_crc_reg[21], liteethmaccrc32checker_crc_reg[22], liteethmaccrc32checker_crc_reg[23], liteethmaccrc32checker_crc_reg[24], liteethmaccrc32checker_crc_reg[25], liteethmaccrc32checker_crc_reg[26], liteethmaccrc32checker_crc_reg[27], liteethmaccrc32checker_crc_reg[28], liteethmaccrc32checker_crc_reg[29], liteethmaccrc32checker_crc_reg[30], liteethmaccrc32checker_crc_reg[31]}); -assign liteethmaccrc32checker_crc_error = (liteethmaccrc32checker_crc_next != 32'd3338984827); -always @(*) begin - liteethmaccrc32checker_crc_next <= 32'd0; - liteethmaccrc32checker_crc_next[0] <= (((liteethmaccrc32checker_crc_last[24] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[1] <= (((((((liteethmaccrc32checker_crc_last[25] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[2] <= (((((((((liteethmaccrc32checker_crc_last[26] ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[3] <= (((((((liteethmaccrc32checker_crc_last[27] ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[4] <= (((((((((liteethmaccrc32checker_crc_last[28] ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[5] <= (((((((((((((liteethmaccrc32checker_crc_last[29] ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[6] <= (((((((((((liteethmaccrc32checker_crc_last[30] ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[7] <= (((((((((liteethmaccrc32checker_crc_last[31] ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[8] <= ((((((((liteethmaccrc32checker_crc_last[0] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[9] <= ((((((((liteethmaccrc32checker_crc_last[1] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[10] <= ((((((((liteethmaccrc32checker_crc_last[2] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[11] <= ((((((((liteethmaccrc32checker_crc_last[3] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[12] <= ((((((((((((liteethmaccrc32checker_crc_last[4] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[13] <= ((((((((((((liteethmaccrc32checker_crc_last[5] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[14] <= ((((((((((liteethmaccrc32checker_crc_last[6] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[15] <= ((((((((liteethmaccrc32checker_crc_last[7] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[16] <= ((((((liteethmaccrc32checker_crc_last[8] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[17] <= ((((((liteethmaccrc32checker_crc_last[9] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[18] <= ((((((liteethmaccrc32checker_crc_last[10] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[19] <= ((((liteethmaccrc32checker_crc_last[11] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[20] <= ((liteethmaccrc32checker_crc_last[12] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]); - liteethmaccrc32checker_crc_next[21] <= ((liteethmaccrc32checker_crc_last[13] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]); - liteethmaccrc32checker_crc_next[22] <= ((liteethmaccrc32checker_crc_last[14] ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[23] <= ((((((liteethmaccrc32checker_crc_last[15] ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[24] <= ((((((liteethmaccrc32checker_crc_last[16] ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[25] <= ((((liteethmaccrc32checker_crc_last[17] ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[26] <= ((((((((liteethmaccrc32checker_crc_last[18] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]); - liteethmaccrc32checker_crc_next[27] <= ((((((((liteethmaccrc32checker_crc_last[19] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]); - liteethmaccrc32checker_crc_next[28] <= ((((((liteethmaccrc32checker_crc_last[20] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]); - liteethmaccrc32checker_crc_next[29] <= ((((((liteethmaccrc32checker_crc_last[21] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]); - liteethmaccrc32checker_crc_next[30] <= ((((liteethmaccrc32checker_crc_last[22] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]); - liteethmaccrc32checker_crc_next[31] <= ((liteethmaccrc32checker_crc_last[23] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]); -end -assign liteethmaccrc32checker_syncfifo_syncfifo_din = {liteethmaccrc32checker_syncfifo_fifo_in_last, liteethmaccrc32checker_syncfifo_fifo_in_first, liteethmaccrc32checker_syncfifo_fifo_in_payload_error, liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; -assign {liteethmaccrc32checker_syncfifo_fifo_out_last, liteethmaccrc32checker_syncfifo_fifo_out_first, liteethmaccrc32checker_syncfifo_fifo_out_payload_error, liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = liteethmaccrc32checker_syncfifo_syncfifo_dout; -assign liteethmaccrc32checker_syncfifo_sink_ready = liteethmaccrc32checker_syncfifo_syncfifo_writable; -assign liteethmaccrc32checker_syncfifo_syncfifo_we = liteethmaccrc32checker_syncfifo_sink_valid; -assign liteethmaccrc32checker_syncfifo_fifo_in_first = liteethmaccrc32checker_syncfifo_sink_first; -assign liteethmaccrc32checker_syncfifo_fifo_in_last = liteethmaccrc32checker_syncfifo_sink_last; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_data = liteethmaccrc32checker_syncfifo_sink_payload_data; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = liteethmaccrc32checker_syncfifo_sink_payload_last_be; -assign liteethmaccrc32checker_syncfifo_fifo_in_payload_error = liteethmaccrc32checker_syncfifo_sink_payload_error; -assign liteethmaccrc32checker_syncfifo_source_valid = liteethmaccrc32checker_syncfifo_syncfifo_readable; -assign liteethmaccrc32checker_syncfifo_source_first = liteethmaccrc32checker_syncfifo_fifo_out_first; -assign liteethmaccrc32checker_syncfifo_source_last = liteethmaccrc32checker_syncfifo_fifo_out_last; -assign liteethmaccrc32checker_syncfifo_source_payload_data = liteethmaccrc32checker_syncfifo_fifo_out_payload_data; -assign liteethmaccrc32checker_syncfifo_source_payload_last_be = liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; -assign liteethmaccrc32checker_syncfifo_source_payload_error = liteethmaccrc32checker_syncfifo_fifo_out_payload_error; -assign liteethmaccrc32checker_syncfifo_syncfifo_re = liteethmaccrc32checker_syncfifo_source_ready; -always @(*) begin - liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; - if (liteethmaccrc32checker_syncfifo_replace) begin - liteethmaccrc32checker_syncfifo_wrport_adr <= (liteethmaccrc32checker_syncfifo_produce - 1'd1); - end else begin - liteethmaccrc32checker_syncfifo_wrport_adr <= liteethmaccrc32checker_syncfifo_produce; - end -end -assign liteethmaccrc32checker_syncfifo_wrport_dat_w = liteethmaccrc32checker_syncfifo_syncfifo_din; -assign liteethmaccrc32checker_syncfifo_wrport_we = (liteethmaccrc32checker_syncfifo_syncfifo_we & (liteethmaccrc32checker_syncfifo_syncfifo_writable | liteethmaccrc32checker_syncfifo_replace)); -assign liteethmaccrc32checker_syncfifo_do_read = (liteethmaccrc32checker_syncfifo_syncfifo_readable & liteethmaccrc32checker_syncfifo_syncfifo_re); -assign liteethmaccrc32checker_syncfifo_rdport_adr = liteethmaccrc32checker_syncfifo_consume; -assign liteethmaccrc32checker_syncfifo_syncfifo_dout = liteethmaccrc32checker_syncfifo_rdport_dat_r; -assign liteethmaccrc32checker_syncfifo_syncfifo_writable = (liteethmaccrc32checker_syncfifo_level != 3'd5); -assign liteethmaccrc32checker_syncfifo_syncfifo_readable = (liteethmaccrc32checker_syncfifo_level != 1'd0); -always @(*) begin - liteethmaccrc32checker_crc_ce <= 1'd0; - liteethmaccrc32checker_crc_reset <= 1'd0; - subfragments_liteethmaccrc32checker_next_state <= 2'd0; - liteethmaccrc32checker_fifo_reset <= 1'd0; - subfragments_liteethmaccrc32checker_next_state <= subfragments_liteethmaccrc32checker_state; - case (subfragments_liteethmaccrc32checker_state) - 1'd1: begin - if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin - liteethmaccrc32checker_crc_ce <= 1'd1; - subfragments_liteethmaccrc32checker_next_state <= 2'd2; - end - end - 2'd2: begin - if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin - liteethmaccrc32checker_crc_ce <= 1'd1; - if (liteethmaccrc32checker_sink_sink_last) begin - subfragments_liteethmaccrc32checker_next_state <= 1'd0; - end - end - end - default: begin - liteethmaccrc32checker_crc_reset <= 1'd1; - liteethmaccrc32checker_fifo_reset <= 1'd1; - subfragments_liteethmaccrc32checker_next_state <= 1'd1; - end - endcase -end -assign crc32_checker_sink_ready = ((~crc32_checker_source_valid) | crc32_checker_source_ready); -assign ps_preamble_error_o = (ps_preamble_error_toggle_o ^ ps_preamble_error_toggle_o_r); -assign ps_crc_error_o = (ps_crc_error_toggle_o ^ ps_crc_error_toggle_o_r); -assign padding_inserter_counter_done = (padding_inserter_counter >= 6'd59); -always @(*) begin - padding_inserter_source_valid <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0; - padding_inserter_source_first <= 1'd0; - padding_inserter_source_last <= 1'd0; - padding_inserter_source_payload_data <= 8'd0; - padding_inserter_source_payload_last_be <= 1'd0; - padding_inserter_source_payload_error <= 1'd0; - padding_inserter_sink_ready <= 1'd0; - subfragments_liteethmacpaddinginserter_next_state <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0; - subfragments_liteethmacpaddinginserter_next_state <= subfragments_liteethmacpaddinginserter_state; - case (subfragments_liteethmacpaddinginserter_state) - 1'd1: begin - padding_inserter_source_valid <= 1'd1; - padding_inserter_source_last <= padding_inserter_counter_done; - padding_inserter_source_payload_data <= 1'd0; - if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1); - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (padding_inserter_counter_done) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - subfragments_liteethmacpaddinginserter_next_state <= 1'd0; - end - end - end - default: begin - padding_inserter_source_valid <= padding_inserter_sink_valid; - padding_inserter_sink_ready <= padding_inserter_source_ready; - padding_inserter_source_first <= padding_inserter_sink_first; - padding_inserter_source_last <= padding_inserter_sink_last; - padding_inserter_source_payload_data <= padding_inserter_sink_payload_data; - padding_inserter_source_payload_last_be <= padding_inserter_sink_payload_last_be; - padding_inserter_source_payload_error <= padding_inserter_sink_payload_error; - if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1); - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - if (padding_inserter_sink_last) begin - if ((~padding_inserter_counter_done)) begin - padding_inserter_source_last <= 1'd0; - subfragments_liteethmacpaddinginserter_next_state <= 1'd1; - end else begin - padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0; - padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1; - end - end - end - end - endcase -end -assign padding_checker_source_valid = padding_checker_sink_valid; -assign padding_checker_sink_ready = padding_checker_source_ready; -assign padding_checker_source_first = padding_checker_sink_first; -assign padding_checker_source_last = padding_checker_sink_last; -assign padding_checker_source_payload_data = padding_checker_sink_payload_data; -assign padding_checker_source_payload_last_be = padding_checker_sink_payload_last_be; -assign padding_checker_source_payload_error = padding_checker_sink_payload_error; -always @(*) begin - tx_last_be_source_payload_data <= 8'd0; - subfragments_liteethmactxlastbe_next_state <= 1'd0; - tx_last_be_source_payload_error <= 1'd0; - tx_last_be_sink_ready <= 1'd0; - tx_last_be_source_valid <= 1'd0; - tx_last_be_source_first <= 1'd0; - tx_last_be_source_last <= 1'd0; - subfragments_liteethmactxlastbe_next_state <= subfragments_liteethmactxlastbe_state; - case (subfragments_liteethmactxlastbe_state) - 1'd1: begin - tx_last_be_sink_ready <= 1'd1; - if ((tx_last_be_sink_valid & tx_last_be_sink_last)) begin - subfragments_liteethmactxlastbe_next_state <= 1'd0; - end - end - default: begin - tx_last_be_source_valid <= tx_last_be_sink_valid; - tx_last_be_sink_ready <= tx_last_be_source_ready; - tx_last_be_source_first <= tx_last_be_sink_first; - tx_last_be_source_payload_data <= tx_last_be_sink_payload_data; - tx_last_be_source_payload_error <= tx_last_be_sink_payload_error; - tx_last_be_source_last <= tx_last_be_sink_payload_last_be; - if ((tx_last_be_sink_valid & tx_last_be_sink_ready)) begin - if ((tx_last_be_sink_payload_last_be & (~tx_last_be_sink_last))) begin - subfragments_liteethmactxlastbe_next_state <= 1'd1; - end - end - end - endcase -end -assign rx_last_be_source_valid = rx_last_be_sink_valid; -assign rx_last_be_sink_ready = rx_last_be_source_ready; -assign rx_last_be_source_first = rx_last_be_sink_first; -assign rx_last_be_source_last = rx_last_be_sink_last; -assign rx_last_be_source_payload_data = rx_last_be_sink_payload_data; -assign rx_last_be_source_payload_error = rx_last_be_sink_payload_error; -always @(*) begin - rx_last_be_source_payload_last_be <= 1'd0; - rx_last_be_source_payload_last_be <= rx_last_be_sink_payload_last_be; - rx_last_be_source_payload_last_be <= rx_last_be_sink_last; -end -assign tx_converter_converter_sink_valid = tx_converter_sink_valid; -assign tx_converter_converter_sink_first = tx_converter_sink_first; -assign tx_converter_converter_sink_last = tx_converter_sink_last; -assign tx_converter_sink_ready = tx_converter_converter_sink_ready; -always @(*) begin - tx_converter_converter_sink_payload_data <= 40'd0; - tx_converter_converter_sink_payload_data[7:0] <= tx_converter_sink_payload_data[7:0]; - tx_converter_converter_sink_payload_data[8] <= tx_converter_sink_payload_last_be[0]; - tx_converter_converter_sink_payload_data[9] <= tx_converter_sink_payload_error[0]; - tx_converter_converter_sink_payload_data[17:10] <= tx_converter_sink_payload_data[15:8]; - tx_converter_converter_sink_payload_data[18] <= tx_converter_sink_payload_last_be[1]; - tx_converter_converter_sink_payload_data[19] <= tx_converter_sink_payload_error[1]; - tx_converter_converter_sink_payload_data[27:20] <= tx_converter_sink_payload_data[23:16]; - tx_converter_converter_sink_payload_data[28] <= tx_converter_sink_payload_last_be[2]; - tx_converter_converter_sink_payload_data[29] <= tx_converter_sink_payload_error[2]; - tx_converter_converter_sink_payload_data[37:30] <= tx_converter_sink_payload_data[31:24]; - tx_converter_converter_sink_payload_data[38] <= tx_converter_sink_payload_last_be[3]; - tx_converter_converter_sink_payload_data[39] <= tx_converter_sink_payload_error[3]; -end -assign tx_converter_source_valid = tx_converter_source_source_valid; -assign tx_converter_source_first = tx_converter_source_source_first; -assign tx_converter_source_last = tx_converter_source_source_last; -assign tx_converter_source_source_ready = tx_converter_source_ready; -assign {tx_converter_source_payload_error, tx_converter_source_payload_last_be, tx_converter_source_payload_data} = tx_converter_source_source_payload_data; -assign tx_converter_source_source_valid = tx_converter_converter_source_valid; -assign tx_converter_converter_source_ready = tx_converter_source_source_ready; -assign tx_converter_source_source_first = tx_converter_converter_source_first; -assign tx_converter_source_source_last = tx_converter_converter_source_last; -assign tx_converter_source_source_payload_data = tx_converter_converter_source_payload_data; -assign tx_converter_converter_first = (tx_converter_converter_mux == 1'd0); -assign tx_converter_converter_last = (tx_converter_converter_mux == 2'd3); -assign tx_converter_converter_source_valid = tx_converter_converter_sink_valid; -assign tx_converter_converter_source_first = (tx_converter_converter_sink_first & tx_converter_converter_first); -assign tx_converter_converter_source_last = (tx_converter_converter_sink_last & tx_converter_converter_last); -assign tx_converter_converter_sink_ready = (tx_converter_converter_last & tx_converter_converter_source_ready); -always @(*) begin - tx_converter_converter_source_payload_data <= 10'd0; - case (tx_converter_converter_mux) - 1'd0: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[9:0]; - end - 1'd1: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[19:10]; - end - 2'd2: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[29:20]; - end - default: begin - tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[39:30]; - end - endcase -end -assign tx_converter_converter_source_payload_valid_token_count = tx_converter_converter_last; -assign rx_converter_converter_sink_valid = rx_converter_sink_valid; -assign rx_converter_converter_sink_first = rx_converter_sink_first; -assign rx_converter_converter_sink_last = rx_converter_sink_last; -assign rx_converter_sink_ready = rx_converter_converter_sink_ready; -assign rx_converter_converter_sink_payload_data = {rx_converter_sink_payload_error, rx_converter_sink_payload_last_be, rx_converter_sink_payload_data}; -assign rx_converter_source_valid = rx_converter_source_source_valid; -assign rx_converter_source_first = rx_converter_source_source_first; -assign rx_converter_source_last = rx_converter_source_source_last; -assign rx_converter_source_source_ready = rx_converter_source_ready; -always @(*) begin - rx_converter_source_payload_data <= 32'd0; - rx_converter_source_payload_data[7:0] <= rx_converter_source_source_payload_data[7:0]; - rx_converter_source_payload_data[15:8] <= rx_converter_source_source_payload_data[17:10]; - rx_converter_source_payload_data[23:16] <= rx_converter_source_source_payload_data[27:20]; - rx_converter_source_payload_data[31:24] <= rx_converter_source_source_payload_data[37:30]; -end -always @(*) begin - rx_converter_source_payload_last_be <= 4'd0; - rx_converter_source_payload_last_be[0] <= rx_converter_source_source_payload_data[8]; - rx_converter_source_payload_last_be[1] <= rx_converter_source_source_payload_data[18]; - rx_converter_source_payload_last_be[2] <= rx_converter_source_source_payload_data[28]; - rx_converter_source_payload_last_be[3] <= rx_converter_source_source_payload_data[38]; -end -always @(*) begin - rx_converter_source_payload_error <= 4'd0; - rx_converter_source_payload_error[0] <= rx_converter_source_source_payload_data[9]; - rx_converter_source_payload_error[1] <= rx_converter_source_source_payload_data[19]; - rx_converter_source_payload_error[2] <= rx_converter_source_source_payload_data[29]; - rx_converter_source_payload_error[3] <= rx_converter_source_source_payload_data[39]; -end -assign rx_converter_source_source_valid = rx_converter_converter_source_valid; -assign rx_converter_converter_source_ready = rx_converter_source_source_ready; -assign rx_converter_source_source_first = rx_converter_converter_source_first; -assign rx_converter_source_source_last = rx_converter_converter_source_last; -assign rx_converter_source_source_payload_data = rx_converter_converter_source_payload_data; -assign rx_converter_converter_sink_ready = ((~rx_converter_converter_strobe_all) | rx_converter_converter_source_ready); -assign rx_converter_converter_source_valid = rx_converter_converter_strobe_all; -assign rx_converter_converter_load_part = (rx_converter_converter_sink_valid & rx_converter_converter_sink_ready); -assign tx_cdc_cdc_sink_valid = tx_cdc_sink_sink_valid; -assign tx_cdc_sink_sink_ready = tx_cdc_cdc_sink_ready; -assign tx_cdc_cdc_sink_first = tx_cdc_sink_sink_first; -assign tx_cdc_cdc_sink_last = tx_cdc_sink_sink_last; -assign tx_cdc_cdc_sink_payload_data = tx_cdc_sink_sink_payload_data; -assign tx_cdc_cdc_sink_payload_last_be = tx_cdc_sink_sink_payload_last_be; -assign tx_cdc_cdc_sink_payload_error = tx_cdc_sink_sink_payload_error; -assign tx_cdc_source_source_valid = tx_cdc_cdc_source_valid; -assign tx_cdc_cdc_source_ready = tx_cdc_source_source_ready; -assign tx_cdc_source_source_first = tx_cdc_cdc_source_first; -assign tx_cdc_source_source_last = tx_cdc_cdc_source_last; -assign tx_cdc_source_source_payload_data = tx_cdc_cdc_source_payload_data; -assign tx_cdc_source_source_payload_last_be = tx_cdc_cdc_source_payload_last_be; -assign tx_cdc_source_source_payload_error = tx_cdc_cdc_source_payload_error; -assign tx_cdc_cdc_asyncfifo_din = {tx_cdc_cdc_fifo_in_last, tx_cdc_cdc_fifo_in_first, tx_cdc_cdc_fifo_in_payload_error, tx_cdc_cdc_fifo_in_payload_last_be, tx_cdc_cdc_fifo_in_payload_data}; -assign {tx_cdc_cdc_fifo_out_last, tx_cdc_cdc_fifo_out_first, tx_cdc_cdc_fifo_out_payload_error, tx_cdc_cdc_fifo_out_payload_last_be, tx_cdc_cdc_fifo_out_payload_data} = tx_cdc_cdc_asyncfifo_dout; -assign tx_cdc_cdc_sink_ready = tx_cdc_cdc_asyncfifo_writable; -assign tx_cdc_cdc_asyncfifo_we = tx_cdc_cdc_sink_valid; -assign tx_cdc_cdc_fifo_in_first = tx_cdc_cdc_sink_first; -assign tx_cdc_cdc_fifo_in_last = tx_cdc_cdc_sink_last; -assign tx_cdc_cdc_fifo_in_payload_data = tx_cdc_cdc_sink_payload_data; -assign tx_cdc_cdc_fifo_in_payload_last_be = tx_cdc_cdc_sink_payload_last_be; -assign tx_cdc_cdc_fifo_in_payload_error = tx_cdc_cdc_sink_payload_error; -assign tx_cdc_cdc_source_valid = tx_cdc_cdc_asyncfifo_readable; -assign tx_cdc_cdc_source_first = tx_cdc_cdc_fifo_out_first; -assign tx_cdc_cdc_source_last = tx_cdc_cdc_fifo_out_last; -assign tx_cdc_cdc_source_payload_data = tx_cdc_cdc_fifo_out_payload_data; -assign tx_cdc_cdc_source_payload_last_be = tx_cdc_cdc_fifo_out_payload_last_be; -assign tx_cdc_cdc_source_payload_error = tx_cdc_cdc_fifo_out_payload_error; -assign tx_cdc_cdc_asyncfifo_re = tx_cdc_cdc_source_ready; -assign tx_cdc_cdc_graycounter0_ce = (tx_cdc_cdc_asyncfifo_writable & tx_cdc_cdc_asyncfifo_we); -assign tx_cdc_cdc_graycounter1_ce = (tx_cdc_cdc_asyncfifo_readable & tx_cdc_cdc_asyncfifo_re); -assign tx_cdc_cdc_asyncfifo_writable = (((tx_cdc_cdc_graycounter0_q[5] == tx_cdc_cdc_consume_wdomain[5]) | (tx_cdc_cdc_graycounter0_q[4] == tx_cdc_cdc_consume_wdomain[4])) | (tx_cdc_cdc_graycounter0_q[3:0] != tx_cdc_cdc_consume_wdomain[3:0])); -assign tx_cdc_cdc_asyncfifo_readable = (tx_cdc_cdc_graycounter1_q != tx_cdc_cdc_produce_rdomain); -assign tx_cdc_cdc_wrport_adr = tx_cdc_cdc_graycounter0_q_binary[4:0]; -assign tx_cdc_cdc_wrport_dat_w = tx_cdc_cdc_asyncfifo_din; -assign tx_cdc_cdc_wrport_we = tx_cdc_cdc_graycounter0_ce; -assign tx_cdc_cdc_rdport_adr = tx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign tx_cdc_cdc_asyncfifo_dout = tx_cdc_cdc_rdport_dat_r; -always @(*) begin - tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (tx_cdc_cdc_graycounter0_ce) begin - tx_cdc_cdc_graycounter0_q_next_binary <= (tx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - tx_cdc_cdc_graycounter0_q_next_binary <= tx_cdc_cdc_graycounter0_q_binary; - end -end -assign tx_cdc_cdc_graycounter0_q_next = (tx_cdc_cdc_graycounter0_q_next_binary ^ tx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (tx_cdc_cdc_graycounter1_ce) begin - tx_cdc_cdc_graycounter1_q_next_binary <= (tx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - tx_cdc_cdc_graycounter1_q_next_binary <= tx_cdc_cdc_graycounter1_q_binary; - end -end -assign tx_cdc_cdc_graycounter1_q_next = (tx_cdc_cdc_graycounter1_q_next_binary ^ tx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign rx_cdc_cdc_sink_valid = rx_cdc_sink_sink_valid; -assign rx_cdc_sink_sink_ready = rx_cdc_cdc_sink_ready; -assign rx_cdc_cdc_sink_first = rx_cdc_sink_sink_first; -assign rx_cdc_cdc_sink_last = rx_cdc_sink_sink_last; -assign rx_cdc_cdc_sink_payload_data = rx_cdc_sink_sink_payload_data; -assign rx_cdc_cdc_sink_payload_last_be = rx_cdc_sink_sink_payload_last_be; -assign rx_cdc_cdc_sink_payload_error = rx_cdc_sink_sink_payload_error; -assign rx_cdc_source_source_valid = rx_cdc_cdc_source_valid; -assign rx_cdc_cdc_source_ready = rx_cdc_source_source_ready; -assign rx_cdc_source_source_first = rx_cdc_cdc_source_first; -assign rx_cdc_source_source_last = rx_cdc_cdc_source_last; -assign rx_cdc_source_source_payload_data = rx_cdc_cdc_source_payload_data; -assign rx_cdc_source_source_payload_last_be = rx_cdc_cdc_source_payload_last_be; -assign rx_cdc_source_source_payload_error = rx_cdc_cdc_source_payload_error; -assign rx_cdc_cdc_asyncfifo_din = {rx_cdc_cdc_fifo_in_last, rx_cdc_cdc_fifo_in_first, rx_cdc_cdc_fifo_in_payload_error, rx_cdc_cdc_fifo_in_payload_last_be, rx_cdc_cdc_fifo_in_payload_data}; -assign {rx_cdc_cdc_fifo_out_last, rx_cdc_cdc_fifo_out_first, rx_cdc_cdc_fifo_out_payload_error, rx_cdc_cdc_fifo_out_payload_last_be, rx_cdc_cdc_fifo_out_payload_data} = rx_cdc_cdc_asyncfifo_dout; -assign rx_cdc_cdc_sink_ready = rx_cdc_cdc_asyncfifo_writable; -assign rx_cdc_cdc_asyncfifo_we = rx_cdc_cdc_sink_valid; -assign rx_cdc_cdc_fifo_in_first = rx_cdc_cdc_sink_first; -assign rx_cdc_cdc_fifo_in_last = rx_cdc_cdc_sink_last; -assign rx_cdc_cdc_fifo_in_payload_data = rx_cdc_cdc_sink_payload_data; -assign rx_cdc_cdc_fifo_in_payload_last_be = rx_cdc_cdc_sink_payload_last_be; -assign rx_cdc_cdc_fifo_in_payload_error = rx_cdc_cdc_sink_payload_error; -assign rx_cdc_cdc_source_valid = rx_cdc_cdc_asyncfifo_readable; -assign rx_cdc_cdc_source_first = rx_cdc_cdc_fifo_out_first; -assign rx_cdc_cdc_source_last = rx_cdc_cdc_fifo_out_last; -assign rx_cdc_cdc_source_payload_data = rx_cdc_cdc_fifo_out_payload_data; -assign rx_cdc_cdc_source_payload_last_be = rx_cdc_cdc_fifo_out_payload_last_be; -assign rx_cdc_cdc_source_payload_error = rx_cdc_cdc_fifo_out_payload_error; -assign rx_cdc_cdc_asyncfifo_re = rx_cdc_cdc_source_ready; -assign rx_cdc_cdc_graycounter0_ce = (rx_cdc_cdc_asyncfifo_writable & rx_cdc_cdc_asyncfifo_we); -assign rx_cdc_cdc_graycounter1_ce = (rx_cdc_cdc_asyncfifo_readable & rx_cdc_cdc_asyncfifo_re); -assign rx_cdc_cdc_asyncfifo_writable = (((rx_cdc_cdc_graycounter0_q[5] == rx_cdc_cdc_consume_wdomain[5]) | (rx_cdc_cdc_graycounter0_q[4] == rx_cdc_cdc_consume_wdomain[4])) | (rx_cdc_cdc_graycounter0_q[3:0] != rx_cdc_cdc_consume_wdomain[3:0])); -assign rx_cdc_cdc_asyncfifo_readable = (rx_cdc_cdc_graycounter1_q != rx_cdc_cdc_produce_rdomain); -assign rx_cdc_cdc_wrport_adr = rx_cdc_cdc_graycounter0_q_binary[4:0]; -assign rx_cdc_cdc_wrport_dat_w = rx_cdc_cdc_asyncfifo_din; -assign rx_cdc_cdc_wrport_we = rx_cdc_cdc_graycounter0_ce; -assign rx_cdc_cdc_rdport_adr = rx_cdc_cdc_graycounter1_q_next_binary[4:0]; -assign rx_cdc_cdc_asyncfifo_dout = rx_cdc_cdc_rdport_dat_r; -always @(*) begin - rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; - if (rx_cdc_cdc_graycounter0_ce) begin - rx_cdc_cdc_graycounter0_q_next_binary <= (rx_cdc_cdc_graycounter0_q_binary + 1'd1); - end else begin - rx_cdc_cdc_graycounter0_q_next_binary <= rx_cdc_cdc_graycounter0_q_binary; - end -end -assign rx_cdc_cdc_graycounter0_q_next = (rx_cdc_cdc_graycounter0_q_next_binary ^ rx_cdc_cdc_graycounter0_q_next_binary[5:1]); -always @(*) begin - rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; - if (rx_cdc_cdc_graycounter1_ce) begin - rx_cdc_cdc_graycounter1_q_next_binary <= (rx_cdc_cdc_graycounter1_q_binary + 1'd1); - end else begin - rx_cdc_cdc_graycounter1_q_next_binary <= rx_cdc_cdc_graycounter1_q_binary; - end -end -assign rx_cdc_cdc_graycounter1_q_next = (rx_cdc_cdc_graycounter1_q_next_binary ^ rx_cdc_cdc_graycounter1_q_next_binary[5:1]); -assign tx_converter_sink_valid = tx_cdc_source_source_valid; -assign tx_cdc_source_source_ready = tx_converter_sink_ready; -assign tx_converter_sink_first = tx_cdc_source_source_first; -assign tx_converter_sink_last = tx_cdc_source_source_last; -assign tx_converter_sink_payload_data = tx_cdc_source_source_payload_data; -assign tx_converter_sink_payload_last_be = tx_cdc_source_source_payload_last_be; -assign tx_converter_sink_payload_error = tx_cdc_source_source_payload_error; -assign tx_last_be_sink_valid = tx_converter_source_valid; -assign tx_converter_source_ready = tx_last_be_sink_ready; -assign tx_last_be_sink_first = tx_converter_source_first; -assign tx_last_be_sink_last = tx_converter_source_last; -assign tx_last_be_sink_payload_data = tx_converter_source_payload_data; -assign tx_last_be_sink_payload_last_be = tx_converter_source_payload_last_be; -assign tx_last_be_sink_payload_error = tx_converter_source_payload_error; -assign padding_inserter_sink_valid = tx_last_be_source_valid; -assign tx_last_be_source_ready = padding_inserter_sink_ready; -assign padding_inserter_sink_first = tx_last_be_source_first; -assign padding_inserter_sink_last = tx_last_be_source_last; -assign padding_inserter_sink_payload_data = tx_last_be_source_payload_data; -assign padding_inserter_sink_payload_last_be = tx_last_be_source_payload_last_be; -assign padding_inserter_sink_payload_error = tx_last_be_source_payload_error; -assign crc32_inserter_sink_valid = padding_inserter_source_valid; -assign padding_inserter_source_ready = crc32_inserter_sink_ready; -assign crc32_inserter_sink_first = padding_inserter_source_first; -assign crc32_inserter_sink_last = padding_inserter_source_last; -assign crc32_inserter_sink_payload_data = padding_inserter_source_payload_data; -assign crc32_inserter_sink_payload_last_be = padding_inserter_source_payload_last_be; -assign crc32_inserter_sink_payload_error = padding_inserter_source_payload_error; -assign preamble_inserter_sink_valid = liteethmaccrc32inserter_source_valid; -assign liteethmaccrc32inserter_source_ready = preamble_inserter_sink_ready; -assign preamble_inserter_sink_first = liteethmaccrc32inserter_source_first; -assign preamble_inserter_sink_last = liteethmaccrc32inserter_source_last; -assign preamble_inserter_sink_payload_data = liteethmaccrc32inserter_source_payload_data; -assign preamble_inserter_sink_payload_last_be = liteethmaccrc32inserter_source_payload_last_be; -assign preamble_inserter_sink_payload_error = liteethmaccrc32inserter_source_payload_error; -assign tx_gap_inserter_sink_valid = preamble_inserter_source_valid; -assign preamble_inserter_source_ready = tx_gap_inserter_sink_ready; -assign tx_gap_inserter_sink_first = preamble_inserter_source_first; -assign tx_gap_inserter_sink_last = preamble_inserter_source_last; -assign tx_gap_inserter_sink_payload_data = preamble_inserter_source_payload_data; -assign tx_gap_inserter_sink_payload_last_be = preamble_inserter_source_payload_last_be; -assign tx_gap_inserter_sink_payload_error = preamble_inserter_source_payload_error; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0 = tx_gap_inserter_source_valid; -assign tx_gap_inserter_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first0 = tx_gap_inserter_source_first; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last0 = tx_gap_inserter_source_last; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0 = tx_gap_inserter_source_payload_data; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0 = tx_gap_inserter_source_payload_last_be; -assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0 = tx_gap_inserter_source_payload_error; -assign preamble_checker_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid0; -assign maccore_ethphy_liteethphygmiimiirx_source_source_ready0 = preamble_checker_sink_ready; -assign preamble_checker_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first0; -assign preamble_checker_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last0; -assign preamble_checker_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0; -assign preamble_checker_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0; -assign preamble_checker_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0; -assign crc32_checker_sink_valid = preamble_checker_source_valid; -assign preamble_checker_source_ready = crc32_checker_sink_ready; -assign crc32_checker_sink_first = preamble_checker_source_first; -assign crc32_checker_sink_last = preamble_checker_source_last; -assign crc32_checker_sink_payload_data = preamble_checker_source_payload_data; -assign crc32_checker_sink_payload_last_be = preamble_checker_source_payload_last_be; -assign crc32_checker_sink_payload_error = preamble_checker_source_payload_error; -assign padding_checker_sink_valid = liteethmaccrc32checker_source_source_valid; -assign liteethmaccrc32checker_source_source_ready = padding_checker_sink_ready; -assign padding_checker_sink_first = liteethmaccrc32checker_source_source_first; -assign padding_checker_sink_last = liteethmaccrc32checker_source_source_last; -assign padding_checker_sink_payload_data = liteethmaccrc32checker_source_source_payload_data; -assign padding_checker_sink_payload_last_be = liteethmaccrc32checker_source_source_payload_last_be; -assign padding_checker_sink_payload_error = liteethmaccrc32checker_source_source_payload_error; -assign rx_last_be_sink_valid = padding_checker_source_valid; -assign padding_checker_source_ready = rx_last_be_sink_ready; -assign rx_last_be_sink_first = padding_checker_source_first; -assign rx_last_be_sink_last = padding_checker_source_last; -assign rx_last_be_sink_payload_data = padding_checker_source_payload_data; -assign rx_last_be_sink_payload_last_be = padding_checker_source_payload_last_be; -assign rx_last_be_sink_payload_error = padding_checker_source_payload_error; -assign rx_converter_sink_valid = rx_last_be_source_valid; -assign rx_last_be_source_ready = rx_converter_sink_ready; -assign rx_converter_sink_first = rx_last_be_source_first; -assign rx_converter_sink_last = rx_last_be_source_last; -assign rx_converter_sink_payload_data = rx_last_be_source_payload_data; -assign rx_converter_sink_payload_last_be = rx_last_be_source_payload_last_be; -assign rx_converter_sink_payload_error = rx_last_be_source_payload_error; -assign rx_cdc_sink_sink_valid = rx_converter_source_valid; -assign rx_converter_source_ready = rx_cdc_sink_sink_ready; -assign rx_cdc_sink_sink_first = rx_converter_source_first; -assign rx_cdc_sink_sink_last = rx_converter_source_last; -assign rx_cdc_sink_sink_payload_data = rx_converter_source_payload_data; -assign rx_cdc_sink_sink_payload_last_be = rx_converter_source_payload_last_be; -assign rx_cdc_sink_sink_payload_error = rx_converter_source_payload_error; -assign writer_sink_sink_valid = sink_valid; -assign sink_ready = writer_sink_sink_ready; -assign writer_sink_sink_first = sink_first; -assign writer_sink_sink_last = sink_last; -assign writer_sink_sink_payload_data = sink_payload_data; -assign writer_sink_sink_payload_last_be = sink_payload_last_be; -assign writer_sink_sink_payload_error = sink_payload_error; -assign source_valid = reader_source_source_valid; -assign reader_source_source_ready = source_ready; -assign source_first = reader_source_source_first; -assign source_last = reader_source_source_last; -assign source_payload_data = reader_source_source_payload_data; -assign source_payload_last_be = reader_source_source_payload_last_be; -assign source_payload_error = reader_source_source_payload_error; -always @(*) begin - writer_inc <= 3'd0; - case (writer_sink_sink_payload_last_be) - 1'd1: begin - writer_inc <= 1'd1; - end - 2'd2: begin - writer_inc <= 2'd2; - end - 3'd4: begin - writer_inc <= 2'd3; - end - default: begin - writer_inc <= 3'd4; - end - endcase -end -assign writer_stat_fifo_sink_payload_slot = writer_slot; -assign writer_stat_fifo_sink_payload_length = writer_counter; -assign writer_stat_fifo_source_ready = writer_available_clear; -assign writer_available_trigger = writer_stat_fifo_source_valid; -assign writer_slot_status = writer_stat_fifo_source_payload_slot; -assign writer_length_status = writer_stat_fifo_source_payload_length; -always @(*) begin - writer_memory1_adr <= 9'd0; - writer_memory1_we <= 1'd0; - writer_memory0_adr <= 9'd0; - writer_memory1_dat_w <= 32'd0; - writer_memory0_we <= 1'd0; - writer_memory0_dat_w <= 32'd0; - case (writer_slot) - 1'd0: begin - writer_memory0_adr <= writer_counter[31:2]; - writer_memory0_dat_w <= writer_sink_sink_payload_data; - if ((writer_sink_sink_valid & writer_ongoing)) begin - writer_memory0_we <= 4'd15; - end - end - 1'd1: begin - writer_memory1_adr <= writer_counter[31:2]; - writer_memory1_dat_w <= writer_sink_sink_payload_data; - if ((writer_sink_sink_valid & writer_ongoing)) begin - writer_memory1_we <= 4'd15; - end - end - endcase -end -assign writer_available0 = writer_available_status; -assign writer_available1 = writer_available_pending; -always @(*) begin - writer_available_clear <= 1'd0; - if ((writer_pending_re & writer_pending_r)) begin - writer_available_clear <= 1'd1; - end -end -assign writer_irq = (writer_pending_status & writer_enable_storage); -assign writer_available_status = writer_available_trigger; -assign writer_available_pending = writer_available_trigger; -assign writer_stat_fifo_syncfifo_din = {writer_stat_fifo_fifo_in_last, writer_stat_fifo_fifo_in_first, writer_stat_fifo_fifo_in_payload_length, writer_stat_fifo_fifo_in_payload_slot}; -assign {writer_stat_fifo_fifo_out_last, writer_stat_fifo_fifo_out_first, writer_stat_fifo_fifo_out_payload_length, writer_stat_fifo_fifo_out_payload_slot} = writer_stat_fifo_syncfifo_dout; -assign writer_stat_fifo_sink_ready = writer_stat_fifo_syncfifo_writable; -assign writer_stat_fifo_syncfifo_we = writer_stat_fifo_sink_valid; -assign writer_stat_fifo_fifo_in_first = writer_stat_fifo_sink_first; -assign writer_stat_fifo_fifo_in_last = writer_stat_fifo_sink_last; -assign writer_stat_fifo_fifo_in_payload_slot = writer_stat_fifo_sink_payload_slot; -assign writer_stat_fifo_fifo_in_payload_length = writer_stat_fifo_sink_payload_length; -assign writer_stat_fifo_source_valid = writer_stat_fifo_syncfifo_readable; -assign writer_stat_fifo_source_first = writer_stat_fifo_fifo_out_first; -assign writer_stat_fifo_source_last = writer_stat_fifo_fifo_out_last; -assign writer_stat_fifo_source_payload_slot = writer_stat_fifo_fifo_out_payload_slot; -assign writer_stat_fifo_source_payload_length = writer_stat_fifo_fifo_out_payload_length; -assign writer_stat_fifo_syncfifo_re = writer_stat_fifo_source_ready; -always @(*) begin - writer_stat_fifo_wrport_adr <= 1'd0; - if (writer_stat_fifo_replace) begin - writer_stat_fifo_wrport_adr <= (writer_stat_fifo_produce - 1'd1); - end else begin - writer_stat_fifo_wrport_adr <= writer_stat_fifo_produce; - end -end -assign writer_stat_fifo_wrport_dat_w = writer_stat_fifo_syncfifo_din; -assign writer_stat_fifo_wrport_we = (writer_stat_fifo_syncfifo_we & (writer_stat_fifo_syncfifo_writable | writer_stat_fifo_replace)); -assign writer_stat_fifo_do_read = (writer_stat_fifo_syncfifo_readable & writer_stat_fifo_syncfifo_re); -assign writer_stat_fifo_rdport_adr = writer_stat_fifo_consume; -assign writer_stat_fifo_syncfifo_dout = writer_stat_fifo_rdport_dat_r; -assign writer_stat_fifo_syncfifo_writable = (writer_stat_fifo_level != 2'd2); -assign writer_stat_fifo_syncfifo_readable = (writer_stat_fifo_level != 1'd0); -always @(*) begin - subfragments_liteethmacsramwriter_next_state <= 3'd0; - writer_counter_t_next_value <= 32'd0; - writer_counter_t_next_value_ce <= 1'd0; - writer_errors_status_f_next_value <= 32'd0; - writer_errors_status_f_next_value_ce <= 1'd0; - writer_slot_ce <= 1'd0; - writer_start <= 1'd0; - writer_ongoing <= 1'd0; - writer_stat_fifo_sink_valid <= 1'd0; - subfragments_liteethmacsramwriter_next_state <= subfragments_liteethmacsramwriter_state; - case (subfragments_liteethmacsramwriter_state) - 1'd1: begin - if (writer_sink_sink_valid) begin - if ((writer_counter == 11'd1530)) begin - subfragments_liteethmacsramwriter_next_state <= 2'd3; - end else begin - writer_counter_t_next_value <= (writer_counter + writer_inc); - writer_counter_t_next_value_ce <= 1'd1; - writer_ongoing <= 1'd1; - end - if (writer_sink_sink_last) begin - if (((writer_sink_sink_payload_error & writer_sink_sink_payload_last_be) != 1'd0)) begin - subfragments_liteethmacsramwriter_next_state <= 2'd2; - end else begin - subfragments_liteethmacsramwriter_next_state <= 3'd4; - end - end - end - end - 2'd2: begin - writer_counter_t_next_value <= 1'd0; - writer_counter_t_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd0; - end - 2'd3: begin - if ((writer_sink_sink_valid & writer_sink_sink_last)) begin - subfragments_liteethmacsramwriter_next_state <= 3'd4; - end - end - 3'd4: begin - writer_counter_t_next_value <= 1'd0; - writer_counter_t_next_value_ce <= 1'd1; - writer_slot_ce <= 1'd1; - writer_stat_fifo_sink_valid <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd0; - end - default: begin - if (writer_sink_sink_valid) begin - if (writer_stat_fifo_sink_ready) begin - writer_start <= 1'd1; - writer_ongoing <= 1'd1; - writer_counter_t_next_value <= (writer_counter + writer_inc); - writer_counter_t_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 1'd1; - end else begin - writer_errors_status_f_next_value <= (writer_errors_status + 1'd1); - writer_errors_status_f_next_value_ce <= 1'd1; - subfragments_liteethmacsramwriter_next_state <= 2'd3; - end - end - end - endcase -end -assign reader_cmd_fifo_sink_valid = reader_start_start_re; -assign reader_cmd_fifo_sink_payload_slot = reader_slot_storage; -assign reader_cmd_fifo_sink_payload_length = reader_length_storage; -assign reader_ready_status = reader_cmd_fifo_sink_ready; -assign reader_level_status = reader_cmd_fifo_level; -always @(*) begin - reader_source_source_payload_last_be <= 4'd0; - if (reader_source_source_last) begin - case (reader_cmd_fifo_source_payload_length[1:0]) - 1'd0: begin - reader_source_source_payload_last_be <= 4'd8; - end - 1'd1: begin - reader_source_source_payload_last_be <= 1'd1; - end - 2'd2: begin - reader_source_source_payload_last_be <= 2'd2; - end - 2'd3: begin - reader_source_source_payload_last_be <= 3'd4; - end - endcase - end -end -assign reader_memory0_adr = reader_read_address[10:2]; -assign reader_memory1_adr = reader_read_address[10:2]; -always @(*) begin - reader_source_source_payload_data <= 32'd0; - case (reader_cmd_fifo_source_payload_slot) - 1'd0: begin - reader_source_source_payload_data <= reader_memory0_dat_r; - end - 1'd1: begin - reader_source_source_payload_data <= reader_memory1_dat_r; - end - endcase -end -assign reader_event00 = reader_eventsourcepulse_status; -assign reader_event01 = reader_eventsourcepulse_pending; -always @(*) begin - reader_eventsourcepulse_clear <= 1'd0; - if ((reader_pending_re & reader_pending_r)) begin - reader_eventsourcepulse_clear <= 1'd1; - end -end -assign reader_irq = (reader_pending_status & reader_enable_storage); -assign reader_eventsourcepulse_status = 1'd0; -assign reader_cmd_fifo_syncfifo_din = {reader_cmd_fifo_fifo_in_last, reader_cmd_fifo_fifo_in_first, reader_cmd_fifo_fifo_in_payload_length, reader_cmd_fifo_fifo_in_payload_slot}; -assign {reader_cmd_fifo_fifo_out_last, reader_cmd_fifo_fifo_out_first, reader_cmd_fifo_fifo_out_payload_length, reader_cmd_fifo_fifo_out_payload_slot} = reader_cmd_fifo_syncfifo_dout; -assign reader_cmd_fifo_sink_ready = reader_cmd_fifo_syncfifo_writable; -assign reader_cmd_fifo_syncfifo_we = reader_cmd_fifo_sink_valid; -assign reader_cmd_fifo_fifo_in_first = reader_cmd_fifo_sink_first; -assign reader_cmd_fifo_fifo_in_last = reader_cmd_fifo_sink_last; -assign reader_cmd_fifo_fifo_in_payload_slot = reader_cmd_fifo_sink_payload_slot; -assign reader_cmd_fifo_fifo_in_payload_length = reader_cmd_fifo_sink_payload_length; -assign reader_cmd_fifo_source_valid = reader_cmd_fifo_syncfifo_readable; -assign reader_cmd_fifo_source_first = reader_cmd_fifo_fifo_out_first; -assign reader_cmd_fifo_source_last = reader_cmd_fifo_fifo_out_last; -assign reader_cmd_fifo_source_payload_slot = reader_cmd_fifo_fifo_out_payload_slot; -assign reader_cmd_fifo_source_payload_length = reader_cmd_fifo_fifo_out_payload_length; -assign reader_cmd_fifo_syncfifo_re = reader_cmd_fifo_source_ready; -always @(*) begin - reader_cmd_fifo_wrport_adr <= 1'd0; - if (reader_cmd_fifo_replace) begin - reader_cmd_fifo_wrport_adr <= (reader_cmd_fifo_produce - 1'd1); - end else begin - reader_cmd_fifo_wrport_adr <= reader_cmd_fifo_produce; - end -end -assign reader_cmd_fifo_wrport_dat_w = reader_cmd_fifo_syncfifo_din; -assign reader_cmd_fifo_wrport_we = (reader_cmd_fifo_syncfifo_we & (reader_cmd_fifo_syncfifo_writable | reader_cmd_fifo_replace)); -assign reader_cmd_fifo_do_read = (reader_cmd_fifo_syncfifo_readable & reader_cmd_fifo_syncfifo_re); -assign reader_cmd_fifo_rdport_adr = reader_cmd_fifo_consume; -assign reader_cmd_fifo_syncfifo_dout = reader_cmd_fifo_rdport_dat_r; -assign reader_cmd_fifo_syncfifo_writable = (reader_cmd_fifo_level != 2'd2); -assign reader_cmd_fifo_syncfifo_readable = (reader_cmd_fifo_level != 1'd0); -always @(*) begin - reader_cmd_fifo_source_ready <= 1'd0; - reader_eventsourcepulse_trigger <= 1'd0; - subfragments_liteethmacsramreader_next_state <= 2'd0; - reader_counter_next_value <= 11'd0; - reader_counter_next_value_ce <= 1'd0; - reader_source_source_valid <= 1'd0; - reader_start <= 1'd0; - reader_source_source_last <= 1'd0; - reader_read_address <= 11'd0; - subfragments_liteethmacsramreader_next_state <= subfragments_liteethmacsramreader_state; - case (subfragments_liteethmacsramreader_state) - 1'd1: begin - reader_source_source_valid <= 1'd1; - reader_source_source_last <= (reader_counter >= (reader_cmd_fifo_source_payload_length - 3'd4)); - reader_read_address <= reader_counter; - if (reader_source_source_ready) begin - reader_read_address <= (reader_counter + 3'd4); - reader_counter_next_value <= (reader_counter + 3'd4); - reader_counter_next_value_ce <= 1'd1; - if (reader_source_source_last) begin - subfragments_liteethmacsramreader_next_state <= 2'd2; - end - end - end - 2'd2: begin - reader_eventsourcepulse_trigger <= 1'd1; - reader_cmd_fifo_source_ready <= 1'd1; - subfragments_liteethmacsramreader_next_state <= 1'd0; - end - default: begin - reader_counter_next_value <= 1'd0; - reader_counter_next_value_ce <= 1'd1; - if (reader_cmd_fifo_source_valid) begin - reader_start <= 1'd1; - subfragments_liteethmacsramreader_next_state <= 1'd1; - end - end - endcase -end -assign ev_irq = (writer_irq | reader_irq); -assign sram0_adr0 = sram0_bus_adr0[8:0]; -assign sram0_bus_dat_r0 = sram0_dat_r0; -assign sram1_adr0 = sram1_bus_adr0[8:0]; -assign sram1_bus_dat_r0 = sram1_dat_r0; -always @(*) begin - sram0_we <= 4'd0; - sram0_we[0] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[0]); - sram0_we[1] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[1]); - sram0_we[2] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[2]); - sram0_we[3] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[3]); -end -assign sram0_adr1 = sram0_bus_adr1[8:0]; -assign sram0_bus_dat_r1 = sram0_dat_r1; -assign sram0_dat_w = sram0_bus_dat_w1; -always @(*) begin - sram1_we <= 4'd0; - sram1_we[0] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[0]); - sram1_we[1] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[1]); - sram1_we[2] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[2]); - sram1_we[3] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[3]); -end -assign sram1_adr1 = sram1_bus_adr1[8:0]; -assign sram1_bus_dat_r1 = sram1_dat_r1; -assign sram1_dat_w = sram1_bus_dat_w1; -always @(*) begin - slave_sel <= 4'd0; - slave_sel[0] <= (bus_adr[10:9] == 1'd0); - slave_sel[1] <= (bus_adr[10:9] == 1'd1); - slave_sel[2] <= (bus_adr[10:9] == 2'd2); - slave_sel[3] <= (bus_adr[10:9] == 2'd3); -end -assign sram0_bus_adr0 = bus_adr; -assign sram0_bus_dat_w0 = bus_dat_w; -assign sram0_bus_sel0 = bus_sel; -assign sram0_bus_stb0 = bus_stb; -assign sram0_bus_we0 = bus_we; -assign sram0_bus_cti0 = bus_cti; -assign sram0_bus_bte0 = bus_bte; -assign sram1_bus_adr0 = bus_adr; -assign sram1_bus_dat_w0 = bus_dat_w; -assign sram1_bus_sel0 = bus_sel; -assign sram1_bus_stb0 = bus_stb; -assign sram1_bus_we0 = bus_we; -assign sram1_bus_cti0 = bus_cti; -assign sram1_bus_bte0 = bus_bte; -assign sram0_bus_adr1 = bus_adr; -assign sram0_bus_dat_w1 = bus_dat_w; -assign sram0_bus_sel1 = bus_sel; -assign sram0_bus_stb1 = bus_stb; -assign sram0_bus_we1 = bus_we; -assign sram0_bus_cti1 = bus_cti; -assign sram0_bus_bte1 = bus_bte; -assign sram1_bus_adr1 = bus_adr; -assign sram1_bus_dat_w1 = bus_dat_w; -assign sram1_bus_sel1 = bus_sel; -assign sram1_bus_stb1 = bus_stb; -assign sram1_bus_we1 = bus_we; -assign sram1_bus_cti1 = bus_cti; -assign sram1_bus_bte1 = bus_bte; -assign sram0_bus_cyc0 = (bus_cyc & slave_sel[0]); -assign sram1_bus_cyc0 = (bus_cyc & slave_sel[1]); -assign sram0_bus_cyc1 = (bus_cyc & slave_sel[2]); -assign sram1_bus_cyc1 = (bus_cyc & slave_sel[3]); -assign bus_ack = (((sram0_bus_ack0 | sram1_bus_ack0) | sram0_bus_ack1) | sram1_bus_ack1); -assign bus_err = (((sram0_bus_err0 | sram1_bus_err0) | sram0_bus_err1) | sram1_bus_err1); -assign bus_dat_r = (((({32{slave_sel_r[0]}} & sram0_bus_dat_r0) | ({32{slave_sel_r[1]}} & sram1_bus_dat_r0)) | ({32{slave_sel_r[2]}} & sram0_bus_dat_r1)) | ({32{slave_sel_r[3]}} & sram1_bus_dat_r1)); -always @(*) begin - maccore_maccore_we <= 1'd0; - maccore_maccore_dat_w <= 32'd0; - maccore_maccore_wishbone_ack <= 1'd0; - maccore_next_state <= 1'd0; - maccore_maccore_wishbone_dat_r <= 32'd0; - maccore_maccore_adr <= 14'd0; - maccore_next_state <= maccore_state; - case (maccore_state) - 1'd1: begin - maccore_maccore_wishbone_ack <= 1'd1; - maccore_maccore_wishbone_dat_r <= maccore_maccore_dat_r; - maccore_next_state <= 1'd0; - end - default: begin - maccore_maccore_dat_w <= maccore_maccore_wishbone_dat_w; - if ((maccore_maccore_wishbone_cyc & maccore_maccore_wishbone_stb)) begin - maccore_maccore_adr <= maccore_maccore_wishbone_adr; - maccore_maccore_we <= (maccore_maccore_wishbone_we & (maccore_maccore_wishbone_sel != 1'd0)); - maccore_next_state <= 1'd1; - end - end - endcase -end -assign maccore_shared_adr = array_muxed0; -assign maccore_shared_dat_w = array_muxed1; -assign maccore_shared_sel = array_muxed2; -assign maccore_shared_cyc = array_muxed3; -assign maccore_shared_stb = array_muxed4; -assign maccore_shared_we = array_muxed5; -assign maccore_shared_cti = array_muxed6; -assign maccore_shared_bte = array_muxed7; -assign wb_bus_dat_r = maccore_shared_dat_r; -assign wb_bus_ack = (maccore_shared_ack & (maccore_grant == 1'd0)); -assign wb_bus_err = (maccore_shared_err & (maccore_grant == 1'd0)); -assign maccore_request = {wb_bus_cyc}; -assign maccore_grant = 1'd0; -always @(*) begin - maccore_slave_sel <= 2'd0; - maccore_slave_sel[0] <= (maccore_shared_adr[29:11] == 4'd8); - maccore_slave_sel[1] <= (maccore_shared_adr[29:14] == 1'd0); -end -assign bus_adr = maccore_shared_adr; -assign bus_dat_w = maccore_shared_dat_w; -assign bus_sel = maccore_shared_sel; -assign bus_stb = maccore_shared_stb; -assign bus_we = maccore_shared_we; -assign bus_cti = maccore_shared_cti; -assign bus_bte = maccore_shared_bte; -assign maccore_maccore_wishbone_adr = maccore_shared_adr; -assign maccore_maccore_wishbone_dat_w = maccore_shared_dat_w; -assign maccore_maccore_wishbone_sel = maccore_shared_sel; -assign maccore_maccore_wishbone_stb = maccore_shared_stb; -assign maccore_maccore_wishbone_we = maccore_shared_we; -assign maccore_maccore_wishbone_cti = maccore_shared_cti; -assign maccore_maccore_wishbone_bte = maccore_shared_bte; -assign bus_cyc = (maccore_shared_cyc & maccore_slave_sel[0]); -assign maccore_maccore_wishbone_cyc = (maccore_shared_cyc & maccore_slave_sel[1]); -assign maccore_shared_err = (bus_err | maccore_maccore_wishbone_err); -assign maccore_wait = ((maccore_shared_stb & maccore_shared_cyc) & (~maccore_shared_ack)); -always @(*) begin - maccore_error <= 1'd0; - maccore_shared_dat_r <= 32'd0; - maccore_shared_ack <= 1'd0; - maccore_shared_ack <= (bus_ack | maccore_maccore_wishbone_ack); - maccore_shared_dat_r <= (({32{maccore_slave_sel_r[0]}} & bus_dat_r) | ({32{maccore_slave_sel_r[1]}} & maccore_maccore_wishbone_dat_r)); - if (maccore_done) begin - maccore_shared_dat_r <= 32'd4294967295; - maccore_shared_ack <= 1'd1; - maccore_error <= 1'd1; - end -end -assign maccore_done = (maccore_count == 1'd0); -assign maccore_csrbank0_sel = (maccore_interface0_bank_bus_adr[13:9] == 1'd0); -assign maccore_csrbank0_reset0_r = maccore_interface0_bank_bus_dat_w[1:0]; -always @(*) begin - maccore_csrbank0_reset0_re <= 1'd0; - maccore_csrbank0_reset0_we <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank0_reset0_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_reset0_we <= (~maccore_interface0_bank_bus_we); - end -end -assign maccore_csrbank0_scratch0_r = maccore_interface0_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank0_scratch0_re <= 1'd0; - maccore_csrbank0_scratch0_we <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank0_scratch0_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_scratch0_we <= (~maccore_interface0_bank_bus_we); - end -end -assign maccore_csrbank0_bus_errors_r = maccore_interface0_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank0_bus_errors_we <= 1'd0; - maccore_csrbank0_bus_errors_re <= 1'd0; - if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank0_bus_errors_re <= maccore_interface0_bank_bus_we; - maccore_csrbank0_bus_errors_we <= (~maccore_interface0_bank_bus_we); - end -end -always @(*) begin - maccore_maccore_soc_rst <= 1'd0; - if (maccore_maccore_reset_re) begin - maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0]; - end -end -assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1]; -assign maccore_csrbank0_reset0_w = maccore_maccore_reset_storage[1:0]; -assign maccore_csrbank0_scratch0_w = maccore_maccore_scratch_storage[31:0]; -assign maccore_csrbank0_bus_errors_w = maccore_maccore_bus_errors_status[31:0]; -assign maccore_maccore_bus_errors_we = maccore_csrbank0_bus_errors_we; -assign maccore_csrbank1_sel = (maccore_interface1_bank_bus_adr[13:9] == 2'd2); -assign maccore_csrbank1_sram_writer_slot_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_slot_we <= 1'd0; - maccore_csrbank1_sram_writer_slot_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank1_sram_writer_slot_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_slot_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_length_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_sram_writer_length_we <= 1'd0; - maccore_csrbank1_sram_writer_length_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank1_sram_writer_length_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_length_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_sram_writer_errors_re <= 1'd0; - maccore_csrbank1_sram_writer_errors_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank1_sram_writer_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_status_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_status_re <= 1'd0; - maccore_csrbank1_sram_writer_ev_status_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd3))) begin - maccore_csrbank1_sram_writer_ev_status_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_status_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_pending_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_pending_we <= 1'd0; - maccore_csrbank1_sram_writer_ev_pending_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd4))) begin - maccore_csrbank1_sram_writer_ev_pending_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_pending_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_writer_ev_enable0_we <= 1'd0; - maccore_csrbank1_sram_writer_ev_enable0_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd5))) begin - maccore_csrbank1_sram_writer_ev_enable0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_writer_ev_enable0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign reader_start_start_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - reader_start_start_re <= 1'd0; - reader_start_start_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd6))) begin - reader_start_start_re <= maccore_interface1_bank_bus_we; - reader_start_start_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ready_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ready_re <= 1'd0; - maccore_csrbank1_sram_reader_ready_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd7))) begin - maccore_csrbank1_sram_reader_ready_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ready_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_level_r = maccore_interface1_bank_bus_dat_w[1:0]; -always @(*) begin - maccore_csrbank1_sram_reader_level_we <= 1'd0; - maccore_csrbank1_sram_reader_level_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd8))) begin - maccore_csrbank1_sram_reader_level_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_level_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_slot0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_slot0_we <= 1'd0; - maccore_csrbank1_sram_reader_slot0_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd9))) begin - maccore_csrbank1_sram_reader_slot0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_slot0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_length0_r = maccore_interface1_bank_bus_dat_w[10:0]; -always @(*) begin - maccore_csrbank1_sram_reader_length0_re <= 1'd0; - maccore_csrbank1_sram_reader_length0_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd10))) begin - maccore_csrbank1_sram_reader_length0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_length0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_status_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_status_we <= 1'd0; - maccore_csrbank1_sram_reader_ev_status_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd11))) begin - maccore_csrbank1_sram_reader_ev_status_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_status_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_pending_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_pending_we <= 1'd0; - maccore_csrbank1_sram_reader_ev_pending_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd12))) begin - maccore_csrbank1_sram_reader_ev_pending_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_pending_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_reader_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_sram_reader_ev_enable0_re <= 1'd0; - maccore_csrbank1_sram_reader_ev_enable0_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd13))) begin - maccore_csrbank1_sram_reader_ev_enable0_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_sram_reader_ev_enable0_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_preamble_crc_r = maccore_interface1_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank1_preamble_crc_we <= 1'd0; - maccore_csrbank1_preamble_crc_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd14))) begin - maccore_csrbank1_preamble_crc_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_preamble_crc_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_preamble_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_preamble_errors_we <= 1'd0; - maccore_csrbank1_preamble_errors_re <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd15))) begin - maccore_csrbank1_preamble_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_preamble_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_crc_errors_r = maccore_interface1_bank_bus_dat_w[31:0]; -always @(*) begin - maccore_csrbank1_crc_errors_re <= 1'd0; - maccore_csrbank1_crc_errors_we <= 1'd0; - if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 5'd16))) begin - maccore_csrbank1_crc_errors_re <= maccore_interface1_bank_bus_we; - maccore_csrbank1_crc_errors_we <= (~maccore_interface1_bank_bus_we); - end -end -assign maccore_csrbank1_sram_writer_slot_w = writer_slot_status; -assign writer_slot_we = maccore_csrbank1_sram_writer_slot_we; -assign maccore_csrbank1_sram_writer_length_w = writer_length_status[31:0]; -assign writer_length_we = maccore_csrbank1_sram_writer_length_we; -assign maccore_csrbank1_sram_writer_errors_w = writer_errors_status[31:0]; -assign writer_errors_we = maccore_csrbank1_sram_writer_errors_we; -assign writer_status_status = writer_available0; -assign maccore_csrbank1_sram_writer_ev_status_w = writer_status_status; -assign writer_status_we = maccore_csrbank1_sram_writer_ev_status_we; -assign writer_pending_status = writer_available1; -assign maccore_csrbank1_sram_writer_ev_pending_w = writer_pending_status; -assign writer_pending_we = maccore_csrbank1_sram_writer_ev_pending_we; -assign writer_available2 = writer_enable_storage; -assign maccore_csrbank1_sram_writer_ev_enable0_w = writer_enable_storage; -assign maccore_csrbank1_sram_reader_ready_w = reader_ready_status; -assign reader_ready_we = maccore_csrbank1_sram_reader_ready_we; -assign maccore_csrbank1_sram_reader_level_w = reader_level_status[1:0]; -assign reader_level_we = maccore_csrbank1_sram_reader_level_we; -assign maccore_csrbank1_sram_reader_slot0_w = reader_slot_storage; -assign maccore_csrbank1_sram_reader_length0_w = reader_length_storage[10:0]; -assign reader_status_status = reader_event00; -assign maccore_csrbank1_sram_reader_ev_status_w = reader_status_status; -assign reader_status_we = maccore_csrbank1_sram_reader_ev_status_we; -assign reader_pending_status = reader_event01; -assign maccore_csrbank1_sram_reader_ev_pending_w = reader_pending_status; -assign reader_pending_we = maccore_csrbank1_sram_reader_ev_pending_we; -assign reader_event02 = reader_enable_storage; -assign maccore_csrbank1_sram_reader_ev_enable0_w = reader_enable_storage; -assign maccore_csrbank1_preamble_crc_w = preamble_crc_status; -assign preamble_crc_we = maccore_csrbank1_preamble_crc_we; -assign maccore_csrbank1_preamble_errors_w = preamble_errors_status[31:0]; -assign preamble_errors_we = maccore_csrbank1_preamble_errors_we; -assign maccore_csrbank1_crc_errors_w = crc_errors_status[31:0]; -assign crc_errors_we = maccore_csrbank1_crc_errors_we; -assign maccore_csrbank2_sel = (maccore_interface2_bank_bus_adr[13:9] == 1'd1); -assign maccore_csrbank2_mode_detection_mode_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_mode_detection_mode_re <= 1'd0; - maccore_csrbank2_mode_detection_mode_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd0))) begin - maccore_csrbank2_mode_detection_mode_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mode_detection_mode_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_crg_reset0_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_crg_reset0_re <= 1'd0; - maccore_csrbank2_crg_reset0_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd1))) begin - maccore_csrbank2_crg_reset0_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_crg_reset0_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mdio_w0_r = maccore_interface2_bank_bus_dat_w[2:0]; -always @(*) begin - maccore_csrbank2_mdio_w0_we <= 1'd0; - maccore_csrbank2_mdio_w0_re <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd2))) begin - maccore_csrbank2_mdio_w0_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mdio_w0_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mdio_r_r = maccore_interface2_bank_bus_dat_w[0]; -always @(*) begin - maccore_csrbank2_mdio_r_re <= 1'd0; - maccore_csrbank2_mdio_r_we <= 1'd0; - if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd3))) begin - maccore_csrbank2_mdio_r_re <= maccore_interface2_bank_bus_we; - maccore_csrbank2_mdio_r_we <= (~maccore_interface2_bank_bus_we); - end -end -assign maccore_csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status; -assign maccore_ethphy_mode_we = maccore_csrbank2_mode_detection_mode_we; -assign maccore_csrbank2_crg_reset0_w = maccore_ethphy_reset_storage; -assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0]; -assign maccore_ethphy_oe = maccore_ethphy__w_storage[1]; -assign maccore_ethphy_w = maccore_ethphy__w_storage[2]; -assign maccore_csrbank2_mdio_w0_w = maccore_ethphy__w_storage[2:0]; -assign maccore_csrbank2_mdio_r_w = maccore_ethphy__r_status; -assign maccore_ethphy__r_we = maccore_csrbank2_mdio_r_we; -assign maccore_csr_interconnect_adr = maccore_maccore_adr; -assign maccore_csr_interconnect_we = maccore_maccore_we; -assign maccore_csr_interconnect_dat_w = maccore_maccore_dat_w; -assign maccore_maccore_dat_r = maccore_csr_interconnect_dat_r; -assign maccore_interface0_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface1_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface2_bank_bus_adr = maccore_csr_interconnect_adr; -assign maccore_interface0_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface1_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface2_bank_bus_we = maccore_csr_interconnect_we; -assign maccore_interface0_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_interface1_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_interface2_bank_bus_dat_w = maccore_csr_interconnect_dat_w; -assign maccore_csr_interconnect_dat_r = ((maccore_interface0_bank_bus_dat_r | maccore_interface1_bank_bus_dat_r) | maccore_interface2_bank_bus_dat_r); -always @(*) begin - array_muxed0 <= 30'd0; - case (maccore_grant) - default: begin - array_muxed0 <= wb_bus_adr; - end - endcase -end -always @(*) begin - array_muxed1 <= 32'd0; - case (maccore_grant) - default: begin - array_muxed1 <= wb_bus_dat_w; - end - endcase -end -always @(*) begin - array_muxed2 <= 4'd0; - case (maccore_grant) - default: begin - array_muxed2 <= wb_bus_sel; - end - endcase -end -always @(*) begin - array_muxed3 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed3 <= wb_bus_cyc; - end - endcase -end -always @(*) begin - array_muxed4 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed4 <= wb_bus_stb; - end - endcase -end -always @(*) begin - array_muxed5 <= 1'd0; - case (maccore_grant) - default: begin - array_muxed5 <= wb_bus_we; - end - endcase -end -always @(*) begin - array_muxed6 <= 3'd0; - case (maccore_grant) - default: begin - array_muxed6 <= wb_bus_cti; - end - endcase -end -always @(*) begin - array_muxed7 <= 2'd0; - case (maccore_grant) - default: begin - array_muxed7 <= wb_bus_bte; - end - endcase -end -assign maccore_ethphy_toggle_o = xilinxmultiregimpl0_regs1; -always @(*) begin - maccore_ethphy__r_status <= 1'd0; - maccore_ethphy__r_status <= maccore_ethphy_r; - maccore_ethphy__r_status <= xilinxmultiregimpl1_regs1; -end -assign ps_preamble_error_toggle_o = xilinxmultiregimpl2_regs1; -assign ps_crc_error_toggle_o = xilinxmultiregimpl3_regs1; -assign tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl4_regs1; -assign tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl5_regs1; -assign rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl6_regs1; -assign rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl7_regs1; +assign sys_rst = main_maccore_int_rst; +assign main_maccore_ethphy_mode_status = main_maccore_ethphy_mode0; +assign main_maccore_ethphy_eth_tick = (main_maccore_ethphy_eth_counter == 1'd0); +assign main_maccore_ethphy_i = main_maccore_ethphy_eth_tick; +assign main_maccore_ethphy_sys_tick = main_maccore_ethphy_o; +assign main_maccore_ethphy_o = (main_maccore_ethphy_toggle_o ^ main_maccore_ethphy_toggle_o_r); +always @(*) begin + builder_liteethphygmiimii_next_state <= 2'd0; + main_maccore_ethphy_mode1 <= 1'd0; + main_maccore_ethphy_sys_counter_ce <= 1'd0; + main_maccore_ethphy_sys_counter_reset <= 1'd0; + main_maccore_ethphy_update_mode <= 1'd0; + builder_liteethphygmiimii_next_state <= builder_liteethphygmiimii_state; + case (builder_liteethphygmiimii_state) + 1'd1: begin + main_maccore_ethphy_sys_counter_ce <= 1'd1; + if (main_maccore_ethphy_sys_tick) begin + builder_liteethphygmiimii_next_state <= 2'd2; + end + end + 2'd2: begin + main_maccore_ethphy_update_mode <= 1'd1; + if ((main_maccore_ethphy_sys_counter > 10'd860)) begin + main_maccore_ethphy_mode1 <= 1'd1; + end else begin + main_maccore_ethphy_mode1 <= 1'd0; + end + builder_liteethphygmiimii_next_state <= 1'd0; + end + default: begin + main_maccore_ethphy_sys_counter_reset <= 1'd1; + if (main_maccore_ethphy_sys_tick) begin + builder_liteethphygmiimii_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + main_maccore_ethphy_eth_tx_clk <= 1'd0; + if ((main_maccore_ethphy_mode0 == 1'd1)) begin + main_maccore_ethphy_eth_tx_clk <= gmii_clocks_tx; + end else begin + main_maccore_ethphy_eth_tx_clk <= gmii_clocks_rx; + end +end +assign main_maccore_ethphy_reset0 = (main_maccore_ethphy_reset_storage | main_maccore_ethphy_reset1); +assign gmii_rst_n = (~main_maccore_ethphy_reset0); +assign main_maccore_ethphy_counter_done = (main_maccore_ethphy_counter == 9'd256); +assign main_maccore_ethphy_counter_ce = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_reset1 = (~main_maccore_ethphy_counter_done); +assign main_maccore_ethphy_demux_sel = (main_maccore_ethphy_mode0 == 1'd1); +assign main_maccore_ethphy_demux_sink_valid = main_maccore_ethphy_sink_sink_valid; +assign main_maccore_ethphy_sink_sink_ready = main_maccore_ethphy_demux_sink_ready; +assign main_maccore_ethphy_demux_sink_first = main_maccore_ethphy_sink_sink_first; +assign main_maccore_ethphy_demux_sink_last = main_maccore_ethphy_sink_sink_last; +assign main_maccore_ethphy_demux_sink_payload_data = main_maccore_ethphy_sink_sink_payload_data; +assign main_maccore_ethphy_demux_sink_payload_last_be = main_maccore_ethphy_sink_sink_payload_last_be; +assign main_maccore_ethphy_demux_sink_payload_error = main_maccore_ethphy_sink_sink_payload_error; +assign main_maccore_ethphy_gmii_tx_sink_valid = main_maccore_ethphy_demux_endpoint0_source_valid; +assign main_maccore_ethphy_demux_endpoint0_source_ready = main_maccore_ethphy_gmii_tx_sink_ready; +assign main_maccore_ethphy_gmii_tx_sink_first = main_maccore_ethphy_demux_endpoint0_source_first; +assign main_maccore_ethphy_gmii_tx_sink_last = main_maccore_ethphy_demux_endpoint0_source_last; +assign main_maccore_ethphy_gmii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint0_source_payload_data; +assign main_maccore_ethphy_gmii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint0_source_payload_last_be; +assign main_maccore_ethphy_gmii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint0_source_payload_error; +assign main_maccore_ethphy_mii_tx_sink_valid = main_maccore_ethphy_demux_endpoint1_source_valid; +assign main_maccore_ethphy_demux_endpoint1_source_ready = main_maccore_ethphy_mii_tx_sink_ready; +assign main_maccore_ethphy_mii_tx_sink_first = main_maccore_ethphy_demux_endpoint1_source_first; +assign main_maccore_ethphy_mii_tx_sink_last = main_maccore_ethphy_demux_endpoint1_source_last; +assign main_maccore_ethphy_mii_tx_sink_payload_data = main_maccore_ethphy_demux_endpoint1_source_payload_data; +assign main_maccore_ethphy_mii_tx_sink_payload_last_be = main_maccore_ethphy_demux_endpoint1_source_payload_last_be; +assign main_maccore_ethphy_mii_tx_sink_payload_error = main_maccore_ethphy_demux_endpoint1_source_payload_error; +assign gmii_tx_er = 1'd0; +assign main_maccore_ethphy_mii_tx_converter_sink_valid = main_maccore_ethphy_mii_tx_sink_valid; +assign main_maccore_ethphy_mii_tx_converter_sink_payload_data = main_maccore_ethphy_mii_tx_sink_payload_data; +assign main_maccore_ethphy_mii_tx_sink_ready = main_maccore_ethphy_mii_tx_converter_sink_ready; +assign main_maccore_ethphy_mii_tx_source_source_ready = 1'd1; +assign main_maccore_ethphy_mii_tx_source_source_valid = main_maccore_ethphy_mii_tx_converter_source_valid; +assign main_maccore_ethphy_mii_tx_converter_source_ready = main_maccore_ethphy_mii_tx_source_source_ready; +assign main_maccore_ethphy_mii_tx_source_source_first = main_maccore_ethphy_mii_tx_converter_source_first; +assign main_maccore_ethphy_mii_tx_source_source_last = main_maccore_ethphy_mii_tx_converter_source_last; +assign main_maccore_ethphy_mii_tx_source_source_payload_data = main_maccore_ethphy_mii_tx_converter_source_payload_data; +assign main_maccore_ethphy_mii_tx_converter_first = (main_maccore_ethphy_mii_tx_converter_mux == 1'd0); +assign main_maccore_ethphy_mii_tx_converter_last = (main_maccore_ethphy_mii_tx_converter_mux == 1'd1); +assign main_maccore_ethphy_mii_tx_converter_source_valid = main_maccore_ethphy_mii_tx_converter_sink_valid; +assign main_maccore_ethphy_mii_tx_converter_source_first = (main_maccore_ethphy_mii_tx_converter_sink_first & main_maccore_ethphy_mii_tx_converter_first); +assign main_maccore_ethphy_mii_tx_converter_source_last = (main_maccore_ethphy_mii_tx_converter_sink_last & main_maccore_ethphy_mii_tx_converter_last); +assign main_maccore_ethphy_mii_tx_converter_sink_ready = (main_maccore_ethphy_mii_tx_converter_last & main_maccore_ethphy_mii_tx_converter_source_ready); +always @(*) begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= 4'd0; + case (main_maccore_ethphy_mii_tx_converter_mux) + 1'd0: begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[3:0]; + end + default: begin + main_maccore_ethphy_mii_tx_converter_source_payload_data <= main_maccore_ethphy_mii_tx_converter_sink_payload_data[7:4]; + end + endcase +end +assign main_maccore_ethphy_mii_tx_converter_source_payload_valid_token_count = main_maccore_ethphy_mii_tx_converter_last; +always @(*) begin + main_maccore_ethphy_demux_endpoint0_source_first <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_last <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_data <= 8'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_error <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= 1'd0; + main_maccore_ethphy_demux_endpoint0_source_valid <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_first <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_last <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_data <= 8'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_error <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= 1'd0; + main_maccore_ethphy_demux_endpoint1_source_valid <= 1'd0; + main_maccore_ethphy_demux_sink_ready <= 1'd0; + case (main_maccore_ethphy_demux_sel) + 1'd0: begin + main_maccore_ethphy_demux_endpoint0_source_valid <= main_maccore_ethphy_demux_sink_valid; + main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint0_source_ready; + main_maccore_ethphy_demux_endpoint0_source_first <= main_maccore_ethphy_demux_sink_first; + main_maccore_ethphy_demux_endpoint0_source_last <= main_maccore_ethphy_demux_sink_last; + main_maccore_ethphy_demux_endpoint0_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; + main_maccore_ethphy_demux_endpoint0_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; + main_maccore_ethphy_demux_endpoint0_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + end + 1'd1: begin + main_maccore_ethphy_demux_endpoint1_source_valid <= main_maccore_ethphy_demux_sink_valid; + main_maccore_ethphy_demux_sink_ready <= main_maccore_ethphy_demux_endpoint1_source_ready; + main_maccore_ethphy_demux_endpoint1_source_first <= main_maccore_ethphy_demux_sink_first; + main_maccore_ethphy_demux_endpoint1_source_last <= main_maccore_ethphy_demux_sink_last; + main_maccore_ethphy_demux_endpoint1_source_payload_data <= main_maccore_ethphy_demux_sink_payload_data; + main_maccore_ethphy_demux_endpoint1_source_payload_last_be <= main_maccore_ethphy_demux_sink_payload_last_be; + main_maccore_ethphy_demux_endpoint1_source_payload_error <= main_maccore_ethphy_demux_sink_payload_error; + end + endcase +end +assign main_maccore_ethphy_mux_sel = (main_maccore_ethphy_mode0 == 1'd1); +assign main_maccore_ethphy_mux_endpoint0_sink_valid = main_maccore_ethphy_gmii_rx_source_valid; +assign main_maccore_ethphy_gmii_rx_source_ready = main_maccore_ethphy_mux_endpoint0_sink_ready; +assign main_maccore_ethphy_mux_endpoint0_sink_first = main_maccore_ethphy_gmii_rx_source_first; +assign main_maccore_ethphy_mux_endpoint0_sink_last = main_maccore_ethphy_gmii_rx_source_last; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_data = main_maccore_ethphy_gmii_rx_source_payload_data; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_last_be = main_maccore_ethphy_gmii_rx_source_payload_last_be; +assign main_maccore_ethphy_mux_endpoint0_sink_payload_error = main_maccore_ethphy_gmii_rx_source_payload_error; +assign main_maccore_ethphy_mux_endpoint1_sink_valid = main_maccore_ethphy_mii_rx_source_valid; +assign main_maccore_ethphy_mii_rx_source_ready = main_maccore_ethphy_mux_endpoint1_sink_ready; +assign main_maccore_ethphy_mux_endpoint1_sink_first = main_maccore_ethphy_mii_rx_source_first; +assign main_maccore_ethphy_mux_endpoint1_sink_last = main_maccore_ethphy_mii_rx_source_last; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_data = main_maccore_ethphy_mii_rx_source_payload_data; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_last_be = main_maccore_ethphy_mii_rx_source_payload_last_be; +assign main_maccore_ethphy_mux_endpoint1_sink_payload_error = main_maccore_ethphy_mii_rx_source_payload_error; +assign main_maccore_ethphy_source_source_valid = main_maccore_ethphy_mux_source_valid; +assign main_maccore_ethphy_mux_source_ready = main_maccore_ethphy_source_source_ready; +assign main_maccore_ethphy_source_source_first = main_maccore_ethphy_mux_source_first; +assign main_maccore_ethphy_source_source_last = main_maccore_ethphy_mux_source_last; +assign main_maccore_ethphy_source_source_payload_data = main_maccore_ethphy_mux_source_payload_data; +assign main_maccore_ethphy_source_source_payload_last_be = main_maccore_ethphy_mux_source_payload_last_be; +assign main_maccore_ethphy_source_source_payload_error = main_maccore_ethphy_mux_source_payload_error; +assign main_maccore_ethphy_gmii_rx_source_last = ((~main_maccore_ethphy_pads_d_rx_dv) & main_maccore_ethphy_gmii_rx_dv_d); +assign main_maccore_ethphy_mii_rx_converter_sink_last = (~main_maccore_ethphy_pads_d_rx_dv); +assign main_maccore_ethphy_mii_rx_source_valid = main_maccore_ethphy_mii_rx_source_source_valid; +assign main_maccore_ethphy_mii_rx_source_source_ready = main_maccore_ethphy_mii_rx_source_ready; +assign main_maccore_ethphy_mii_rx_source_first = main_maccore_ethphy_mii_rx_source_source_first; +assign main_maccore_ethphy_mii_rx_source_last = main_maccore_ethphy_mii_rx_source_source_last; +assign main_maccore_ethphy_mii_rx_source_payload_data = main_maccore_ethphy_mii_rx_source_source_payload_data; +assign main_maccore_ethphy_mii_rx_source_source_valid = main_maccore_ethphy_mii_rx_converter_source_valid; +assign main_maccore_ethphy_mii_rx_converter_source_ready = main_maccore_ethphy_mii_rx_source_source_ready; +assign main_maccore_ethphy_mii_rx_source_source_first = main_maccore_ethphy_mii_rx_converter_source_first; +assign main_maccore_ethphy_mii_rx_source_source_last = main_maccore_ethphy_mii_rx_converter_source_last; +assign main_maccore_ethphy_mii_rx_source_source_payload_data = main_maccore_ethphy_mii_rx_converter_source_payload_data; +assign main_maccore_ethphy_mii_rx_converter_sink_ready = ((~main_maccore_ethphy_mii_rx_converter_strobe_all) | main_maccore_ethphy_mii_rx_converter_source_ready); +assign main_maccore_ethphy_mii_rx_converter_source_valid = main_maccore_ethphy_mii_rx_converter_strobe_all; +assign main_maccore_ethphy_mii_rx_converter_load_part = (main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready); +always @(*) begin + main_maccore_ethphy_mux_endpoint0_sink_ready <= 1'd0; + main_maccore_ethphy_mux_endpoint1_sink_ready <= 1'd0; + main_maccore_ethphy_mux_source_first <= 1'd0; + main_maccore_ethphy_mux_source_last <= 1'd0; + main_maccore_ethphy_mux_source_payload_data <= 8'd0; + main_maccore_ethphy_mux_source_payload_error <= 1'd0; + main_maccore_ethphy_mux_source_payload_last_be <= 1'd0; + main_maccore_ethphy_mux_source_valid <= 1'd0; + case (main_maccore_ethphy_mux_sel) + 1'd0: begin + main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint0_sink_valid; + main_maccore_ethphy_mux_endpoint0_sink_ready <= main_maccore_ethphy_mux_source_ready; + main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint0_sink_first; + main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint0_sink_last; + main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint0_sink_payload_data; + main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint0_sink_payload_last_be; + main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint0_sink_payload_error; + end + 1'd1: begin + main_maccore_ethphy_mux_source_valid <= main_maccore_ethphy_mux_endpoint1_sink_valid; + main_maccore_ethphy_mux_endpoint1_sink_ready <= main_maccore_ethphy_mux_source_ready; + main_maccore_ethphy_mux_source_first <= main_maccore_ethphy_mux_endpoint1_sink_first; + main_maccore_ethphy_mux_source_last <= main_maccore_ethphy_mux_endpoint1_sink_last; + main_maccore_ethphy_mux_source_payload_data <= main_maccore_ethphy_mux_endpoint1_sink_payload_data; + main_maccore_ethphy_mux_source_payload_last_be <= main_maccore_ethphy_mux_endpoint1_sink_payload_last_be; + main_maccore_ethphy_mux_source_payload_error <= main_maccore_ethphy_mux_endpoint1_sink_payload_error; + end + endcase +end +assign gmii_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_sink_ready; +assign main_maccore_ethphy_sink_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); +assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); +assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); +assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; +assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; +end +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +end +assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); +assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end +end +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; +assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; +assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; +assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; +assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; +assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; +assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; +assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; +assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; +assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; +assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; +assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; +assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; +assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; +assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; +assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; +assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; +assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; +assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; +assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; +assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; +assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; +assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; +assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; +assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; +assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; +assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; +assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; +assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); +assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); +assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); +assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); +assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; +assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; +assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_source_valid; +assign main_maccore_ethphy_source_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_source_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_source_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; +assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_wishbone2csr_next_state <= 1'd0; + builder_wishbone2csr_next_state <= builder_wishbone2csr_state; + case (builder_wishbone2csr_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_wishbone2csr_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end +end +always @(*) begin + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end +end +assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank2_mode_detection_mode_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mode_detection_mode_re <= 1'd0; + builder_csrbank2_mode_detection_mode_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_mode_detection_mode_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mode_detection_mode_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mode_detection_mode_w = main_maccore_ethphy_mode_status; +assign main_maccore_ethphy_mode_we = builder_csrbank2_mode_detection_mode_we; +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; +assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +assign main_maccore_ethphy_toggle_o = builder_xilinxmultiregimpl01; +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_xilinxmultiregimpl11; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl21; +assign main_tx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl31; +assign main_pulsesynchronizer0_toggle_o = builder_xilinxmultiregimpl41; +assign main_pulsesynchronizer1_toggle_o = builder_xilinxmultiregimpl51; +assign main_rx_cdc_cdc_produce_rdomain = builder_xilinxmultiregimpl61; +assign main_rx_cdc_cdc_consume_wdomain = builder_xilinxmultiregimpl71; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ always @(posedge eth_rx_clk) begin - maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1); - if (maccore_ethphy_i) begin - maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i); - end - maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv <= gmii_eth_rx_dv; - maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data <= gmii_eth_rx_data; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data; - maccore_ethphy_liteethphygmiimiirx_converter_reset <= (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv); - maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd1; - maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data; - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - if (((maccore_ethphy_liteethphygmiimiirx_converter_converter_demux == 1'd1) | maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd1; - end else begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1); - end - end - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready)) begin - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last; - end else begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first); - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last); - end - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - case (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux) - 1'd0: begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; - end - 1'd1: begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data; - end - endcase - end - if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1); - end - if (maccore_ethphy_liteethphygmiimiirx_converter_reset) begin - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - end - subfragments_liteethmacpreamblechecker_state <= subfragments_liteethmacpreamblechecker_next_state; - if (liteethmaccrc32checker_crc_ce) begin - liteethmaccrc32checker_crc_reg <= liteethmaccrc32checker_crc_next; - end - if (liteethmaccrc32checker_crc_reset) begin - liteethmaccrc32checker_crc_reg <= 32'd4294967295; - end - if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin - if ((liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin - liteethmaccrc32checker_syncfifo_produce <= 1'd0; - end else begin - liteethmaccrc32checker_syncfifo_produce <= (liteethmaccrc32checker_syncfifo_produce + 1'd1); - end - end - if (liteethmaccrc32checker_syncfifo_do_read) begin - if ((liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin - liteethmaccrc32checker_syncfifo_consume <= 1'd0; - end else begin - liteethmaccrc32checker_syncfifo_consume <= (liteethmaccrc32checker_syncfifo_consume + 1'd1); - end - end - if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin - if ((~liteethmaccrc32checker_syncfifo_do_read)) begin - liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level + 1'd1); - end - end else begin - if (liteethmaccrc32checker_syncfifo_do_read) begin - liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level - 1'd1); - end - end - if (liteethmaccrc32checker_fifo_reset) begin - liteethmaccrc32checker_syncfifo_level <= 3'd0; - liteethmaccrc32checker_syncfifo_produce <= 3'd0; - liteethmaccrc32checker_syncfifo_consume <= 3'd0; - end - subfragments_liteethmaccrc32checker_state <= subfragments_liteethmaccrc32checker_next_state; - if (((~crc32_checker_source_valid) | crc32_checker_source_ready)) begin - crc32_checker_source_valid <= crc32_checker_sink_valid; - crc32_checker_source_first <= crc32_checker_sink_first; - crc32_checker_source_last <= crc32_checker_sink_last; - crc32_checker_source_payload_data <= crc32_checker_sink_payload_data; - crc32_checker_source_payload_last_be <= crc32_checker_sink_payload_last_be; - crc32_checker_source_payload_error <= crc32_checker_sink_payload_error; - end - if (ps_preamble_error_i) begin - ps_preamble_error_toggle_i <= (~ps_preamble_error_toggle_i); - end - if (ps_crc_error_i) begin - ps_crc_error_toggle_i <= (~ps_crc_error_toggle_i); - end - if (rx_converter_converter_source_ready) begin - rx_converter_converter_strobe_all <= 1'd0; - end - if (rx_converter_converter_load_part) begin - if (((rx_converter_converter_demux == 2'd3) | rx_converter_converter_sink_last)) begin - rx_converter_converter_demux <= 1'd0; - rx_converter_converter_strobe_all <= 1'd1; - end else begin - rx_converter_converter_demux <= (rx_converter_converter_demux + 1'd1); - end - end - if ((rx_converter_converter_source_valid & rx_converter_converter_source_ready)) begin - if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin - rx_converter_converter_source_first <= rx_converter_converter_sink_first; - rx_converter_converter_source_last <= rx_converter_converter_sink_last; - end else begin - rx_converter_converter_source_first <= 1'd0; - rx_converter_converter_source_last <= 1'd0; - end - end else begin - if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin - rx_converter_converter_source_first <= (rx_converter_converter_sink_first | rx_converter_converter_source_first); - rx_converter_converter_source_last <= (rx_converter_converter_sink_last | rx_converter_converter_source_last); - end - end - if (rx_converter_converter_load_part) begin - case (rx_converter_converter_demux) - 1'd0: begin - rx_converter_converter_source_payload_data[9:0] <= rx_converter_converter_sink_payload_data; - end - 1'd1: begin - rx_converter_converter_source_payload_data[19:10] <= rx_converter_converter_sink_payload_data; - end - 2'd2: begin - rx_converter_converter_source_payload_data[29:20] <= rx_converter_converter_sink_payload_data; - end - 2'd3: begin - rx_converter_converter_source_payload_data[39:30] <= rx_converter_converter_sink_payload_data; - end - endcase - end - if (rx_converter_converter_load_part) begin - rx_converter_converter_source_payload_valid_token_count <= (rx_converter_converter_demux + 1'd1); - end - rx_cdc_cdc_graycounter0_q_binary <= rx_cdc_cdc_graycounter0_q_next_binary; - rx_cdc_cdc_graycounter0_q <= rx_cdc_cdc_graycounter0_q_next; - if (eth_rx_rst) begin - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= 4'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0; - maccore_ethphy_liteethphygmiimiirx_converter_reset <= 1'd0; - liteethmaccrc32checker_crc_reg <= 32'd4294967295; - liteethmaccrc32checker_syncfifo_level <= 3'd0; - liteethmaccrc32checker_syncfifo_produce <= 3'd0; - liteethmaccrc32checker_syncfifo_consume <= 3'd0; - crc32_checker_source_valid <= 1'd0; - crc32_checker_source_payload_data <= 8'd0; - crc32_checker_source_payload_last_be <= 1'd0; - crc32_checker_source_payload_error <= 1'd0; - rx_converter_converter_source_payload_data <= 40'd0; - rx_converter_converter_source_payload_valid_token_count <= 3'd0; - rx_converter_converter_demux <= 2'd0; - rx_converter_converter_strobe_all <= 1'd0; - rx_cdc_cdc_graycounter0_q <= 6'd0; - rx_cdc_cdc_graycounter0_q_binary <= 6'd0; - subfragments_liteethmacpreamblechecker_state <= 1'd0; - subfragments_liteethmaccrc32checker_state <= 2'd0; - end - xilinxmultiregimpl7_regs0 <= rx_cdc_cdc_graycounter1_q; - xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0; + main_maccore_ethphy_eth_counter <= (main_maccore_ethphy_eth_counter + 1'd1); + if (main_maccore_ethphy_i) begin + main_maccore_ethphy_toggle_i <= (~main_maccore_ethphy_toggle_i); + end + main_maccore_ethphy_pads_d_rx_dv <= gmii_rx_dv; + main_maccore_ethphy_pads_d_rx_data <= gmii_rx_data; + main_maccore_ethphy_gmii_rx_dv_d <= main_maccore_ethphy_pads_d_rx_dv; + main_maccore_ethphy_gmii_rx_source_valid <= main_maccore_ethphy_pads_d_rx_dv; + main_maccore_ethphy_gmii_rx_source_payload_data <= main_maccore_ethphy_pads_d_rx_data; + main_maccore_ethphy_mii_rx_reset <= (~main_maccore_ethphy_pads_d_rx_dv); + main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd1; + main_maccore_ethphy_mii_rx_converter_sink_payload_data <= main_maccore_ethphy_pads_d_rx_data; + if (main_maccore_ethphy_mii_rx_converter_source_ready) begin + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + if (((main_maccore_ethphy_mii_rx_converter_demux == 1'd1) | main_maccore_ethphy_mii_rx_converter_sink_last)) begin + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd1; + end else begin + main_maccore_ethphy_mii_rx_converter_demux <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + end + end + if ((main_maccore_ethphy_mii_rx_converter_source_valid & main_maccore_ethphy_mii_rx_converter_source_ready)) begin + if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin + main_maccore_ethphy_mii_rx_converter_source_first <= main_maccore_ethphy_mii_rx_converter_sink_first; + main_maccore_ethphy_mii_rx_converter_source_last <= main_maccore_ethphy_mii_rx_converter_sink_last; + end else begin + main_maccore_ethphy_mii_rx_converter_source_first <= 1'd0; + main_maccore_ethphy_mii_rx_converter_source_last <= 1'd0; + end + end else begin + if ((main_maccore_ethphy_mii_rx_converter_sink_valid & main_maccore_ethphy_mii_rx_converter_sink_ready)) begin + main_maccore_ethphy_mii_rx_converter_source_first <= (main_maccore_ethphy_mii_rx_converter_sink_first | main_maccore_ethphy_mii_rx_converter_source_first); + main_maccore_ethphy_mii_rx_converter_source_last <= (main_maccore_ethphy_mii_rx_converter_sink_last | main_maccore_ethphy_mii_rx_converter_source_last); + end + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + case (main_maccore_ethphy_mii_rx_converter_demux) + 1'd0: begin + main_maccore_ethphy_mii_rx_converter_source_payload_data[3:0] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + end + 1'd1: begin + main_maccore_ethphy_mii_rx_converter_source_payload_data[7:4] <= main_maccore_ethphy_mii_rx_converter_sink_payload_data; + end + endcase + end + if (main_maccore_ethphy_mii_rx_converter_load_part) begin + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= (main_maccore_ethphy_mii_rx_converter_demux + 1'd1); + end + if (main_maccore_ethphy_mii_rx_reset) begin + main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_gmii_rx_source_valid <= 1'd0; + main_maccore_ethphy_gmii_rx_source_payload_data <= 8'd0; + main_maccore_ethphy_gmii_rx_dv_d <= 1'd0; + main_maccore_ethphy_mii_rx_converter_sink_valid <= 1'd0; + main_maccore_ethphy_mii_rx_converter_sink_payload_data <= 4'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_data <= 8'd0; + main_maccore_ethphy_mii_rx_converter_source_payload_valid_token_count <= 2'd0; + main_maccore_ethphy_mii_rx_converter_demux <= 1'd0; + main_maccore_ethphy_mii_rx_converter_strobe_all <= 1'd0; + main_maccore_ethphy_mii_rx_reset <= 1'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_xilinxmultiregimpl70 <= main_rx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl71 <= builder_xilinxmultiregimpl70; end always @(posedge eth_tx_clk) begin - if ((maccore_ethphy_mode0 == 1'd1)) begin - gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en; - gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data; - end else begin - gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en; - gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data; - end - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data; - maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd1; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_converter_source_valid; - maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data; - if ((maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready)) begin - if (maccore_ethphy_liteethphygmiimiitx_converter_converter_last) begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0; - end else begin - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux + 1'd1); - end - end - subfragments_liteethmacgap_state <= subfragments_liteethmacgap_next_state; - if (tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin - tx_gap_inserter_counter <= tx_gap_inserter_counter_liteethmacgap_next_value; - end - subfragments_liteethmacpreambleinserter_state <= subfragments_liteethmacpreambleinserter_next_state; - if (preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin - preamble_inserter_count <= preamble_inserter_count_liteethmacpreambleinserter_next_value; - end - if (liteethmaccrc32inserter_is_ongoing0) begin - liteethmaccrc32inserter_cnt <= 2'd3; - end else begin - if ((liteethmaccrc32inserter_is_ongoing1 & (~liteethmaccrc32inserter_cnt_done))) begin - liteethmaccrc32inserter_cnt <= (liteethmaccrc32inserter_cnt - liteethmaccrc32inserter_source_ready); - end - end - if (liteethmaccrc32inserter_ce) begin - liteethmaccrc32inserter_reg <= liteethmaccrc32inserter_next; - end - if (liteethmaccrc32inserter_reset) begin - liteethmaccrc32inserter_reg <= 32'd4294967295; - end - subfragments_liteethmaccrc32inserter_state <= subfragments_liteethmaccrc32inserter_next_state; - if (((~crc32_inserter_source_valid) | crc32_inserter_source_ready)) begin - crc32_inserter_source_valid <= crc32_inserter_sink_valid; - crc32_inserter_source_first <= crc32_inserter_sink_first; - crc32_inserter_source_last <= crc32_inserter_sink_last; - crc32_inserter_source_payload_data <= crc32_inserter_sink_payload_data; - crc32_inserter_source_payload_last_be <= crc32_inserter_sink_payload_last_be; - crc32_inserter_source_payload_error <= crc32_inserter_sink_payload_error; - end - subfragments_liteethmacpaddinginserter_state <= subfragments_liteethmacpaddinginserter_next_state; - if (padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin - padding_inserter_counter <= padding_inserter_counter_liteethmacpaddinginserter_next_value; - end - subfragments_liteethmactxlastbe_state <= subfragments_liteethmactxlastbe_next_state; - if ((tx_converter_converter_source_valid & tx_converter_converter_source_ready)) begin - if (tx_converter_converter_last) begin - tx_converter_converter_mux <= 1'd0; - end else begin - tx_converter_converter_mux <= (tx_converter_converter_mux + 1'd1); - end - end - tx_cdc_cdc_graycounter1_q_binary <= tx_cdc_cdc_graycounter1_q_next_binary; - tx_cdc_cdc_graycounter1_q <= tx_cdc_cdc_graycounter1_q_next; - if (eth_tx_rst) begin - maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd0; - maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0; - liteethmaccrc32inserter_reg <= 32'd4294967295; - liteethmaccrc32inserter_cnt <= 2'd3; - crc32_inserter_source_valid <= 1'd0; - crc32_inserter_source_payload_data <= 8'd0; - crc32_inserter_source_payload_last_be <= 1'd0; - crc32_inserter_source_payload_error <= 1'd0; - padding_inserter_counter <= 16'd0; - tx_converter_converter_mux <= 2'd0; - tx_cdc_cdc_graycounter1_q <= 6'd0; - tx_cdc_cdc_graycounter1_q_binary <= 6'd0; - subfragments_liteethmacgap_state <= 1'd0; - subfragments_liteethmacpreambleinserter_state <= 2'd0; - subfragments_liteethmaccrc32inserter_state <= 2'd0; - subfragments_liteethmacpaddinginserter_state <= 1'd0; - subfragments_liteethmactxlastbe_state <= 1'd0; - end - xilinxmultiregimpl4_regs0 <= tx_cdc_cdc_graycounter0_q; - xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0; + if ((main_maccore_ethphy_mode0 == 1'd1)) begin + gmii_tx_en <= main_maccore_ethphy_mii_tx_pads_tx_en; + gmii_tx_data <= main_maccore_ethphy_mii_tx_pads_tx_data; + end else begin + gmii_tx_en <= main_maccore_ethphy_gmii_tx_pads_tx_en; + gmii_tx_data <= main_maccore_ethphy_gmii_tx_pads_tx_data; + end + main_maccore_ethphy_gmii_tx_pads_tx_er <= 1'd0; + main_maccore_ethphy_gmii_tx_pads_tx_en <= main_maccore_ethphy_gmii_tx_sink_valid; + main_maccore_ethphy_gmii_tx_pads_tx_data <= main_maccore_ethphy_gmii_tx_sink_payload_data; + main_maccore_ethphy_gmii_tx_sink_ready <= 1'd1; + main_maccore_ethphy_mii_tx_pads_tx_er <= 1'd0; + main_maccore_ethphy_mii_tx_pads_tx_en <= main_maccore_ethphy_mii_tx_source_source_valid; + main_maccore_ethphy_mii_tx_pads_tx_data <= main_maccore_ethphy_mii_tx_source_source_payload_data; + if ((main_maccore_ethphy_mii_tx_converter_source_valid & main_maccore_ethphy_mii_tx_converter_source_ready)) begin + if (main_maccore_ethphy_mii_tx_converter_last) begin + main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; + end else begin + main_maccore_ethphy_mii_tx_converter_mux <= (main_maccore_ethphy_mii_tx_converter_mux + 1'd1); + end + end + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_maccore_ethphy_gmii_tx_sink_ready <= 1'd0; + main_maccore_ethphy_mii_tx_converter_mux <= 1'd0; + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_xilinxmultiregimpl20 <= main_tx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl21 <= builder_xilinxmultiregimpl20; end always @(posedge por_clk) begin - maccore_int_rst <= sys_reset; + main_maccore_int_rst <= sys_reset; end always @(posedge sys_clk) begin - if ((maccore_maccore_bus_errors != 32'd4294967295)) begin - if (maccore_maccore_bus_error) begin - maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1); - end - end - if (maccore_ethphy_update_mode) begin - maccore_ethphy_mode0 <= maccore_ethphy_mode1; - end - if (maccore_ethphy_sys_counter_reset) begin - maccore_ethphy_sys_counter <= 1'd0; - end else begin - if (maccore_ethphy_sys_counter_ce) begin - maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1); - end - end - maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o; - subfragments_state <= subfragments_next_state; - if (maccore_ethphy_counter_ce) begin - maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1); - end - if (ps_preamble_error_o) begin - preamble_errors_status <= (preamble_errors_status + 1'd1); - end - if (ps_crc_error_o) begin - crc_errors_status <= (crc_errors_status + 1'd1); - end - ps_preamble_error_toggle_o_r <= ps_preamble_error_toggle_o; - ps_crc_error_toggle_o_r <= ps_crc_error_toggle_o; - tx_cdc_cdc_graycounter0_q_binary <= tx_cdc_cdc_graycounter0_q_next_binary; - tx_cdc_cdc_graycounter0_q <= tx_cdc_cdc_graycounter0_q_next; - rx_cdc_cdc_graycounter1_q_binary <= rx_cdc_cdc_graycounter1_q_next_binary; - rx_cdc_cdc_graycounter1_q <= rx_cdc_cdc_graycounter1_q_next; - if (writer_slot_ce) begin - writer_slot <= (writer_slot + 1'd1); - end - if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin - writer_stat_fifo_produce <= (writer_stat_fifo_produce + 1'd1); - end - if (writer_stat_fifo_do_read) begin - writer_stat_fifo_consume <= (writer_stat_fifo_consume + 1'd1); - end - if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin - if ((~writer_stat_fifo_do_read)) begin - writer_stat_fifo_level <= (writer_stat_fifo_level + 1'd1); - end - end else begin - if (writer_stat_fifo_do_read) begin - writer_stat_fifo_level <= (writer_stat_fifo_level - 1'd1); - end - end - subfragments_liteethmacsramwriter_state <= subfragments_liteethmacsramwriter_next_state; - if (writer_counter_t_next_value_ce) begin - writer_counter <= writer_counter_t_next_value; - end - if (writer_errors_status_f_next_value_ce) begin - writer_errors_status <= writer_errors_status_f_next_value; - end - if (reader_eventsourcepulse_clear) begin - reader_eventsourcepulse_pending <= 1'd0; - end - if (reader_eventsourcepulse_trigger) begin - reader_eventsourcepulse_pending <= 1'd1; - end - if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin - reader_cmd_fifo_produce <= (reader_cmd_fifo_produce + 1'd1); - end - if (reader_cmd_fifo_do_read) begin - reader_cmd_fifo_consume <= (reader_cmd_fifo_consume + 1'd1); - end - if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin - if ((~reader_cmd_fifo_do_read)) begin - reader_cmd_fifo_level <= (reader_cmd_fifo_level + 1'd1); - end - end else begin - if (reader_cmd_fifo_do_read) begin - reader_cmd_fifo_level <= (reader_cmd_fifo_level - 1'd1); - end - end - subfragments_liteethmacsramreader_state <= subfragments_liteethmacsramreader_next_state; - if (reader_counter_next_value_ce) begin - reader_counter <= reader_counter_next_value; - end - sram0_bus_ack0 <= 1'd0; - if (((sram0_bus_cyc0 & sram0_bus_stb0) & (~sram0_bus_ack0))) begin - sram0_bus_ack0 <= 1'd1; - end - sram1_bus_ack0 <= 1'd0; - if (((sram1_bus_cyc0 & sram1_bus_stb0) & (~sram1_bus_ack0))) begin - sram1_bus_ack0 <= 1'd1; - end - sram0_bus_ack1 <= 1'd0; - if (((sram0_bus_cyc1 & sram0_bus_stb1) & (~sram0_bus_ack1))) begin - sram0_bus_ack1 <= 1'd1; - end - sram1_bus_ack1 <= 1'd0; - if (((sram1_bus_cyc1 & sram1_bus_stb1) & (~sram1_bus_ack1))) begin - sram1_bus_ack1 <= 1'd1; - end - slave_sel_r <= slave_sel; - maccore_state <= maccore_next_state; - maccore_slave_sel_r <= maccore_slave_sel; - if (maccore_wait) begin - if ((~maccore_done)) begin - maccore_count <= (maccore_count - 1'd1); - end - end else begin - maccore_count <= 20'd1000000; - end - maccore_interface0_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank0_sel) begin - case (maccore_interface0_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_reset0_w; - end - 1'd1: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_scratch0_w; - end - 2'd2: begin - maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_bus_errors_w; - end - endcase - end - if (maccore_csrbank0_reset0_re) begin - maccore_maccore_reset_storage[1:0] <= maccore_csrbank0_reset0_r; - end - maccore_maccore_reset_re <= maccore_csrbank0_reset0_re; - if (maccore_csrbank0_scratch0_re) begin - maccore_maccore_scratch_storage[31:0] <= maccore_csrbank0_scratch0_r; - end - maccore_maccore_scratch_re <= maccore_csrbank0_scratch0_re; - maccore_maccore_bus_errors_re <= maccore_csrbank0_bus_errors_re; - maccore_interface1_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank1_sel) begin - case (maccore_interface1_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_slot_w; - end - 1'd1: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_length_w; - end - 2'd2: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_errors_w; - end - 2'd3: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_status_w; - end - 3'd4: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_pending_w; - end - 3'd5: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_enable0_w; - end - 3'd6: begin - maccore_interface1_bank_bus_dat_r <= reader_start_start_w; - end - 3'd7: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ready_w; - end - 4'd8: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_level_w; - end - 4'd9: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_slot0_w; - end - 4'd10: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_length0_w; - end - 4'd11: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_status_w; - end - 4'd12: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_pending_w; - end - 4'd13: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_enable0_w; - end - 4'd14: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_crc_w; - end - 4'd15: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_errors_w; - end - 5'd16: begin - maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_crc_errors_w; - end - endcase - end - writer_slot_re <= maccore_csrbank1_sram_writer_slot_re; - writer_length_re <= maccore_csrbank1_sram_writer_length_re; - writer_errors_re <= maccore_csrbank1_sram_writer_errors_re; - writer_status_re <= maccore_csrbank1_sram_writer_ev_status_re; - if (maccore_csrbank1_sram_writer_ev_pending_re) begin - writer_pending_r <= maccore_csrbank1_sram_writer_ev_pending_r; - end - writer_pending_re <= maccore_csrbank1_sram_writer_ev_pending_re; - if (maccore_csrbank1_sram_writer_ev_enable0_re) begin - writer_enable_storage <= maccore_csrbank1_sram_writer_ev_enable0_r; - end - writer_enable_re <= maccore_csrbank1_sram_writer_ev_enable0_re; - reader_ready_re <= maccore_csrbank1_sram_reader_ready_re; - reader_level_re <= maccore_csrbank1_sram_reader_level_re; - if (maccore_csrbank1_sram_reader_slot0_re) begin - reader_slot_storage <= maccore_csrbank1_sram_reader_slot0_r; - end - reader_slot_re <= maccore_csrbank1_sram_reader_slot0_re; - if (maccore_csrbank1_sram_reader_length0_re) begin - reader_length_storage[10:0] <= maccore_csrbank1_sram_reader_length0_r; - end - reader_length_re <= maccore_csrbank1_sram_reader_length0_re; - reader_status_re <= maccore_csrbank1_sram_reader_ev_status_re; - if (maccore_csrbank1_sram_reader_ev_pending_re) begin - reader_pending_r <= maccore_csrbank1_sram_reader_ev_pending_r; - end - reader_pending_re <= maccore_csrbank1_sram_reader_ev_pending_re; - if (maccore_csrbank1_sram_reader_ev_enable0_re) begin - reader_enable_storage <= maccore_csrbank1_sram_reader_ev_enable0_r; - end - reader_enable_re <= maccore_csrbank1_sram_reader_ev_enable0_re; - preamble_crc_re <= maccore_csrbank1_preamble_crc_re; - preamble_errors_re <= maccore_csrbank1_preamble_errors_re; - crc_errors_re <= maccore_csrbank1_crc_errors_re; - maccore_interface2_bank_bus_dat_r <= 1'd0; - if (maccore_csrbank2_sel) begin - case (maccore_interface2_bank_bus_adr[8:0]) - 1'd0: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mode_detection_mode_w; - end - 1'd1: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_crg_reset0_w; - end - 2'd2: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_w0_w; - end - 2'd3: begin - maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_r_w; - end - endcase - end - maccore_ethphy_mode_re <= maccore_csrbank2_mode_detection_mode_re; - if (maccore_csrbank2_crg_reset0_re) begin - maccore_ethphy_reset_storage <= maccore_csrbank2_crg_reset0_r; - end - maccore_ethphy_reset_re <= maccore_csrbank2_crg_reset0_re; - if (maccore_csrbank2_mdio_w0_re) begin - maccore_ethphy__w_storage[2:0] <= maccore_csrbank2_mdio_w0_r; - end - maccore_ethphy__w_re <= maccore_csrbank2_mdio_w0_re; - maccore_ethphy__r_re <= maccore_csrbank2_mdio_r_re; - if (sys_rst) begin - maccore_maccore_reset_storage <= 2'd0; - maccore_maccore_reset_re <= 1'd0; - maccore_maccore_scratch_storage <= 32'd305419896; - maccore_maccore_scratch_re <= 1'd0; - maccore_maccore_bus_errors_re <= 1'd0; - maccore_maccore_bus_errors <= 32'd0; - maccore_ethphy_mode0 <= 1'd0; - maccore_ethphy_mode_re <= 1'd0; - maccore_ethphy_reset_storage <= 1'd0; - maccore_ethphy_reset_re <= 1'd0; - maccore_ethphy_counter <= 9'd0; - maccore_ethphy__w_storage <= 3'd0; - maccore_ethphy__w_re <= 1'd0; - maccore_ethphy__r_re <= 1'd0; - preamble_crc_re <= 1'd0; - preamble_errors_status <= 32'd0; - preamble_errors_re <= 1'd0; - crc_errors_status <= 32'd0; - crc_errors_re <= 1'd0; - tx_cdc_cdc_graycounter0_q <= 6'd0; - tx_cdc_cdc_graycounter0_q_binary <= 6'd0; - rx_cdc_cdc_graycounter1_q <= 6'd0; - rx_cdc_cdc_graycounter1_q_binary <= 6'd0; - writer_slot_re <= 1'd0; - writer_length_re <= 1'd0; - writer_errors_status <= 32'd0; - writer_errors_re <= 1'd0; - writer_status_re <= 1'd0; - writer_pending_re <= 1'd0; - writer_pending_r <= 1'd0; - writer_enable_storage <= 1'd0; - writer_enable_re <= 1'd0; - writer_counter <= 32'd0; - writer_slot <= 1'd0; - writer_stat_fifo_level <= 2'd0; - writer_stat_fifo_produce <= 1'd0; - writer_stat_fifo_consume <= 1'd0; - reader_ready_re <= 1'd0; - reader_level_re <= 1'd0; - reader_slot_re <= 1'd0; - reader_length_re <= 1'd0; - reader_eventsourcepulse_pending <= 1'd0; - reader_status_re <= 1'd0; - reader_pending_re <= 1'd0; - reader_pending_r <= 1'd0; - reader_enable_storage <= 1'd0; - reader_enable_re <= 1'd0; - reader_cmd_fifo_level <= 2'd0; - reader_cmd_fifo_produce <= 1'd0; - reader_cmd_fifo_consume <= 1'd0; - reader_counter <= 11'd0; - sram0_bus_ack0 <= 1'd0; - sram1_bus_ack0 <= 1'd0; - sram0_bus_ack1 <= 1'd0; - sram1_bus_ack1 <= 1'd0; - slave_sel_r <= 4'd0; - subfragments_state <= 2'd0; - subfragments_liteethmacsramwriter_state <= 3'd0; - subfragments_liteethmacsramreader_state <= 2'd0; - maccore_slave_sel_r <= 2'd0; - maccore_count <= 20'd1000000; - maccore_state <= 1'd0; - end - xilinxmultiregimpl0_regs0 <= maccore_ethphy_toggle_i; - xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0; - xilinxmultiregimpl1_regs0 <= maccore_ethphy_data_r; - xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0; - xilinxmultiregimpl2_regs0 <= ps_preamble_error_toggle_i; - xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0; - xilinxmultiregimpl3_regs0 <= ps_crc_error_toggle_i; - xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0; - xilinxmultiregimpl5_regs0 <= tx_cdc_cdc_graycounter1_q; - xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0; - xilinxmultiregimpl6_regs0 <= rx_cdc_cdc_graycounter0_q; - xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0; + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + if (main_maccore_ethphy_update_mode) begin + main_maccore_ethphy_mode0 <= main_maccore_ethphy_mode1; + end + if (main_maccore_ethphy_sys_counter_reset) begin + main_maccore_ethphy_sys_counter <= 1'd0; + end else begin + if (main_maccore_ethphy_sys_counter_ce) begin + main_maccore_ethphy_sys_counter <= (main_maccore_ethphy_sys_counter + 1'd1); + end + end + main_maccore_ethphy_toggle_o_r <= main_maccore_ethphy_toggle_o; + builder_liteethphygmiimii_state <= builder_liteethphygmiimii_next_state; + if (main_maccore_ethphy_counter_ce) begin + main_maccore_ethphy_counter <= (main_maccore_ethphy_counter + 1'd1); + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_wishbone2csr_state <= builder_wishbone2csr_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mode_detection_mode_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd3: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + main_maccore_ethphy_mode_re <= builder_csrbank2_mode_detection_mode_re; + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_mode0 <= 1'd0; + main_maccore_ethphy_mode_re <= 1'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_counter <= 9'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethphygmiimii_state <= 2'd0; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_wishbone2csr_state <= 1'd0; + end + builder_xilinxmultiregimpl00 <= main_maccore_ethphy_toggle_i; + builder_xilinxmultiregimpl01 <= builder_xilinxmultiregimpl00; + builder_xilinxmultiregimpl10 <= main_maccore_ethphy_data_r; + builder_xilinxmultiregimpl11 <= builder_xilinxmultiregimpl10; + builder_xilinxmultiregimpl30 <= main_tx_cdc_cdc_graycounter1_q; + builder_xilinxmultiregimpl31 <= builder_xilinxmultiregimpl30; + builder_xilinxmultiregimpl40 <= main_pulsesynchronizer0_toggle_i; + builder_xilinxmultiregimpl41 <= builder_xilinxmultiregimpl40; + builder_xilinxmultiregimpl50 <= main_pulsesynchronizer1_toggle_i; + builder_xilinxmultiregimpl51 <= builder_xilinxmultiregimpl50; + builder_xilinxmultiregimpl60 <= main_rx_cdc_cdc_graycounter0_q; + builder_xilinxmultiregimpl61 <= builder_xilinxmultiregimpl60; end + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance BUFG of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG( - .I(gmii_eth_clocks_rx), - .O(eth_rx_clk) + // Inputs. + .I (gmii_clocks_rx), + + // Outputs. + .O (eth_rx_clk) ); +//------------------------------------------------------------------------------ +// Instance BUFG_1 of BUFG Module. +//------------------------------------------------------------------------------ BUFG BUFG_1( - .I(maccore_ethphy_eth_tx_clk), - .O(eth_tx_clk) + // Inputs. + .I (main_maccore_ethphy_eth_tx_clk), + + // Outputs. + .O (eth_tx_clk) ); -assign gmii_eth_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz; -assign maccore_ethphy_data_r = gmii_eth_mdio; +assign gmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = gmii_mdio; -reg [11:0] storage[0:4]; -reg [11:0] memdat; -always @(posedge eth_rx_clk) begin - if (liteethmaccrc32checker_syncfifo_wrport_we) - storage[liteethmaccrc32checker_syncfifo_wrport_adr] <= liteethmaccrc32checker_syncfifo_wrport_dat_w; - memdat <= storage[liteethmaccrc32checker_syncfifo_wrport_adr]; +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; end - -always @(posedge eth_rx_clk) begin +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; -assign liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat; -assign liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[liteethmaccrc32checker_syncfifo_rdport_adr]; -reg [41:0] storage_1[0:31]; -reg [4:0] memadr; -reg [4:0] memadr_1; -always @(posedge sys_clk) begin - if (tx_cdc_cdc_wrport_we) - storage_1[tx_cdc_cdc_wrport_adr] <= tx_cdc_cdc_wrport_dat_w; - memadr <= tx_cdc_cdc_wrport_adr; +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; end - -always @(posedge eth_tx_clk) begin - memadr_1 <= tx_cdc_cdc_rdport_adr; +always @(posedge eth_rx_clk) begin end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; -assign tx_cdc_cdc_wrport_dat_r = storage_1[memadr]; -assign tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1]; +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | reg [41:0] storage_2[0:31]; -reg [4:0] memadr_2; -reg [4:0] memadr_3; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; always @(posedge eth_rx_clk) begin - if (rx_cdc_cdc_wrport_we) - storage_2[rx_cdc_cdc_wrport_adr] <= rx_cdc_cdc_wrport_dat_w; - memadr_2 <= rx_cdc_cdc_wrport_adr; + if (main_rx_cdc_cdc_wrport_we) + storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; end - always @(posedge sys_clk) begin - memadr_3 <= rx_cdc_cdc_rdport_adr; + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; -assign rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2]; -assign rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3]; -reg [34:0] storage_3[0:1]; -reg [34:0] memdat_1; +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; always @(posedge sys_clk) begin - if (writer_stat_fifo_wrport_we) - storage_3[writer_stat_fifo_wrport_adr] <= writer_stat_fifo_wrport_dat_w; - memdat_1 <= storage_3[writer_stat_fifo_wrport_adr]; + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; end - always @(posedge sys_clk) begin end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; -assign writer_stat_fifo_wrport_dat_r = memdat_1; -assign writer_stat_fifo_rdport_dat_r = storage_3[writer_stat_fifo_rdport_adr]; -reg [31:0] mem[0:381]; -reg [8:0] memadr_4; -reg [31:0] memdat_2; +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; always @(posedge sys_clk) begin - if (writer_memory0_we) - mem[writer_memory0_adr] <= writer_memory0_dat_w; - memadr_4 <= writer_memory0_adr; + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; end - always @(posedge sys_clk) begin - memdat_2 <= mem[sram0_adr0]; + mem_dat1 <= mem[main_sram0_adr]; end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; -assign writer_memory0_dat_r = mem[memadr_4]; -assign sram0_dat_r0 = memdat_2; -reg [31:0] mem_1[0:381]; -reg [8:0] memadr_5; -reg [31:0] memdat_3; +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; always @(posedge sys_clk) begin - if (writer_memory1_we) - mem_1[writer_memory1_adr] <= writer_memory1_dat_w; - memadr_5 <= writer_memory1_adr; + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; end - always @(posedge sys_clk) begin - memdat_3 <= mem_1[sram1_adr0]; + mem_1_dat1 <= mem_1[main_sram1_adr]; end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; -assign writer_memory1_dat_r = mem_1[memadr_5]; -assign sram1_dat_r0 = memdat_3; +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | reg [13:0] storage_4[0:1]; -reg [13:0] memdat_4; +reg [13:0] storage_4_dat0; always @(posedge sys_clk) begin - if (reader_cmd_fifo_wrport_we) - storage_4[reader_cmd_fifo_wrport_adr] <= reader_cmd_fifo_wrport_dat_w; - memdat_4 <= storage_4[reader_cmd_fifo_wrport_adr]; + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; end - always @(posedge sys_clk) begin end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; -assign reader_cmd_fifo_wrport_dat_r = memdat_4; -assign reader_cmd_fifo_rdport_dat_r = storage_4[reader_cmd_fifo_rdport_adr]; -reg [31:0] mem_2[0:381]; -reg [8:0] memadr_6; -reg [8:0] memadr_7; +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; always @(posedge sys_clk) begin - memadr_6 <= reader_memory0_adr; + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; end - always @(posedge sys_clk) begin - if (sram0_we[0]) - mem_2[sram0_adr1][7:0] <= sram0_dat_w[7:0]; - if (sram0_we[1]) - mem_2[sram0_adr1][15:8] <= sram0_dat_w[15:8]; - if (sram0_we[2]) - mem_2[sram0_adr1][23:16] <= sram0_dat_w[23:16]; - if (sram0_we[3]) - mem_2[sram0_adr1][31:24] <= sram0_dat_w[31:24]; - memadr_7 <= sram0_adr1; + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; -assign reader_memory0_dat_r = mem_2[memadr_6]; -assign sram0_dat_r1 = mem_2[memadr_7]; -reg [31:0] mem_3[0:381]; -reg [8:0] memadr_8; -reg [8:0] memadr_9; +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; always @(posedge sys_clk) begin - memadr_8 <= reader_memory1_adr; + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; end - always @(posedge sys_clk) begin - if (sram1_we[0]) - mem_3[sram1_adr1][7:0] <= sram1_dat_w[7:0]; - if (sram1_we[1]) - mem_3[sram1_adr1][15:8] <= sram1_dat_w[15:8]; - if (sram1_we[2]) - mem_3[sram1_adr1][23:16] <= sram1_dat_w[23:16]; - if (sram1_we[3]) - mem_3[sram1_adr1][31:24] <= sram1_dat_w[31:24]; - memadr_9 <= sram1_adr1; + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; -assign reader_memory1_dat_r = mem_3[memadr_8]; -assign sram1_dat_r1 = mem_3[memadr_9]; +//------------------------------------------------------------------------------ +// Instance ODDR of ODDR Module. +//------------------------------------------------------------------------------ ODDR #( - .DDR_CLK_EDGE("SAME_EDGE") + // Parameters. + .DDR_CLK_EDGE ("SAME_EDGE") ) ODDR ( - .C(eth_tx_clk), - .CE(1'd1), - .D1(1'd1), - .D2((maccore_ethphy_mode0 == 1'd1)), - .R(1'd0), - .S(1'd0), - .Q(gmii_eth_clocks_gtx) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D1 (1'd1), + .D2 ((main_maccore_ethphy_mode0 == 1'd1)), + .R (1'd0), + .S (1'd0), + + // Outputs. + .Q (gmii_clocks_gtx) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE ( - .C(eth_tx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(maccore_ethphy_reset0), - .Q(rst_meta0) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_rst_meta0) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_1 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_1 ( - .C(eth_tx_clk), - .CE(1'd1), - .D(rst_meta0), - .PRE(maccore_ethphy_reset0), - .Q(eth_tx_rst) + // Inputs. + .C (eth_tx_clk), + .CE (1'd1), + .D (builder_rst_meta0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (eth_tx_rst) ); -(* ars_ff1 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff1 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_2 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_2 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(1'd0), - .PRE(maccore_ethphy_reset0), - .Q(rst_meta1) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (1'd0), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (builder_rst_meta1) ); -(* ars_ff2 = "true", async_reg = "true" *) FDPE #( - .INIT(1'd1) +(* ars_ff2 = "true", async_reg = "true" *) +//------------------------------------------------------------------------------ +// Instance FDPE_3 of FDPE Module. +//------------------------------------------------------------------------------ +FDPE #( + // Parameters. + .INIT (1'd1) ) FDPE_3 ( - .C(eth_rx_clk), - .CE(1'd1), - .D(rst_meta1), - .PRE(maccore_ethphy_reset0), - .Q(eth_rx_rst) + // Inputs. + .C (eth_rx_clk), + .CE (1'd1), + .D (builder_rst_meta1), + .PRE (main_maccore_ethphy_reset0), + + // Outputs. + .Q (eth_rx_rst) ); endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-05 17:38:50. +//------------------------------------------------------------------------------