diff --git a/predecode.vhdl b/predecode.vhdl index 585626f..852c96c 100644 --- a/predecode.vhdl +++ b/predecode.vhdl @@ -29,16 +29,17 @@ architecture behaviour of predecoder is type predecoder_rom_t is array(0 to 2047) of insn_code; + -- indexed by instruction bits 31..26 and 4..0 constant major_predecode_rom : predecoder_rom_t := ( - 2#001100_00000# to 2#001100_11111# => INSN_addic, - 2#001101_00000# to 2#001101_11111# => INSN_addic_dot, - 2#001110_00000# to 2#001110_11111# => INSN_addi, - 2#001111_00000# to 2#001111_11111# => INSN_addis, - 2#010011_00100# to 2#010011_00101# => INSN_addpcis, - 2#011100_00000# to 2#011100_11111# => INSN_andi_dot, - 2#011101_00000# to 2#011101_11111# => INSN_andis_dot, - 2#000000_00000# => INSN_attn, - 2#010010_00000# to 2#010010_00001# => INSN_brel, + 2#001100_00000# to 2#001100_11111# => INSN_addic, -- 12 + 2#001101_00000# to 2#001101_11111# => INSN_addic_dot, -- 13 + 2#001110_00000# to 2#001110_11111# => INSN_addi, -- 14 + 2#001111_00000# to 2#001111_11111# => INSN_addis, -- 15 + 2#010011_00100# to 2#010011_00101# => INSN_addpcis, -- 19 + 2#011100_00000# to 2#011100_11111# => INSN_andi_dot, -- 28 + 2#011101_00000# to 2#011101_11111# => INSN_andis_dot, -- 29 + 2#000000_00000# => INSN_attn, -- 0 + 2#010010_00000# to 2#010010_00001# => INSN_brel, -- 18 2#010010_00010# to 2#010010_00011# => INSN_babs, 2#010010_00100# to 2#010010_00101# => INSN_brel, 2#010010_00110# to 2#010010_00111# => INSN_babs, @@ -54,7 +55,7 @@ architecture behaviour of predecoder is 2#010010_11010# to 2#010010_11011# => INSN_babs, 2#010010_11100# to 2#010010_11101# => INSN_brel, 2#010010_11110# to 2#010010_11111# => INSN_babs, - 2#010000_00000# to 2#010000_00001# => INSN_bcrel, + 2#010000_00000# to 2#010000_00001# => INSN_bcrel, -- 16 2#010000_00010# to 2#010000_00011# => INSN_bcabs, 2#010000_00100# to 2#010000_00101# => INSN_bcrel, 2#010000_00110# to 2#010000_00111# => INSN_bcabs, @@ -70,42 +71,42 @@ architecture behaviour of predecoder is 2#010000_11010# to 2#010000_11011# => INSN_bcabs, 2#010000_11100# to 2#010000_11101# => INSN_bcrel, 2#010000_11110# to 2#010000_11111# => INSN_bcabs, - 2#001011_00000# to 2#001011_11111# => INSN_cmpi, - 2#001010_00000# to 2#001010_11111# => INSN_cmpli, - 2#100010_00000# to 2#100010_11111# => INSN_lbz, - 2#100011_00000# to 2#100011_11111# => INSN_lbzu, - 2#110010_00000# to 2#110010_11111# => INSN_lfd, - 2#110011_00000# to 2#110011_11111# => INSN_lfdu, - 2#110000_00000# to 2#110000_11111# => INSN_lfs, - 2#110001_00000# to 2#110001_11111# => INSN_lfsu, - 2#101010_00000# to 2#101010_11111# => INSN_lha, - 2#101011_00000# to 2#101011_11111# => INSN_lhau, - 2#101000_00000# to 2#101000_11111# => INSN_lhz, - 2#101001_00000# to 2#101001_11111# => INSN_lhzu, - 2#100000_00000# to 2#100000_11111# => INSN_lwz, - 2#100001_00000# to 2#100001_11111# => INSN_lwzu, - 2#000111_00000# to 2#000111_11111# => INSN_mulli, - 2#011000_00000# to 2#011000_11111# => INSN_ori, - 2#011001_00000# to 2#011001_11111# => INSN_oris, - 2#010100_00000# to 2#010100_11111# => INSN_rlwimi, - 2#010101_00000# to 2#010101_11111# => INSN_rlwinm, - 2#010111_00000# to 2#010111_11111# => INSN_rlwnm, - 2#010001_00000# to 2#010001_11111# => INSN_sc, - 2#100110_00000# to 2#100110_11111# => INSN_stb, - 2#100111_00000# to 2#100111_11111# => INSN_stbu, - 2#110110_00000# to 2#110110_11111# => INSN_stfd, - 2#110111_00000# to 2#110111_11111# => INSN_stfdu, - 2#110100_00000# to 2#110100_11111# => INSN_stfs, - 2#110101_00000# to 2#110101_11111# => INSN_stfsu, - 2#101100_00000# to 2#101100_11111# => INSN_sth, - 2#101101_00000# to 2#101101_11111# => INSN_sthu, - 2#100100_00000# to 2#100100_11111# => INSN_stw, - 2#100101_00000# to 2#100101_11111# => INSN_stwu, - 2#001000_00000# to 2#001000_11111# => INSN_subfic, - 2#000010_00000# to 2#000010_11111# => INSN_tdi, - 2#000011_00000# to 2#000011_11111# => INSN_twi, - 2#011010_00000# to 2#011010_11111# => INSN_xori, - 2#011011_00000# to 2#011011_11111# => INSN_xoris, + 2#001011_00000# to 2#001011_11111# => INSN_cmpi, -- 11 + 2#001010_00000# to 2#001010_11111# => INSN_cmpli, -- 10 + 2#100010_00000# to 2#100010_11111# => INSN_lbz, -- 34 + 2#100011_00000# to 2#100011_11111# => INSN_lbzu, -- 35 + 2#110010_00000# to 2#110010_11111# => INSN_lfd, -- 50 + 2#110011_00000# to 2#110011_11111# => INSN_lfdu, -- 51 + 2#110000_00000# to 2#110000_11111# => INSN_lfs, -- 56 + 2#110001_00000# to 2#110001_11111# => INSN_lfsu, -- 57 + 2#101010_00000# to 2#101010_11111# => INSN_lha, -- 42 + 2#101011_00000# to 2#101011_11111# => INSN_lhau, -- 43 + 2#101000_00000# to 2#101000_11111# => INSN_lhz, -- 40 + 2#101001_00000# to 2#101001_11111# => INSN_lhzu, -- 41 + 2#100000_00000# to 2#100000_11111# => INSN_lwz, -- 32 + 2#100001_00000# to 2#100001_11111# => INSN_lwzu, -- 33 + 2#000111_00000# to 2#000111_11111# => INSN_mulli, -- 7 + 2#011000_00000# to 2#011000_11111# => INSN_ori, -- 24 + 2#011001_00000# to 2#011001_11111# => INSN_oris, -- 25 + 2#010100_00000# to 2#010100_11111# => INSN_rlwimi, -- 20 + 2#010101_00000# to 2#010101_11111# => INSN_rlwinm, -- 21 + 2#010111_00000# to 2#010111_11111# => INSN_rlwnm, -- 23 + 2#010001_00000# to 2#010001_11111# => INSN_sc, -- 17 + 2#100110_00000# to 2#100110_11111# => INSN_stb, -- 38 + 2#100111_00000# to 2#100111_11111# => INSN_stbu, -- 39 + 2#110110_00000# to 2#110110_11111# => INSN_stfd, -- 54 + 2#110111_00000# to 2#110111_11111# => INSN_stfdu, -- 55 + 2#110100_00000# to 2#110100_11111# => INSN_stfs, -- 52 + 2#110101_00000# to 2#110101_11111# => INSN_stfsu, -- 53 + 2#101100_00000# to 2#101100_11111# => INSN_sth, -- 44 + 2#101101_00000# to 2#101101_11111# => INSN_sthu, -- 45 + 2#100100_00000# to 2#100100_11111# => INSN_stw, -- 36 + 2#100101_00000# to 2#100101_11111# => INSN_stwu, -- 37 + 2#001000_00000# to 2#001000_11111# => INSN_subfic, -- 8 + 2#000010_00000# to 2#000010_11111# => INSN_tdi, -- 2 + 2#000011_00000# to 2#000011_11111# => INSN_twi, -- 3 + 2#011010_00000# to 2#011010_11111# => INSN_xori, -- 26 + 2#011011_00000# to 2#011011_11111# => INSN_xoris, -- 27 -- major opcode 4 2#000100_10000# => INSN_maddhd, 2#000100_10001# => INSN_maddhdu,