From 84ae593a098906ea434671b7dbfe62497dc11c68 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Sat, 6 Apr 2024 19:14:04 +1100 Subject: [PATCH] ECPIX-5: Add liteeth support Signed-off-by: Paul Mackerras --- Makefile | 1 + constraints/ecpix-5.lpf | 37 + fpga/top-ecpix5.vhdl | 101 +- liteeth/gen-src/ecpix-5.yml | 18 + liteeth/gen-src/generate.sh | 2 +- liteeth/generated/ecpix-5/liteeth_core.v | 4289 ++++++++++++++++++++++ 6 files changed, 4446 insertions(+), 2 deletions(-) create mode 100644 liteeth/gen-src/ecpix-5.yml create mode 100644 liteeth/generated/ecpix-5/liteeth_core.v diff --git a/Makefile b/Makefile index aae24f0..fb591a4 100644 --- a/Makefile +++ b/Makefile @@ -228,6 +228,7 @@ OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg toplevel=fpga/top-ecpix5.vhdl litedram_target=ecpix-5 soc_extra_v += litesdcard/generated/lattice.50e6/litesdcard_core.v +soc_extra_v += liteeth/generated/ecpix-5/liteeth_core.v dmi_dtm=dmi_dtm_ecp5.vhdl endif diff --git a/constraints/ecpix-5.lpf b/constraints/ecpix-5.lpf index 4681dee..b4da68d 100644 --- a/constraints/ecpix-5.lpf +++ b/constraints/ecpix-5.lpf @@ -58,6 +58,43 @@ IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33; LOCATE COMP "spi_flash_hold_n" SITE "AE1"; IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33; +// Ethernet +LOCATE COMP "rgmii_clocks_rx" SITE "E11"; +LOCATE COMP "rgmii_clocks_tx" SITE "A12"; +LOCATE COMP "rgmii_rst_n" SITE "C13"; +LOCATE COMP "rgmii_int_n" SITE "B13"; +LOCATE COMP "rgmii_mdc" SITE "C11"; +LOCATE COMP "rgmii_mdio" SITE "A13"; +LOCATE COMP "rgmii_rx_ctl" SITE "A11"; +LOCATE COMP "rgmii_rx_data[0]" SITE "B11"; +LOCATE COMP "rgmii_rx_data[1]" SITE "A10"; +LOCATE COMP "rgmii_rx_data[2]" SITE "B10"; +LOCATE COMP "rgmii_rx_data[3]" SITE "A9"; +LOCATE COMP "rgmii_tx_ctl" SITE "C9"; +LOCATE COMP "rgmii_tx_data[0]" SITE "D8"; +LOCATE COMP "rgmii_tx_data[1]" SITE "C8"; +LOCATE COMP "rgmii_tx_data[2]" SITE "B8"; +LOCATE COMP "rgmii_tx_data[3]" SITE "A8"; +IOBUF PORT "rgmii_clocks_rx" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_clocks_tx" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rst_n" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_int_n" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_mdc" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_mdio" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rx_ctl" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_rx_data[0]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[1]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[2]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_rx_data[3]" IO_TYPE=LVCMOS33 PULLMODE=UP; +IOBUF PORT "rgmii_tx_ctl" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[0]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[1]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[2]" IO_TYPE=LVCMOS33; +IOBUF PORT "rgmii_tx_data[3]" IO_TYPE=LVCMOS33; +FREQUENCY PORT "eth_rx_clk" 125.0 MHz; +FREQUENCY PORT "eth_tx_clk" 125.0 MHz; +FREQUENCY PORT "rgmii_clocks_rx" 125.0 MHz; + // SD card slot and level translator LOCATE COMP "sdcard_data[0]" SITE "N26"; LOCATE COMP "sdcard_data[1]" SITE "N25"; diff --git a/fpga/top-ecpix5.vhdl b/fpga/top-ecpix5.vhdl index 7016067..301f573 100644 --- a/fpga/top-ecpix5.vhdl +++ b/fpga/top-ecpix5.vhdl @@ -23,6 +23,7 @@ entity toplevel is LOG_LENGTH : natural := 0; UART_IS_16550 : boolean := true; HAS_UART1 : boolean := false; + USE_LITEETH : boolean := true; USE_LITESDCARD : boolean := true; ICACHE_NUM_LINES : natural := 64; NGPIO : natural := 0 @@ -57,6 +58,18 @@ entity toplevel is spi_flash_wp_n : inout std_ulogic; spi_flash_hold_n : inout std_ulogic; + -- Ethernet + rgmii_clocks_rx : in std_ulogic; + rgmii_clocks_tx : out std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); + -- SD card wires sdcard_data : inout std_ulogic_vector(3 downto 0); sdcard_cmd : inout std_ulogic; @@ -166,6 +179,7 @@ architecture behaviour of toplevel is signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_eth : std_ulogic; signal wb_ext_is_sdcard : std_ulogic; -- DRAM main data wishbone connection @@ -175,6 +189,10 @@ architecture behaviour of toplevel is -- DRAM control wishbone connection signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + -- LiteEth connection + signal ext_irq_eth : std_ulogic; + signal wb_eth_out : wb_io_slave_out := wb_io_slave_out_init; + -- LiteSDCard connection signal ext_irq_sdcard : std_ulogic := '0'; signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; @@ -246,6 +264,7 @@ begin LOG_LENGTH => LOG_LENGTH, UART0_IS_16550 => UART_IS_16550, HAS_UART1 => HAS_UART1, + HAS_LITEETH => USE_LITEETH, HAS_SD_CARD => USE_LITESDCARD, ICACHE_NUM_LINES => ICACHE_NUM_LINES, NGPIO => NGPIO @@ -267,6 +286,7 @@ begin spi_flash_sdat_i => spi_sdat_i, -- External interrupts + ext_irq_eth => ext_irq_eth, ext_irq_sdcard => ext_irq_sdcard, -- DRAM wishbone @@ -278,6 +298,7 @@ begin wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_eth => wb_ext_is_eth, wb_ext_is_sdcard => wb_ext_is_sdcard, -- DMA wishbone @@ -420,6 +441,83 @@ begin led8_g_n <= not (dram_init_done and not dram_init_error); end generate; + has_liteeth : if USE_LITEETH generate + + component liteeth_core port ( + sys_clock : in std_ulogic; + sys_reset : in std_ulogic; + rgmii_clocks_tx : out std_ulogic; + rgmii_clocks_rx : in std_ulogic; + rgmii_rst_n : out std_ulogic; + rgmii_int_n : in std_ulogic; + rgmii_mdio : inout std_ulogic; + rgmii_mdc : out std_ulogic; + rgmii_rx_ctl : in std_ulogic; + rgmii_rx_data : in std_ulogic_vector(3 downto 0); + rgmii_tx_ctl : out std_ulogic; + rgmii_tx_data : out std_ulogic_vector(3 downto 0); + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic; + interrupt : out std_ulogic + ); + end component; + + signal wb_eth_cyc : std_ulogic; + signal wb_eth_adr : std_ulogic_vector(29 downto 0); + + begin + liteeth : liteeth_core + port map( + sys_clock => system_clk, + sys_reset => soc_rst, + rgmii_clocks_tx => rgmii_clocks_tx, + rgmii_clocks_rx => rgmii_clocks_rx, + rgmii_rst_n => rgmii_rst_n, + rgmii_int_n => rgmii_int_n, + rgmii_mdio => rgmii_mdio, + rgmii_mdc => rgmii_mdc, + rgmii_rx_ctl => rgmii_rx_ctl, + rgmii_rx_data => rgmii_rx_data, + rgmii_tx_ctl => rgmii_tx_ctl, + rgmii_tx_data => rgmii_tx_data, + wishbone_adr => wb_eth_adr, + wishbone_dat_w => wb_ext_io_in.dat, + wishbone_dat_r => wb_eth_out.dat, + wishbone_sel => wb_ext_io_in.sel, + wishbone_cyc => wb_eth_cyc, + wishbone_stb => wb_ext_io_in.stb, + wishbone_ack => wb_eth_out.ack, + wishbone_we => wb_ext_io_in.we, + wishbone_cti => "000", + wishbone_bte => "00", + wishbone_err => open, + interrupt => ext_irq_eth + ); + + -- Gate cyc with "chip select" from soc + wb_eth_cyc <= wb_ext_io_in.cyc and wb_ext_is_eth; + + -- Remove top address bits as liteeth decoder doesn't know about them + wb_eth_adr <= x"000" & "000" & wb_ext_io_in.adr(14 downto 0); + + -- LiteETH isn't pipelined + wb_eth_out.stall <= not wb_eth_out.ack; + + end generate; + + no_liteeth : if not USE_LITEETH generate + ext_irq_eth <= '0'; + end generate; + -- SD card -- The ECPIX-5 has a buffer/level translator chip in order to be able to -- support 1.8V signalling to the SD card as well as 3V signalling. @@ -537,7 +635,8 @@ begin end generate; -- Mux WB response on the IO bus - wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_ext_io_out <= wb_eth_out when wb_ext_is_eth = '1' else + wb_sdcard_out when wb_ext_is_sdcard = '1' else wb_dram_ctrl_out; led5_r_n <= '1'; diff --git a/liteeth/gen-src/ecpix-5.yml b/liteeth/gen-src/ecpix-5.yml new file mode 100644 index 0000000..9803c4b --- /dev/null +++ b/liteeth/gen-src/ecpix-5.yml @@ -0,0 +1,18 @@ +# This file is derived from nexys_video.yml, which is: +# Copyright (c) 2020 Florent Kermarrec +# License: BSD + +# PHY ---------------------------------------------------------------------- +phy: LiteEthECP5PHYRGMII +vendor: lattice +# Core --------------------------------------------------------------------- +clk_freq: 125e6 +core: wishbone +endianness: little +ntxslots: 2 +nrxslots: 2 +phy_rx_delay: 0 + +soc: + mem_map: + ethmac: 0x00010000 diff --git a/liteeth/gen-src/generate.sh b/liteeth/gen-src/generate.sh index 96203eb..a631b3e 100755 --- a/liteeth/gen-src/generate.sh +++ b/liteeth/gen-src/generate.sh @@ -1,6 +1,6 @@ #!/bin/bash -TARGETS="arty nexys-video wukong-v2" +TARGETS="arty nexys-video wukong-v2 ecpix-5" ME=$(realpath $0) echo ME=$ME diff --git a/liteeth/generated/ecpix-5/liteeth_core.v b/liteeth/generated/ecpix-5/liteeth_core.v new file mode 100644 index 0000000..50fde14 --- /dev/null +++ b/liteeth/generated/ecpix-5/liteeth_core.v @@ -0,0 +1,4289 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : liteeth_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-09 14:20:58 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module liteeth_core ( + output wire interrupt, + input wire rgmii_clocks_rx, + output wire rgmii_clocks_tx, + input wire rgmii_int_n, + output wire rgmii_mdc, + inout wire rgmii_mdio, + output wire rgmii_rst_n, + input wire rgmii_rx_ctl, + input wire [3:0] rgmii_rx_data, + output wire rgmii_tx_ctl, + output wire [3:0] rgmii_tx_data, + input wire sys_clock, + input wire sys_reset, + output wire wishbone_ack, + input wire [29:0] wishbone_adr, + input wire [1:0] wishbone_bte, + input wire [2:0] wishbone_cti, + input wire wishbone_cyc, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + output wire wishbone_err, + input wire [3:0] wishbone_sel, + input wire wishbone_stb, + input wire wishbone_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +MACCore +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── crg (CRG) +└─── ethphy (LiteEthPHYRGMII) +│ └─── crg (LiteEthPHYRGMIICRG) +│ │ └─── [DELAYG] +│ └─── tx (LiteEthPHYRGMIITX) +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ └─── rx (LiteEthPHYRGMIIRX) +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ │ └─── [DELAYG] +│ └─── mdio (LiteEthPHYMDIO) +└─── ethmac (LiteEthMAC) +│ └─── core (LiteEthMACCore) +│ │ └─── tx_datapath (TXDatapath) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _downconverter_0* (_DownConverter) +│ │ │ └─── liteethmactxlastbe_0* (LiteEthMACTXLastBE) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacpaddinginserter_0* (LiteEthMACPaddingInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmaccrc32inserter_0* (LiteEthMACCRC32Inserter) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── liteethmacpreambleinserter_0* (LiteEthMACPreambleInserter) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── liteethmacgap_0* (LiteEthMACGap) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pipeline_0* (Pipeline) +│ │ └─── rx_datapath (RXDatapath) +│ │ │ └─── liteethmacpreamblechecker_0* (LiteEthMACPreambleChecker) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── pulsesynchronizer_0* (PulseSynchronizer) +│ │ │ └─── liteethmaccrc32checker_0* (LiteEthMACCRC32Checker) +│ │ │ │ └─── crc (LiteEthMACCRC32) +│ │ │ │ │ └─── liteethmaccrcengine_0* (LiteEthMACCRCEngine) +│ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ │ └─── buffer_0* (Buffer) +│ │ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ │ └─── pipeline (Pipeline) +│ │ │ └─── pulsesynchronizer_1* (PulseSynchronizer) +│ │ │ └─── liteethmacpaddingchecker_0* (LiteEthMACPaddingChecker) +│ │ │ └─── liteethmacrxlastbe_0* (LiteEthMACRXLastBE) +│ │ │ └─── strideconverter_0* (StrideConverter) +│ │ │ │ └─── converter_0* (Converter) +│ │ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── clockdomaincrossing_0* (ClockDomainCrossing) +│ │ │ │ └─── asyncfifo_0* (AsyncFIFO) +│ │ │ │ │ └─── fifo (AsyncFIFO) +│ │ │ │ │ │ └─── graycounter_0* (GrayCounter) +│ │ │ │ │ │ └─── graycounter_1* (GrayCounter) +│ │ │ └─── pipeline_0* (Pipeline) +│ └─── interface (LiteEthMACWishboneInterface) +│ │ └─── sram (LiteEthMACSRAM) +│ │ │ └─── writer (LiteEthMACSRAMWriter) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcelevel_0* (EventSourceLevel) +│ │ │ │ └─── stat_fifo (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── reader (LiteEthMACSRAMReader) +│ │ │ │ └─── ev (EventManager) +│ │ │ │ │ └─── eventsourcepulse_0* (EventSourcePulse) +│ │ │ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ │ │ └─── fifo (SyncFIFO) +│ │ │ │ └─── fsm (FSM) +│ │ │ └─── ev (SharedIRQ) +│ │ └─── sram_0* (SRAM) +│ │ └─── sram_1* (SRAM) +│ │ └─── sram_2* (SRAM) +│ │ └─── sram_3* (SRAM) +│ │ └─── decoder_0* (Decoder) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstatus_3* (CSRStatus) +│ │ └─── csrstatus_4* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_5* (CSRStatus) +│ │ └─── csrstatus_6* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_7* (CSRStatus) +│ │ └─── csrstatus_8* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_9* (CSRStatus) +│ │ └─── csrstatus_10* (CSRStatus) +│ │ └─── csrstatus_11* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [ODDRX1F] +└─── [IDDRX1F] +└─── [ODDRX1F] +└─── [ODDRX1F] +└─── [FD1S3BX] +└─── [FD1S3BX] +└─── [ODDRX1F] +└─── [IDDRX1F] +└─── [IDDRX1F] +└─── [FD1S3BX] +└─── [ODDRX1F] +└─── [ODDRX1F] +└─── [FD1S3BX] +└─── [IDDRX1F] +└─── [IDDRX1F] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] builder_adr; +wire [39:0] builder_complexslicelowerer_slice_proxy; +reg [19:0] builder_count = 20'd1000000; +wire [31:0] builder_csrbank0_bus_errors_r; +reg builder_csrbank0_bus_errors_re = 1'd0; +wire [31:0] builder_csrbank0_bus_errors_w; +reg builder_csrbank0_bus_errors_we = 1'd0; +wire [1:0] builder_csrbank0_reset0_r; +reg builder_csrbank0_reset0_re = 1'd0; +wire [1:0] builder_csrbank0_reset0_w; +reg builder_csrbank0_reset0_we = 1'd0; +wire [31:0] builder_csrbank0_scratch0_r; +reg builder_csrbank0_scratch0_re = 1'd0; +wire [31:0] builder_csrbank0_scratch0_w; +reg builder_csrbank0_scratch0_we = 1'd0; +wire builder_csrbank0_sel; +wire builder_csrbank1_preamble_crc_r; +reg builder_csrbank1_preamble_crc_re = 1'd0; +wire builder_csrbank1_preamble_crc_w; +reg builder_csrbank1_preamble_crc_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_r; +reg builder_csrbank1_rx_datapath_crc_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_crc_errors_w; +reg builder_csrbank1_rx_datapath_crc_errors_we = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_r; +reg builder_csrbank1_rx_datapath_preamble_errors_re = 1'd0; +wire [31:0] builder_csrbank1_rx_datapath_preamble_errors_w; +reg builder_csrbank1_rx_datapath_preamble_errors_we = 1'd0; +wire builder_csrbank1_sel; +wire builder_csrbank1_sram_reader_ev_enable0_r; +reg builder_csrbank1_sram_reader_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_enable0_w; +reg builder_csrbank1_sram_reader_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_r; +reg builder_csrbank1_sram_reader_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_pending_w; +reg builder_csrbank1_sram_reader_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_r; +reg builder_csrbank1_sram_reader_ev_status_re = 1'd0; +wire builder_csrbank1_sram_reader_ev_status_w; +reg builder_csrbank1_sram_reader_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_r; +reg builder_csrbank1_sram_reader_length0_re = 1'd0; +wire [10:0] builder_csrbank1_sram_reader_length0_w; +reg builder_csrbank1_sram_reader_length0_we = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_r; +reg builder_csrbank1_sram_reader_level_re = 1'd0; +wire [1:0] builder_csrbank1_sram_reader_level_w; +reg builder_csrbank1_sram_reader_level_we = 1'd0; +wire builder_csrbank1_sram_reader_ready_r; +reg builder_csrbank1_sram_reader_ready_re = 1'd0; +wire builder_csrbank1_sram_reader_ready_w; +reg builder_csrbank1_sram_reader_ready_we = 1'd0; +wire builder_csrbank1_sram_reader_slot0_r; +reg builder_csrbank1_sram_reader_slot0_re = 1'd0; +wire builder_csrbank1_sram_reader_slot0_w; +reg builder_csrbank1_sram_reader_slot0_we = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_r; +reg builder_csrbank1_sram_writer_errors_re = 1'd0; +wire [31:0] builder_csrbank1_sram_writer_errors_w; +reg builder_csrbank1_sram_writer_errors_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_r; +reg builder_csrbank1_sram_writer_ev_enable0_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_enable0_w; +reg builder_csrbank1_sram_writer_ev_enable0_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_r; +reg builder_csrbank1_sram_writer_ev_pending_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_pending_w; +reg builder_csrbank1_sram_writer_ev_pending_we = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_r; +reg builder_csrbank1_sram_writer_ev_status_re = 1'd0; +wire builder_csrbank1_sram_writer_ev_status_w; +reg builder_csrbank1_sram_writer_ev_status_we = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_r; +reg builder_csrbank1_sram_writer_length_re = 1'd0; +wire [10:0] builder_csrbank1_sram_writer_length_w; +reg builder_csrbank1_sram_writer_length_we = 1'd0; +wire builder_csrbank1_sram_writer_slot_r; +reg builder_csrbank1_sram_writer_slot_re = 1'd0; +wire builder_csrbank1_sram_writer_slot_w; +reg builder_csrbank1_sram_writer_slot_we = 1'd0; +wire builder_csrbank2_crg_reset0_r; +reg builder_csrbank2_crg_reset0_re = 1'd0; +wire builder_csrbank2_crg_reset0_w; +reg builder_csrbank2_crg_reset0_we = 1'd0; +wire builder_csrbank2_mdio_r_r; +reg builder_csrbank2_mdio_r_re = 1'd0; +wire builder_csrbank2_mdio_r_w; +reg builder_csrbank2_mdio_r_we = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_r; +reg builder_csrbank2_mdio_w0_re = 1'd0; +wire [2:0] builder_csrbank2_mdio_w0_w; +reg builder_csrbank2_mdio_w0_we = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_r; +reg builder_csrbank2_rx_inband_status_re = 1'd0; +wire [2:0] builder_csrbank2_rx_inband_status_w; +reg builder_csrbank2_rx_inband_status_we = 1'd0; +wire builder_csrbank2_sel; +wire [31:0] builder_dat_r; +wire [31:0] builder_dat_w; +wire builder_done; +reg builder_error = 1'd0; +wire builder_grant; +reg builder_interface0_ack = 1'd0; +wire [29:0] builder_interface0_adr; +wire [13:0] builder_interface0_bank_bus_adr; +reg [31:0] builder_interface0_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface0_bank_bus_dat_w; +wire builder_interface0_bank_bus_we; +wire [1:0] builder_interface0_bte; +wire [2:0] builder_interface0_cti; +wire builder_interface0_cyc; +reg [31:0] builder_interface0_dat_r = 32'd0; +wire [31:0] builder_interface0_dat_w; +reg builder_interface0_err = 1'd0; +wire [3:0] builder_interface0_sel; +wire builder_interface0_stb; +wire builder_interface0_we; +reg [13:0] builder_interface1_adr = 14'd0; +wire [13:0] builder_interface1_bank_bus_adr; +reg [31:0] builder_interface1_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface1_bank_bus_dat_w; +wire builder_interface1_bank_bus_we; +wire [31:0] builder_interface1_dat_r; +reg [31:0] builder_interface1_dat_w = 32'd0; +reg builder_interface1_we = 1'd0; +wire [13:0] builder_interface2_bank_bus_adr; +reg [31:0] builder_interface2_bank_bus_dat_r = 32'd0; +wire [31:0] builder_interface2_bank_bus_dat_w; +wire builder_interface2_bank_bus_we; +reg [1:0] builder_liteethmacsramreader_next_state = 2'd0; +reg [1:0] builder_liteethmacsramreader_state = 2'd0; +reg [2:0] builder_liteethmacsramwriter_next_state = 3'd0; +reg [2:0] builder_liteethmacsramwriter_state = 3'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl00 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl01 = 1'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl10 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl11 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl20 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl21 = 6'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl30 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl31 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl40 = 1'd0; +(* syn_no_retiming = "true" *) +reg builder_multiregimpl41 = 1'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl50 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl51 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl60 = 6'd0; +(* syn_no_retiming = "true" *) +reg [5:0] builder_multiregimpl61 = 6'd0; +reg builder_next_state = 1'd0; +wire builder_request; +wire builder_rst10; +wire builder_rst11; +reg [1:0] builder_rxdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_rxdatapath_bufferizeendpoints_state = 2'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_next_state = 1'd0; +reg builder_rxdatapath_liteethmacpreamblechecker_state = 1'd0; +reg [29:0] builder_self0 = 30'd0; +reg [31:0] builder_self1 = 32'd0; +reg [3:0] builder_self2 = 4'd0; +reg builder_self3 = 1'd0; +reg builder_self4 = 1'd0; +reg builder_self5 = 1'd0; +reg [2:0] builder_self6 = 3'd0; +reg [1:0] builder_self7 = 2'd0; +reg builder_shared_ack = 1'd0; +wire [29:0] builder_shared_adr; +wire [1:0] builder_shared_bte; +wire [2:0] builder_shared_cti; +wire builder_shared_cyc; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [31:0] builder_shared_dat_w; +wire builder_shared_err; +wire [3:0] builder_shared_sel; +wire builder_shared_stb; +wire builder_shared_we; +reg [1:0] builder_slave_sel = 2'd0; +reg [1:0] builder_slave_sel_r = 2'd0; +reg builder_state = 1'd0; +wire [31:0] builder_t_slice_proxy0; +wire [31:0] builder_t_slice_proxy1; +wire [31:0] builder_t_slice_proxy10; +wire [31:0] builder_t_slice_proxy11; +wire [31:0] builder_t_slice_proxy12; +wire [31:0] builder_t_slice_proxy13; +wire [31:0] builder_t_slice_proxy14; +wire [31:0] builder_t_slice_proxy15; +wire [31:0] builder_t_slice_proxy16; +wire [31:0] builder_t_slice_proxy17; +wire [31:0] builder_t_slice_proxy18; +wire [31:0] builder_t_slice_proxy19; +wire [31:0] builder_t_slice_proxy2; +wire [31:0] builder_t_slice_proxy20; +wire [31:0] builder_t_slice_proxy21; +wire [31:0] builder_t_slice_proxy22; +wire [31:0] builder_t_slice_proxy23; +wire [31:0] builder_t_slice_proxy24; +wire [31:0] builder_t_slice_proxy25; +wire [31:0] builder_t_slice_proxy26; +wire [31:0] builder_t_slice_proxy27; +wire [31:0] builder_t_slice_proxy28; +wire [31:0] builder_t_slice_proxy29; +wire [31:0] builder_t_slice_proxy3; +wire [31:0] builder_t_slice_proxy30; +wire [31:0] builder_t_slice_proxy31; +wire [31:0] builder_t_slice_proxy32; +wire [31:0] builder_t_slice_proxy33; +wire [31:0] builder_t_slice_proxy34; +wire [31:0] builder_t_slice_proxy35; +wire [31:0] builder_t_slice_proxy36; +wire [31:0] builder_t_slice_proxy37; +wire [31:0] builder_t_slice_proxy38; +wire [31:0] builder_t_slice_proxy39; +wire [31:0] builder_t_slice_proxy4; +wire [31:0] builder_t_slice_proxy40; +wire [31:0] builder_t_slice_proxy41; +wire [31:0] builder_t_slice_proxy42; +wire [31:0] builder_t_slice_proxy43; +wire [31:0] builder_t_slice_proxy44; +wire [31:0] builder_t_slice_proxy45; +wire [31:0] builder_t_slice_proxy46; +wire [31:0] builder_t_slice_proxy47; +wire [31:0] builder_t_slice_proxy48; +wire [31:0] builder_t_slice_proxy49; +wire [31:0] builder_t_slice_proxy5; +wire [31:0] builder_t_slice_proxy50; +wire [31:0] builder_t_slice_proxy51; +wire [31:0] builder_t_slice_proxy52; +wire [31:0] builder_t_slice_proxy53; +wire [31:0] builder_t_slice_proxy54; +wire [31:0] builder_t_slice_proxy55; +wire [31:0] builder_t_slice_proxy56; +wire [31:0] builder_t_slice_proxy57; +wire [31:0] builder_t_slice_proxy58; +wire [31:0] builder_t_slice_proxy59; +wire [31:0] builder_t_slice_proxy6; +wire [31:0] builder_t_slice_proxy60; +wire [31:0] builder_t_slice_proxy61; +wire [31:0] builder_t_slice_proxy62; +wire [31:0] builder_t_slice_proxy63; +wire [31:0] builder_t_slice_proxy7; +wire [31:0] builder_t_slice_proxy8; +wire [31:0] builder_t_slice_proxy9; +reg [1:0] builder_txdatapath_bufferizeendpoints_next_state = 2'd0; +reg [1:0] builder_txdatapath_bufferizeendpoints_state = 2'd0; +reg builder_txdatapath_liteethmacgap_next_state = 1'd0; +reg builder_txdatapath_liteethmacgap_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_next_state = 1'd0; +reg builder_txdatapath_liteethmacpaddinginserter_state = 1'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_next_state = 2'd0; +reg [1:0] builder_txdatapath_liteethmacpreambleinserter_state = 2'd0; +reg builder_txdatapath_liteethmactxlastbe_next_state = 1'd0; +reg builder_txdatapath_liteethmactxlastbe_state = 1'd0; +wire builder_wait; +wire builder_we; +(* syn_keep = "true" *) +wire eth_rx_clk; +wire eth_rx_rst; +(* syn_keep = "true" *) +wire eth_tx_clk; +wire eth_tx_rst; +wire main_bufferizeendpoints_pipe_valid_sink_first; +wire main_bufferizeendpoints_pipe_valid_sink_last; +wire [7:0] main_bufferizeendpoints_pipe_valid_sink_payload_data; +wire main_bufferizeendpoints_pipe_valid_sink_payload_error; +wire main_bufferizeendpoints_pipe_valid_sink_payload_last_be; +wire main_bufferizeendpoints_pipe_valid_sink_ready; +wire main_bufferizeendpoints_pipe_valid_sink_valid; +reg main_bufferizeendpoints_pipe_valid_source_first = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_last = 1'd0; +reg [7:0] main_bufferizeendpoints_pipe_valid_source_payload_data = 8'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_error = 1'd0; +reg main_bufferizeendpoints_pipe_valid_source_payload_last_be = 1'd0; +wire main_bufferizeendpoints_pipe_valid_source_ready; +reg main_bufferizeendpoints_pipe_valid_source_valid = 1'd0; +wire main_bufferizeendpoints_sink_sink_first; +wire main_bufferizeendpoints_sink_sink_last; +wire [7:0] main_bufferizeendpoints_sink_sink_payload_data; +wire main_bufferizeendpoints_sink_sink_payload_error; +wire main_bufferizeendpoints_sink_sink_payload_last_be; +wire main_bufferizeendpoints_sink_sink_ready; +wire main_bufferizeendpoints_sink_sink_valid; +wire main_bufferizeendpoints_source_source_first; +wire main_bufferizeendpoints_source_source_last; +wire [7:0] main_bufferizeendpoints_source_source_payload_data; +wire main_bufferizeendpoints_source_source_payload_error; +wire main_bufferizeendpoints_source_source_payload_last_be; +wire main_bufferizeendpoints_source_source_ready; +wire main_bufferizeendpoints_source_source_valid; +wire main_bus_ack; +wire [29:0] main_bus_adr; +wire [1:0] main_bus_bte; +wire [2:0] main_bus_cti; +wire main_bus_cyc; +wire [31:0] main_bus_dat_r; +wire [31:0] main_bus_dat_w; +wire main_bus_err; +wire [3:0] main_bus_sel; +wire main_bus_stb; +wire main_bus_we; +reg main_crc_errors_re = 1'd0; +reg [31:0] main_crc_errors_status = 32'd0; +wire main_crc_errors_we; +reg main_interface0_ack = 1'd0; +wire [29:0] main_interface0_adr; +wire [1:0] main_interface0_bte; +wire [2:0] main_interface0_cti; +wire main_interface0_cyc; +wire [31:0] main_interface0_dat_r; +wire [31:0] main_interface0_dat_w; +reg main_interface0_err = 1'd0; +wire [3:0] main_interface0_sel; +wire main_interface0_stb; +wire main_interface0_we; +reg main_interface1_ack = 1'd0; +wire [29:0] main_interface1_adr; +wire [1:0] main_interface1_bte; +wire [2:0] main_interface1_cti; +wire main_interface1_cyc; +wire [31:0] main_interface1_dat_r; +wire [31:0] main_interface1_dat_w; +reg main_interface1_err = 1'd0; +wire [3:0] main_interface1_sel; +wire main_interface1_stb; +wire main_interface1_we; +reg main_interface2_ack = 1'd0; +wire [29:0] main_interface2_adr; +wire [1:0] main_interface2_bte; +wire [2:0] main_interface2_cti; +wire main_interface2_cyc; +wire [31:0] main_interface2_dat_r; +wire [31:0] main_interface2_dat_w; +reg main_interface2_err = 1'd0; +wire [3:0] main_interface2_sel; +wire main_interface2_stb; +wire main_interface2_we; +reg main_interface3_ack = 1'd0; +wire [29:0] main_interface3_adr; +wire [1:0] main_interface3_bte; +wire [2:0] main_interface3_cti; +wire main_interface3_cyc; +wire [31:0] main_interface3_dat_r; +wire [31:0] main_interface3_dat_w; +reg main_interface3_err = 1'd0; +wire [3:0] main_interface3_sel; +wire main_interface3_stb; +wire main_interface3_we; +reg [3:0] main_length_inc = 4'd0; +wire main_liteethmaccrc32checker_crc_be; +reg main_liteethmaccrc32checker_crc_ce = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_crc_next = 32'd0; +wire [31:0] main_liteethmaccrc32checker_crc_crc_prev; +wire [7:0] main_liteethmaccrc32checker_crc_data0; +wire [7:0] main_liteethmaccrc32checker_crc_data1; +reg main_liteethmaccrc32checker_crc_error0 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value1 = 1'd0; +reg main_liteethmaccrc32checker_crc_error1_next_value_ce1 = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_reg = 32'd4294967295; +reg main_liteethmaccrc32checker_crc_reset = 1'd0; +reg [31:0] main_liteethmaccrc32checker_crc_value = 32'd0; +reg main_liteethmaccrc32checker_error = 1'd0; +wire main_liteethmaccrc32checker_fifo_full; +wire main_liteethmaccrc32checker_fifo_in; +wire main_liteethmaccrc32checker_fifo_out; +reg main_liteethmaccrc32checker_fifo_reset = 1'd0; +reg main_liteethmaccrc32checker_last_be = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value0 = 1'd0; +reg main_liteethmaccrc32checker_last_be_next_value_ce0 = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_first; +wire main_liteethmaccrc32checker_sink_sink_last; +wire [7:0] main_liteethmaccrc32checker_sink_sink_payload_data; +wire main_liteethmaccrc32checker_sink_sink_payload_error; +wire main_liteethmaccrc32checker_sink_sink_payload_last_be; +reg main_liteethmaccrc32checker_sink_sink_ready = 1'd0; +wire main_liteethmaccrc32checker_sink_sink_valid; +wire main_liteethmaccrc32checker_source_source_first; +reg main_liteethmaccrc32checker_source_source_last = 1'd0; +wire [7:0] main_liteethmaccrc32checker_source_source_payload_data; +reg main_liteethmaccrc32checker_source_source_payload_error = 1'd0; +reg main_liteethmaccrc32checker_source_source_payload_last_be = 1'd0; +wire main_liteethmaccrc32checker_source_source_ready; +reg main_liteethmaccrc32checker_source_source_valid = 1'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_consume = 3'd0; +wire main_liteethmaccrc32checker_syncfifo_do_read; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_first; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +wire main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +reg [2:0] main_liteethmaccrc32checker_syncfifo_level = 3'd0; +reg [2:0] main_liteethmaccrc32checker_syncfifo_produce = 3'd0; +wire [2:0] main_liteethmaccrc32checker_syncfifo_rdport_adr; +wire [11:0] main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +reg main_liteethmaccrc32checker_syncfifo_replace = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_sink_first; +wire main_liteethmaccrc32checker_syncfifo_sink_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_sink_payload_data; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_error; +wire main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +wire main_liteethmaccrc32checker_syncfifo_sink_ready; +reg main_liteethmaccrc32checker_syncfifo_sink_valid = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_first; +wire main_liteethmaccrc32checker_syncfifo_source_last; +wire [7:0] main_liteethmaccrc32checker_syncfifo_source_payload_data; +wire main_liteethmaccrc32checker_syncfifo_source_payload_error; +wire main_liteethmaccrc32checker_syncfifo_source_payload_last_be; +reg main_liteethmaccrc32checker_syncfifo_source_ready = 1'd0; +wire main_liteethmaccrc32checker_syncfifo_source_valid; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_din; +wire [11:0] main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_re; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_we; +wire main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +reg [2:0] main_liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_r; +wire [11:0] main_liteethmaccrc32checker_syncfifo_wrport_dat_w; +wire main_liteethmaccrc32checker_syncfifo_wrport_we; +reg main_maccore_ethphy__r_re = 1'd0; +reg main_maccore_ethphy__r_status = 1'd0; +wire main_maccore_ethphy__r_we; +reg main_maccore_ethphy__w_re = 1'd0; +reg [2:0] main_maccore_ethphy__w_storage = 3'd0; +reg main_maccore_ethphy_clock_speed = 1'd0; +wire main_maccore_ethphy_data_oe; +wire main_maccore_ethphy_data_r; +wire main_maccore_ethphy_data_w; +reg main_maccore_ethphy_duplex_status = 1'd0; +wire main_maccore_ethphy_eth_tx_clk_o; +wire main_maccore_ethphy_last; +reg main_maccore_ethphy_link_status = 1'd0; +wire main_maccore_ethphy_mdc; +wire main_maccore_ethphy_oe; +reg main_maccore_ethphy_r = 1'd0; +reg main_maccore_ethphy_re = 1'd0; +wire main_maccore_ethphy_reset; +reg main_maccore_ethphy_reset_re = 1'd0; +reg main_maccore_ethphy_reset_storage = 1'd0; +wire [1:0] main_maccore_ethphy_rx_ctl; +wire main_maccore_ethphy_rx_ctl_delayf; +reg [1:0] main_maccore_ethphy_rx_ctl_reg = 2'd0; +reg [1:0] main_maccore_ethphy_rx_ctl_reg_d = 2'd0; +wire [7:0] main_maccore_ethphy_rx_data; +wire [3:0] main_maccore_ethphy_rx_data_delayf; +reg [7:0] main_maccore_ethphy_rx_data_reg = 8'd0; +wire main_maccore_ethphy_sink_first; +wire main_maccore_ethphy_sink_last; +wire [7:0] main_maccore_ethphy_sink_payload_data; +wire main_maccore_ethphy_sink_payload_error; +wire main_maccore_ethphy_sink_payload_last_be; +wire main_maccore_ethphy_sink_ready; +wire main_maccore_ethphy_sink_valid; +reg main_maccore_ethphy_source_first = 1'd0; +wire main_maccore_ethphy_source_last; +reg [7:0] main_maccore_ethphy_source_payload_data = 8'd0; +reg main_maccore_ethphy_source_payload_error = 1'd0; +reg main_maccore_ethphy_source_payload_last_be = 1'd0; +wire main_maccore_ethphy_source_ready; +reg main_maccore_ethphy_source_valid = 1'd0; +reg [2:0] main_maccore_ethphy_status = 3'd0; +wire main_maccore_ethphy_tx_ctl_oddrx1f; +wire [3:0] main_maccore_ethphy_tx_data_oddrx1f; +wire main_maccore_ethphy_w; +wire main_maccore_ethphy_we; +reg main_maccore_int_rst = 1'd1; +wire main_maccore_maccore_bus_error; +reg [31:0] main_maccore_maccore_bus_errors = 32'd0; +reg main_maccore_maccore_bus_errors_re = 1'd0; +wire [31:0] main_maccore_maccore_bus_errors_status; +wire main_maccore_maccore_bus_errors_we; +wire main_maccore_maccore_cpu_rst; +reg main_maccore_maccore_reset_re = 1'd0; +reg [1:0] main_maccore_maccore_reset_storage = 2'd0; +reg main_maccore_maccore_scratch_re = 1'd0; +reg [31:0] main_maccore_maccore_scratch_storage = 32'd305419896; +reg main_maccore_maccore_soc_rst = 1'd0; +reg main_preamble_errors_re = 1'd0; +reg [31:0] main_preamble_errors_status = 32'd0; +wire main_preamble_errors_we; +wire main_pulsesynchronizer0_i; +wire main_pulsesynchronizer0_o; +reg main_pulsesynchronizer0_toggle_i = 1'd0; +wire main_pulsesynchronizer0_toggle_o; +reg main_pulsesynchronizer0_toggle_o_r = 1'd0; +wire main_pulsesynchronizer1_i; +wire main_pulsesynchronizer1_o; +reg main_pulsesynchronizer1_toggle_i = 1'd0; +wire main_pulsesynchronizer1_toggle_o; +reg main_pulsesynchronizer1_toggle_o_r = 1'd0; +reg [31:0] main_rd_data = 32'd0; +reg main_re = 1'd0; +reg main_read = 1'd0; +wire [41:0] main_rx_cdc_cdc_asyncfifo_din; +wire [41:0] main_rx_cdc_cdc_asyncfifo_dout; +wire main_rx_cdc_cdc_asyncfifo_re; +wire main_rx_cdc_cdc_asyncfifo_readable; +wire main_rx_cdc_cdc_asyncfifo_we; +wire main_rx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_rx_cdc_cdc_consume_wdomain; +wire main_rx_cdc_cdc_fifo_in_first; +wire main_rx_cdc_cdc_fifo_in_last; +wire [31:0] main_rx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_in_payload_last_be; +wire main_rx_cdc_cdc_fifo_out_first; +wire main_rx_cdc_cdc_fifo_out_last; +wire [31:0] main_rx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_rx_cdc_cdc_fifo_out_payload_last_be; +wire main_rx_cdc_cdc_graycounter0_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_rx_cdc_cdc_graycounter1_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_rx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_rx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_rx_cdc_cdc_produce_rdomain; +wire [4:0] main_rx_cdc_cdc_rdport_adr; +wire [41:0] main_rx_cdc_cdc_rdport_dat_r; +wire main_rx_cdc_cdc_sink_first; +wire main_rx_cdc_cdc_sink_last; +wire [31:0] main_rx_cdc_cdc_sink_payload_data; +wire [3:0] main_rx_cdc_cdc_sink_payload_error; +wire [3:0] main_rx_cdc_cdc_sink_payload_last_be; +wire main_rx_cdc_cdc_sink_ready; +wire main_rx_cdc_cdc_sink_valid; +wire main_rx_cdc_cdc_source_first; +wire main_rx_cdc_cdc_source_last; +wire [31:0] main_rx_cdc_cdc_source_payload_data; +wire [3:0] main_rx_cdc_cdc_source_payload_error; +wire [3:0] main_rx_cdc_cdc_source_payload_last_be; +wire main_rx_cdc_cdc_source_ready; +wire main_rx_cdc_cdc_source_valid; +wire [4:0] main_rx_cdc_cdc_wrport_adr; +wire [41:0] main_rx_cdc_cdc_wrport_dat_r; +wire [41:0] main_rx_cdc_cdc_wrport_dat_w; +wire main_rx_cdc_cdc_wrport_we; +wire main_rx_cdc_sink_sink_first; +wire main_rx_cdc_sink_sink_last; +wire [31:0] main_rx_cdc_sink_sink_payload_data; +wire [3:0] main_rx_cdc_sink_sink_payload_error; +wire [3:0] main_rx_cdc_sink_sink_payload_last_be; +wire main_rx_cdc_sink_sink_ready; +wire main_rx_cdc_sink_sink_valid; +wire main_rx_cdc_source_source_first; +wire main_rx_cdc_source_source_last; +wire [31:0] main_rx_cdc_source_source_payload_data; +wire [3:0] main_rx_cdc_source_source_payload_error; +wire [3:0] main_rx_cdc_source_source_payload_last_be; +wire main_rx_cdc_source_source_ready; +wire main_rx_cdc_source_source_valid; +reg [1:0] main_rx_converter_converter_demux = 2'd0; +wire main_rx_converter_converter_load_part; +wire main_rx_converter_converter_sink_first; +wire main_rx_converter_converter_sink_last; +wire [9:0] main_rx_converter_converter_sink_payload_data; +wire main_rx_converter_converter_sink_ready; +wire main_rx_converter_converter_sink_valid; +reg main_rx_converter_converter_source_first = 1'd0; +reg main_rx_converter_converter_source_last = 1'd0; +reg [39:0] main_rx_converter_converter_source_payload_data = 40'd0; +reg [2:0] main_rx_converter_converter_source_payload_valid_token_count = 3'd0; +wire main_rx_converter_converter_source_ready; +wire main_rx_converter_converter_source_valid; +reg main_rx_converter_converter_strobe_all = 1'd0; +wire main_rx_converter_sink_first; +wire main_rx_converter_sink_last; +wire [7:0] main_rx_converter_sink_payload_data; +wire main_rx_converter_sink_payload_error; +wire main_rx_converter_sink_payload_last_be; +wire main_rx_converter_sink_ready; +wire main_rx_converter_sink_valid; +wire main_rx_converter_source_first; +wire main_rx_converter_source_last; +reg [31:0] main_rx_converter_source_payload_data = 32'd0; +reg [3:0] main_rx_converter_source_payload_error = 4'd0; +reg [3:0] main_rx_converter_source_payload_last_be = 4'd0; +wire main_rx_converter_source_ready; +wire main_rx_converter_source_source_first; +wire main_rx_converter_source_source_last; +wire [39:0] main_rx_converter_source_source_payload_data; +wire main_rx_converter_source_source_ready; +wire main_rx_converter_source_source_valid; +wire main_rx_converter_source_valid; +wire main_rx_last_be_sink_first; +wire main_rx_last_be_sink_last; +wire [7:0] main_rx_last_be_sink_payload_data; +wire main_rx_last_be_sink_payload_error; +wire main_rx_last_be_sink_payload_last_be; +wire main_rx_last_be_sink_ready; +wire main_rx_last_be_sink_valid; +wire main_rx_last_be_source_first; +wire main_rx_last_be_source_last; +wire [7:0] main_rx_last_be_source_payload_data; +wire main_rx_last_be_source_payload_error; +reg main_rx_last_be_source_payload_last_be = 1'd0; +wire main_rx_last_be_source_ready; +wire main_rx_last_be_source_valid; +wire main_rx_padding_sink_first; +wire main_rx_padding_sink_last; +wire [7:0] main_rx_padding_sink_payload_data; +wire main_rx_padding_sink_payload_error; +wire main_rx_padding_sink_payload_last_be; +wire main_rx_padding_sink_ready; +wire main_rx_padding_sink_valid; +wire main_rx_padding_source_first; +wire main_rx_padding_source_last; +wire [7:0] main_rx_padding_source_payload_data; +wire main_rx_padding_source_payload_error; +wire main_rx_padding_source_payload_last_be; +wire main_rx_padding_source_ready; +wire main_rx_padding_source_valid; +reg main_rx_preamble_error = 1'd0; +reg [63:0] main_rx_preamble_preamble = 64'd15372286728091293013; +wire main_rx_preamble_sink_first; +wire main_rx_preamble_sink_last; +wire [7:0] main_rx_preamble_sink_payload_data; +wire main_rx_preamble_sink_payload_error; +wire main_rx_preamble_sink_payload_last_be; +reg main_rx_preamble_sink_ready = 1'd0; +wire main_rx_preamble_sink_valid; +reg main_rx_preamble_source_first = 1'd0; +reg main_rx_preamble_source_last = 1'd0; +wire [7:0] main_rx_preamble_source_payload_data; +reg main_rx_preamble_source_payload_error = 1'd0; +wire main_rx_preamble_source_payload_last_be; +wire main_rx_preamble_source_ready; +reg main_rx_preamble_source_valid = 1'd0; +wire main_sink_first; +wire main_sink_last; +wire [31:0] main_sink_payload_data; +wire [3:0] main_sink_payload_error; +wire [3:0] main_sink_payload_last_be; +wire main_sink_ready; +wire main_sink_sink_first; +wire main_sink_sink_last; +wire [31:0] main_sink_sink_payload_data; +wire [3:0] main_sink_sink_payload_error; +wire [3:0] main_sink_sink_payload_last_be; +wire main_sink_sink_ready; +wire main_sink_sink_valid; +wire main_sink_valid; +reg [3:0] main_slave_sel = 4'd0; +reg [3:0] main_slave_sel_r = 4'd0; +reg main_slot = 1'd0; +reg main_slot_liteethmacsramwriter_next_value = 1'd0; +reg main_slot_liteethmacsramwriter_next_value_ce = 1'd0; +wire main_source_first; +wire main_source_last; +wire [31:0] main_source_payload_data; +wire [3:0] main_source_payload_error; +wire [3:0] main_source_payload_last_be; +wire main_source_ready; +wire main_source_source_first; +wire main_source_source_last; +wire [31:0] main_source_source_payload_data; +wire [3:0] main_source_source_payload_error; +wire [3:0] main_source_source_payload_last_be; +wire main_source_source_ready; +wire main_source_source_valid; +wire main_source_valid; +wire [8:0] main_sram0_adr; +reg main_sram0_adr_burst = 1'd0; +wire [31:0] main_sram0_dat_r; +wire main_sram0_sink_valid; +reg main_sram100_storage = 1'd0; +reg main_sram101_re = 1'd0; +reg [10:0] main_sram102_storage = 11'd0; +reg main_sram103_re = 1'd0; +wire main_sram104_irq; +wire main_sram105_status; +reg main_sram106_pending = 1'd0; +reg main_sram107_trigger = 1'd0; +reg main_sram108_clear = 1'd0; +wire main_sram109_event0; +wire [10:0] main_sram10_status; +reg main_sram110_status = 1'd0; +wire main_sram111_we; +reg main_sram112_re = 1'd0; +wire main_sram113_event0; +reg main_sram114_status = 1'd0; +wire main_sram115_we; +reg main_sram116_re = 1'd0; +reg main_sram117_r = 1'd0; +wire main_sram118_event0; +reg main_sram119_storage = 1'd0; +wire main_sram11_we; +reg main_sram120_re = 1'd0; +reg [10:0] main_sram122_length = 11'd0; +reg [10:0] main_sram122_length_liteethmacsramreader_next_value = 11'd0; +reg main_sram122_length_liteethmacsramreader_next_value_ce = 1'd0; +wire main_sram123_sink_valid; +wire main_sram124_sink_ready; +reg main_sram125_sink_first = 1'd0; +reg main_sram126_sink_last = 1'd0; +wire main_sram127_sink_payload_slot; +wire [10:0] main_sram128_sink_payload_length; +wire main_sram129_source_valid; +reg main_sram12_re = 1'd0; +reg main_sram130_source_ready = 1'd0; +wire main_sram131_source_first; +wire main_sram132_source_last; +wire main_sram133_source_payload_slot; +wire [10:0] main_sram134_source_payload_length; +wire main_sram135_we; +wire main_sram136_writable; +wire main_sram137_re; +wire main_sram138_readable; +wire [13:0] main_sram139_din; +reg [31:0] main_sram13_status = 32'd0; +reg [31:0] main_sram13_status_liteethmacsramwriter_f_next_value = 32'd0; +reg main_sram13_status_liteethmacsramwriter_f_next_value_ce = 1'd0; +wire [13:0] main_sram140_dout; +reg [1:0] main_sram141_level = 2'd0; +reg main_sram142_replace = 1'd0; +reg main_sram143_produce = 1'd0; +reg main_sram144_consume = 1'd0; +reg main_sram145_adr = 1'd0; +wire [13:0] main_sram146_dat_r; +wire main_sram147_we; +wire [13:0] main_sram148_dat_w; +wire main_sram149_do_read; +wire main_sram14_we; +wire main_sram150_adr; +wire [13:0] main_sram151_dat_r; +wire main_sram152_fifo_in_payload_slot; +wire [10:0] main_sram153_fifo_in_payload_length; +wire main_sram154_fifo_in_first; +wire main_sram155_fifo_in_last; +wire main_sram156_fifo_out_payload_slot; +wire [10:0] main_sram157_fifo_out_payload_length; +wire main_sram158_fifo_out_first; +wire main_sram159_fifo_out_last; +reg main_sram15_re = 1'd0; +wire [8:0] main_sram161_adr; +wire [31:0] main_sram162_dat_r; +wire main_sram163_re; +wire [8:0] main_sram164_adr; +wire [31:0] main_sram165_dat_r; +wire main_sram166_re; +wire main_sram167_irq; +wire main_sram16_irq; +wire main_sram17_status; +wire main_sram18_pending; +wire main_sram19_trigger; +wire [8:0] main_sram1_adr; +reg main_sram1_adr_burst = 1'd0; +wire [31:0] main_sram1_dat_r; +reg main_sram1_sink_ready = 1'd1; +reg main_sram20_clear = 1'd0; +wire main_sram21_available; +reg main_sram22_status = 1'd0; +wire main_sram23_we; +reg main_sram24_re = 1'd0; +wire main_sram25_available; +reg main_sram26_status = 1'd0; +wire main_sram27_we; +reg main_sram28_re = 1'd0; +reg main_sram29_r = 1'd0; +wire [8:0] main_sram2_adr; +reg main_sram2_adr_burst = 1'd0; +wire [31:0] main_sram2_dat_r; +wire [31:0] main_sram2_dat_w; +wire main_sram2_sink_first; +reg [3:0] main_sram2_we = 4'd0; +wire main_sram30_available; +reg main_sram31_storage = 1'd0; +reg main_sram32_re = 1'd0; +reg [10:0] main_sram35_length = 11'd0; +reg [10:0] main_sram35_length_liteethmacsramwriter_t_next_value = 11'd0; +reg main_sram35_length_liteethmacsramwriter_t_next_value_ce = 1'd0; +reg main_sram37_sink_valid = 1'd0; +wire main_sram38_sink_ready; +reg main_sram39_sink_first = 1'd0; +wire [8:0] main_sram3_adr; +reg main_sram3_adr_burst = 1'd0; +wire [31:0] main_sram3_dat_r; +wire [31:0] main_sram3_dat_w; +wire main_sram3_sink_last; +reg [3:0] main_sram3_we = 4'd0; +reg main_sram40_sink_last = 1'd0; +reg main_sram41_sink_payload_slot = 1'd0; +reg [10:0] main_sram42_sink_payload_length = 11'd0; +wire main_sram43_source_valid; +wire main_sram44_source_ready; +wire main_sram45_source_first; +wire main_sram46_source_last; +wire main_sram47_source_payload_slot; +wire [10:0] main_sram48_source_payload_length; +wire main_sram49_we; +wire [31:0] main_sram4_sink_payload_data; +wire main_sram50_writable; +wire main_sram51_re; +wire main_sram52_readable; +wire [13:0] main_sram53_din; +wire [13:0] main_sram54_dout; +reg [1:0] main_sram55_level = 2'd0; +reg main_sram56_replace = 1'd0; +reg main_sram57_produce = 1'd0; +reg main_sram58_consume = 1'd0; +reg main_sram59_adr = 1'd0; +wire [3:0] main_sram5_sink_payload_last_be; +wire [13:0] main_sram60_dat_r; +wire main_sram61_we; +wire [13:0] main_sram62_dat_w; +wire main_sram63_do_read; +wire main_sram64_adr; +wire [13:0] main_sram65_dat_r; +wire main_sram66_fifo_in_payload_slot; +wire [10:0] main_sram67_fifo_in_payload_length; +wire main_sram68_fifo_in_first; +wire main_sram69_fifo_in_last; +wire [3:0] main_sram6_sink_payload_error; +wire main_sram70_fifo_out_payload_slot; +wire [10:0] main_sram71_fifo_out_payload_length; +wire main_sram72_fifo_out_first; +wire main_sram73_fifo_out_last; +reg [8:0] main_sram75_adr = 9'd0; +wire [31:0] main_sram76_dat_r; +reg main_sram77_we = 1'd0; +reg [31:0] main_sram78_dat_w = 32'd0; +reg [8:0] main_sram79_adr = 9'd0; +wire main_sram7_status; +wire [31:0] main_sram80_dat_r; +reg main_sram81_we = 1'd0; +reg [31:0] main_sram82_dat_w = 32'd0; +reg main_sram83_source_valid = 1'd0; +wire main_sram84_source_ready; +reg main_sram85_source_first = 1'd0; +reg main_sram86_source_last = 1'd0; +wire [31:0] main_sram87_source_payload_data; +reg [3:0] main_sram88_source_payload_last_be = 4'd0; +reg [3:0] main_sram89_source_payload_error = 4'd0; +wire main_sram8_we; +wire main_sram94_status; +wire main_sram95_we; +reg main_sram96_re = 1'd0; +wire [1:0] main_sram97_status; +wire main_sram98_we; +reg main_sram99_re = 1'd0; +reg main_sram9_re = 1'd0; +wire main_start_r; +reg main_start_re = 1'd0; +reg main_start_w = 1'd0; +reg main_start_we = 1'd0; +reg main_status = 1'd1; +wire [41:0] main_tx_cdc_cdc_asyncfifo_din; +wire [41:0] main_tx_cdc_cdc_asyncfifo_dout; +wire main_tx_cdc_cdc_asyncfifo_re; +wire main_tx_cdc_cdc_asyncfifo_readable; +wire main_tx_cdc_cdc_asyncfifo_we; +wire main_tx_cdc_cdc_asyncfifo_writable; +wire [5:0] main_tx_cdc_cdc_consume_wdomain; +wire main_tx_cdc_cdc_fifo_in_first; +wire main_tx_cdc_cdc_fifo_in_last; +wire [31:0] main_tx_cdc_cdc_fifo_in_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_in_payload_last_be; +wire main_tx_cdc_cdc_fifo_out_first; +wire main_tx_cdc_cdc_fifo_out_last; +wire [31:0] main_tx_cdc_cdc_fifo_out_payload_data; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_error; +wire [3:0] main_tx_cdc_cdc_fifo_out_payload_last_be; +wire main_tx_cdc_cdc_graycounter0_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter0_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter0_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter0_q_next_binary = 6'd0; +wire main_tx_cdc_cdc_graycounter1_ce; +(* syn_no_retiming = "true" *) +reg [5:0] main_tx_cdc_cdc_graycounter1_q = 6'd0; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_graycounter1_q_next; +reg [5:0] main_tx_cdc_cdc_graycounter1_q_next_binary = 6'd0; +wire [5:0] main_tx_cdc_cdc_produce_rdomain; +wire [4:0] main_tx_cdc_cdc_rdport_adr; +wire [41:0] main_tx_cdc_cdc_rdport_dat_r; +wire main_tx_cdc_cdc_sink_first; +wire main_tx_cdc_cdc_sink_last; +wire [31:0] main_tx_cdc_cdc_sink_payload_data; +wire [3:0] main_tx_cdc_cdc_sink_payload_error; +wire [3:0] main_tx_cdc_cdc_sink_payload_last_be; +wire main_tx_cdc_cdc_sink_ready; +wire main_tx_cdc_cdc_sink_valid; +wire main_tx_cdc_cdc_source_first; +wire main_tx_cdc_cdc_source_last; +wire [31:0] main_tx_cdc_cdc_source_payload_data; +wire [3:0] main_tx_cdc_cdc_source_payload_error; +wire [3:0] main_tx_cdc_cdc_source_payload_last_be; +wire main_tx_cdc_cdc_source_ready; +wire main_tx_cdc_cdc_source_valid; +wire [4:0] main_tx_cdc_cdc_wrport_adr; +wire [41:0] main_tx_cdc_cdc_wrport_dat_r; +wire [41:0] main_tx_cdc_cdc_wrport_dat_w; +wire main_tx_cdc_cdc_wrport_we; +wire main_tx_cdc_sink_sink_first; +wire main_tx_cdc_sink_sink_last; +wire [31:0] main_tx_cdc_sink_sink_payload_data; +wire [3:0] main_tx_cdc_sink_sink_payload_error; +wire [3:0] main_tx_cdc_sink_sink_payload_last_be; +wire main_tx_cdc_sink_sink_ready; +wire main_tx_cdc_sink_sink_valid; +wire main_tx_cdc_source_source_first; +wire main_tx_cdc_source_source_last; +wire [31:0] main_tx_cdc_source_source_payload_data; +wire [3:0] main_tx_cdc_source_source_payload_error; +wire [3:0] main_tx_cdc_source_source_payload_last_be; +wire main_tx_cdc_source_source_ready; +wire main_tx_cdc_source_source_valid; +wire main_tx_converter_converter_first; +wire main_tx_converter_converter_last; +reg [1:0] main_tx_converter_converter_mux = 2'd0; +wire main_tx_converter_converter_sink_first; +wire main_tx_converter_converter_sink_last; +reg [39:0] main_tx_converter_converter_sink_payload_data = 40'd0; +wire main_tx_converter_converter_sink_ready; +wire main_tx_converter_converter_sink_valid; +wire main_tx_converter_converter_source_first; +wire main_tx_converter_converter_source_last; +reg [9:0] main_tx_converter_converter_source_payload_data = 10'd0; +wire main_tx_converter_converter_source_payload_valid_token_count; +wire main_tx_converter_converter_source_ready; +wire main_tx_converter_converter_source_valid; +wire main_tx_converter_sink_first; +wire main_tx_converter_sink_last; +wire [31:0] main_tx_converter_sink_payload_data; +wire [3:0] main_tx_converter_sink_payload_error; +wire [3:0] main_tx_converter_sink_payload_last_be; +wire main_tx_converter_sink_ready; +wire main_tx_converter_sink_valid; +wire main_tx_converter_source_first; +wire main_tx_converter_source_last; +wire [7:0] main_tx_converter_source_payload_data; +wire main_tx_converter_source_payload_error; +wire main_tx_converter_source_payload_last_be; +wire main_tx_converter_source_ready; +wire main_tx_converter_source_source_first; +wire main_tx_converter_source_source_last; +wire [9:0] main_tx_converter_source_source_payload_data; +wire main_tx_converter_source_source_ready; +wire main_tx_converter_source_source_valid; +wire main_tx_converter_source_valid; +wire main_tx_crc_be; +reg main_tx_crc_ce = 1'd0; +reg [1:0] main_tx_crc_cnt = 2'd3; +wire main_tx_crc_cnt_done; +reg [31:0] main_tx_crc_crc_next = 32'd0; +reg [31:0] main_tx_crc_crc_packet = 32'd0; +reg [31:0] main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 = 32'd0; +reg main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 = 1'd0; +wire [31:0] main_tx_crc_crc_prev; +wire [7:0] main_tx_crc_data0; +wire [7:0] main_tx_crc_data1; +reg main_tx_crc_error = 1'd0; +reg main_tx_crc_is_ongoing0 = 1'd0; +reg main_tx_crc_is_ongoing1 = 1'd0; +reg main_tx_crc_last_be = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value1 = 1'd0; +reg main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 = 1'd0; +wire main_tx_crc_pipe_valid_sink_first; +wire main_tx_crc_pipe_valid_sink_last; +wire [7:0] main_tx_crc_pipe_valid_sink_payload_data; +wire main_tx_crc_pipe_valid_sink_payload_error; +wire main_tx_crc_pipe_valid_sink_payload_last_be; +wire main_tx_crc_pipe_valid_sink_ready; +wire main_tx_crc_pipe_valid_sink_valid; +reg main_tx_crc_pipe_valid_source_first = 1'd0; +reg main_tx_crc_pipe_valid_source_last = 1'd0; +reg [7:0] main_tx_crc_pipe_valid_source_payload_data = 8'd0; +reg main_tx_crc_pipe_valid_source_payload_error = 1'd0; +reg main_tx_crc_pipe_valid_source_payload_last_be = 1'd0; +wire main_tx_crc_pipe_valid_source_ready; +reg main_tx_crc_pipe_valid_source_valid = 1'd0; +reg [31:0] main_tx_crc_reg = 32'd4294967295; +reg main_tx_crc_reset = 1'd0; +wire main_tx_crc_sink_first; +wire main_tx_crc_sink_last; +wire [7:0] main_tx_crc_sink_payload_data; +wire main_tx_crc_sink_payload_error; +wire main_tx_crc_sink_payload_last_be; +reg main_tx_crc_sink_ready = 1'd0; +wire main_tx_crc_sink_sink_first; +wire main_tx_crc_sink_sink_last; +wire [7:0] main_tx_crc_sink_sink_payload_data; +wire main_tx_crc_sink_sink_payload_error; +wire main_tx_crc_sink_sink_payload_last_be; +wire main_tx_crc_sink_sink_ready; +wire main_tx_crc_sink_sink_valid; +wire main_tx_crc_sink_valid; +reg main_tx_crc_source_first = 1'd0; +reg main_tx_crc_source_last = 1'd0; +reg [7:0] main_tx_crc_source_payload_data = 8'd0; +reg main_tx_crc_source_payload_error = 1'd0; +reg main_tx_crc_source_payload_last_be = 1'd0; +wire main_tx_crc_source_ready; +wire main_tx_crc_source_source_first; +wire main_tx_crc_source_source_last; +wire [7:0] main_tx_crc_source_source_payload_data; +wire main_tx_crc_source_source_payload_error; +wire main_tx_crc_source_source_payload_last_be; +wire main_tx_crc_source_source_ready; +wire main_tx_crc_source_source_valid; +reg main_tx_crc_source_valid = 1'd0; +reg [31:0] main_tx_crc_value = 32'd0; +reg [3:0] main_tx_gap_counter = 4'd0; +reg [3:0] main_tx_gap_counter_clockdomainsrenamer3_next_value = 4'd0; +reg main_tx_gap_counter_clockdomainsrenamer3_next_value_ce = 1'd0; +wire main_tx_gap_sink_first; +wire main_tx_gap_sink_last; +wire [7:0] main_tx_gap_sink_payload_data; +wire main_tx_gap_sink_payload_error; +wire main_tx_gap_sink_payload_last_be; +reg main_tx_gap_sink_ready = 1'd0; +wire main_tx_gap_sink_valid; +reg main_tx_gap_source_first = 1'd0; +reg main_tx_gap_source_last = 1'd0; +reg [7:0] main_tx_gap_source_payload_data = 8'd0; +reg main_tx_gap_source_payload_error = 1'd0; +reg main_tx_gap_source_payload_last_be = 1'd0; +wire main_tx_gap_source_ready; +reg main_tx_gap_source_valid = 1'd0; +wire main_tx_last_be_sink_first; +wire main_tx_last_be_sink_last; +wire [7:0] main_tx_last_be_sink_payload_data; +wire main_tx_last_be_sink_payload_error; +wire main_tx_last_be_sink_payload_last_be; +reg main_tx_last_be_sink_ready = 1'd0; +wire main_tx_last_be_sink_valid; +reg main_tx_last_be_source_first = 1'd0; +reg main_tx_last_be_source_last = 1'd0; +reg [7:0] main_tx_last_be_source_payload_data = 8'd0; +reg main_tx_last_be_source_payload_error = 1'd0; +reg main_tx_last_be_source_payload_last_be = 1'd0; +wire main_tx_last_be_source_ready; +reg main_tx_last_be_source_valid = 1'd0; +reg [15:0] main_tx_padding_counter = 16'd0; +reg [15:0] main_tx_padding_counter_clockdomainsrenamer0_next_value = 16'd0; +reg main_tx_padding_counter_clockdomainsrenamer0_next_value_ce = 1'd0; +wire main_tx_padding_counter_done; +wire main_tx_padding_sink_first; +wire main_tx_padding_sink_last; +wire [7:0] main_tx_padding_sink_payload_data; +wire main_tx_padding_sink_payload_error; +wire main_tx_padding_sink_payload_last_be; +reg main_tx_padding_sink_ready = 1'd0; +wire main_tx_padding_sink_valid; +reg main_tx_padding_source_first = 1'd0; +reg main_tx_padding_source_last = 1'd0; +reg [7:0] main_tx_padding_source_payload_data = 8'd0; +reg main_tx_padding_source_payload_error = 1'd0; +reg main_tx_padding_source_payload_last_be = 1'd0; +wire main_tx_padding_source_ready; +reg main_tx_padding_source_valid = 1'd0; +reg [2:0] main_tx_preamble_count = 3'd0; +reg [2:0] main_tx_preamble_count_clockdomainsrenamer2_next_value = 3'd0; +reg main_tx_preamble_count_clockdomainsrenamer2_next_value_ce = 1'd0; +reg [63:0] main_tx_preamble_preamble = 64'd15372286728091293013; +wire main_tx_preamble_sink_first; +wire main_tx_preamble_sink_last; +wire [7:0] main_tx_preamble_sink_payload_data; +wire main_tx_preamble_sink_payload_error; +wire main_tx_preamble_sink_payload_last_be; +reg main_tx_preamble_sink_ready = 1'd0; +wire main_tx_preamble_sink_valid; +reg main_tx_preamble_source_first = 1'd0; +reg main_tx_preamble_source_last = 1'd0; +reg [7:0] main_tx_preamble_source_payload_data = 8'd0; +reg main_tx_preamble_source_payload_error = 1'd0; +wire main_tx_preamble_source_payload_last_be; +wire main_tx_preamble_source_ready; +reg main_tx_preamble_source_valid = 1'd0; +wire main_wb_bus_ack; +wire [29:0] main_wb_bus_adr; +wire [1:0] main_wb_bus_bte; +wire [2:0] main_wb_bus_cti; +wire main_wb_bus_cyc; +wire [31:0] main_wb_bus_dat_r; +wire [31:0] main_wb_bus_dat_w; +wire main_wb_bus_err; +wire [3:0] main_wb_bus_sel; +wire main_wb_bus_stb; +wire main_wb_bus_we; +wire main_we; +wire [31:0] main_wr_data; +reg main_write = 1'd0; +wire por_clk; +(* syn_keep = "true" *) +wire sys_clk; +wire sys_rst; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_wb_bus_adr = wishbone_adr; +assign main_wb_bus_dat_w = wishbone_dat_w; +assign wishbone_dat_r = main_wb_bus_dat_r; +assign main_wb_bus_sel = wishbone_sel; +assign main_wb_bus_cyc = wishbone_cyc; +assign main_wb_bus_stb = wishbone_stb; +assign wishbone_ack = main_wb_bus_ack; +assign main_wb_bus_we = wishbone_we; +assign main_wb_bus_cti = wishbone_cti; +assign main_wb_bus_bte = wishbone_bte; +assign wishbone_err = main_wb_bus_err; +assign interrupt = main_sram167_irq; +assign main_maccore_maccore_bus_error = builder_error; +assign builder_shared_adr = builder_self0; +assign builder_shared_dat_w = builder_self1; +assign builder_shared_sel = builder_self2; +assign builder_shared_cyc = builder_self3; +assign builder_shared_stb = builder_self4; +assign builder_shared_we = builder_self5; +assign builder_shared_cti = builder_self6; +assign builder_shared_bte = builder_self7; +assign main_wb_bus_dat_r = builder_shared_dat_r; +assign main_wb_bus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_wb_bus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign builder_request = {main_wb_bus_cyc}; +assign builder_grant = 1'd0; +always @(*) begin + builder_slave_sel <= 2'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:11] == 4'd8); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd0); +end +assign main_bus_adr = builder_shared_adr; +assign main_bus_dat_w = builder_shared_dat_w; +assign main_bus_sel = builder_shared_sel; +assign main_bus_stb = builder_shared_stb; +assign main_bus_we = builder_shared_we; +assign main_bus_cti = builder_shared_cti; +assign main_bus_bte = builder_shared_bte; +assign builder_interface0_adr = builder_shared_adr; +assign builder_interface0_dat_w = builder_shared_dat_w; +assign builder_interface0_sel = builder_shared_sel; +assign builder_interface0_stb = builder_shared_stb; +assign builder_interface0_we = builder_shared_we; +assign builder_interface0_cti = builder_shared_cti; +assign builder_interface0_bte = builder_shared_bte; +assign main_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign builder_interface0_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign builder_shared_err = (main_bus_err | builder_interface0_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (main_bus_ack | builder_interface0_ack); + builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_interface0_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign main_maccore_maccore_bus_errors_status = main_maccore_maccore_bus_errors; +assign sys_clk = sys_clock; +assign por_clk = sys_clock; +assign sys_rst = main_maccore_int_rst; +assign eth_rx_clk = rgmii_clocks_rx; +assign eth_tx_clk = eth_rx_clk; +assign main_maccore_ethphy_reset = main_maccore_ethphy_reset_storage; +assign rgmii_rst_n = (~main_maccore_ethphy_reset); +assign main_maccore_ethphy_sink_ready = 1'd1; +assign main_maccore_ethphy_last = ((~main_maccore_ethphy_rx_ctl_reg[0]) & main_maccore_ethphy_rx_ctl_reg_d[0]); +assign main_maccore_ethphy_source_last = main_maccore_ethphy_last; +assign rgmii_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_data_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_data_w = main_maccore_ethphy__w_storage[2]; +assign main_sink_valid = main_source_source_valid; +assign main_source_source_ready = main_sink_ready; +assign main_sink_first = main_source_source_first; +assign main_sink_last = main_source_source_last; +assign main_sink_payload_data = main_source_source_payload_data; +assign main_sink_payload_last_be = main_source_source_payload_last_be; +assign main_sink_payload_error = main_source_source_payload_error; +assign main_sink_sink_valid = main_source_valid; +assign main_source_ready = main_sink_sink_ready; +assign main_sink_sink_first = main_source_first; +assign main_sink_sink_last = main_source_last; +assign main_sink_sink_payload_data = main_source_payload_data; +assign main_sink_sink_payload_last_be = main_source_payload_last_be; +assign main_sink_sink_payload_error = main_source_payload_error; +assign main_tx_cdc_cdc_sink_valid = main_tx_cdc_sink_sink_valid; +assign main_tx_cdc_sink_sink_ready = main_tx_cdc_cdc_sink_ready; +assign main_tx_cdc_cdc_sink_first = main_tx_cdc_sink_sink_first; +assign main_tx_cdc_cdc_sink_last = main_tx_cdc_sink_sink_last; +assign main_tx_cdc_cdc_sink_payload_data = main_tx_cdc_sink_sink_payload_data; +assign main_tx_cdc_cdc_sink_payload_last_be = main_tx_cdc_sink_sink_payload_last_be; +assign main_tx_cdc_cdc_sink_payload_error = main_tx_cdc_sink_sink_payload_error; +assign main_tx_cdc_source_source_valid = main_tx_cdc_cdc_source_valid; +assign main_tx_cdc_cdc_source_ready = main_tx_cdc_source_source_ready; +assign main_tx_cdc_source_source_first = main_tx_cdc_cdc_source_first; +assign main_tx_cdc_source_source_last = main_tx_cdc_cdc_source_last; +assign main_tx_cdc_source_source_payload_data = main_tx_cdc_cdc_source_payload_data; +assign main_tx_cdc_source_source_payload_last_be = main_tx_cdc_cdc_source_payload_last_be; +assign main_tx_cdc_source_source_payload_error = main_tx_cdc_cdc_source_payload_error; +assign main_tx_cdc_cdc_asyncfifo_din = {main_tx_cdc_cdc_fifo_in_last, main_tx_cdc_cdc_fifo_in_first, main_tx_cdc_cdc_fifo_in_payload_error, main_tx_cdc_cdc_fifo_in_payload_last_be, main_tx_cdc_cdc_fifo_in_payload_data}; +assign {main_tx_cdc_cdc_fifo_out_last, main_tx_cdc_cdc_fifo_out_first, main_tx_cdc_cdc_fifo_out_payload_error, main_tx_cdc_cdc_fifo_out_payload_last_be, main_tx_cdc_cdc_fifo_out_payload_data} = main_tx_cdc_cdc_asyncfifo_dout; +assign main_tx_cdc_cdc_sink_ready = main_tx_cdc_cdc_asyncfifo_writable; +assign main_tx_cdc_cdc_asyncfifo_we = main_tx_cdc_cdc_sink_valid; +assign main_tx_cdc_cdc_fifo_in_first = main_tx_cdc_cdc_sink_first; +assign main_tx_cdc_cdc_fifo_in_last = main_tx_cdc_cdc_sink_last; +assign main_tx_cdc_cdc_fifo_in_payload_data = main_tx_cdc_cdc_sink_payload_data; +assign main_tx_cdc_cdc_fifo_in_payload_last_be = main_tx_cdc_cdc_sink_payload_last_be; +assign main_tx_cdc_cdc_fifo_in_payload_error = main_tx_cdc_cdc_sink_payload_error; +assign main_tx_cdc_cdc_source_valid = main_tx_cdc_cdc_asyncfifo_readable; +assign main_tx_cdc_cdc_source_first = main_tx_cdc_cdc_fifo_out_first; +assign main_tx_cdc_cdc_source_last = main_tx_cdc_cdc_fifo_out_last; +assign main_tx_cdc_cdc_source_payload_data = main_tx_cdc_cdc_fifo_out_payload_data; +assign main_tx_cdc_cdc_source_payload_last_be = main_tx_cdc_cdc_fifo_out_payload_last_be; +assign main_tx_cdc_cdc_source_payload_error = main_tx_cdc_cdc_fifo_out_payload_error; +assign main_tx_cdc_cdc_asyncfifo_re = main_tx_cdc_cdc_source_ready; +assign main_tx_cdc_cdc_graycounter0_ce = (main_tx_cdc_cdc_asyncfifo_writable & main_tx_cdc_cdc_asyncfifo_we); +assign main_tx_cdc_cdc_graycounter1_ce = (main_tx_cdc_cdc_asyncfifo_readable & main_tx_cdc_cdc_asyncfifo_re); +assign main_tx_cdc_cdc_asyncfifo_writable = (((main_tx_cdc_cdc_graycounter0_q[5] == main_tx_cdc_cdc_consume_wdomain[5]) | (main_tx_cdc_cdc_graycounter0_q[4] == main_tx_cdc_cdc_consume_wdomain[4])) | (main_tx_cdc_cdc_graycounter0_q[3:0] != main_tx_cdc_cdc_consume_wdomain[3:0])); +assign main_tx_cdc_cdc_asyncfifo_readable = (main_tx_cdc_cdc_graycounter1_q != main_tx_cdc_cdc_produce_rdomain); +assign main_tx_cdc_cdc_wrport_adr = main_tx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_tx_cdc_cdc_wrport_dat_w = main_tx_cdc_cdc_asyncfifo_din; +assign main_tx_cdc_cdc_wrport_we = main_tx_cdc_cdc_graycounter0_ce; +assign main_tx_cdc_cdc_rdport_adr = main_tx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_tx_cdc_cdc_asyncfifo_dout = main_tx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter0_ce) begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= (main_tx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter0_q_next_binary <= main_tx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter0_q_next = (main_tx_cdc_cdc_graycounter0_q_next_binary ^ main_tx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_tx_cdc_cdc_graycounter1_ce) begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= (main_tx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_tx_cdc_cdc_graycounter1_q_next_binary <= main_tx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_tx_cdc_cdc_graycounter1_q_next = (main_tx_cdc_cdc_graycounter1_q_next_binary ^ main_tx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_tx_converter_converter_sink_valid = main_tx_converter_sink_valid; +assign main_tx_converter_converter_sink_first = main_tx_converter_sink_first; +assign main_tx_converter_converter_sink_last = main_tx_converter_sink_last; +assign main_tx_converter_sink_ready = main_tx_converter_converter_sink_ready; +always @(*) begin + main_tx_converter_converter_sink_payload_data <= 40'd0; + main_tx_converter_converter_sink_payload_data[7:0] <= main_tx_converter_sink_payload_data[7:0]; + main_tx_converter_converter_sink_payload_data[8] <= main_tx_converter_sink_payload_last_be[0]; + main_tx_converter_converter_sink_payload_data[9] <= main_tx_converter_sink_payload_error[0]; + main_tx_converter_converter_sink_payload_data[17:10] <= main_tx_converter_sink_payload_data[15:8]; + main_tx_converter_converter_sink_payload_data[18] <= main_tx_converter_sink_payload_last_be[1]; + main_tx_converter_converter_sink_payload_data[19] <= main_tx_converter_sink_payload_error[1]; + main_tx_converter_converter_sink_payload_data[27:20] <= main_tx_converter_sink_payload_data[23:16]; + main_tx_converter_converter_sink_payload_data[28] <= main_tx_converter_sink_payload_last_be[2]; + main_tx_converter_converter_sink_payload_data[29] <= main_tx_converter_sink_payload_error[2]; + main_tx_converter_converter_sink_payload_data[37:30] <= main_tx_converter_sink_payload_data[31:24]; + main_tx_converter_converter_sink_payload_data[38] <= main_tx_converter_sink_payload_last_be[3]; + main_tx_converter_converter_sink_payload_data[39] <= main_tx_converter_sink_payload_error[3]; +end +assign main_tx_converter_source_valid = main_tx_converter_source_source_valid; +assign main_tx_converter_source_first = main_tx_converter_source_source_first; +assign main_tx_converter_source_last = main_tx_converter_source_source_last; +assign main_tx_converter_source_source_ready = main_tx_converter_source_ready; +assign {main_tx_converter_source_payload_error, main_tx_converter_source_payload_last_be, main_tx_converter_source_payload_data} = main_tx_converter_source_source_payload_data; +assign main_tx_converter_source_source_valid = main_tx_converter_converter_source_valid; +assign main_tx_converter_converter_source_ready = main_tx_converter_source_source_ready; +assign main_tx_converter_source_source_first = main_tx_converter_converter_source_first; +assign main_tx_converter_source_source_last = main_tx_converter_converter_source_last; +assign main_tx_converter_source_source_payload_data = main_tx_converter_converter_source_payload_data; +assign main_tx_converter_converter_first = (main_tx_converter_converter_mux == 1'd0); +assign main_tx_converter_converter_last = (main_tx_converter_converter_mux == 2'd3); +assign main_tx_converter_converter_source_valid = main_tx_converter_converter_sink_valid; +assign main_tx_converter_converter_source_first = (main_tx_converter_converter_sink_first & main_tx_converter_converter_first); +assign main_tx_converter_converter_source_last = (main_tx_converter_converter_sink_last & main_tx_converter_converter_last); +assign main_tx_converter_converter_sink_ready = (main_tx_converter_converter_last & main_tx_converter_converter_source_ready); +always @(*) begin + main_tx_converter_converter_source_payload_data <= 10'd0; + case (main_tx_converter_converter_mux) + 1'd0: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[9:0]; + end + 1'd1: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[19:10]; + end + 2'd2: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[29:20]; + end + default: begin + main_tx_converter_converter_source_payload_data <= main_tx_converter_converter_sink_payload_data[39:30]; + end + endcase +end +assign main_tx_converter_converter_source_payload_valid_token_count = main_tx_converter_converter_last; +always @(*) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + main_tx_last_be_sink_ready <= 1'd0; + main_tx_last_be_source_first <= 1'd0; + main_tx_last_be_source_last <= 1'd0; + main_tx_last_be_source_payload_data <= 8'd0; + main_tx_last_be_source_payload_error <= 1'd0; + main_tx_last_be_source_payload_last_be <= 1'd0; + main_tx_last_be_source_valid <= 1'd0; + builder_txdatapath_liteethmactxlastbe_next_state <= builder_txdatapath_liteethmactxlastbe_state; + case (builder_txdatapath_liteethmactxlastbe_state) + 1'd1: begin + main_tx_last_be_sink_ready <= 1'd1; + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_last)) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd0; + end + end + default: begin + main_tx_last_be_source_valid <= main_tx_last_be_sink_valid; + main_tx_last_be_sink_ready <= main_tx_last_be_source_ready; + main_tx_last_be_source_first <= main_tx_last_be_sink_first; + main_tx_last_be_source_last <= main_tx_last_be_sink_last; + main_tx_last_be_source_payload_data <= main_tx_last_be_sink_payload_data; + main_tx_last_be_source_payload_last_be <= main_tx_last_be_sink_payload_last_be; + main_tx_last_be_source_payload_error <= main_tx_last_be_sink_payload_error; + main_tx_last_be_source_last <= (main_tx_last_be_sink_payload_last_be != 1'd0); + if ((main_tx_last_be_sink_valid & main_tx_last_be_sink_ready)) begin + if ((main_tx_last_be_source_last & (~main_tx_last_be_sink_last))) begin + builder_txdatapath_liteethmactxlastbe_next_state <= 1'd1; + end + end + end + endcase +end +assign main_tx_padding_counter_done = (main_tx_padding_counter >= 6'd59); +always @(*) begin + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 16'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd0; + main_tx_padding_sink_ready <= 1'd0; + main_tx_padding_source_first <= 1'd0; + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_data <= 8'd0; + main_tx_padding_source_payload_error <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + main_tx_padding_source_valid <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= builder_txdatapath_liteethmacpaddinginserter_state; + case (builder_txdatapath_liteethmacpaddinginserter_state) + 1'd1: begin + main_tx_padding_source_valid <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_source_payload_last_be <= 1'd1; + main_tx_padding_source_last <= 1'd1; + end + main_tx_padding_source_payload_data <= 1'd0; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_counter_done) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd0; + end + end + end + default: begin + main_tx_padding_source_valid <= main_tx_padding_sink_valid; + main_tx_padding_sink_ready <= main_tx_padding_source_ready; + main_tx_padding_source_first <= main_tx_padding_sink_first; + main_tx_padding_source_last <= main_tx_padding_sink_last; + main_tx_padding_source_payload_data <= main_tx_padding_sink_payload_data; + main_tx_padding_source_payload_last_be <= main_tx_padding_sink_payload_last_be; + main_tx_padding_source_payload_error <= main_tx_padding_sink_payload_error; + if ((main_tx_padding_source_valid & main_tx_padding_source_ready)) begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= (main_tx_padding_counter + 1'd1); + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + if (main_tx_padding_sink_last) begin + if ((~main_tx_padding_counter_done)) begin + main_tx_padding_source_last <= 1'd0; + main_tx_padding_source_payload_last_be <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_next_state <= 1'd1; + end else begin + if (((main_tx_padding_counter == 6'd59) & (main_tx_padding_sink_payload_last_be < 1'd1))) begin + main_tx_padding_source_payload_last_be <= 1'd1; + end else begin + main_tx_padding_counter_clockdomainsrenamer0_next_value <= 1'd0; + main_tx_padding_counter_clockdomainsrenamer0_next_value_ce <= 1'd1; + end + end + end + end + end + endcase +end +assign main_tx_crc_data0 = main_tx_crc_sink_payload_data; +assign main_tx_crc_be = main_tx_crc_sink_payload_last_be; +assign main_tx_crc_cnt_done = (main_tx_crc_cnt == 1'd0); +assign main_tx_crc_sink_valid = main_tx_crc_source_source_valid; +assign main_tx_crc_source_source_ready = main_tx_crc_sink_ready; +assign main_tx_crc_sink_first = main_tx_crc_source_source_first; +assign main_tx_crc_sink_last = main_tx_crc_source_source_last; +assign main_tx_crc_sink_payload_data = main_tx_crc_source_source_payload_data; +assign main_tx_crc_sink_payload_last_be = main_tx_crc_source_source_payload_last_be; +assign main_tx_crc_sink_payload_error = main_tx_crc_source_source_payload_error; +assign main_tx_crc_data1 = main_tx_crc_data0[7:0]; +assign main_tx_crc_crc_prev = main_tx_crc_reg; +always @(*) begin + main_tx_crc_error <= 1'd0; + main_tx_crc_value <= 32'd0; + if (main_tx_crc_be) begin + main_tx_crc_value <= {builder_t_slice_proxy31[0], builder_t_slice_proxy30[1], builder_t_slice_proxy29[2], builder_t_slice_proxy28[3], builder_t_slice_proxy27[4], builder_t_slice_proxy26[5], builder_t_slice_proxy25[6], builder_t_slice_proxy24[7], builder_t_slice_proxy23[8], builder_t_slice_proxy22[9], builder_t_slice_proxy21[10], builder_t_slice_proxy20[11], builder_t_slice_proxy19[12], builder_t_slice_proxy18[13], builder_t_slice_proxy17[14], builder_t_slice_proxy16[15], builder_t_slice_proxy15[16], builder_t_slice_proxy14[17], builder_t_slice_proxy13[18], builder_t_slice_proxy12[19], builder_t_slice_proxy11[20], builder_t_slice_proxy10[21], builder_t_slice_proxy9[22], builder_t_slice_proxy8[23], builder_t_slice_proxy7[24], builder_t_slice_proxy6[25], builder_t_slice_proxy5[26], builder_t_slice_proxy4[27], builder_t_slice_proxy3[28], builder_t_slice_proxy2[29], builder_t_slice_proxy1[30], builder_t_slice_proxy0[31]}; + main_tx_crc_error <= (main_tx_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_tx_crc_crc_next <= 32'd0; + main_tx_crc_crc_next[0] <= (((main_tx_crc_crc_prev[24] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[1] <= (((((((main_tx_crc_crc_prev[25] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[2] <= (((((((((main_tx_crc_crc_prev[26] ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[3] <= (((((((main_tx_crc_crc_prev[27] ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[4] <= (((((((((main_tx_crc_crc_prev[28] ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[5] <= (((((((((((((main_tx_crc_crc_prev[29] ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[6] <= (((((((((((main_tx_crc_crc_prev[30] ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[7] <= (((((((((main_tx_crc_crc_prev[31] ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[8] <= ((((((((main_tx_crc_crc_prev[0] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[9] <= ((((((((main_tx_crc_crc_prev[1] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[10] <= ((((((((main_tx_crc_crc_prev[2] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[11] <= ((((((((main_tx_crc_crc_prev[3] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[12] <= ((((((((((((main_tx_crc_crc_prev[4] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[13] <= ((((((((((((main_tx_crc_crc_prev[5] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[14] <= ((((((((((main_tx_crc_crc_prev[6] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[15] <= ((((((((main_tx_crc_crc_prev[7] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[16] <= ((((((main_tx_crc_crc_prev[8] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[17] <= ((((((main_tx_crc_crc_prev[9] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[18] <= ((((((main_tx_crc_crc_prev[10] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[19] <= ((((main_tx_crc_crc_prev[11] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[20] <= ((main_tx_crc_crc_prev[12] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[21] <= ((main_tx_crc_crc_prev[13] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); + main_tx_crc_crc_next[22] <= ((main_tx_crc_crc_prev[14] ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[23] <= ((((((main_tx_crc_crc_prev[15] ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_data1[6]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[24] <= ((((((main_tx_crc_crc_prev[16] ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[25] <= ((((main_tx_crc_crc_prev[17] ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[26] <= ((((((((main_tx_crc_crc_prev[18] ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]) ^ main_tx_crc_crc_prev[24]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_data1[7]); + main_tx_crc_crc_next[27] <= ((((((((main_tx_crc_crc_prev[19] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]) ^ main_tx_crc_crc_prev[25]) ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_data1[6]); + main_tx_crc_crc_next[28] <= ((((((main_tx_crc_crc_prev[20] ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]) ^ main_tx_crc_crc_prev[26]) ^ main_tx_crc_data1[5]); + main_tx_crc_crc_next[29] <= ((((((main_tx_crc_crc_prev[21] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[30]) ^ main_tx_crc_data1[1]) ^ main_tx_crc_crc_prev[27]) ^ main_tx_crc_data1[4]); + main_tx_crc_crc_next[30] <= ((((main_tx_crc_crc_prev[22] ^ main_tx_crc_crc_prev[31]) ^ main_tx_crc_data1[0]) ^ main_tx_crc_crc_prev[28]) ^ main_tx_crc_data1[3]); + main_tx_crc_crc_next[31] <= ((main_tx_crc_crc_prev[23] ^ main_tx_crc_crc_prev[29]) ^ main_tx_crc_data1[2]); +end +always @(*) begin + builder_txdatapath_bufferizeendpoints_next_state <= 2'd0; + main_tx_crc_ce <= 1'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= 32'd0; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd0; + main_tx_crc_is_ongoing0 <= 1'd0; + main_tx_crc_is_ongoing1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= 1'd0; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd0; + main_tx_crc_reset <= 1'd0; + main_tx_crc_sink_ready <= 1'd0; + main_tx_crc_source_first <= 1'd0; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_data <= 8'd0; + main_tx_crc_source_payload_error <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + main_tx_crc_source_valid <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= builder_txdatapath_bufferizeendpoints_state; + case (builder_txdatapath_bufferizeendpoints_state) + 1'd1: begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + main_tx_crc_source_valid <= main_tx_crc_sink_valid; + main_tx_crc_sink_ready <= main_tx_crc_source_ready; + main_tx_crc_source_first <= main_tx_crc_sink_first; + main_tx_crc_source_last <= main_tx_crc_sink_last; + main_tx_crc_source_payload_data <= main_tx_crc_sink_payload_data; + main_tx_crc_source_payload_last_be <= main_tx_crc_sink_payload_last_be; + main_tx_crc_source_payload_error <= main_tx_crc_sink_payload_error; + main_tx_crc_source_last <= 1'd0; + main_tx_crc_source_payload_last_be <= 1'd0; + if (main_tx_crc_sink_last) begin + if (main_tx_crc_sink_payload_last_be) begin + main_tx_crc_source_payload_data <= builder_complexslicelowerer_slice_proxy[7:0]; + end + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + main_tx_crc_source_last <= 1'd1; + main_tx_crc_source_payload_last_be <= (main_tx_crc_sink_payload_last_be <<< -3'd3); + end + end else begin + main_tx_crc_ce <= (main_tx_crc_sink_valid & main_tx_crc_source_ready); + end + if (((main_tx_crc_sink_valid & main_tx_crc_sink_last) & main_tx_crc_source_ready)) begin + if ((1'd0 & (main_tx_crc_sink_payload_last_be <= 4'd15))) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end else begin + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0 <= main_tx_crc_value; + main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0 <= 1'd1; + if (1'd0) begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= (main_tx_crc_sink_payload_last_be >>> 3'd4); + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end else begin + main_tx_crc_last_be_clockdomainsrenamer1_next_value1 <= main_tx_crc_sink_payload_last_be; + main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1 <= 1'd1; + end + builder_txdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_tx_crc_source_valid <= 1'd1; + case (main_tx_crc_cnt) + 1'd0: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[31:24]; + end + 1'd1: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[23:16]; + end + 2'd2: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[15:8]; + end + default: begin + main_tx_crc_source_payload_data <= main_tx_crc_crc_packet[7:0]; + end + endcase + if (main_tx_crc_cnt_done) begin + main_tx_crc_source_last <= 1'd1; + if (main_tx_crc_source_ready) begin + builder_txdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + main_tx_crc_is_ongoing1 <= 1'd1; + end + default: begin + main_tx_crc_reset <= 1'd1; + main_tx_crc_sink_ready <= 1'd1; + if (main_tx_crc_sink_valid) begin + main_tx_crc_sink_ready <= 1'd0; + builder_txdatapath_bufferizeendpoints_next_state <= 1'd1; + end + main_tx_crc_is_ongoing0 <= 1'd1; + end + endcase +end +assign main_tx_crc_pipe_valid_sink_ready = ((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready); +assign main_tx_crc_pipe_valid_sink_valid = main_tx_crc_sink_sink_valid; +assign main_tx_crc_sink_sink_ready = main_tx_crc_pipe_valid_sink_ready; +assign main_tx_crc_pipe_valid_sink_first = main_tx_crc_sink_sink_first; +assign main_tx_crc_pipe_valid_sink_last = main_tx_crc_sink_sink_last; +assign main_tx_crc_pipe_valid_sink_payload_data = main_tx_crc_sink_sink_payload_data; +assign main_tx_crc_pipe_valid_sink_payload_last_be = main_tx_crc_sink_sink_payload_last_be; +assign main_tx_crc_pipe_valid_sink_payload_error = main_tx_crc_sink_sink_payload_error; +assign main_tx_crc_source_source_valid = main_tx_crc_pipe_valid_source_valid; +assign main_tx_crc_pipe_valid_source_ready = main_tx_crc_source_source_ready; +assign main_tx_crc_source_source_first = main_tx_crc_pipe_valid_source_first; +assign main_tx_crc_source_source_last = main_tx_crc_pipe_valid_source_last; +assign main_tx_crc_source_source_payload_data = main_tx_crc_pipe_valid_source_payload_data; +assign main_tx_crc_source_source_payload_last_be = main_tx_crc_pipe_valid_source_payload_last_be; +assign main_tx_crc_source_source_payload_error = main_tx_crc_pipe_valid_source_payload_error; +assign main_tx_preamble_source_payload_last_be = main_tx_preamble_sink_payload_last_be; +always @(*) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 3'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd0; + main_tx_preamble_sink_ready <= 1'd0; + main_tx_preamble_source_first <= 1'd0; + main_tx_preamble_source_last <= 1'd0; + main_tx_preamble_source_payload_data <= 8'd0; + main_tx_preamble_source_payload_error <= 1'd0; + main_tx_preamble_source_valid <= 1'd0; + main_tx_preamble_source_payload_data <= main_tx_preamble_sink_payload_data; + builder_txdatapath_liteethmacpreambleinserter_next_state <= builder_txdatapath_liteethmacpreambleinserter_state; + case (builder_txdatapath_liteethmacpreambleinserter_state) + 1'd1: begin + main_tx_preamble_source_valid <= 1'd1; + case (main_tx_preamble_count) + 1'd0: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[7:0]; + end + 1'd1: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[15:8]; + end + 2'd2: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[23:16]; + end + 2'd3: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[31:24]; + end + 3'd4: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[39:32]; + end + 3'd5: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[47:40]; + end + 3'd6: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[55:48]; + end + default: begin + main_tx_preamble_source_payload_data <= main_tx_preamble_preamble[63:56]; + end + endcase + if (main_tx_preamble_source_ready) begin + if ((main_tx_preamble_count == 3'd7)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 2'd2; + end else begin + main_tx_preamble_count_clockdomainsrenamer2_next_value <= (main_tx_preamble_count + 1'd1); + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + end + end + end + 2'd2: begin + main_tx_preamble_source_valid <= main_tx_preamble_sink_valid; + main_tx_preamble_sink_ready <= main_tx_preamble_source_ready; + main_tx_preamble_source_first <= main_tx_preamble_sink_first; + main_tx_preamble_source_last <= main_tx_preamble_sink_last; + main_tx_preamble_source_payload_error <= main_tx_preamble_sink_payload_error; + if (((main_tx_preamble_sink_valid & main_tx_preamble_sink_last) & main_tx_preamble_source_ready)) begin + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd0; + end + end + default: begin + main_tx_preamble_sink_ready <= 1'd1; + main_tx_preamble_count_clockdomainsrenamer2_next_value <= 1'd0; + main_tx_preamble_count_clockdomainsrenamer2_next_value_ce <= 1'd1; + if (main_tx_preamble_sink_valid) begin + main_tx_preamble_sink_ready <= 1'd0; + builder_txdatapath_liteethmacpreambleinserter_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 4'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd0; + main_tx_gap_sink_ready <= 1'd0; + main_tx_gap_source_first <= 1'd0; + main_tx_gap_source_last <= 1'd0; + main_tx_gap_source_payload_data <= 8'd0; + main_tx_gap_source_payload_error <= 1'd0; + main_tx_gap_source_payload_last_be <= 1'd0; + main_tx_gap_source_valid <= 1'd0; + builder_txdatapath_liteethmacgap_next_state <= builder_txdatapath_liteethmacgap_state; + case (builder_txdatapath_liteethmacgap_state) + 1'd1: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= (main_tx_gap_counter + 1'd1); + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + if ((main_tx_gap_counter == 4'd11)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd0; + end + end + default: begin + main_tx_gap_counter_clockdomainsrenamer3_next_value <= 1'd0; + main_tx_gap_counter_clockdomainsrenamer3_next_value_ce <= 1'd1; + main_tx_gap_source_valid <= main_tx_gap_sink_valid; + main_tx_gap_sink_ready <= main_tx_gap_source_ready; + main_tx_gap_source_first <= main_tx_gap_sink_first; + main_tx_gap_source_last <= main_tx_gap_sink_last; + main_tx_gap_source_payload_data <= main_tx_gap_sink_payload_data; + main_tx_gap_source_payload_last_be <= main_tx_gap_sink_payload_last_be; + main_tx_gap_source_payload_error <= main_tx_gap_sink_payload_error; + if (((main_tx_gap_sink_valid & main_tx_gap_sink_last) & main_tx_gap_sink_ready)) begin + builder_txdatapath_liteethmacgap_next_state <= 1'd1; + end + end + endcase +end +assign main_tx_cdc_sink_sink_valid = main_sink_valid; +assign main_sink_ready = main_tx_cdc_sink_sink_ready; +assign main_tx_cdc_sink_sink_first = main_sink_first; +assign main_tx_cdc_sink_sink_last = main_sink_last; +assign main_tx_cdc_sink_sink_payload_data = main_sink_payload_data; +assign main_tx_cdc_sink_sink_payload_last_be = main_sink_payload_last_be; +assign main_tx_cdc_sink_sink_payload_error = main_sink_payload_error; +assign main_tx_converter_sink_valid = main_tx_cdc_source_source_valid; +assign main_tx_cdc_source_source_ready = main_tx_converter_sink_ready; +assign main_tx_converter_sink_first = main_tx_cdc_source_source_first; +assign main_tx_converter_sink_last = main_tx_cdc_source_source_last; +assign main_tx_converter_sink_payload_data = main_tx_cdc_source_source_payload_data; +assign main_tx_converter_sink_payload_last_be = main_tx_cdc_source_source_payload_last_be; +assign main_tx_converter_sink_payload_error = main_tx_cdc_source_source_payload_error; +assign main_tx_last_be_sink_valid = main_tx_converter_source_valid; +assign main_tx_converter_source_ready = main_tx_last_be_sink_ready; +assign main_tx_last_be_sink_first = main_tx_converter_source_first; +assign main_tx_last_be_sink_last = main_tx_converter_source_last; +assign main_tx_last_be_sink_payload_data = main_tx_converter_source_payload_data; +assign main_tx_last_be_sink_payload_last_be = main_tx_converter_source_payload_last_be; +assign main_tx_last_be_sink_payload_error = main_tx_converter_source_payload_error; +assign main_tx_padding_sink_valid = main_tx_last_be_source_valid; +assign main_tx_last_be_source_ready = main_tx_padding_sink_ready; +assign main_tx_padding_sink_first = main_tx_last_be_source_first; +assign main_tx_padding_sink_last = main_tx_last_be_source_last; +assign main_tx_padding_sink_payload_data = main_tx_last_be_source_payload_data; +assign main_tx_padding_sink_payload_last_be = main_tx_last_be_source_payload_last_be; +assign main_tx_padding_sink_payload_error = main_tx_last_be_source_payload_error; +assign main_tx_crc_sink_sink_valid = main_tx_padding_source_valid; +assign main_tx_padding_source_ready = main_tx_crc_sink_sink_ready; +assign main_tx_crc_sink_sink_first = main_tx_padding_source_first; +assign main_tx_crc_sink_sink_last = main_tx_padding_source_last; +assign main_tx_crc_sink_sink_payload_data = main_tx_padding_source_payload_data; +assign main_tx_crc_sink_sink_payload_last_be = main_tx_padding_source_payload_last_be; +assign main_tx_crc_sink_sink_payload_error = main_tx_padding_source_payload_error; +assign main_tx_preamble_sink_valid = main_tx_crc_source_valid; +assign main_tx_crc_source_ready = main_tx_preamble_sink_ready; +assign main_tx_preamble_sink_first = main_tx_crc_source_first; +assign main_tx_preamble_sink_last = main_tx_crc_source_last; +assign main_tx_preamble_sink_payload_data = main_tx_crc_source_payload_data; +assign main_tx_preamble_sink_payload_last_be = main_tx_crc_source_payload_last_be; +assign main_tx_preamble_sink_payload_error = main_tx_crc_source_payload_error; +assign main_tx_gap_sink_valid = main_tx_preamble_source_valid; +assign main_tx_preamble_source_ready = main_tx_gap_sink_ready; +assign main_tx_gap_sink_first = main_tx_preamble_source_first; +assign main_tx_gap_sink_last = main_tx_preamble_source_last; +assign main_tx_gap_sink_payload_data = main_tx_preamble_source_payload_data; +assign main_tx_gap_sink_payload_last_be = main_tx_preamble_source_payload_last_be; +assign main_tx_gap_sink_payload_error = main_tx_preamble_source_payload_error; +assign main_maccore_ethphy_sink_valid = main_tx_gap_source_valid; +assign main_tx_gap_source_ready = main_maccore_ethphy_sink_ready; +assign main_maccore_ethphy_sink_first = main_tx_gap_source_first; +assign main_maccore_ethphy_sink_last = main_tx_gap_source_last; +assign main_maccore_ethphy_sink_payload_data = main_tx_gap_source_payload_data; +assign main_maccore_ethphy_sink_payload_last_be = main_tx_gap_source_payload_last_be; +assign main_maccore_ethphy_sink_payload_error = main_tx_gap_source_payload_error; +assign main_pulsesynchronizer0_i = main_rx_preamble_error; +assign main_pulsesynchronizer1_i = main_liteethmaccrc32checker_error; +assign main_rx_preamble_source_payload_data = main_rx_preamble_sink_payload_data; +assign main_rx_preamble_source_payload_last_be = main_rx_preamble_sink_payload_last_be; +always @(*) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + main_rx_preamble_error <= 1'd0; + main_rx_preamble_sink_ready <= 1'd0; + main_rx_preamble_source_first <= 1'd0; + main_rx_preamble_source_last <= 1'd0; + main_rx_preamble_source_payload_error <= 1'd0; + main_rx_preamble_source_valid <= 1'd0; + builder_rxdatapath_liteethmacpreamblechecker_next_state <= builder_rxdatapath_liteethmacpreamblechecker_state; + case (builder_rxdatapath_liteethmacpreamblechecker_state) + 1'd1: begin + main_rx_preamble_source_valid <= main_rx_preamble_sink_valid; + main_rx_preamble_sink_ready <= main_rx_preamble_source_ready; + main_rx_preamble_source_first <= main_rx_preamble_sink_first; + main_rx_preamble_source_last <= main_rx_preamble_sink_last; + main_rx_preamble_source_payload_error <= main_rx_preamble_sink_payload_error; + if (((main_rx_preamble_source_valid & main_rx_preamble_source_last) & main_rx_preamble_source_ready)) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd0; + end + end + default: begin + main_rx_preamble_sink_ready <= 1'd1; + if (((main_rx_preamble_sink_valid & (~main_rx_preamble_sink_last)) & (main_rx_preamble_sink_payload_data == main_rx_preamble_preamble[63:56]))) begin + builder_rxdatapath_liteethmacpreamblechecker_next_state <= 1'd1; + end + if ((main_rx_preamble_sink_valid & main_rx_preamble_sink_last)) begin + main_rx_preamble_error <= 1'd1; + end + end + endcase +end +assign main_pulsesynchronizer0_o = (main_pulsesynchronizer0_toggle_o ^ main_pulsesynchronizer0_toggle_o_r); +assign main_liteethmaccrc32checker_fifo_full = (main_liteethmaccrc32checker_syncfifo_level == 3'd4); +assign main_liteethmaccrc32checker_fifo_in = (main_liteethmaccrc32checker_sink_sink_valid & ((~main_liteethmaccrc32checker_fifo_full) | main_liteethmaccrc32checker_fifo_out)); +assign main_liteethmaccrc32checker_fifo_out = (main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready); +assign main_liteethmaccrc32checker_syncfifo_sink_first = main_liteethmaccrc32checker_sink_sink_first; +assign main_liteethmaccrc32checker_syncfifo_sink_last = main_liteethmaccrc32checker_sink_sink_last; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_data = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_last_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_sink_payload_error = main_liteethmaccrc32checker_sink_sink_payload_error; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_sink_sink_valid; + main_liteethmaccrc32checker_syncfifo_sink_valid <= main_liteethmaccrc32checker_fifo_in; +end +always @(*) begin + main_liteethmaccrc32checker_sink_sink_ready <= 1'd0; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_syncfifo_sink_ready; + main_liteethmaccrc32checker_sink_sink_ready <= main_liteethmaccrc32checker_fifo_in; +end +assign main_liteethmaccrc32checker_crc_data0 = main_liteethmaccrc32checker_sink_sink_payload_data; +assign main_liteethmaccrc32checker_crc_be = main_liteethmaccrc32checker_sink_sink_payload_last_be; +assign main_liteethmaccrc32checker_source_source_first = main_liteethmaccrc32checker_syncfifo_source_first; +assign main_liteethmaccrc32checker_source_source_payload_data = main_liteethmaccrc32checker_syncfifo_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_valid = main_bufferizeendpoints_source_source_valid; +assign main_bufferizeendpoints_source_source_ready = main_liteethmaccrc32checker_sink_sink_ready; +assign main_liteethmaccrc32checker_sink_sink_first = main_bufferizeendpoints_source_source_first; +assign main_liteethmaccrc32checker_sink_sink_last = main_bufferizeendpoints_source_source_last; +assign main_liteethmaccrc32checker_sink_sink_payload_data = main_bufferizeendpoints_source_source_payload_data; +assign main_liteethmaccrc32checker_sink_sink_payload_last_be = main_bufferizeendpoints_source_source_payload_last_be; +assign main_liteethmaccrc32checker_sink_sink_payload_error = main_bufferizeendpoints_source_source_payload_error; +assign main_liteethmaccrc32checker_crc_data1 = main_liteethmaccrc32checker_crc_data0[7:0]; +assign main_liteethmaccrc32checker_crc_crc_prev = main_liteethmaccrc32checker_crc_reg; +always @(*) begin + main_liteethmaccrc32checker_crc_error0 <= 1'd0; + main_liteethmaccrc32checker_crc_value <= 32'd0; + if (main_liteethmaccrc32checker_crc_be) begin + main_liteethmaccrc32checker_crc_value <= {builder_t_slice_proxy63[0], builder_t_slice_proxy62[1], builder_t_slice_proxy61[2], builder_t_slice_proxy60[3], builder_t_slice_proxy59[4], builder_t_slice_proxy58[5], builder_t_slice_proxy57[6], builder_t_slice_proxy56[7], builder_t_slice_proxy55[8], builder_t_slice_proxy54[9], builder_t_slice_proxy53[10], builder_t_slice_proxy52[11], builder_t_slice_proxy51[12], builder_t_slice_proxy50[13], builder_t_slice_proxy49[14], builder_t_slice_proxy48[15], builder_t_slice_proxy47[16], builder_t_slice_proxy46[17], builder_t_slice_proxy45[18], builder_t_slice_proxy44[19], builder_t_slice_proxy43[20], builder_t_slice_proxy42[21], builder_t_slice_proxy41[22], builder_t_slice_proxy40[23], builder_t_slice_proxy39[24], builder_t_slice_proxy38[25], builder_t_slice_proxy37[26], builder_t_slice_proxy36[27], builder_t_slice_proxy35[28], builder_t_slice_proxy34[29], builder_t_slice_proxy33[30], builder_t_slice_proxy32[31]}; + main_liteethmaccrc32checker_crc_error0 <= (main_liteethmaccrc32checker_crc_crc_next != 32'd3338984827); + end +end +always @(*) begin + main_liteethmaccrc32checker_crc_crc_next <= 32'd0; + main_liteethmaccrc32checker_crc_crc_next[0] <= (((main_liteethmaccrc32checker_crc_crc_prev[24] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[1] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[25] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[2] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[26] ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[3] <= (((((((main_liteethmaccrc32checker_crc_crc_prev[27] ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[4] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[28] ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[5] <= (((((((((((((main_liteethmaccrc32checker_crc_crc_prev[29] ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[6] <= (((((((((((main_liteethmaccrc32checker_crc_crc_prev[30] ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[7] <= (((((((((main_liteethmaccrc32checker_crc_crc_prev[31] ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[8] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[0] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[9] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[1] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[10] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[2] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[11] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[3] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[12] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[4] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[13] <= ((((((((((((main_liteethmaccrc32checker_crc_crc_prev[5] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[14] <= ((((((((((main_liteethmaccrc32checker_crc_crc_prev[6] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[15] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[7] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[16] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[8] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[17] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[9] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[18] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[10] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[19] <= ((((main_liteethmaccrc32checker_crc_crc_prev[11] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[20] <= ((main_liteethmaccrc32checker_crc_crc_prev[12] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[21] <= ((main_liteethmaccrc32checker_crc_crc_prev[13] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); + main_liteethmaccrc32checker_crc_crc_next[22] <= ((main_liteethmaccrc32checker_crc_crc_prev[14] ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[23] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[15] ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_data1[6]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[24] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[16] ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[25] <= ((((main_liteethmaccrc32checker_crc_crc_prev[17] ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[26] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[18] ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]) ^ main_liteethmaccrc32checker_crc_crc_prev[24]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_data1[7]); + main_liteethmaccrc32checker_crc_crc_next[27] <= ((((((((main_liteethmaccrc32checker_crc_crc_prev[19] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]) ^ main_liteethmaccrc32checker_crc_crc_prev[25]) ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_data1[6]); + main_liteethmaccrc32checker_crc_crc_next[28] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[20] ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]) ^ main_liteethmaccrc32checker_crc_crc_prev[26]) ^ main_liteethmaccrc32checker_crc_data1[5]); + main_liteethmaccrc32checker_crc_crc_next[29] <= ((((((main_liteethmaccrc32checker_crc_crc_prev[21] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[30]) ^ main_liteethmaccrc32checker_crc_data1[1]) ^ main_liteethmaccrc32checker_crc_crc_prev[27]) ^ main_liteethmaccrc32checker_crc_data1[4]); + main_liteethmaccrc32checker_crc_crc_next[30] <= ((((main_liteethmaccrc32checker_crc_crc_prev[22] ^ main_liteethmaccrc32checker_crc_crc_prev[31]) ^ main_liteethmaccrc32checker_crc_data1[0]) ^ main_liteethmaccrc32checker_crc_crc_prev[28]) ^ main_liteethmaccrc32checker_crc_data1[3]); + main_liteethmaccrc32checker_crc_crc_next[31] <= ((main_liteethmaccrc32checker_crc_crc_prev[23] ^ main_liteethmaccrc32checker_crc_crc_prev[29]) ^ main_liteethmaccrc32checker_crc_data1[2]); +end +assign main_liteethmaccrc32checker_syncfifo_syncfifo_din = {main_liteethmaccrc32checker_syncfifo_fifo_in_last, main_liteethmaccrc32checker_syncfifo_fifo_in_first, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data}; +assign {main_liteethmaccrc32checker_syncfifo_fifo_out_last, main_liteethmaccrc32checker_syncfifo_fifo_out_first, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = main_liteethmaccrc32checker_syncfifo_syncfifo_dout; +assign main_liteethmaccrc32checker_syncfifo_sink_ready = main_liteethmaccrc32checker_syncfifo_syncfifo_writable; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_we = main_liteethmaccrc32checker_syncfifo_sink_valid; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_first = main_liteethmaccrc32checker_syncfifo_sink_first; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_last = main_liteethmaccrc32checker_syncfifo_sink_last; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_data = main_liteethmaccrc32checker_syncfifo_sink_payload_data; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = main_liteethmaccrc32checker_syncfifo_sink_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_fifo_in_payload_error = main_liteethmaccrc32checker_syncfifo_sink_payload_error; +assign main_liteethmaccrc32checker_syncfifo_source_valid = main_liteethmaccrc32checker_syncfifo_syncfifo_readable; +assign main_liteethmaccrc32checker_syncfifo_source_first = main_liteethmaccrc32checker_syncfifo_fifo_out_first; +assign main_liteethmaccrc32checker_syncfifo_source_last = main_liteethmaccrc32checker_syncfifo_fifo_out_last; +assign main_liteethmaccrc32checker_syncfifo_source_payload_data = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_data; +assign main_liteethmaccrc32checker_syncfifo_source_payload_last_be = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be; +assign main_liteethmaccrc32checker_syncfifo_source_payload_error = main_liteethmaccrc32checker_syncfifo_fifo_out_payload_error; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_re = main_liteethmaccrc32checker_syncfifo_source_ready; +always @(*) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0; + if (main_liteethmaccrc32checker_syncfifo_replace) begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= (main_liteethmaccrc32checker_syncfifo_produce - 1'd1); + end else begin + main_liteethmaccrc32checker_syncfifo_wrport_adr <= main_liteethmaccrc32checker_syncfifo_produce; + end +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_w = main_liteethmaccrc32checker_syncfifo_syncfifo_din; +assign main_liteethmaccrc32checker_syncfifo_wrport_we = (main_liteethmaccrc32checker_syncfifo_syncfifo_we & (main_liteethmaccrc32checker_syncfifo_syncfifo_writable | main_liteethmaccrc32checker_syncfifo_replace)); +assign main_liteethmaccrc32checker_syncfifo_do_read = (main_liteethmaccrc32checker_syncfifo_syncfifo_readable & main_liteethmaccrc32checker_syncfifo_syncfifo_re); +assign main_liteethmaccrc32checker_syncfifo_rdport_adr = main_liteethmaccrc32checker_syncfifo_consume; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_dout = main_liteethmaccrc32checker_syncfifo_rdport_dat_r; +assign main_liteethmaccrc32checker_syncfifo_syncfifo_writable = (main_liteethmaccrc32checker_syncfifo_level != 3'd5); +assign main_liteethmaccrc32checker_syncfifo_syncfifo_readable = (main_liteethmaccrc32checker_syncfifo_level != 1'd0); +always @(*) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd0; + main_liteethmaccrc32checker_crc_ce <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value1 <= 1'd0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd0; + main_liteethmaccrc32checker_crc_reset <= 1'd0; + main_liteethmaccrc32checker_error <= 1'd0; + main_liteethmaccrc32checker_fifo_reset <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value0 <= 1'd0; + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd0; + main_liteethmaccrc32checker_source_source_last <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_last_be <= 1'd0; + main_liteethmaccrc32checker_source_source_valid <= 1'd0; + main_liteethmaccrc32checker_syncfifo_source_ready <= 1'd0; + main_liteethmaccrc32checker_source_source_payload_error <= main_liteethmaccrc32checker_syncfifo_source_payload_error; + builder_rxdatapath_bufferizeendpoints_next_state <= builder_rxdatapath_bufferizeendpoints_state; + case (builder_rxdatapath_bufferizeendpoints_state) + 1'd1: begin + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd2; + end + end + 2'd2: begin + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_fifo_out; + main_liteethmaccrc32checker_source_source_valid <= (main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_fifo_full); + if (1'd1) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_sink_sink_payload_last_be; + end else begin + if ((main_liteethmaccrc32checker_sink_sink_payload_last_be & 4'd15)) begin + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_sink_sink_last; + main_liteethmaccrc32checker_source_source_payload_last_be <= (main_liteethmaccrc32checker_sink_sink_payload_last_be <<< -3'd3); + end else begin + main_liteethmaccrc32checker_last_be_next_value0 <= (main_liteethmaccrc32checker_sink_sink_payload_last_be >>> 3'd4); + main_liteethmaccrc32checker_last_be_next_value_ce0 <= 1'd1; + main_liteethmaccrc32checker_crc_error1_next_value1 <= main_liteethmaccrc32checker_crc_error0; + main_liteethmaccrc32checker_crc_error1_next_value_ce1 <= 1'd1; + end + end + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_sink_sink_payload_error | {1{(main_liteethmaccrc32checker_crc_error0 & main_liteethmaccrc32checker_sink_sink_last)}}); + main_liteethmaccrc32checker_error <= ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_last) & main_liteethmaccrc32checker_crc_error0); + if ((main_liteethmaccrc32checker_sink_sink_valid & main_liteethmaccrc32checker_sink_sink_ready)) begin + main_liteethmaccrc32checker_crc_ce <= 1'd1; + if ((main_liteethmaccrc32checker_sink_sink_last & (main_liteethmaccrc32checker_sink_sink_payload_last_be > 4'd15))) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 2'd3; + end else begin + if (main_liteethmaccrc32checker_sink_sink_last) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + end + end + 2'd3: begin + main_liteethmaccrc32checker_source_source_valid <= main_liteethmaccrc32checker_syncfifo_source_valid; + main_liteethmaccrc32checker_syncfifo_source_ready <= main_liteethmaccrc32checker_source_source_ready; + main_liteethmaccrc32checker_source_source_last <= main_liteethmaccrc32checker_syncfifo_source_last; + main_liteethmaccrc32checker_source_source_payload_error <= (main_liteethmaccrc32checker_syncfifo_source_payload_error | {1{main_liteethmaccrc32checker_crc_error1}}); + main_liteethmaccrc32checker_source_source_payload_last_be <= main_liteethmaccrc32checker_last_be; + if ((main_liteethmaccrc32checker_source_source_valid & main_liteethmaccrc32checker_source_source_ready)) begin + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd0; + end + end + default: begin + main_liteethmaccrc32checker_crc_reset <= 1'd1; + main_liteethmaccrc32checker_fifo_reset <= 1'd1; + builder_rxdatapath_bufferizeendpoints_next_state <= 1'd1; + end + endcase +end +assign main_bufferizeendpoints_pipe_valid_sink_ready = ((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready); +assign main_bufferizeendpoints_pipe_valid_sink_valid = main_bufferizeendpoints_sink_sink_valid; +assign main_bufferizeendpoints_sink_sink_ready = main_bufferizeendpoints_pipe_valid_sink_ready; +assign main_bufferizeendpoints_pipe_valid_sink_first = main_bufferizeendpoints_sink_sink_first; +assign main_bufferizeendpoints_pipe_valid_sink_last = main_bufferizeendpoints_sink_sink_last; +assign main_bufferizeendpoints_pipe_valid_sink_payload_data = main_bufferizeendpoints_sink_sink_payload_data; +assign main_bufferizeendpoints_pipe_valid_sink_payload_last_be = main_bufferizeendpoints_sink_sink_payload_last_be; +assign main_bufferizeendpoints_pipe_valid_sink_payload_error = main_bufferizeendpoints_sink_sink_payload_error; +assign main_bufferizeendpoints_source_source_valid = main_bufferizeendpoints_pipe_valid_source_valid; +assign main_bufferizeendpoints_pipe_valid_source_ready = main_bufferizeendpoints_source_source_ready; +assign main_bufferizeendpoints_source_source_first = main_bufferizeendpoints_pipe_valid_source_first; +assign main_bufferizeendpoints_source_source_last = main_bufferizeendpoints_pipe_valid_source_last; +assign main_bufferizeendpoints_source_source_payload_data = main_bufferizeendpoints_pipe_valid_source_payload_data; +assign main_bufferizeendpoints_source_source_payload_last_be = main_bufferizeendpoints_pipe_valid_source_payload_last_be; +assign main_bufferizeendpoints_source_source_payload_error = main_bufferizeendpoints_pipe_valid_source_payload_error; +assign main_pulsesynchronizer1_o = (main_pulsesynchronizer1_toggle_o ^ main_pulsesynchronizer1_toggle_o_r); +assign main_rx_padding_source_valid = main_rx_padding_sink_valid; +assign main_rx_padding_sink_ready = main_rx_padding_source_ready; +assign main_rx_padding_source_first = main_rx_padding_sink_first; +assign main_rx_padding_source_last = main_rx_padding_sink_last; +assign main_rx_padding_source_payload_data = main_rx_padding_sink_payload_data; +assign main_rx_padding_source_payload_last_be = main_rx_padding_sink_payload_last_be; +assign main_rx_padding_source_payload_error = main_rx_padding_sink_payload_error; +assign main_rx_last_be_source_valid = main_rx_last_be_sink_valid; +assign main_rx_last_be_sink_ready = main_rx_last_be_source_ready; +assign main_rx_last_be_source_first = main_rx_last_be_sink_first; +assign main_rx_last_be_source_last = main_rx_last_be_sink_last; +assign main_rx_last_be_source_payload_data = main_rx_last_be_sink_payload_data; +assign main_rx_last_be_source_payload_error = main_rx_last_be_sink_payload_error; +always @(*) begin + main_rx_last_be_source_payload_last_be <= 1'd0; + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_payload_last_be; + if (1'd1) begin + main_rx_last_be_source_payload_last_be <= main_rx_last_be_sink_last; + end +end +assign main_rx_converter_converter_sink_valid = main_rx_converter_sink_valid; +assign main_rx_converter_converter_sink_first = main_rx_converter_sink_first; +assign main_rx_converter_converter_sink_last = main_rx_converter_sink_last; +assign main_rx_converter_sink_ready = main_rx_converter_converter_sink_ready; +assign main_rx_converter_converter_sink_payload_data = {main_rx_converter_sink_payload_error, main_rx_converter_sink_payload_last_be, main_rx_converter_sink_payload_data}; +assign main_rx_converter_source_valid = main_rx_converter_source_source_valid; +assign main_rx_converter_source_first = main_rx_converter_source_source_first; +assign main_rx_converter_source_last = main_rx_converter_source_source_last; +assign main_rx_converter_source_source_ready = main_rx_converter_source_ready; +always @(*) begin + main_rx_converter_source_payload_data <= 32'd0; + main_rx_converter_source_payload_data[7:0] <= main_rx_converter_source_source_payload_data[7:0]; + main_rx_converter_source_payload_data[15:8] <= main_rx_converter_source_source_payload_data[17:10]; + main_rx_converter_source_payload_data[23:16] <= main_rx_converter_source_source_payload_data[27:20]; + main_rx_converter_source_payload_data[31:24] <= main_rx_converter_source_source_payload_data[37:30]; +end +always @(*) begin + main_rx_converter_source_payload_last_be <= 4'd0; + main_rx_converter_source_payload_last_be[0] <= main_rx_converter_source_source_payload_data[8]; + main_rx_converter_source_payload_last_be[1] <= main_rx_converter_source_source_payload_data[18]; + main_rx_converter_source_payload_last_be[2] <= main_rx_converter_source_source_payload_data[28]; + main_rx_converter_source_payload_last_be[3] <= main_rx_converter_source_source_payload_data[38]; +end +always @(*) begin + main_rx_converter_source_payload_error <= 4'd0; + main_rx_converter_source_payload_error[0] <= main_rx_converter_source_source_payload_data[9]; + main_rx_converter_source_payload_error[1] <= main_rx_converter_source_source_payload_data[19]; + main_rx_converter_source_payload_error[2] <= main_rx_converter_source_source_payload_data[29]; + main_rx_converter_source_payload_error[3] <= main_rx_converter_source_source_payload_data[39]; +end +assign main_rx_converter_source_source_valid = main_rx_converter_converter_source_valid; +assign main_rx_converter_converter_source_ready = main_rx_converter_source_source_ready; +assign main_rx_converter_source_source_first = main_rx_converter_converter_source_first; +assign main_rx_converter_source_source_last = main_rx_converter_converter_source_last; +assign main_rx_converter_source_source_payload_data = main_rx_converter_converter_source_payload_data; +assign main_rx_converter_converter_sink_ready = ((~main_rx_converter_converter_strobe_all) | main_rx_converter_converter_source_ready); +assign main_rx_converter_converter_source_valid = main_rx_converter_converter_strobe_all; +assign main_rx_converter_converter_load_part = (main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready); +assign main_rx_cdc_cdc_sink_valid = main_rx_cdc_sink_sink_valid; +assign main_rx_cdc_sink_sink_ready = main_rx_cdc_cdc_sink_ready; +assign main_rx_cdc_cdc_sink_first = main_rx_cdc_sink_sink_first; +assign main_rx_cdc_cdc_sink_last = main_rx_cdc_sink_sink_last; +assign main_rx_cdc_cdc_sink_payload_data = main_rx_cdc_sink_sink_payload_data; +assign main_rx_cdc_cdc_sink_payload_last_be = main_rx_cdc_sink_sink_payload_last_be; +assign main_rx_cdc_cdc_sink_payload_error = main_rx_cdc_sink_sink_payload_error; +assign main_rx_cdc_source_source_valid = main_rx_cdc_cdc_source_valid; +assign main_rx_cdc_cdc_source_ready = main_rx_cdc_source_source_ready; +assign main_rx_cdc_source_source_first = main_rx_cdc_cdc_source_first; +assign main_rx_cdc_source_source_last = main_rx_cdc_cdc_source_last; +assign main_rx_cdc_source_source_payload_data = main_rx_cdc_cdc_source_payload_data; +assign main_rx_cdc_source_source_payload_last_be = main_rx_cdc_cdc_source_payload_last_be; +assign main_rx_cdc_source_source_payload_error = main_rx_cdc_cdc_source_payload_error; +assign main_rx_cdc_cdc_asyncfifo_din = {main_rx_cdc_cdc_fifo_in_last, main_rx_cdc_cdc_fifo_in_first, main_rx_cdc_cdc_fifo_in_payload_error, main_rx_cdc_cdc_fifo_in_payload_last_be, main_rx_cdc_cdc_fifo_in_payload_data}; +assign {main_rx_cdc_cdc_fifo_out_last, main_rx_cdc_cdc_fifo_out_first, main_rx_cdc_cdc_fifo_out_payload_error, main_rx_cdc_cdc_fifo_out_payload_last_be, main_rx_cdc_cdc_fifo_out_payload_data} = main_rx_cdc_cdc_asyncfifo_dout; +assign main_rx_cdc_cdc_sink_ready = main_rx_cdc_cdc_asyncfifo_writable; +assign main_rx_cdc_cdc_asyncfifo_we = main_rx_cdc_cdc_sink_valid; +assign main_rx_cdc_cdc_fifo_in_first = main_rx_cdc_cdc_sink_first; +assign main_rx_cdc_cdc_fifo_in_last = main_rx_cdc_cdc_sink_last; +assign main_rx_cdc_cdc_fifo_in_payload_data = main_rx_cdc_cdc_sink_payload_data; +assign main_rx_cdc_cdc_fifo_in_payload_last_be = main_rx_cdc_cdc_sink_payload_last_be; +assign main_rx_cdc_cdc_fifo_in_payload_error = main_rx_cdc_cdc_sink_payload_error; +assign main_rx_cdc_cdc_source_valid = main_rx_cdc_cdc_asyncfifo_readable; +assign main_rx_cdc_cdc_source_first = main_rx_cdc_cdc_fifo_out_first; +assign main_rx_cdc_cdc_source_last = main_rx_cdc_cdc_fifo_out_last; +assign main_rx_cdc_cdc_source_payload_data = main_rx_cdc_cdc_fifo_out_payload_data; +assign main_rx_cdc_cdc_source_payload_last_be = main_rx_cdc_cdc_fifo_out_payload_last_be; +assign main_rx_cdc_cdc_source_payload_error = main_rx_cdc_cdc_fifo_out_payload_error; +assign main_rx_cdc_cdc_asyncfifo_re = main_rx_cdc_cdc_source_ready; +assign main_rx_cdc_cdc_graycounter0_ce = (main_rx_cdc_cdc_asyncfifo_writable & main_rx_cdc_cdc_asyncfifo_we); +assign main_rx_cdc_cdc_graycounter1_ce = (main_rx_cdc_cdc_asyncfifo_readable & main_rx_cdc_cdc_asyncfifo_re); +assign main_rx_cdc_cdc_asyncfifo_writable = (((main_rx_cdc_cdc_graycounter0_q[5] == main_rx_cdc_cdc_consume_wdomain[5]) | (main_rx_cdc_cdc_graycounter0_q[4] == main_rx_cdc_cdc_consume_wdomain[4])) | (main_rx_cdc_cdc_graycounter0_q[3:0] != main_rx_cdc_cdc_consume_wdomain[3:0])); +assign main_rx_cdc_cdc_asyncfifo_readable = (main_rx_cdc_cdc_graycounter1_q != main_rx_cdc_cdc_produce_rdomain); +assign main_rx_cdc_cdc_wrport_adr = main_rx_cdc_cdc_graycounter0_q_binary[4:0]; +assign main_rx_cdc_cdc_wrport_dat_w = main_rx_cdc_cdc_asyncfifo_din; +assign main_rx_cdc_cdc_wrport_we = main_rx_cdc_cdc_graycounter0_ce; +assign main_rx_cdc_cdc_rdport_adr = main_rx_cdc_cdc_graycounter1_q_next_binary[4:0]; +assign main_rx_cdc_cdc_asyncfifo_dout = main_rx_cdc_cdc_rdport_dat_r; +always @(*) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter0_ce) begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= (main_rx_cdc_cdc_graycounter0_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter0_q_next_binary <= main_rx_cdc_cdc_graycounter0_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter0_q_next = (main_rx_cdc_cdc_graycounter0_q_next_binary ^ main_rx_cdc_cdc_graycounter0_q_next_binary[5:1]); +always @(*) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0; + if (main_rx_cdc_cdc_graycounter1_ce) begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= (main_rx_cdc_cdc_graycounter1_q_binary + 1'd1); + end else begin + main_rx_cdc_cdc_graycounter1_q_next_binary <= main_rx_cdc_cdc_graycounter1_q_binary; + end +end +assign main_rx_cdc_cdc_graycounter1_q_next = (main_rx_cdc_cdc_graycounter1_q_next_binary ^ main_rx_cdc_cdc_graycounter1_q_next_binary[5:1]); +assign main_rx_preamble_sink_valid = main_maccore_ethphy_source_valid; +assign main_maccore_ethphy_source_ready = main_rx_preamble_sink_ready; +assign main_rx_preamble_sink_first = main_maccore_ethphy_source_first; +assign main_rx_preamble_sink_last = main_maccore_ethphy_source_last; +assign main_rx_preamble_sink_payload_data = main_maccore_ethphy_source_payload_data; +assign main_rx_preamble_sink_payload_last_be = main_maccore_ethphy_source_payload_last_be; +assign main_rx_preamble_sink_payload_error = main_maccore_ethphy_source_payload_error; +assign main_bufferizeendpoints_sink_sink_valid = main_rx_preamble_source_valid; +assign main_rx_preamble_source_ready = main_bufferizeendpoints_sink_sink_ready; +assign main_bufferizeendpoints_sink_sink_first = main_rx_preamble_source_first; +assign main_bufferizeendpoints_sink_sink_last = main_rx_preamble_source_last; +assign main_bufferizeendpoints_sink_sink_payload_data = main_rx_preamble_source_payload_data; +assign main_bufferizeendpoints_sink_sink_payload_last_be = main_rx_preamble_source_payload_last_be; +assign main_bufferizeendpoints_sink_sink_payload_error = main_rx_preamble_source_payload_error; +assign main_rx_padding_sink_valid = main_liteethmaccrc32checker_source_source_valid; +assign main_liteethmaccrc32checker_source_source_ready = main_rx_padding_sink_ready; +assign main_rx_padding_sink_first = main_liteethmaccrc32checker_source_source_first; +assign main_rx_padding_sink_last = main_liteethmaccrc32checker_source_source_last; +assign main_rx_padding_sink_payload_data = main_liteethmaccrc32checker_source_source_payload_data; +assign main_rx_padding_sink_payload_last_be = main_liteethmaccrc32checker_source_source_payload_last_be; +assign main_rx_padding_sink_payload_error = main_liteethmaccrc32checker_source_source_payload_error; +assign main_rx_last_be_sink_valid = main_rx_padding_source_valid; +assign main_rx_padding_source_ready = main_rx_last_be_sink_ready; +assign main_rx_last_be_sink_first = main_rx_padding_source_first; +assign main_rx_last_be_sink_last = main_rx_padding_source_last; +assign main_rx_last_be_sink_payload_data = main_rx_padding_source_payload_data; +assign main_rx_last_be_sink_payload_last_be = main_rx_padding_source_payload_last_be; +assign main_rx_last_be_sink_payload_error = main_rx_padding_source_payload_error; +assign main_rx_converter_sink_valid = main_rx_last_be_source_valid; +assign main_rx_last_be_source_ready = main_rx_converter_sink_ready; +assign main_rx_converter_sink_first = main_rx_last_be_source_first; +assign main_rx_converter_sink_last = main_rx_last_be_source_last; +assign main_rx_converter_sink_payload_data = main_rx_last_be_source_payload_data; +assign main_rx_converter_sink_payload_last_be = main_rx_last_be_source_payload_last_be; +assign main_rx_converter_sink_payload_error = main_rx_last_be_source_payload_error; +assign main_rx_cdc_sink_sink_valid = main_rx_converter_source_valid; +assign main_rx_converter_source_ready = main_rx_cdc_sink_sink_ready; +assign main_rx_cdc_sink_sink_first = main_rx_converter_source_first; +assign main_rx_cdc_sink_sink_last = main_rx_converter_source_last; +assign main_rx_cdc_sink_sink_payload_data = main_rx_converter_source_payload_data; +assign main_rx_cdc_sink_sink_payload_last_be = main_rx_converter_source_payload_last_be; +assign main_rx_cdc_sink_sink_payload_error = main_rx_converter_source_payload_error; +assign main_source_valid = main_rx_cdc_source_source_valid; +assign main_rx_cdc_source_source_ready = main_source_ready; +assign main_source_first = main_rx_cdc_source_source_first; +assign main_source_last = main_rx_cdc_source_source_last; +assign main_source_payload_data = main_rx_cdc_source_source_payload_data; +assign main_source_payload_last_be = main_rx_cdc_source_source_payload_last_be; +assign main_source_payload_error = main_rx_cdc_source_source_payload_error; +assign main_sram0_sink_valid = main_sink_sink_valid; +assign main_sink_sink_ready = main_sram1_sink_ready; +assign main_sram2_sink_first = main_sink_sink_first; +assign main_sram3_sink_last = main_sink_sink_last; +assign main_sram4_sink_payload_data = main_sink_sink_payload_data; +assign main_sram5_sink_payload_last_be = main_sink_sink_payload_last_be; +assign main_sram6_sink_payload_error = main_sink_sink_payload_error; +assign main_source_source_valid = main_sram83_source_valid; +assign main_sram84_source_ready = main_source_source_ready; +assign main_source_source_first = main_sram85_source_first; +assign main_source_source_last = main_sram86_source_last; +assign main_source_source_payload_data = main_sram87_source_payload_data; +assign main_source_source_payload_last_be = main_sram88_source_payload_last_be; +assign main_source_source_payload_error = main_sram89_source_payload_error; +always @(*) begin + main_length_inc <= 4'd0; + case (main_sram5_sink_payload_last_be) + 1'd1: begin + main_length_inc <= 1'd1; + end + 2'd2: begin + main_length_inc <= 2'd2; + end + 3'd4: begin + main_length_inc <= 2'd3; + end + 4'd8: begin + main_length_inc <= 3'd4; + end + 5'd16: begin + main_length_inc <= 3'd5; + end + 6'd32: begin + main_length_inc <= 3'd6; + end + 7'd64: begin + main_length_inc <= 3'd7; + end + default: begin + main_length_inc <= 3'd4; + end + endcase +end +assign main_sram44_source_ready = main_sram20_clear; +assign main_sram19_trigger = main_sram43_source_valid; +assign main_sram7_status = main_sram47_source_payload_slot; +assign main_sram10_status = main_sram48_source_payload_length; +assign main_wr_data = main_sram4_sink_payload_data; +always @(*) begin + main_sram75_adr <= 9'd0; + main_sram77_we <= 1'd0; + main_sram78_dat_w <= 32'd0; + main_sram79_adr <= 9'd0; + main_sram81_we <= 1'd0; + main_sram82_dat_w <= 32'd0; + case (main_slot) + 1'd0: begin + main_sram75_adr <= main_sram35_length[10:2]; + main_sram78_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram77_we <= 1'd1; + end + end + 1'd1: begin + main_sram79_adr <= main_sram35_length[10:2]; + main_sram82_dat_w <= main_wr_data; + if ((main_sram0_sink_valid & main_write)) begin + main_sram81_we <= 1'd1; + end + end + endcase +end +assign main_sram21_available = main_sram17_status; +assign main_sram25_available = main_sram18_pending; +always @(*) begin + main_sram20_clear <= 1'd0; + if ((main_sram28_re & main_sram29_r)) begin + main_sram20_clear <= 1'd1; + end +end +assign main_sram16_irq = (main_sram26_status & main_sram31_storage); +assign main_sram17_status = main_sram19_trigger; +assign main_sram18_pending = main_sram19_trigger; +assign main_sram53_din = {main_sram69_fifo_in_last, main_sram68_fifo_in_first, main_sram67_fifo_in_payload_length, main_sram66_fifo_in_payload_slot}; +assign {main_sram73_fifo_out_last, main_sram72_fifo_out_first, main_sram71_fifo_out_payload_length, main_sram70_fifo_out_payload_slot} = main_sram54_dout; +assign main_sram38_sink_ready = main_sram50_writable; +assign main_sram49_we = main_sram37_sink_valid; +assign main_sram68_fifo_in_first = main_sram39_sink_first; +assign main_sram69_fifo_in_last = main_sram40_sink_last; +assign main_sram66_fifo_in_payload_slot = main_sram41_sink_payload_slot; +assign main_sram67_fifo_in_payload_length = main_sram42_sink_payload_length; +assign main_sram43_source_valid = main_sram52_readable; +assign main_sram45_source_first = main_sram72_fifo_out_first; +assign main_sram46_source_last = main_sram73_fifo_out_last; +assign main_sram47_source_payload_slot = main_sram70_fifo_out_payload_slot; +assign main_sram48_source_payload_length = main_sram71_fifo_out_payload_length; +assign main_sram51_re = main_sram44_source_ready; +always @(*) begin + main_sram59_adr <= 1'd0; + if (main_sram56_replace) begin + main_sram59_adr <= (main_sram57_produce - 1'd1); + end else begin + main_sram59_adr <= main_sram57_produce; + end +end +assign main_sram62_dat_w = main_sram53_din; +assign main_sram61_we = (main_sram49_we & (main_sram50_writable | main_sram56_replace)); +assign main_sram63_do_read = (main_sram52_readable & main_sram51_re); +assign main_sram64_adr = main_sram58_consume; +assign main_sram54_dout = main_sram65_dat_r; +assign main_sram50_writable = (main_sram55_level != 2'd2); +assign main_sram52_readable = (main_sram55_level != 1'd0); +always @(*) begin + builder_liteethmacsramwriter_next_state <= 3'd0; + main_slot_liteethmacsramwriter_next_value <= 1'd0; + main_slot_liteethmacsramwriter_next_value_ce <= 1'd0; + main_sram13_status_liteethmacsramwriter_f_next_value <= 32'd0; + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value <= 11'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd0; + main_sram37_sink_valid <= 1'd0; + main_sram41_sink_payload_slot <= 1'd0; + main_sram42_sink_payload_length <= 11'd0; + main_write <= 1'd0; + builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state; + case (builder_liteethmacsramwriter_state) + 1'd1: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end + 2'd2: begin + if ((main_sram0_sink_valid & main_sram3_sink_last)) begin + if ((main_sram5_sink_payload_last_be != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + 3'd4: begin + main_sram37_sink_valid <= 1'd1; + main_sram41_sink_payload_slot <= main_slot; + main_sram42_sink_payload_length <= main_sram35_length; + main_sram35_length_liteethmacsramwriter_t_next_value <= 1'd0; + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + main_slot_liteethmacsramwriter_next_value <= (main_slot + 1'd1); + main_slot_liteethmacsramwriter_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 1'd0; + end + default: begin + if (main_sram0_sink_valid) begin + if (main_sram38_sink_ready) begin + main_write <= 1'd1; + main_sram35_length_liteethmacsramwriter_t_next_value <= (main_sram35_length + main_length_inc); + main_sram35_length_liteethmacsramwriter_t_next_value_ce <= 1'd1; + if ((main_sram35_length >= 11'd1530)) begin + builder_liteethmacsramwriter_next_state <= 1'd1; + end + if (main_sram3_sink_last) begin + if (((main_sram6_sink_payload_error & main_sram5_sink_payload_last_be) != 1'd0)) begin + builder_liteethmacsramwriter_next_state <= 2'd3; + end else begin + builder_liteethmacsramwriter_next_state <= 3'd4; + end + end + end else begin + main_sram13_status_liteethmacsramwriter_f_next_value <= (main_sram13_status + 1'd1); + main_sram13_status_liteethmacsramwriter_f_next_value_ce <= 1'd1; + builder_liteethmacsramwriter_next_state <= 2'd2; + end + end + end + endcase +end +assign main_sram123_sink_valid = main_start_re; +assign main_sram127_sink_payload_slot = main_sram100_storage; +assign main_sram128_sink_payload_length = main_sram102_storage; +assign main_sram94_status = main_sram124_sink_ready; +assign main_sram97_status = main_sram141_level; +always @(*) begin + main_sram88_source_payload_last_be <= 4'd0; + if (main_sram86_source_last) begin + case (main_sram134_source_payload_length[1:0]) + 1'd1: begin + main_sram88_source_payload_last_be <= 1'd1; + end + 2'd2: begin + main_sram88_source_payload_last_be <= 2'd2; + end + 2'd3: begin + main_sram88_source_payload_last_be <= 3'd4; + end + 3'd4: begin + main_sram88_source_payload_last_be <= 4'd8; + end + 3'd5: begin + main_sram88_source_payload_last_be <= 5'd16; + end + 3'd6: begin + main_sram88_source_payload_last_be <= 6'd32; + end + 3'd7: begin + main_sram88_source_payload_last_be <= 7'd64; + end + default: begin + main_sram88_source_payload_last_be <= 4'd8; + end + endcase + end +end +assign main_sram163_re = main_read; +assign main_sram161_adr = main_sram122_length[10:2]; +assign main_sram166_re = main_read; +assign main_sram164_adr = main_sram122_length[10:2]; +always @(*) begin + main_rd_data <= 32'd0; + case (main_sram133_source_payload_slot) + 1'd0: begin + main_rd_data <= main_sram162_dat_r; + end + 1'd1: begin + main_rd_data <= main_sram165_dat_r; + end + endcase +end +assign main_sram87_source_payload_data = main_rd_data; +assign main_sram109_event0 = main_sram105_status; +assign main_sram113_event0 = main_sram106_pending; +always @(*) begin + main_sram108_clear <= 1'd0; + if ((main_sram116_re & main_sram117_r)) begin + main_sram108_clear <= 1'd1; + end +end +assign main_sram104_irq = (main_sram114_status & main_sram119_storage); +assign main_sram105_status = 1'd0; +assign main_sram139_din = {main_sram155_fifo_in_last, main_sram154_fifo_in_first, main_sram153_fifo_in_payload_length, main_sram152_fifo_in_payload_slot}; +assign {main_sram159_fifo_out_last, main_sram158_fifo_out_first, main_sram157_fifo_out_payload_length, main_sram156_fifo_out_payload_slot} = main_sram140_dout; +assign main_sram124_sink_ready = main_sram136_writable; +assign main_sram135_we = main_sram123_sink_valid; +assign main_sram154_fifo_in_first = main_sram125_sink_first; +assign main_sram155_fifo_in_last = main_sram126_sink_last; +assign main_sram152_fifo_in_payload_slot = main_sram127_sink_payload_slot; +assign main_sram153_fifo_in_payload_length = main_sram128_sink_payload_length; +assign main_sram129_source_valid = main_sram138_readable; +assign main_sram131_source_first = main_sram158_fifo_out_first; +assign main_sram132_source_last = main_sram159_fifo_out_last; +assign main_sram133_source_payload_slot = main_sram156_fifo_out_payload_slot; +assign main_sram134_source_payload_length = main_sram157_fifo_out_payload_length; +assign main_sram137_re = main_sram130_source_ready; +always @(*) begin + main_sram145_adr <= 1'd0; + if (main_sram142_replace) begin + main_sram145_adr <= (main_sram143_produce - 1'd1); + end else begin + main_sram145_adr <= main_sram143_produce; + end +end +assign main_sram148_dat_w = main_sram139_din; +assign main_sram147_we = (main_sram135_we & (main_sram136_writable | main_sram142_replace)); +assign main_sram149_do_read = (main_sram138_readable & main_sram137_re); +assign main_sram150_adr = main_sram144_consume; +assign main_sram140_dout = main_sram151_dat_r; +assign main_sram136_writable = (main_sram141_level != 2'd2); +assign main_sram138_readable = (main_sram141_level != 1'd0); +always @(*) begin + builder_liteethmacsramreader_next_state <= 2'd0; + main_read <= 1'd0; + main_sram107_trigger <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value <= 11'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd0; + main_sram130_source_ready <= 1'd0; + main_sram83_source_valid <= 1'd0; + main_sram86_source_last <= 1'd0; + builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state; + case (builder_liteethmacsramreader_state) + 1'd1: begin + main_sram83_source_valid <= 1'd1; + main_sram86_source_last <= (main_sram122_length >= main_sram134_source_payload_length); + if (main_sram84_source_ready) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= (main_sram122_length + 3'd4); + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + if (main_sram86_source_last) begin + builder_liteethmacsramreader_next_state <= 2'd2; + end + end + end + 2'd2: begin + main_sram122_length_liteethmacsramreader_next_value <= 1'd0; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + main_sram107_trigger <= 1'd1; + main_sram130_source_ready <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd0; + end + default: begin + if (main_sram129_source_valid) begin + main_read <= 1'd1; + main_sram122_length_liteethmacsramreader_next_value <= 3'd4; + main_sram122_length_liteethmacsramreader_next_value_ce <= 1'd1; + builder_liteethmacsramreader_next_state <= 1'd1; + end + end + endcase +end +assign main_sram167_irq = (main_sram16_irq | main_sram104_irq); +assign main_sram0_adr = main_interface0_adr[8:0]; +assign main_interface0_dat_r = main_sram0_dat_r; +assign main_sram1_adr = main_interface1_adr[8:0]; +assign main_interface1_dat_r = main_sram1_dat_r; +always @(*) begin + main_sram2_we <= 4'd0; + main_sram2_we[0] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[0]); + main_sram2_we[1] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[1]); + main_sram2_we[2] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[2]); + main_sram2_we[3] <= (((main_interface2_cyc & main_interface2_stb) & main_interface2_we) & main_interface2_sel[3]); +end +assign main_sram2_adr = main_interface2_adr[8:0]; +assign main_interface2_dat_r = main_sram2_dat_r; +assign main_sram2_dat_w = main_interface2_dat_w; +always @(*) begin + main_sram3_we <= 4'd0; + main_sram3_we[0] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[0]); + main_sram3_we[1] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[1]); + main_sram3_we[2] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[2]); + main_sram3_we[3] <= (((main_interface3_cyc & main_interface3_stb) & main_interface3_we) & main_interface3_sel[3]); +end +assign main_sram3_adr = main_interface3_adr[8:0]; +assign main_interface3_dat_r = main_sram3_dat_r; +assign main_sram3_dat_w = main_interface3_dat_w; +always @(*) begin + main_slave_sel <= 4'd0; + main_slave_sel[0] <= (main_bus_adr[10:9] == 1'd0); + main_slave_sel[1] <= (main_bus_adr[10:9] == 1'd1); + main_slave_sel[2] <= (main_bus_adr[10:9] == 2'd2); + main_slave_sel[3] <= (main_bus_adr[10:9] == 2'd3); +end +assign main_interface0_adr = main_bus_adr; +assign main_interface0_dat_w = main_bus_dat_w; +assign main_interface0_sel = main_bus_sel; +assign main_interface0_stb = main_bus_stb; +assign main_interface0_we = main_bus_we; +assign main_interface0_cti = main_bus_cti; +assign main_interface0_bte = main_bus_bte; +assign main_interface1_adr = main_bus_adr; +assign main_interface1_dat_w = main_bus_dat_w; +assign main_interface1_sel = main_bus_sel; +assign main_interface1_stb = main_bus_stb; +assign main_interface1_we = main_bus_we; +assign main_interface1_cti = main_bus_cti; +assign main_interface1_bte = main_bus_bte; +assign main_interface2_adr = main_bus_adr; +assign main_interface2_dat_w = main_bus_dat_w; +assign main_interface2_sel = main_bus_sel; +assign main_interface2_stb = main_bus_stb; +assign main_interface2_we = main_bus_we; +assign main_interface2_cti = main_bus_cti; +assign main_interface2_bte = main_bus_bte; +assign main_interface3_adr = main_bus_adr; +assign main_interface3_dat_w = main_bus_dat_w; +assign main_interface3_sel = main_bus_sel; +assign main_interface3_stb = main_bus_stb; +assign main_interface3_we = main_bus_we; +assign main_interface3_cti = main_bus_cti; +assign main_interface3_bte = main_bus_bte; +assign main_interface0_cyc = (main_bus_cyc & main_slave_sel[0]); +assign main_interface1_cyc = (main_bus_cyc & main_slave_sel[1]); +assign main_interface2_cyc = (main_bus_cyc & main_slave_sel[2]); +assign main_interface3_cyc = (main_bus_cyc & main_slave_sel[3]); +assign main_bus_ack = (((main_interface0_ack | main_interface1_ack) | main_interface2_ack) | main_interface3_ack); +assign main_bus_err = (((main_interface0_err | main_interface1_err) | main_interface2_err) | main_interface3_err); +assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_interface0_dat_r) | ({32{main_slave_sel_r[1]}} & main_interface1_dat_r)) | ({32{main_slave_sel_r[2]}} & main_interface2_dat_r)) | ({32{main_slave_sel_r[3]}} & main_interface3_dat_r)); +always @(*) begin + builder_interface0_ack <= 1'd0; + builder_interface0_dat_r <= 32'd0; + builder_interface1_adr <= 14'd0; + builder_interface1_dat_w <= 32'd0; + builder_interface1_we <= 1'd0; + builder_next_state <= 1'd0; + builder_next_state <= builder_state; + case (builder_state) + 1'd1: begin + builder_interface0_ack <= 1'd1; + builder_interface0_dat_r <= builder_interface1_dat_r; + builder_next_state <= 1'd0; + end + default: begin + builder_interface1_dat_w <= builder_interface0_dat_w; + if ((builder_interface0_cyc & builder_interface0_stb)) begin + builder_interface1_adr <= builder_interface0_adr[29:0]; + builder_interface1_we <= (builder_interface0_we & (builder_interface0_sel != 1'd0)); + builder_next_state <= 1'd1; + end + end + endcase +end +assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0); +assign builder_csrbank0_reset0_r = builder_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank0_reset0_re <= 1'd0; + builder_csrbank0_reset0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank0_reset0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_reset0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_scratch0_re <= 1'd0; + builder_csrbank0_scratch0_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we; + builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we); + end +end +assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank0_bus_errors_re <= 1'd0; + builder_csrbank0_bus_errors_we <= 1'd0; + if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we; + builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we); + end +end +always @(*) begin + main_maccore_maccore_soc_rst <= 1'd0; + if (main_maccore_maccore_reset_re) begin + main_maccore_maccore_soc_rst <= main_maccore_maccore_reset_storage[0]; + end +end +assign main_maccore_maccore_cpu_rst = main_maccore_maccore_reset_storage[1]; +assign builder_csrbank0_reset0_w = main_maccore_maccore_reset_storage[1:0]; +assign builder_csrbank0_scratch0_w = main_maccore_maccore_scratch_storage[31:0]; +assign builder_csrbank0_bus_errors_w = main_maccore_maccore_bus_errors_status[31:0]; +assign main_maccore_maccore_bus_errors_we = builder_csrbank0_bus_errors_we; +assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2); +assign builder_csrbank1_sram_writer_slot_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_slot_re <= 1'd0; + builder_csrbank1_sram_writer_slot_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank1_sram_writer_slot_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_slot_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_writer_length_re <= 1'd0; + builder_csrbank1_sram_writer_length_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_sram_writer_errors_re <= 1'd0; + builder_csrbank1_sram_writer_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank1_sram_writer_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_status_re <= 1'd0; + builder_csrbank1_sram_writer_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_pending_re <= 1'd0; + builder_csrbank1_sram_writer_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin + builder_csrbank1_sram_writer_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin + builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign main_start_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + main_start_re <= 1'd0; + main_start_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin + main_start_re <= builder_interface1_bank_bus_we; + main_start_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ready_re <= 1'd0; + builder_csrbank1_sram_reader_ready_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin + builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_level_r = builder_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csrbank1_sram_reader_level_re <= 1'd0; + builder_csrbank1_sram_reader_level_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin + builder_csrbank1_sram_reader_level_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_level_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_slot0_re <= 1'd0; + builder_csrbank1_sram_reader_slot0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin + builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_length0_r = builder_interface1_bank_bus_dat_w[10:0]; +always @(*) begin + builder_csrbank1_sram_reader_length0_re <= 1'd0; + builder_csrbank1_sram_reader_length0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin + builder_csrbank1_sram_reader_length0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_length0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_status_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_status_re <= 1'd0; + builder_csrbank1_sram_reader_ev_status_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin + builder_csrbank1_sram_reader_ev_status_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_status_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_pending_re <= 1'd0; + builder_csrbank1_sram_reader_ev_pending_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin + builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_reader_ev_enable0_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_sram_reader_ev_enable0_re <= 1'd0; + builder_csrbank1_sram_reader_ev_enable0_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd13))) begin + builder_csrbank1_sram_reader_ev_enable0_re <= builder_interface1_bank_bus_we; + builder_csrbank1_sram_reader_ev_enable0_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_preamble_crc_r = builder_interface1_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank1_preamble_crc_re <= 1'd0; + builder_csrbank1_preamble_crc_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd14))) begin + builder_csrbank1_preamble_crc_re <= builder_interface1_bank_bus_we; + builder_csrbank1_preamble_crc_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_preamble_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin + builder_csrbank1_rx_datapath_preamble_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_preamble_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_rx_datapath_crc_errors_r = builder_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csrbank1_rx_datapath_crc_errors_re <= 1'd0; + builder_csrbank1_rx_datapath_crc_errors_we <= 1'd0; + if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd16))) begin + builder_csrbank1_rx_datapath_crc_errors_re <= builder_interface1_bank_bus_we; + builder_csrbank1_rx_datapath_crc_errors_we <= (~builder_interface1_bank_bus_we); + end +end +assign builder_csrbank1_sram_writer_slot_w = main_sram7_status; +assign main_sram8_we = builder_csrbank1_sram_writer_slot_we; +assign builder_csrbank1_sram_writer_length_w = main_sram10_status[10:0]; +assign main_sram11_we = builder_csrbank1_sram_writer_length_we; +assign builder_csrbank1_sram_writer_errors_w = main_sram13_status[31:0]; +assign main_sram14_we = builder_csrbank1_sram_writer_errors_we; +always @(*) begin + main_sram22_status <= 1'd0; + main_sram22_status <= main_sram21_available; +end +assign builder_csrbank1_sram_writer_ev_status_w = main_sram22_status; +assign main_sram23_we = builder_csrbank1_sram_writer_ev_status_we; +always @(*) begin + main_sram26_status <= 1'd0; + main_sram26_status <= main_sram25_available; +end +assign builder_csrbank1_sram_writer_ev_pending_w = main_sram26_status; +assign main_sram27_we = builder_csrbank1_sram_writer_ev_pending_we; +assign main_sram30_available = main_sram31_storage; +assign builder_csrbank1_sram_writer_ev_enable0_w = main_sram31_storage; +assign builder_csrbank1_sram_reader_ready_w = main_sram94_status; +assign main_sram95_we = builder_csrbank1_sram_reader_ready_we; +assign builder_csrbank1_sram_reader_level_w = main_sram97_status[1:0]; +assign main_sram98_we = builder_csrbank1_sram_reader_level_we; +assign builder_csrbank1_sram_reader_slot0_w = main_sram100_storage; +assign builder_csrbank1_sram_reader_length0_w = main_sram102_storage[10:0]; +always @(*) begin + main_sram110_status <= 1'd0; + main_sram110_status <= main_sram109_event0; +end +assign builder_csrbank1_sram_reader_ev_status_w = main_sram110_status; +assign main_sram111_we = builder_csrbank1_sram_reader_ev_status_we; +always @(*) begin + main_sram114_status <= 1'd0; + main_sram114_status <= main_sram113_event0; +end +assign builder_csrbank1_sram_reader_ev_pending_w = main_sram114_status; +assign main_sram115_we = builder_csrbank1_sram_reader_ev_pending_we; +assign main_sram118_event0 = main_sram119_storage; +assign builder_csrbank1_sram_reader_ev_enable0_w = main_sram119_storage; +assign builder_csrbank1_preamble_crc_w = main_status; +assign main_we = builder_csrbank1_preamble_crc_we; +assign builder_csrbank1_rx_datapath_preamble_errors_w = main_preamble_errors_status[31:0]; +assign main_preamble_errors_we = builder_csrbank1_rx_datapath_preamble_errors_we; +assign builder_csrbank1_rx_datapath_crc_errors_w = main_crc_errors_status[31:0]; +assign main_crc_errors_we = builder_csrbank1_rx_datapath_crc_errors_we; +assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd1); +assign builder_csrbank2_crg_reset0_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_crg_reset0_re <= 1'd0; + builder_csrbank2_crg_reset0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csrbank2_crg_reset0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_crg_reset0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_rx_inband_status_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_rx_inband_status_re <= 1'd0; + builder_csrbank2_rx_inband_status_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin + builder_csrbank2_rx_inband_status_re <= builder_interface2_bank_bus_we; + builder_csrbank2_rx_inband_status_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0]; +always @(*) begin + builder_csrbank2_mdio_w0_re <= 1'd0; + builder_csrbank2_mdio_w0_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin + builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0]; +always @(*) begin + builder_csrbank2_mdio_r_re <= 1'd0; + builder_csrbank2_mdio_r_we <= 1'd0; + if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin + builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we; + builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we); + end +end +assign builder_csrbank2_crg_reset0_w = main_maccore_ethphy_reset_storage; +always @(*) begin + main_maccore_ethphy_status <= 3'd0; + main_maccore_ethphy_status[0] <= main_maccore_ethphy_link_status; + main_maccore_ethphy_status[1] <= main_maccore_ethphy_clock_speed; + main_maccore_ethphy_status[2] <= main_maccore_ethphy_duplex_status; +end +assign builder_csrbank2_rx_inband_status_w = main_maccore_ethphy_status[2:0]; +assign main_maccore_ethphy_we = builder_csrbank2_rx_inband_status_we; +assign main_maccore_ethphy_mdc = main_maccore_ethphy__w_storage[0]; +assign main_maccore_ethphy_oe = main_maccore_ethphy__w_storage[1]; +assign main_maccore_ethphy_w = main_maccore_ethphy__w_storage[2]; +assign builder_csrbank2_mdio_w0_w = main_maccore_ethphy__w_storage[2:0]; +assign builder_csrbank2_mdio_r_w = main_maccore_ethphy__r_status; +assign main_maccore_ethphy__r_we = builder_csrbank2_mdio_r_we; +assign builder_adr = builder_interface1_adr; +assign builder_we = builder_interface1_we; +assign builder_dat_w = builder_interface1_dat_w; +assign builder_interface1_dat_r = builder_dat_r; +assign builder_interface0_bank_bus_adr = builder_adr; +assign builder_interface1_bank_bus_adr = builder_adr; +assign builder_interface2_bank_bus_adr = builder_adr; +assign builder_interface0_bank_bus_we = builder_we; +assign builder_interface1_bank_bus_we = builder_we; +assign builder_interface2_bank_bus_we = builder_we; +assign builder_interface0_bank_bus_dat_w = builder_dat_w; +assign builder_interface1_bank_bus_dat_w = builder_dat_w; +assign builder_interface2_bank_bus_dat_w = builder_dat_w; +assign builder_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r); +assign builder_t_slice_proxy0 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy1 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy2 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy3 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy4 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy5 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy6 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy7 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy8 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy9 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy10 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy11 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy12 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy13 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy14 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy15 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy16 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy17 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy18 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy19 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy20 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy21 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy22 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy23 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy24 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy25 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy26 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy27 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy28 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy29 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy30 = (~main_tx_crc_crc_next); +assign builder_t_slice_proxy31 = (~main_tx_crc_crc_next); +assign builder_complexslicelowerer_slice_proxy = {main_tx_crc_value, main_tx_crc_sink_payload_data[7:0]}; +assign builder_t_slice_proxy32 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy33 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy34 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy35 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy36 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy37 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy38 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy39 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy40 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy41 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy42 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy43 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy44 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy45 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy46 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy47 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy48 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy49 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy50 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy51 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy52 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy53 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy54 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy55 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy56 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy57 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy58 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy59 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy60 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy61 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy62 = (~main_liteethmaccrc32checker_crc_crc_next); +assign builder_t_slice_proxy63 = (~main_liteethmaccrc32checker_crc_crc_next); +always @(*) begin + builder_self0 <= 30'd0; + case (builder_grant) + default: begin + builder_self0 <= main_wb_bus_adr; + end + endcase +end +always @(*) begin + builder_self1 <= 32'd0; + case (builder_grant) + default: begin + builder_self1 <= main_wb_bus_dat_w; + end + endcase +end +always @(*) begin + builder_self2 <= 4'd0; + case (builder_grant) + default: begin + builder_self2 <= main_wb_bus_sel; + end + endcase +end +always @(*) begin + builder_self3 <= 1'd0; + case (builder_grant) + default: begin + builder_self3 <= main_wb_bus_cyc; + end + endcase +end +always @(*) begin + builder_self4 <= 1'd0; + case (builder_grant) + default: begin + builder_self4 <= main_wb_bus_stb; + end + endcase +end +always @(*) begin + builder_self5 <= 1'd0; + case (builder_grant) + default: begin + builder_self5 <= main_wb_bus_we; + end + endcase +end +always @(*) begin + builder_self6 <= 3'd0; + case (builder_grant) + default: begin + builder_self6 <= main_wb_bus_cti; + end + endcase +end +always @(*) begin + builder_self7 <= 2'd0; + case (builder_grant) + default: begin + builder_self7 <= main_wb_bus_bte; + end + endcase +end +always @(*) begin + main_maccore_ethphy__r_status <= 1'd0; + main_maccore_ethphy__r_status <= main_maccore_ethphy_r; + main_maccore_ethphy__r_status <= builder_multiregimpl01; +end +assign main_tx_cdc_cdc_produce_rdomain = builder_multiregimpl11; +assign main_tx_cdc_cdc_consume_wdomain = builder_multiregimpl21; +assign main_pulsesynchronizer0_toggle_o = builder_multiregimpl31; +assign main_pulsesynchronizer1_toggle_o = builder_multiregimpl41; +assign main_rx_cdc_cdc_produce_rdomain = builder_multiregimpl51; +assign main_rx_cdc_cdc_consume_wdomain = builder_multiregimpl61; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge eth_rx_clk) begin + main_maccore_ethphy_rx_ctl_reg <= main_maccore_ethphy_rx_ctl; + main_maccore_ethphy_rx_data_reg <= main_maccore_ethphy_rx_data; + main_maccore_ethphy_rx_ctl_reg_d <= main_maccore_ethphy_rx_ctl_reg; + main_maccore_ethphy_source_valid <= main_maccore_ethphy_rx_ctl_reg[0]; + main_maccore_ethphy_source_payload_data <= main_maccore_ethphy_rx_data_reg; + if ((main_maccore_ethphy_rx_ctl == 1'd0)) begin + main_maccore_ethphy_link_status <= main_maccore_ethphy_rx_data[0]; + main_maccore_ethphy_clock_speed <= main_maccore_ethphy_rx_data[2:1]; + main_maccore_ethphy_duplex_status <= main_maccore_ethphy_rx_data[3]; + end + builder_rxdatapath_liteethmacpreamblechecker_state <= builder_rxdatapath_liteethmacpreamblechecker_next_state; + if (main_pulsesynchronizer0_i) begin + main_pulsesynchronizer0_toggle_i <= (~main_pulsesynchronizer0_toggle_i); + end + if (main_liteethmaccrc32checker_crc_ce) begin + main_liteethmaccrc32checker_crc_reg <= main_liteethmaccrc32checker_crc_crc_next; + end + if (main_liteethmaccrc32checker_crc_reset) begin + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((main_liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_produce <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_produce <= (main_liteethmaccrc32checker_syncfifo_produce + 1'd1); + end + end + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + if ((main_liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin + main_liteethmaccrc32checker_syncfifo_consume <= 1'd0; + end else begin + main_liteethmaccrc32checker_syncfifo_consume <= (main_liteethmaccrc32checker_syncfifo_consume + 1'd1); + end + end + if (((main_liteethmaccrc32checker_syncfifo_syncfifo_we & main_liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~main_liteethmaccrc32checker_syncfifo_replace))) begin + if ((~main_liteethmaccrc32checker_syncfifo_do_read)) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level + 1'd1); + end + end else begin + if (main_liteethmaccrc32checker_syncfifo_do_read) begin + main_liteethmaccrc32checker_syncfifo_level <= (main_liteethmaccrc32checker_syncfifo_level - 1'd1); + end + end + if (main_liteethmaccrc32checker_fifo_reset) begin + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + end + builder_rxdatapath_bufferizeendpoints_state <= builder_rxdatapath_bufferizeendpoints_next_state; + if (main_liteethmaccrc32checker_last_be_next_value_ce0) begin + main_liteethmaccrc32checker_last_be <= main_liteethmaccrc32checker_last_be_next_value0; + end + if (main_liteethmaccrc32checker_crc_error1_next_value_ce1) begin + main_liteethmaccrc32checker_crc_error1 <= main_liteethmaccrc32checker_crc_error1_next_value1; + end + if (((~main_bufferizeendpoints_pipe_valid_source_valid) | main_bufferizeendpoints_pipe_valid_source_ready)) begin + main_bufferizeendpoints_pipe_valid_source_valid <= main_bufferizeendpoints_pipe_valid_sink_valid; + main_bufferizeendpoints_pipe_valid_source_first <= main_bufferizeendpoints_pipe_valid_sink_first; + main_bufferizeendpoints_pipe_valid_source_last <= main_bufferizeendpoints_pipe_valid_sink_last; + main_bufferizeendpoints_pipe_valid_source_payload_data <= main_bufferizeendpoints_pipe_valid_sink_payload_data; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= main_bufferizeendpoints_pipe_valid_sink_payload_last_be; + main_bufferizeendpoints_pipe_valid_source_payload_error <= main_bufferizeendpoints_pipe_valid_sink_payload_error; + end + if (main_pulsesynchronizer1_i) begin + main_pulsesynchronizer1_toggle_i <= (~main_pulsesynchronizer1_toggle_i); + end + if (main_rx_converter_converter_source_ready) begin + main_rx_converter_converter_strobe_all <= 1'd0; + end + if (main_rx_converter_converter_load_part) begin + if (((main_rx_converter_converter_demux == 2'd3) | main_rx_converter_converter_sink_last)) begin + main_rx_converter_converter_demux <= 1'd0; + main_rx_converter_converter_strobe_all <= 1'd1; + end else begin + main_rx_converter_converter_demux <= (main_rx_converter_converter_demux + 1'd1); + end + end + if ((main_rx_converter_converter_source_valid & main_rx_converter_converter_source_ready)) begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= main_rx_converter_converter_sink_first; + main_rx_converter_converter_source_last <= main_rx_converter_converter_sink_last; + end else begin + main_rx_converter_converter_source_first <= 1'd0; + main_rx_converter_converter_source_last <= 1'd0; + end + end else begin + if ((main_rx_converter_converter_sink_valid & main_rx_converter_converter_sink_ready)) begin + main_rx_converter_converter_source_first <= (main_rx_converter_converter_sink_first | main_rx_converter_converter_source_first); + main_rx_converter_converter_source_last <= (main_rx_converter_converter_sink_last | main_rx_converter_converter_source_last); + end + end + if (main_rx_converter_converter_load_part) begin + case (main_rx_converter_converter_demux) + 1'd0: begin + main_rx_converter_converter_source_payload_data[9:0] <= main_rx_converter_converter_sink_payload_data; + end + 1'd1: begin + main_rx_converter_converter_source_payload_data[19:10] <= main_rx_converter_converter_sink_payload_data; + end + 2'd2: begin + main_rx_converter_converter_source_payload_data[29:20] <= main_rx_converter_converter_sink_payload_data; + end + 2'd3: begin + main_rx_converter_converter_source_payload_data[39:30] <= main_rx_converter_converter_sink_payload_data; + end + endcase + end + if (main_rx_converter_converter_load_part) begin + main_rx_converter_converter_source_payload_valid_token_count <= (main_rx_converter_converter_demux + 1'd1); + end + main_rx_cdc_cdc_graycounter0_q_binary <= main_rx_cdc_cdc_graycounter0_q_next_binary; + main_rx_cdc_cdc_graycounter0_q <= main_rx_cdc_cdc_graycounter0_q_next; + if (eth_rx_rst) begin + main_maccore_ethphy_source_valid <= 1'd0; + main_maccore_ethphy_source_payload_data <= 8'd0; + main_maccore_ethphy_link_status <= 1'd0; + main_maccore_ethphy_clock_speed <= 1'd0; + main_maccore_ethphy_duplex_status <= 1'd0; + main_maccore_ethphy_rx_ctl_reg <= 2'd0; + main_maccore_ethphy_rx_data_reg <= 8'd0; + main_maccore_ethphy_rx_ctl_reg_d <= 2'd0; + main_liteethmaccrc32checker_crc_reg <= 32'd4294967295; + main_liteethmaccrc32checker_syncfifo_level <= 3'd0; + main_liteethmaccrc32checker_syncfifo_produce <= 3'd0; + main_liteethmaccrc32checker_syncfifo_consume <= 3'd0; + main_liteethmaccrc32checker_last_be <= 1'd0; + main_liteethmaccrc32checker_crc_error1 <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_valid <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_data <= 8'd0; + main_bufferizeendpoints_pipe_valid_source_payload_last_be <= 1'd0; + main_bufferizeendpoints_pipe_valid_source_payload_error <= 1'd0; + main_rx_converter_converter_source_payload_data <= 40'd0; + main_rx_converter_converter_source_payload_valid_token_count <= 3'd0; + main_rx_converter_converter_demux <= 2'd0; + main_rx_converter_converter_strobe_all <= 1'd0; + main_rx_cdc_cdc_graycounter0_q <= 6'd0; + main_rx_cdc_cdc_graycounter0_q_binary <= 6'd0; + builder_rxdatapath_liteethmacpreamblechecker_state <= 1'd0; + builder_rxdatapath_bufferizeendpoints_state <= 2'd0; + end + builder_multiregimpl60 <= main_rx_cdc_cdc_graycounter1_q; + builder_multiregimpl61 <= builder_multiregimpl60; +end + +always @(posedge eth_tx_clk) begin + main_tx_cdc_cdc_graycounter1_q_binary <= main_tx_cdc_cdc_graycounter1_q_next_binary; + main_tx_cdc_cdc_graycounter1_q <= main_tx_cdc_cdc_graycounter1_q_next; + if ((main_tx_converter_converter_source_valid & main_tx_converter_converter_source_ready)) begin + if (main_tx_converter_converter_last) begin + main_tx_converter_converter_mux <= 1'd0; + end else begin + main_tx_converter_converter_mux <= (main_tx_converter_converter_mux + 1'd1); + end + end + builder_txdatapath_liteethmactxlastbe_state <= builder_txdatapath_liteethmactxlastbe_next_state; + builder_txdatapath_liteethmacpaddinginserter_state <= builder_txdatapath_liteethmacpaddinginserter_next_state; + if (main_tx_padding_counter_clockdomainsrenamer0_next_value_ce) begin + main_tx_padding_counter <= main_tx_padding_counter_clockdomainsrenamer0_next_value; + end + if (main_tx_crc_is_ongoing0) begin + main_tx_crc_cnt <= 2'd3; + end else begin + if ((main_tx_crc_is_ongoing1 & (~main_tx_crc_cnt_done))) begin + main_tx_crc_cnt <= (main_tx_crc_cnt - main_tx_crc_source_ready); + end + end + if (main_tx_crc_ce) begin + main_tx_crc_reg <= main_tx_crc_crc_next; + end + if (main_tx_crc_reset) begin + main_tx_crc_reg <= 32'd4294967295; + end + builder_txdatapath_bufferizeendpoints_state <= builder_txdatapath_bufferizeendpoints_next_state; + if (main_tx_crc_crc_packet_clockdomainsrenamer1_next_value_ce0) begin + main_tx_crc_crc_packet <= main_tx_crc_crc_packet_clockdomainsrenamer1_next_value0; + end + if (main_tx_crc_last_be_clockdomainsrenamer1_next_value_ce1) begin + main_tx_crc_last_be <= main_tx_crc_last_be_clockdomainsrenamer1_next_value1; + end + if (((~main_tx_crc_pipe_valid_source_valid) | main_tx_crc_pipe_valid_source_ready)) begin + main_tx_crc_pipe_valid_source_valid <= main_tx_crc_pipe_valid_sink_valid; + main_tx_crc_pipe_valid_source_first <= main_tx_crc_pipe_valid_sink_first; + main_tx_crc_pipe_valid_source_last <= main_tx_crc_pipe_valid_sink_last; + main_tx_crc_pipe_valid_source_payload_data <= main_tx_crc_pipe_valid_sink_payload_data; + main_tx_crc_pipe_valid_source_payload_last_be <= main_tx_crc_pipe_valid_sink_payload_last_be; + main_tx_crc_pipe_valid_source_payload_error <= main_tx_crc_pipe_valid_sink_payload_error; + end + builder_txdatapath_liteethmacpreambleinserter_state <= builder_txdatapath_liteethmacpreambleinserter_next_state; + if (main_tx_preamble_count_clockdomainsrenamer2_next_value_ce) begin + main_tx_preamble_count <= main_tx_preamble_count_clockdomainsrenamer2_next_value; + end + builder_txdatapath_liteethmacgap_state <= builder_txdatapath_liteethmacgap_next_state; + if (main_tx_gap_counter_clockdomainsrenamer3_next_value_ce) begin + main_tx_gap_counter <= main_tx_gap_counter_clockdomainsrenamer3_next_value; + end + if (eth_tx_rst) begin + main_tx_cdc_cdc_graycounter1_q <= 6'd0; + main_tx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_tx_converter_converter_mux <= 2'd0; + main_tx_padding_counter <= 16'd0; + main_tx_crc_crc_packet <= 32'd0; + main_tx_crc_last_be <= 1'd0; + main_tx_crc_reg <= 32'd4294967295; + main_tx_crc_cnt <= 2'd3; + main_tx_crc_pipe_valid_source_valid <= 1'd0; + main_tx_crc_pipe_valid_source_payload_data <= 8'd0; + main_tx_crc_pipe_valid_source_payload_last_be <= 1'd0; + main_tx_crc_pipe_valid_source_payload_error <= 1'd0; + builder_txdatapath_liteethmactxlastbe_state <= 1'd0; + builder_txdatapath_liteethmacpaddinginserter_state <= 1'd0; + builder_txdatapath_bufferizeendpoints_state <= 2'd0; + builder_txdatapath_liteethmacpreambleinserter_state <= 2'd0; + builder_txdatapath_liteethmacgap_state <= 1'd0; + end + builder_multiregimpl10 <= main_tx_cdc_cdc_graycounter0_q; + builder_multiregimpl11 <= builder_multiregimpl10; +end + +always @(posedge por_clk) begin + main_maccore_int_rst <= sys_reset; +end + +always @(posedge sys_clk) begin + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + if ((main_maccore_maccore_bus_errors != 32'd4294967295)) begin + if (main_maccore_maccore_bus_error) begin + main_maccore_maccore_bus_errors <= (main_maccore_maccore_bus_errors + 1'd1); + end + end + main_tx_cdc_cdc_graycounter0_q_binary <= main_tx_cdc_cdc_graycounter0_q_next_binary; + main_tx_cdc_cdc_graycounter0_q <= main_tx_cdc_cdc_graycounter0_q_next; + if (main_pulsesynchronizer0_o) begin + main_preamble_errors_status <= (main_preamble_errors_status + 1'd1); + end + if (main_pulsesynchronizer1_o) begin + main_crc_errors_status <= (main_crc_errors_status + 1'd1); + end + main_pulsesynchronizer0_toggle_o_r <= main_pulsesynchronizer0_toggle_o; + main_pulsesynchronizer1_toggle_o_r <= main_pulsesynchronizer1_toggle_o; + main_rx_cdc_cdc_graycounter1_q_binary <= main_rx_cdc_cdc_graycounter1_q_next_binary; + main_rx_cdc_cdc_graycounter1_q <= main_rx_cdc_cdc_graycounter1_q_next; + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + main_sram57_produce <= (main_sram57_produce + 1'd1); + end + if (main_sram63_do_read) begin + main_sram58_consume <= (main_sram58_consume + 1'd1); + end + if (((main_sram49_we & main_sram50_writable) & (~main_sram56_replace))) begin + if ((~main_sram63_do_read)) begin + main_sram55_level <= (main_sram55_level + 1'd1); + end + end else begin + if (main_sram63_do_read) begin + main_sram55_level <= (main_sram55_level - 1'd1); + end + end + builder_liteethmacsramwriter_state <= builder_liteethmacsramwriter_next_state; + if (main_sram35_length_liteethmacsramwriter_t_next_value_ce) begin + main_sram35_length <= main_sram35_length_liteethmacsramwriter_t_next_value; + end + if (main_sram13_status_liteethmacsramwriter_f_next_value_ce) begin + main_sram13_status <= main_sram13_status_liteethmacsramwriter_f_next_value; + end + if (main_slot_liteethmacsramwriter_next_value_ce) begin + main_slot <= main_slot_liteethmacsramwriter_next_value; + end + if (main_sram108_clear) begin + main_sram106_pending <= 1'd0; + end + if (main_sram107_trigger) begin + main_sram106_pending <= 1'd1; + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + main_sram143_produce <= (main_sram143_produce + 1'd1); + end + if (main_sram149_do_read) begin + main_sram144_consume <= (main_sram144_consume + 1'd1); + end + if (((main_sram135_we & main_sram136_writable) & (~main_sram142_replace))) begin + if ((~main_sram149_do_read)) begin + main_sram141_level <= (main_sram141_level + 1'd1); + end + end else begin + if (main_sram149_do_read) begin + main_sram141_level <= (main_sram141_level - 1'd1); + end + end + builder_liteethmacsramreader_state <= builder_liteethmacsramreader_next_state; + if (main_sram122_length_liteethmacsramreader_next_value_ce) begin + main_sram122_length <= main_sram122_length_liteethmacsramreader_next_value; + end + main_interface0_ack <= 1'd0; + if (((main_interface0_cyc & main_interface0_stb) & ((~main_interface0_ack) | main_sram0_adr_burst))) begin + main_interface0_ack <= 1'd1; + end + main_interface1_ack <= 1'd0; + if (((main_interface1_cyc & main_interface1_stb) & ((~main_interface1_ack) | main_sram1_adr_burst))) begin + main_interface1_ack <= 1'd1; + end + main_interface2_ack <= 1'd0; + if (((main_interface2_cyc & main_interface2_stb) & ((~main_interface2_ack) | main_sram2_adr_burst))) begin + main_interface2_ack <= 1'd1; + end + main_interface3_ack <= 1'd0; + if (((main_interface3_cyc & main_interface3_stb) & ((~main_interface3_ack) | main_sram3_adr_burst))) begin + main_interface3_ack <= 1'd1; + end + main_slave_sel_r <= main_slave_sel; + builder_state <= builder_next_state; + builder_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csrbank0_sel) begin + case (builder_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_reset0_w; + end + 1'd1: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_scratch0_w; + end + 2'd2: begin + builder_interface0_bank_bus_dat_r <= builder_csrbank0_bus_errors_w; + end + endcase + end + if (builder_csrbank0_reset0_re) begin + main_maccore_maccore_reset_storage[1:0] <= builder_csrbank0_reset0_r; + end + main_maccore_maccore_reset_re <= builder_csrbank0_reset0_re; + if (builder_csrbank0_scratch0_re) begin + main_maccore_maccore_scratch_storage[31:0] <= builder_csrbank0_scratch0_r; + end + main_maccore_maccore_scratch_re <= builder_csrbank0_scratch0_re; + main_maccore_maccore_bus_errors_re <= builder_csrbank0_bus_errors_re; + builder_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csrbank1_sel) begin + case (builder_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_slot_w; + end + 1'd1: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_length_w; + end + 2'd2: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_errors_w; + end + 2'd3: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_status_w; + end + 3'd4: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_pending_w; + end + 3'd5: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_writer_ev_enable0_w; + end + 3'd6: begin + builder_interface1_bank_bus_dat_r <= main_start_w; + end + 3'd7: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ready_w; + end + 4'd8: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_level_w; + end + 4'd9: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_slot0_w; + end + 4'd10: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_length0_w; + end + 4'd11: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_status_w; + end + 4'd12: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_pending_w; + end + 4'd13: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_sram_reader_ev_enable0_w; + end + 4'd14: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_preamble_crc_w; + end + 4'd15: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_preamble_errors_w; + end + 5'd16: begin + builder_interface1_bank_bus_dat_r <= builder_csrbank1_rx_datapath_crc_errors_w; + end + endcase + end + main_sram9_re <= builder_csrbank1_sram_writer_slot_re; + main_sram12_re <= builder_csrbank1_sram_writer_length_re; + main_sram15_re <= builder_csrbank1_sram_writer_errors_re; + main_sram24_re <= builder_csrbank1_sram_writer_ev_status_re; + if (builder_csrbank1_sram_writer_ev_pending_re) begin + main_sram29_r <= builder_csrbank1_sram_writer_ev_pending_r; + end + main_sram28_re <= builder_csrbank1_sram_writer_ev_pending_re; + if (builder_csrbank1_sram_writer_ev_enable0_re) begin + main_sram31_storage <= builder_csrbank1_sram_writer_ev_enable0_r; + end + main_sram32_re <= builder_csrbank1_sram_writer_ev_enable0_re; + main_sram96_re <= builder_csrbank1_sram_reader_ready_re; + main_sram99_re <= builder_csrbank1_sram_reader_level_re; + if (builder_csrbank1_sram_reader_slot0_re) begin + main_sram100_storage <= builder_csrbank1_sram_reader_slot0_r; + end + main_sram101_re <= builder_csrbank1_sram_reader_slot0_re; + if (builder_csrbank1_sram_reader_length0_re) begin + main_sram102_storage[10:0] <= builder_csrbank1_sram_reader_length0_r; + end + main_sram103_re <= builder_csrbank1_sram_reader_length0_re; + main_sram112_re <= builder_csrbank1_sram_reader_ev_status_re; + if (builder_csrbank1_sram_reader_ev_pending_re) begin + main_sram117_r <= builder_csrbank1_sram_reader_ev_pending_r; + end + main_sram116_re <= builder_csrbank1_sram_reader_ev_pending_re; + if (builder_csrbank1_sram_reader_ev_enable0_re) begin + main_sram119_storage <= builder_csrbank1_sram_reader_ev_enable0_r; + end + main_sram120_re <= builder_csrbank1_sram_reader_ev_enable0_re; + main_re <= builder_csrbank1_preamble_crc_re; + main_preamble_errors_re <= builder_csrbank1_rx_datapath_preamble_errors_re; + main_crc_errors_re <= builder_csrbank1_rx_datapath_crc_errors_re; + builder_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csrbank2_sel) begin + case (builder_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_crg_reset0_w; + end + 1'd1: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_rx_inband_status_w; + end + 2'd2: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_w0_w; + end + 2'd3: begin + builder_interface2_bank_bus_dat_r <= builder_csrbank2_mdio_r_w; + end + endcase + end + if (builder_csrbank2_crg_reset0_re) begin + main_maccore_ethphy_reset_storage <= builder_csrbank2_crg_reset0_r; + end + main_maccore_ethphy_reset_re <= builder_csrbank2_crg_reset0_re; + main_maccore_ethphy_re <= builder_csrbank2_rx_inband_status_re; + if (builder_csrbank2_mdio_w0_re) begin + main_maccore_ethphy__w_storage[2:0] <= builder_csrbank2_mdio_w0_r; + end + main_maccore_ethphy__w_re <= builder_csrbank2_mdio_w0_re; + main_maccore_ethphy__r_re <= builder_csrbank2_mdio_r_re; + if (sys_rst) begin + main_maccore_maccore_reset_storage <= 2'd0; + main_maccore_maccore_reset_re <= 1'd0; + main_maccore_maccore_scratch_storage <= 32'd305419896; + main_maccore_maccore_scratch_re <= 1'd0; + main_maccore_maccore_bus_errors_re <= 1'd0; + main_maccore_maccore_bus_errors <= 32'd0; + main_maccore_ethphy_reset_storage <= 1'd0; + main_maccore_ethphy_reset_re <= 1'd0; + main_maccore_ethphy_re <= 1'd0; + main_maccore_ethphy__w_storage <= 3'd0; + main_maccore_ethphy__w_re <= 1'd0; + main_maccore_ethphy__r_re <= 1'd0; + main_re <= 1'd0; + main_tx_cdc_cdc_graycounter0_q <= 6'd0; + main_tx_cdc_cdc_graycounter0_q_binary <= 6'd0; + main_preamble_errors_status <= 32'd0; + main_preamble_errors_re <= 1'd0; + main_crc_errors_status <= 32'd0; + main_crc_errors_re <= 1'd0; + main_rx_cdc_cdc_graycounter1_q <= 6'd0; + main_rx_cdc_cdc_graycounter1_q_binary <= 6'd0; + main_sram9_re <= 1'd0; + main_sram12_re <= 1'd0; + main_sram13_status <= 32'd0; + main_sram15_re <= 1'd0; + main_sram24_re <= 1'd0; + main_sram28_re <= 1'd0; + main_sram29_r <= 1'd0; + main_sram31_storage <= 1'd0; + main_sram32_re <= 1'd0; + main_slot <= 1'd0; + main_sram35_length <= 11'd0; + main_sram55_level <= 2'd0; + main_sram57_produce <= 1'd0; + main_sram58_consume <= 1'd0; + main_sram96_re <= 1'd0; + main_sram99_re <= 1'd0; + main_sram101_re <= 1'd0; + main_sram103_re <= 1'd0; + main_sram106_pending <= 1'd0; + main_sram112_re <= 1'd0; + main_sram116_re <= 1'd0; + main_sram117_r <= 1'd0; + main_sram119_storage <= 1'd0; + main_sram120_re <= 1'd0; + main_sram122_length <= 11'd0; + main_sram141_level <= 2'd0; + main_sram143_produce <= 1'd0; + main_sram144_consume <= 1'd0; + main_interface0_ack <= 1'd0; + main_interface1_ack <= 1'd0; + main_interface2_ack <= 1'd0; + main_interface3_ack <= 1'd0; + main_slave_sel_r <= 4'd0; + builder_slave_sel_r <= 2'd0; + builder_count <= 20'd1000000; + builder_liteethmacsramwriter_state <= 3'd0; + builder_liteethmacsramreader_state <= 2'd0; + builder_state <= 1'd0; + end + builder_multiregimpl00 <= main_maccore_ethphy_data_r; + builder_multiregimpl01 <= builder_multiregimpl00; + builder_multiregimpl20 <= main_tx_cdc_cdc_graycounter1_q; + builder_multiregimpl21 <= builder_multiregimpl20; + builder_multiregimpl30 <= main_pulsesynchronizer0_toggle_i; + builder_multiregimpl31 <= builder_multiregimpl30; + builder_multiregimpl40 <= main_pulsesynchronizer1_toggle_i; + builder_multiregimpl41 <= builder_multiregimpl40; + builder_multiregimpl50 <= main_rx_cdc_cdc_graycounter0_q; + builder_multiregimpl51 <= builder_multiregimpl50; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Instance DELAYG of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (7'd80) +) DELAYG ( + // Inputs. + .A (main_maccore_ethphy_eth_tx_clk_o), + + // Outputs. + .Z (rgmii_clocks_tx) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_1 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_1 ( + // Inputs. + .A (main_maccore_ethphy_tx_ctl_oddrx1f), + + // Outputs. + .Z (rgmii_tx_ctl) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_2 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_2 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[0]), + + // Outputs. + .Z (rgmii_tx_data[0]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_3 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_3 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[1]), + + // Outputs. + .Z (rgmii_tx_data[1]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_4 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_4 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[2]), + + // Outputs. + .Z (rgmii_tx_data[2]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_5 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_5 ( + // Inputs. + .A (main_maccore_ethphy_tx_data_oddrx1f[3]), + + // Outputs. + .Z (rgmii_tx_data[3]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_6 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_6 ( + // Inputs. + .A (rgmii_rx_ctl), + + // Outputs. + .Z (main_maccore_ethphy_rx_ctl_delayf) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_7 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_7 ( + // Inputs. + .A (rgmii_rx_data[0]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[0]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_8 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_8 ( + // Inputs. + .A (rgmii_rx_data[1]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[1]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_9 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_9 ( + // Inputs. + .A (rgmii_rx_data[2]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[2]) +); + +//------------------------------------------------------------------------------ +// Instance DELAYG_10 of DELAYG Module. +//------------------------------------------------------------------------------ +DELAYG #( + // Parameters. + .DEL_MODE ("SCLK_ALIGNED"), + .DEL_VALUE (1'd0) +) DELAYG_10 ( + // Inputs. + .A (rgmii_rx_data[3]), + + // Outputs. + .Z (main_maccore_ethphy_rx_data_delayf[3]) +); + +assign rgmii_mdio = main_maccore_ethphy_data_oe ? main_maccore_ethphy_data_w : 1'bz; +assign main_maccore_ethphy_data_r = rgmii_mdio; + +//------------------------------------------------------------------------------ +// Memory storage: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage[0:31]; +reg [41:0] storage_dat0; +reg [41:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_tx_cdc_cdc_wrport_we) + storage[main_tx_cdc_cdc_wrport_adr] <= main_tx_cdc_cdc_wrport_dat_w; + storage_dat0 <= storage[main_tx_cdc_cdc_wrport_adr]; +end +always @(posedge eth_tx_clk) begin + storage_dat1 <= storage[main_tx_cdc_cdc_rdport_adr]; +end +assign main_tx_cdc_cdc_wrport_dat_r = storage_dat0; +assign main_tx_cdc_cdc_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 5-words x 12-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 12 +// Port 1 | Read: Async | Write: ---- | +reg [11:0] storage_1[0:4]; +reg [11:0] storage_1_dat0; +always @(posedge eth_rx_clk) begin + if (main_liteethmaccrc32checker_syncfifo_wrport_we) + storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr] <= main_liteethmaccrc32checker_syncfifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_liteethmaccrc32checker_syncfifo_wrport_adr]; +end +always @(posedge eth_rx_clk) begin +end +assign main_liteethmaccrc32checker_syncfifo_wrport_dat_r = storage_1_dat0; +assign main_liteethmaccrc32checker_syncfifo_rdport_dat_r = storage_1[main_liteethmaccrc32checker_syncfifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 32-words x 42-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 42 +// Port 1 | Read: Sync | Write: ---- | +reg [41:0] storage_2[0:31]; +reg [41:0] storage_2_dat0; +reg [41:0] storage_2_dat1; +always @(posedge eth_rx_clk) begin + if (main_rx_cdc_cdc_wrport_we) + storage_2[main_rx_cdc_cdc_wrport_adr] <= main_rx_cdc_cdc_wrport_dat_w; + storage_2_dat0 <= storage_2[main_rx_cdc_cdc_wrport_adr]; +end +always @(posedge sys_clk) begin + storage_2_dat1 <= storage_2[main_rx_cdc_cdc_rdport_adr]; +end +assign main_rx_cdc_cdc_wrport_dat_r = storage_2_dat0; +assign main_rx_cdc_cdc_rdport_dat_r = storage_2_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_3[0:1]; +reg [13:0] storage_3_dat0; +always @(posedge sys_clk) begin + if (main_sram61_we) + storage_3[main_sram59_adr] <= main_sram62_dat_w; + storage_3_dat0 <= storage_3[main_sram59_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram60_dat_r = storage_3_dat0; +assign main_sram65_dat_r = storage_3[main_sram64_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem[0:382]; +reg [8:0] mem_adr0; +reg [31:0] mem_dat1; +always @(posedge sys_clk) begin + if (main_sram77_we) + mem[main_sram75_adr] <= main_sram78_dat_w; + mem_adr0 <= main_sram75_adr; +end +always @(posedge sys_clk) begin + mem_dat1 <= mem[main_sram0_adr]; +end +assign main_sram76_dat_r = mem[mem_adr0]; +assign main_sram0_dat_r = mem_dat1; + + +//------------------------------------------------------------------------------ +// Memory mem_1: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 32 +// Port 1 | Read: Sync | Write: ---- | +reg [31:0] mem_1[0:382]; +reg [8:0] mem_1_adr0; +reg [31:0] mem_1_dat1; +always @(posedge sys_clk) begin + if (main_sram81_we) + mem_1[main_sram79_adr] <= main_sram82_dat_w; + mem_1_adr0 <= main_sram79_adr; +end +always @(posedge sys_clk) begin + mem_1_dat1 <= mem_1[main_sram1_adr]; +end +assign main_sram80_dat_r = mem_1[mem_1_adr0]; +assign main_sram1_dat_r = mem_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 2-words x 14-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 14 +// Port 1 | Read: Async | Write: ---- | +reg [13:0] storage_4[0:1]; +reg [13:0] storage_4_dat0; +always @(posedge sys_clk) begin + if (main_sram147_we) + storage_4[main_sram145_adr] <= main_sram148_dat_w; + storage_4_dat0 <= storage_4[main_sram145_adr]; +end +always @(posedge sys_clk) begin +end +assign main_sram146_dat_r = storage_4_dat0; +assign main_sram151_dat_r = storage_4[main_sram150_adr]; + + +//------------------------------------------------------------------------------ +// Memory mem_2: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_2[0:382]; +reg [31:0] mem_2_dat0; +reg [8:0] mem_2_adr1; +always @(posedge sys_clk) begin + if (main_sram163_re) + mem_2_dat0 <= mem_2[main_sram161_adr]; +end +always @(posedge sys_clk) begin + if (main_sram2_we[0]) + mem_2[main_sram2_adr][7:0] <= main_sram2_dat_w[7:0]; + if (main_sram2_we[1]) + mem_2[main_sram2_adr][15:8] <= main_sram2_dat_w[15:8]; + if (main_sram2_we[2]) + mem_2[main_sram2_adr][23:16] <= main_sram2_dat_w[23:16]; + if (main_sram2_we[3]) + mem_2[main_sram2_adr][31:24] <= main_sram2_dat_w[31:24]; + mem_2_adr1 <= main_sram2_adr; +end +assign main_sram162_dat_r = mem_2_dat0; +assign main_sram2_dat_r = mem_2[mem_2_adr1]; + + +//------------------------------------------------------------------------------ +// Memory mem_3: 383-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +// Port 1 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] mem_3[0:382]; +reg [31:0] mem_3_dat0; +reg [8:0] mem_3_adr1; +always @(posedge sys_clk) begin + if (main_sram166_re) + mem_3_dat0 <= mem_3[main_sram164_adr]; +end +always @(posedge sys_clk) begin + if (main_sram3_we[0]) + mem_3[main_sram3_adr][7:0] <= main_sram3_dat_w[7:0]; + if (main_sram3_we[1]) + mem_3[main_sram3_adr][15:8] <= main_sram3_dat_w[15:8]; + if (main_sram3_we[2]) + mem_3[main_sram3_adr][23:16] <= main_sram3_dat_w[23:16]; + if (main_sram3_we[3]) + mem_3[main_sram3_adr][31:24] <= main_sram3_dat_w[31:24]; + mem_3_adr1 <= main_sram3_adr; +end +assign main_sram165_dat_r = mem_3_dat0; +assign main_sram3_dat_r = mem_3[mem_3_adr1]; + + +//------------------------------------------------------------------------------ +// Instance ODDRX1F of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F( + // Inputs. + .D0 (1'd1), + .D1 (1'd0), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_eth_tx_clk_o) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX( + // Inputs. + .CK (eth_tx_clk), + .D (1'd0), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (builder_rst10) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_1 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_1( + // Inputs. + .CK (eth_tx_clk), + .D (builder_rst10), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (eth_tx_rst) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_2 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_2( + // Inputs. + .CK (eth_rx_clk), + .D (1'd0), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (builder_rst11) +); + +//------------------------------------------------------------------------------ +// Instance FD1S3BX_3 of FD1S3BX Module. +//------------------------------------------------------------------------------ +FD1S3BX FD1S3BX_3( + // Inputs. + .CK (eth_rx_clk), + .D (builder_rst11), + .PD (main_maccore_ethphy_reset), + + // Outputs. + .Q (eth_rx_rst) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_1 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_1( + // Inputs. + .D0 (main_maccore_ethphy_sink_valid), + .D1 (main_maccore_ethphy_sink_valid), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_ctl_oddrx1f) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_2 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_2( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[0]), + .D1 (main_maccore_ethphy_sink_payload_data[4]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[0]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_3 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_3( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[1]), + .D1 (main_maccore_ethphy_sink_payload_data[5]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[1]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_4 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_4( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[2]), + .D1 (main_maccore_ethphy_sink_payload_data[6]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[2]) +); + +//------------------------------------------------------------------------------ +// Instance ODDRX1F_5 of ODDRX1F Module. +//------------------------------------------------------------------------------ +ODDRX1F ODDRX1F_5( + // Inputs. + .D0 (main_maccore_ethphy_sink_payload_data[3]), + .D1 (main_maccore_ethphy_sink_payload_data[7]), + .SCLK (eth_tx_clk), + + // Outputs. + .Q (main_maccore_ethphy_tx_data_oddrx1f[3]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F( + // Inputs. + .D (main_maccore_ethphy_rx_ctl_delayf), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_ctl[0]), + .Q1 (main_maccore_ethphy_rx_ctl[1]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_1 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_1( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[0]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[0]), + .Q1 (main_maccore_ethphy_rx_data[4]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_2 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_2( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[1]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[1]), + .Q1 (main_maccore_ethphy_rx_data[5]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_3 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_3( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[2]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[2]), + .Q1 (main_maccore_ethphy_rx_data[6]) +); + +//------------------------------------------------------------------------------ +// Instance IDDRX1F_4 of IDDRX1F Module. +//------------------------------------------------------------------------------ +IDDRX1F IDDRX1F_4( + // Inputs. + .D (main_maccore_ethphy_rx_data_delayf[3]), + .SCLK (eth_rx_clk), + + // Outputs. + .Q0 (main_maccore_ethphy_rx_data[3]), + .Q1 (main_maccore_ethphy_rx_data[7]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-09 14:20:59. +//------------------------------------------------------------------------------